JPH03259565A - Transistor cell - Google Patents

Abstract

PURPOSE: To minimize the dimension of a cell and to improve mounting density at the same time by housing interconnected capacitors, constituting a latch circuit in the structure of a laminated CMOS transistor. CONSTITUTION: A latch circuit 10 is constituted of two pairs of MOS transistor. These transistors are constituted of first and second P-channel transistors 12 and 14 and first and second N-channel transistors 16 and 18. Respective first sources/drains 20 and 22 of the transistors 12 and 14 are coupled to a supply voltage Vcc at the upper stage. In the same way, first sources/drains 24 and 26 of the transistors 16 and 18 are coupled to the reference voltage, which is the ground at the lower stage. Furthermore, a second source/drain 28 of the transistor 12 and a second source/drain 30 of the transistor 16 are connected. Similarly, second source drains 32 and 34 of the transistors 14 and 18 are coupled. A first section 36 is connected to a gate 38 of a P-channel and a gate 40 of an N-channel. A second section 42 is coupled to gates 44 and 46 of the P-channel and the N-channel, respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION INDUSTRIAL APPLICATION The present invention relates to the art of latching transistors in membranes and, more particularly, to latching cross-connected capacitors forming a latching circuit. Laminated CMO8)-
This is a WA in a transistor structure.

BACKGROUND OF THE INVENTION As SRAM (Stitched RAM) densities increase, it becomes increasingly necessary to find alternative ways to obtain smaller SRAM cells. The product of stacking a P-channel load on top of an N-channel bulk transistor @cM
Memories with 4 megapits or more have been created using O3 technology. As device geometries shrink, each cell within them becomes more susceptible to radiation-induced soft errors. As a result, capacitors must be installed at sensitive nodes to hold charge that can be affected by exposure to soft radiation. According to the existing stacked CMO8 technology, called merged CMO8 (MCMO8), stacked 1tCMOs latches are made of polycrystalline silicon formed on a bulk P-type substrate.
Composed of layers. As a result, the source and drain regions of the underlying N-channel transistor will not be self-aligned with the gate electrode of that transistor. Furthermore, the gate oxides of both N-channel and P-channel transistors are composed of the same oxide, which results in the same thickness for both transistors, which limits the functionality of these transistors. Become. Additionally, there is no way in the prior art to provide a multilayer capacitor within an SRAM structure.

Therefore, a laminated CM containing laminated capacitive elements therein to reduce sensitivity to soft radiation errors.
OS cells have come to be required. There is also a need for stacked cells with source/drain regions that are self-aligned with underlying N-channel transistors. Finally, there is a desire to be able to provide independent gate oxides for buried N-channel transistors and overlying P-channel transistors.

SUMMARY OF THE INVENTION In accordance with the present invention, a transistor cell is provided which essentially eliminates or reduces the disadvantages associated with conventional transistor cell geometries.

The transistor cell of the present invention generally includes a bulk transistor adjacent to a stack of transistors. The invention further includes a stacked capacitive element having first and second opposing electrode plates, the first electrode plate being electrically coupled to the gate of the bulk transistor, and the second electrode plate being electrically coupled to the gate of the bulk transistor. The plate is electrically connected to the gate of the stacked transistor.

In the preferred embodiment, the bulk transistors are N-channel transistors, while the 8-channel transistors are P-channel transistors.
It is a channel transistor. The transistor of the present invention is formed on a semiconductor substrate that includes various diffusion regions therein. One diffusion region in the semiconductor substrate can be used as the gate of a P-channel transistor, the electrode plate of a capacitive element, or even as one of the source/drain regions of an N-channel transistor.

The present invention can provide technical advantages for stacked structures, thereby minimizing cell dimensions and achieving greater packing density. Furthermore, the inclusion of a capacitor in the cell can provide the technical advantage of obtaining a cell with reduced sensitivity to soft radiation errors. Another technical advantage of the present invention is that the gate oxide thickness between the gate and channel of each transistor therein can be provided independently. The independent gate oxide thickness provides the technical advantage of increased gate oxide integrity and the ability to provide selective thresholds for each independent transistor. A further technical advantage is that selective capacitance values can be provided for the capacitive elements obtained by the present invention.

In order that the invention and its advantages may be more fully understood, reference will now be made in detail to specific examples with reference to the drawings.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the invention are best understood by reference to FIGS. 1-4c. In these drawings,
The same reference numbers are used for similar parts.

FIG. 1 shows a schematic diagram of a latch 10 that embodies the present invention. Latch 1o contains two MO8h transistor pairs in the membrane. These transistors include first and second P-channel transistors 12 and 14, and first and second N-channel transistors 16 and 18. The first source/drains 20 and 22 of each of the two P-channel transistors 12 and 14 are connected to the upper supply voltage, VCC. Similarly, the first sources/drains 24 and 26 of N-channel transistors 16 and 18
is tied to a lower reference voltage, which is usually earth. The second source of P-channel transistor 12/
Drain 28 and second source/drain 30 of N-channel transistor 16 are connected. Similarly, P-channel transistor 14 and N-channel transistor 18
The second source/drains 32 and 34 of the transistors are connected.

Digital information is stored in the first node 36 of latch 10. The first node 36 is further coupled to the gate 38 of the P-channel transistor and the gate 40 of the N-channel transistor 18, and to the second source/drains 28 and 30 of transistors 12 and 16, respectively. Second node 42 is coupled to gates 44 and 46 of P-channel transistor 12 and N-channel transistor 16, respectively. The second node 42 stores the inverse of the digital information stored in the first node 36. In addition, the second clause 4
2 are the second sources/drains 32 and 3 of the P-channel transistor 14 and the N-channel transistor 18, respectively.
It is connected to 4. Interconnection from P-channel transistor 12 to N-channel transistor 18 and from N-channel transistor 16 to P-channel transistor 14
A similar connection to is known in the art as a "cross-connect" of a transistor pair. first capacitor 4
8 is connected between the gate 44 of P-channel transistor 12 and first node 36 . Similarly, a second capacitor 50 connects the gate 38 of P-channel transistor 14 to the second capacitor 50.
The node 42 is connected between the node 42 and the node 42.

The operation of latch 10 may be best understood by following the passage of a signal through it. For example, assume VIN is digital 11'', P-channel transistor 14 is in a high impedance state, and N-channel transistor 18 is in a conductive state. The second node 42 is therefore connected to ground, thereby outputting digital 10J. In addition to representing an output signal, this digital rOJ is provided to gates 44 and 46 of P-channel transistor 12 and N-channel transistor 16, respectively. This digital rOJ makes P-channel transistor 12 conductive and N-channel transistor 1
6 is placed in a high impedance state. Therefore, the upper limit supply voltage VCC is passed to the first node 36 and returned to the gates 38 and 40 of P-channel transistor 14 and N-channel transistor 18, respectively. In this way, latch 10
It will be appreciated that through the transistor network therein forms a regenerative feedback structure. Therefore, the latch 10 operates to maintain its state in the -membrane as long as the upper limit voltage VCC is applied.

However, without the addition of capacitors 48 and 50, latch 10 is more sensitive to soft radiation signals. In other words, the soft radiation causes variations in the operation of the transistors within the latch 10, affecting signals therein that would otherwise be valid. Capacitors 48 and 50 thus act to store the signal in the circuit for any short period of time during which the radiation may have a destructive effect.

FIG. 2 schematically shows one of the cross-connected transistor pairs of FIG. More specifically, a second P-channel transistor 14 and a first N-channel transistor 16 are shown. Similarly, other common reference numerals from FIG. 1 are indicated.

The present invention provides a method and special structure for forming the structure of FIG. 2 in a stacked MO8I-transistor configuration. However, it should be understood that the first P-channel transistor 12 and the second N-channel transistor 18 can be similarly constructed in the same manner as described below. Once each pair of transistors has been formed, they are interconnected as required, as shown schematically in FIG.

FIG. 3 shows a prior art product 11c MO8 structure 52 that attempts to implement the structure of FIG. 2 without adding the capacitor 50 shown here.

0MO8 structure 52 includes a semiconductor substrate 54, typically made of P-type semiconductor material. First and second diffusion regions 56 and 58 are formed within semiconductor substrate 54, respectively. White regions 56 and 58 are typically made of N-type semiconductor material. More specifically, these regions are doped to the "N+" level, meaning a high dopant concentration on the order of 10"/α3. An insulating layer 60 is formed over the semiconductor substrate 54. A polycrystalline silicon layer 62 is then formed on the insulating layer 60. The polycrystalline silicon layer is masked and four different regions 64, 66 are formed therein.
．． 68.70. The first doped region 64 may be an N-type region with a similar high doping level as the diffusion regions 56-58. The second and third doped regions 66,68 are also at high doping concentration levels and P
It may be doped with a type dopant. A fourth doped region 70 is formed between the second and third doped regions 66 and 68. The fourth doped region 70 may be P-type or N-type, but is typically a P-type material and is
The threshold voltage between 6 and 68 is relatively low. Insulating sides 172, 74 are formed at the ends of polycrystalline silicon layer 62. A conductive strap 78 electrically connects the first doped region 64 and the second doped region 66.

The relationships between the various areas in FIG. 3 and the structure in FIG. 2 are as follows. The first and second diffusion regions 56 and 58 are
correspond to the first source/drain 24 and second source/drain 30 of the N-channel transistor 16, respectively. In this way, the first expanded wi region 56 is connected to ground according to FIG. First doped region 64 functions as gate 46 of first channel transistor 16 .

Second doped region 66 and third doped region 68 serve as second source/drain 32 and first source/drain 22 of second P-channel transistor 14 . Third doped region 68 is thus coupled to Vcc according to FIG. Additionally, a conductive strap 78 connects the gate 46 of N-channel transistor 16 to the second source/drain 32 of P-channel transistor 14. Fourth doped region 70 &; serves as a channel region of tP channel transistor 14 . Second diffusion region 58 serves as the gate of P-channel transistor 14. Therefore, the second diffusion region 58 is also the gate 38 of the P-channel transistor 14 and the second diffusion region 58 of the N-channel transistor 16.
It is also the source/drain of It should be noted that the fourth doped region 70 may be formed of an N-type semiconductor material, which would increase the threshold voltage between the first and second doped regions 66 and 68. There is.

The prior art 0MO8 structure 52 of FIG. 3 does not include a capacitor therein. As a result, this circuit is sensitive to soft radiation errors, as already mentioned. Additionally, due to the formation of polycrystalline silicon M62, both N-channel transistor 16 and P-channel transistor 14 will have the same thickness of gate insulator between the gate and channel of their respective transistors. It should also be noted that the first and second diffusion regions 56 and 58 are not self-aligned with the first doped region 64 as a gate conductor.

FIGS. 4a to 4c are cross-sectional views illustrating the manufacturing steps of a transistor cell that constitutes the latch 80 of the present invention. Note that although only one half of the latch is shown, the same remaining half is made complementary and connected as shown in FIG.

A latch 80 is formed on a semiconductor substrate 82.

An insulator [184] is formed on the semiconductor substrate 82. The insulating layer 84 may be a deposited film or a grown film, and has a thickness of about 120 angstroms. A gate conductor 86 is then formed on the insulating layer 84. The gate conductor need only be a conductive material, and in a preferred embodiment has a thickness of 2,000 to 3
It is composed of a doped polycrystalline silicon layer processed to have a thickness of about 0.000 angstroms and a length of about 0.6 μm. Further, the doping of the gate conductor 86 may be N-type semiconductor doping, and the dopant concentration of N+ (i.e., 102
1/α3). After the gate conductor is formed by masking and etching a conductive material,
Lightly doped regions 88 and 90 are formed in semiconductor substrate 82 in self-alignment with the sides of gate conductor 86 .

Typically, the lightly doped regions 1Iit 88 and 90 are doped with N-type dopants to the extent of 1018/α3.

Insulating side spacers 92 and 9 are provided at the ends of gate conductor 86.
4 is formed. After forming side spacers 92 and 94, first and second diffusion regions 96 and 98 are formed within semiconductor substrate 82. First and second diffusion regions 96 and 98 are doped from an N-type doping source to form N-channel transistor 16 of FIG. Typically these regions are doped to around 1021/α3. The combination of gate conductor 86 and diffusion regions 96,98 thus forms a bulk N-channel transistor within the semiconductor substrate.

FIG. 4b shows a cross-sectional view of the latch 80 of the present invention at a further stage in the manufacturing process. A second insulating layer 100 is formed over the entire structure. The insulating layer 100 has a thickness of 100 to 200
The oxide may be as thick as angstroms, or any desired thickness, and will affect the capacitance of the capacitor formed in this circuit, and will affect the transistor characteristics of the P-channel transistor. Note that prior to forming the second insulating layer 100, the portion of the insulation@84 over the second diffusion region 98 is removed. Removing this portion of insulating layer 84 increases the integrity of the P-channel transistor's gate oxide.

A semiconductor 11102 is formed on the second insulating layer 100. Typically, semiconductor layer 102 has a thickness of 700 to 140 nm.
It contains about 0 angstroms of polycrystalline silicon. Semiconductor layer 102 is masked with first,
second, third and fourth doped regions, 104 and 10 respectively;
6,108.110. The first doped region 104 is typically doped with an N-type semiconductor dopant to a level on the order of 1021/a13. The second and fourth doped regions 106 and 110 are also doped with P-type semiconductor dopants to a degree of 1021/α3.

The third doped region 108 is also doped with an N-type or P-type dopant. The choice of dopant source affects the threshold voltage between the second and fourth doped regions 106 and 110. In a preferred embodiment, third doped region 108 contains P-type dopants ranging from 5(10)16 to 1(10)17/
It is doped to about 1:1I3. Using a P-type dopant at this dopant level provides a lower threshold voltage between the second and fourth doped regions 106 and 110. An insulating mask 112 is formed over the third doped region 108 .

The structure shown in Figure 4b shows the parts of Figure 2, but the interconnections between them are not shown. The first and second diffusion regions 96 and 98 are lightly doped 1188
and 90, the source of N-channel transistor 16/
Functions as a drain. Gate conductor 86 functions as the gate of N-channel transistor 16. Second diffused region 98 and first doped region 104 function as electrode plates of capacitor 50 . Therefore, the combination of the first insulating layer 84 and the second insulating layer 100 therebetween functions as a dielectric that contributes to the capacitance value of the capacitor 50.

The second doped region 106 and the fourth doped region 110 are P
Source/drain 32 and 2 of channel transistor 14
They each function as 2. Additionally, third diffusion region 108 functions as a channel region of P-channel transistor 14 and second diffusion region 98 functions as gate 38. Thus, the second diffusion region [98 is the second source/drain 30 . One electrode plate of capacitor 50, P channel transistor 1
It functions as the gate 38 of 4.

FIG. 4C shows that in order to realize the circuit shown in FIG.
A cross-sectional view of the latch 80 with the final connection made therein is shown. Following the formation of mask region 112, latch 80 is subjected to a silicide process to form silicide regions 114,1
16.118 is formed. Mask region 112 prevents silicide from forming on third doped region 108 . The silicide regions 114, 116, 118 thereby provide a means for making electrical contact to components adjacent to the silicide. Additionally, silicide region 116 electrically couples first doped region 104 to second doped region 106 . This connection is associated with coupling capacitor 50 to second source/drain 32 of P-channel transistor 14. Following the formation of the silicide regions, a strap contact 120 is formed between the silicide regions 114 and 116. Strap contact 1
20 has the effect of electrically connecting capacitor 50 to the gate of N-channel transistor 16.

Voltage and signal connections are also made according to FIG.

For example, first diffusion region 96 would be connected to ground. Similarly, the fourth doped region 110 will be tied to Vcc. The first node 36 is connected to a second diffusion region 98 to make contact. Second verse 4
2 is connected to the silicide region 116, so that
Contact will be made. The bulk and stacked transistors may be of the SII type opposite to those described here. That is, the bulk transistor may be configured as a P-channel transistor, and the stacked transistor may include an N-channel transistor.

Thus, the present invention provides a method and structure that includes a stacked latch with a capacitor connected between the gates of associated cross-connected P and N channel transistors. The capacitor is formed in a stack to reduce errors due to exposure to soft radiation and to accommodate stacking techniques for the rest of the circuit.

The independent P and N channel transistors in the cell allow for different gate oxide thicknesses to be formed for each independent transistor. The independent gate insulator allows the capacitance associated with cross-connected capacitors to be adjusted.

Finally, the fact that the formation of the gate conductor of the N-channel transistor is independent of the formation of the P-channel transistor
Self-alignment between the gate and source/drain regions of the channel transistor is enabled.

Although the present invention has been described in detail, it should be understood that various changes, substitutions, and modifications can be made without departing from the scope of the invention as set forth in the claims.

Regarding the above description, the following sections are further disclosed.

(1) A transistor cell comprising: a bulk transistor having a gate; a stacked transistor having a gate adjacent to the bulk transistor; a stacked capacitive element having first and second opposing electrode plates; , a stacked capacitive element, wherein the first electrode plate is electrically connected to the gate of the bulk transistor, and the second electrode plate is electrically connected to the gate of the stacked transistor. transistor cell.

(2) The transistor cell of item 1, wherein the bulk transistor further comprises: a semiconductor substrate; first and second diffusion regions located in the semiconductor substrate and having a channel therebetween; an insulating layer between the gate and the semiconductor substrate.

(3) The transistor cell of paragraph 2, wherein the first and second diffusion regions further include lightly doped regions in the semiconductor substrate and are self-aligned to the gate. transistor cell.

(4) The transistor cell of item 1, wherein the stacked transistor further comprises: a semiconductor substrate having the gate of the stacked transistor therein; an insulating layer adjacent to the semiconductor substrate; a semiconductor layer adjacent to the insulating layer on a side opposite to the semiconductor substrate, the semiconductor layer having first and second regions of a first conductivity type and a channel region formed therebetween; transistor cell.

(5) The transistor cell according to item 4, wherein the channel region includes the first conductivity type.

(6) The transistor cell of item 1, wherein the capacitive element is: a semiconductor substrate; the first transistor cell of the capacitive element is located within the semiconductor substrate;
a diffusion region of a predetermined conductivity type acting as an electrode plate of the capacitive element; an insulating layer adjacent to the diffusion region; a semiconductor layer adjacent to the insulating layer on the opposite side of the semiconductor substrate; a semiconductor layer acting as the second electrode plate of a transistor cell.

(7) The transistor cell according to item 6, wherein the insulating layer includes a first insulating layer, and further adjacent to the first insulating layer, a second insulating layer is provided between the semiconductor substrate and the semiconductor layer. A transistor cell, including an insulating layer.

(8) The transistor cell according to item 6, wherein the semiconductor layer includes doped polycrystalline silicon.

(9) The transistor cell according to item 1, wherein the bulk transistor includes first and second source/drain regions, and further includes a diffusion region in the semiconductor substrate that operates as the gate of the stacked transistor, and the capacitor. a transistor cell comprising: said first electrode plate of a magnetic element; and said one of said sources/drains of said bulk transistor.

(10) A transistor cell, comprising: a semiconductor substrate; first and second diffusion regions of a first conductivity type in the semiconductor substrate; an insulating layer adjacent to the semiconductor substrate; adjacent to the insulating layer; a gate conductor for generating a current between the first and second diffusion regions; a semiconductor layer adjacent to the insulating layer; a second conductivity type within the semiconductor layer having a channel region therebetween; a first region and a second region of a transistor cell.

(11) The transistor cell according to item 10, wherein the insulating layer includes a first insulating layer, and further adjacent to the first insulating layer, a second insulating layer is provided between the semiconductor substrate and the semiconductor layer. A transistor cell, including an insulating layer.

(12) The transistor cell according to item 10, wherein the semiconductor substrate includes a P-type substrate.

(13) The transistor cell of item 10, wherein the first and second diffusion regions include N-type diffusion regions.

(14) The transistor cell of paragraph 10, wherein the first and second regions in the semiconductor substrate include doped P-type heads.

(15) The transistor cell of paragraph 14, wherein the channel region includes a doped P-type head region, and the channel region is connected to the first and second gIA in the semiconductor layer.
A transistor cell having a dopant concentration less than the region.

(16) The transistor cell according to item 10, wherein the semiconductor layer includes a third region facing the first diffusion region, and the third region is connected to the third region and the first diffusion region. A transistor cell that acts to create a capacitance between regions.

(17) A method for making a T-transistor cell, comprising: forming a bulk transistor having a gate; forming a stacked transistor having a gate adjacent to the bulk transistor; the first electrode plate is electrically connected to the gate of the bulk transistor, and the second electrode plate is electrically connected to the gate of the stacked transistor.
A method comprising: forming a laminated capacitive element.

(18) The method for making a transistor cell according to item 17, wherein the step of forming the bulk transistor further comprises forming a semiconductor substrate, and forming first and second diffusion regions having a channel therebetween. , forming an insulating layer between the gate of the bulk transistor and the semiconductor substrate.

(19) The method of making a transistor cell according to item 18, wherein the step of forming the first and second diffusion regions further comprises forming lightly doped regions in the semiconductor substrate.
A method comprising self-aligning with a gate.

(20) The method of making a transistor cell according to paragraph 17, wherein the step of forming the stacked transistor further comprises forming a semiconductor substrate having a gate of the stacked transistor formed therein, adjacent to the semiconductor substrate. forming an insulating layer opposite the semiconductor substrate and adjacent to the insulating layer; forming first and second regions of a first conductivity type in the semiconductor layer; forming a channel region between the first and second regions.

(21) A method of making a transistor cell according to paragraph 20, wherein the step of forming the channel region includes shaping a region of a first conductivity type.

(22) The method of making a transistor cell according to paragraph 17, wherein the step of forming the capacitive element comprises forming a semiconductor substrate, and a predetermined electrode plate serving as a first electrode plate of the capacitive element. forming a diffusion region of a conductive type in the semiconductor substrate; forming an insulating layer adjacent to the semiconductor substrate; forming a semiconductor layer that acts as a second electrode plate.

(23) A method for making a transistor cell according to item 22, wherein the step of forming the insulating layer includes forming a first insulating layer, and further includes:
A method comprising forming a second insulating layer between a semiconductor substrate and a semiconductor layer.

(24) A method of making a transistor cell according to paragraph 22, wherein the step of forming the semiconductor layer includes forming doped polycrystalline silicon.

(25) The method for producing a transistor cell according to item 17, wherein the step of forming the bulk transistor is the first step.
and forming a second source/drain region, further comprising a diffusion region in the semiconductor substrate serving as a gate of the stacked transistor, a first electrode plate of the capacitive element, and a second source/drain region of the bulk transistor. A method comprising forming one.

(26) A transistor cell produced by the method of item 17.

(27) A method of making a transistor cell, comprising: forming a semiconductor substrate; forming first and second diffusion regions of a first conductivity type in the semiconductor substrate; adjacent to the semiconductor substrate; forming an insulating layer; forming a gate conductor for generating a current between the first and second diffusion regions; forming a semiconductor layer adjacent to the insulating layer; A method comprising: forming first and second regions of a second conductivity type; forming a channel region between the first and second regions in a semiconductor layer.

(28) The method for producing a transistor cell according to item 27, wherein the step of forming the insulating layer includes forming a first insulating layer, and further includes a semiconductor substrate adjacent to the first insulating layer. and forming a second insulating layer between the semiconductor layer and the semiconductor layer.

(29) The method for making a transistor cell according to item 27, wherein the step of forming the semiconductor substrate includes forming a P-type substrate.

(30) A method for making a transistor cell according to item 27, wherein the step of forming the first and second diffusion regions includes forming an N-type region.

31. The method of making the transistor cell of clause 27, wherein the step of forming first and second regions in the semiconductor layer includes forming a P-type head region.

(32) A method for making a transistor cell according to item 31, wherein the step of forming the channel region includes forming a doped P wall region, and the formed channel region is a first layer in the semiconductor layer. and a lower dopant concentration than the second region.

(33) A method for producing a transistor cell according to item 27, further comprising forming a third region in the semiconductor layer opposite to the first diffusion region in the semiconductor substrate, wherein the region is operative to realize a capacitance between the third region and the first diffusion region.

(34) A transistor cell produced by the method of item 27.

(35) A latch 80 using stacked 0MO8 technology is obtained. Latch 80 is typically formed to a semiconductor substrate 82. An N-channel transistor with first and second diffusion regions 96,98 and a gate conductor 86 is obtained. A P-type transistor is obtained with first and second doped regions 106, 110 and a channel region 108 between them. The second diffusion region [98 of the N-channel transistor also serves as the gate conductor of the P-channel transistor. An insulating layer 84 or insulation 1184,1 between the first doped region 104 and the second diffusion region 98
By having 00, a capacitive element is present.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of a latch memory cell containing cross-connected capacitors therein. FIG. 2 is a schematic diagram of the cross-connected P and N channel transistor pair of FIG. 1, with a capacitor connected between the gates of both transistors. FIG. 3 is a cross-sectional view of a prior art stacked 0MO8 structure. FIG. 4a is a cross-sectional view illustrating an initial processing stage for a preferred laminate structure of the present invention. Figure 4b shows the product 1lill! of the invention! 1 is a cross-sectional view at an intermediate stage during the fabrication of the structure. FIG. 4C shows the interconnected, cross-connected CMO of the present invention.
FIG. 3 is a cross-sectional view of an S transistor. (Reference number) 10...Latch 12.14...P channel transistor 16.18.
・・N-channel transistor 20.22.24.26・
...Source/Drain 28.30.32.34...Source/Drain 36...Node 38.40...Gate 42...Node 44.46...Gate 48.50...・”Capacitor 52...0MO3 54...Semiconductor substrate 56.68...Diffusion region 60...Insulating layer 62...Polycrystalline silicon layer 64.66.68.70...Doped region 72. 74・
... Insulating sidewall 78 ... Conductive strap 80 ... Latch 82 ... Semiconductor substrate 84 ... Insulating layer 86 ... Gate conductor 88.90 ... Doped region 92.94 ... Sidewall spacer 96.98... Diffusion region 100... Insulating layer 102... Semiconductor layer 104.106, 108.110... Doped region 11
2... Mask region 114, 116, 118... Silicide region 120.
・・Strap contact

Claims (2)

[Claims] (1) A transistor cell comprising: a bulk transistor having a gate; a stacked transistor having a gate adjacent to the bulk transistor; a stacked capacitive element having first and second opposing electrode plates; , a stacked capacitive element, wherein the first electrode plate is electrically connected to the gate of the bulk transistor, and the second electrode plate is electrically connected to the gate of the stacked transistor. transistor cell. (2) A method for creating a transistor cell, comprising: forming a bulk transistor having a gate; forming a stacked transistor having a gate adjacent to the bulk transistor; and first and second opposing electrodes. forming a laminated capacitive element having plates, the first electrode plate electrically connected to the gate of the bulk transistor, and the second electrode plate electrically connected to the gate of the laminated transistor. , including a method.