JPS62274773A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To realize a dynamic random access memory cell, small in cell area and excellent in memory-holding capability and long-term reliability, by a method wherein a WRITE transistor of a three-dimensional laminated structure is equipped with a type of conductivity different from that of two lower-layer transistors. CONSTITUTION:In a cell of this design, the type of conductivity of a WRITE- dedicated transistor T2 of a three-dimensional laminated structure is different from that of two lower-layer transistors T1 and T3. At the same time, in this way, a laminated CMOS may be built to constitute a peripheral circuit, which eliminates need for any masking process to create difference between an N- channel element and p-channel element. When, specifically, the transistor T2 is of the P-channel type and Tl and T3 of the M-channel type, the lower-layer transistor T1 and T3 will be further microstructuralized, and the WRITE- dedicated transistor T2 will be improved in lts leak or breakdown strength against kink phenomena.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor memory device using a MoS transistor having a three-dimensional structure, and particularly relates to a dynamic random type semiconductor memory device suitable for high integration. This invention relates to the structure of access memory cells.

Furthermore, the present invention relates to an interlayer contact structure suitable for improving the degree of integration and reliability.

[Conventional technology]

Conventionally, a three-transistor memory cell is known as one of the dynamic random access memory cells using MOS transistors. Figure 2 (,) shows the equivalent circuit configuration, which consists of three transistors Tl.
, T2. T3 constitutes one bit. In this cell, memory information is passed through transistor T2 to data 412.
1 and gate capacitance Ct of transistor T1
is stored in the form of electric charge. Furthermore, since T1 is turned on/off depending on the charge stored in Ct, when the readout transistor T3 is turned on, the data line 21 is connected to the reference potential line 24.
The information stored in Cz can be read out depending on whether the vIL flow flows or not.

This cell has an excellent feature that a large readout signal can be obtained from a small amount of accumulated charge because the transistor T1 has an amplification function in addition to an information storage function. However, on the other hand, the disadvantage is that the number of elements per bit is large and the cell area is larger than that of other technologies (for example, 1 transistor/1 capacitor type memory cell). , a three-dimensional structure in which a write transistor T1 is stacked on two other transistors with an insulating film interposed therebetween was disclosed in Japanese Patent Laid-Open No. 6
0-130160. By adopting a three-dimensional structure, not only can the cell surface area be significantly reduced, but also the resistance to α-ray soft errors can be improved.

Also, consider a semiconductor device having a three-dimensional structure.

The structure used to realize ohmic contact between two different semiconductor layers greatly affects the degree of integration and reliability.

Conventionally, as an interlayer contact structure, a structure in which a through hole is provided in a 1M insulating film as described in the above-mentioned publication has been widely used. FIG. 2(b) shows an example in which a through hole is used to make contact from a semiconductor thin film on an insulating film to an underlying semiconductor region and a gate electrode. That is, the impurity region 12 in the semiconductor substrate and the gate electrode 14 are connected to each other through the through hole formed in the first interlayer insulating film 15.
The impurity region 17 in the semiconductor substrate provided thereon is brought into contact with the semiconductor substrate to realize a desired ohmic contact. In addition, in FIG. 2(b), 11 is a semiconductor substrate, 1
2, 13. 14 are impurity regions constituting the MoS transistor in the substrate, gate oxide film, gate electrode, 15 is an interlayer insulating film, ] 6 is a semiconductor thin film, 17, 18. 19 are M in the thin film.
These are an impurity region, a gate oxide film, and a gate electrode that constitute an OS transistor.

[Problem that the invention seeks to solve]

However, in the prior art described in h., the three-dimensionally accumulated write transistor T2 has the same conductivity type (N-channel or P channel), there were the following problems.

The first problem is the lower layer transistor Tl.

The requirement for conductivity type is different between T3 and the transistor T2 stacked thereon. The conductivity type of the stacked transistor T2 is as follows: (1) Leakage current due to back channel or side channel can be suppressed, and (2) kink phenomenon due to channel portion floating is unlikely to occur.

It is desirable to use the P channel for two reasons. On the other hand, the lower layer transistors Tl and T3 are affected by the thermal process during the manufacturing of multilayer transistors, so the source and drain junctions are N-channel (
It is advantageous to select arsenic (which has a small diffusion coefficient) as an impurity for forming a junction in order to advance miniaturization. Conversely, three transistors Tl, T2 . T
If the conductivity types of the three transistors are the same, no matter which conductivity type is selected, N-channel or P-channel, problems that cannot be ignored in practical terms will arise when miniaturization is advanced to the submicron level.

The second problem is that the element stacking technology adopted in the memory cell section cannot be fully utilized in the peripheral circuit section. Creating CMO8 as a pair of N-channel and P-channel, respectively, has the following two points: (1) There is no need for a mask process to separate the N-channel and P-channel, and (2) There is no need to worry about latch-up. , is an extremely rational and necessary choice. However, if the conductivity types of the stacked transistor T2 and the lower layer transistors Tl and T3 are made the same in the memory cell portion, the above advantage (1) is lost. This is a major disadvantage when using element stacking technology in the peripheral circuit section.

An object of the present invention is to provide a three-transistor type memory cell structure which can solve the above two problems and has a three-dimensional structure suitable for ultra-high integration.

Further, the above-mentioned conventional technology has a problem that in the following two cases, it is the national fortune to realize a highly reliable ohmic contact.

The first case is a case where the conductivity types of the two semiconductor layers with which ohmic contact is to be made are different from each other. In this case, the contact between the two semiconductor layers exhibits rectifying properties due to a pn junction. Using secondary element stacking technology, CMO8 type O8
This phenomenon poses a problem when constructing a converter.

In the second case, a semiconductor thin film provided on an insulating film (Fig. 2 (
This is the case where 16.17) of b) is melted and resolidified.

The crystallinity of the semiconductor thin film is improved by the melting/resolidification process, but at the same time, the semiconductor layer in contact with the thin film is also melted, resulting in a decrease in reliability. Taking the case shown in FIG. 2(b) as an example, there is an increase in junction leakage due to melting of the impurity region 12, an impurity rising to the semiconductor thin film, and a gate oxide film due to melting of the gate electrode 14. 13 becomes a serious problem.

A second object of the present invention is to provide an interlayer contact structure that solves the above problems, does not reduce the degree of integration compared to the prior art, and has excellent reliability.

[Means for solving problems]

The above purpose is to determine the conductivity type of the three-dimensionally stacked write transistor T2, the two lower transistors TI,
This is achieved by making the conductivity types of 1'3 different from each other.

FIG. 1(a) shows the basic structure of a transistor type memory cell according to the present invention. In the figure, 1 is a first conductive type semiconductor substrate, 5 is an element isolation insulating film, 15.16 is an interlayer insulating film, and 17.18 is an electrode wiring. On the main surface of the substrate 1, a gate electrode 8. Insulating film 6. A readout transistor T3 consisting of regions 2 and 3 of the second conductivity type also has a gate electrode o2.
Transistors T]- each having an amplification function and comprising an insulating film 7 and second conductivity type regions 3 and 4 are arranged.

Transistors T1 and T3 share a second conductivity type region 3. Further, a second conductivity type semiconductor thin film 9 is formed on the transistors TI and T3, and gate electrodes 14. Absolute MP31
3. A write transistor T2 consisting of a region 10.11 of a first conductivity type is provided. Write transistor T
2 connects the gate mt+O and the electrode wiring L7.

The electrode wiring 1-7 is further in contact with the second conductivity type region 2, and serves as data for the memory cell. The stored information is written from the data line 7 to the gate capacitor of the transistor T1 via the write transistor T2. At this time, the gate electrode 14 acts as a write word line 6 The written information activates the gate electrode 8. When the readout transistor T3 is made conductive, the data line 17 is connected to the electrode wiring 18.
This is determined by the presence or absence (or magnitude) of a current flowing through it. The gate electrode 8 functions as a read word line, and the second conductivity type region 4 and electrode wiring 18 function as a reference potential line.

In the memory retention state, both transistors T2 and T3 are kept cut off.

FIG. 3 shows the terminal voltages (write word line, read word line, and data line potentials) necessary for the operation of a three-transistor memory cell according to the present invention.
It is assumed that all of the transistors T1 to T3 are of the enhanced quadruple transistor type. (a) is the transistor T
l, T3 is N channel and T2 is P channel, (b
) is the opposite case. In both (a) and (b), the difference from the prior art three-transistor memory cell is that the voltages at which the write word line and read word line are activated are opposite to each other.

FIGS. 1(b) and 1(c) show a three-transistor type memory cell according to the present invention in which a device has been devised to increase the storage gate capacitance value that transmits information.

FIG. 1(b) is characterized in that a trench 19 is dug on the main surface of the substrate 1 to separate the second conductivity type regions 3 and 4, and the side and bottom surfaces of the trench are used as the channel of the transistor T1. Since the gate electrode 0 of T1 is buried in the trench via the insulating film 7, the effective gate area is increased and the storage capacity is increased.

On the other hand, in FIG. 1(c), through the insulating film 20.

By overlapping the gate electrode O of the transistor T1 and the electrode wiring 18, which is a reference potential line, ? It is possible to increase the I product capacity value.

FIG. 1(d) shows a three-transistor type memory cell according to the present invention in which a device has been devised to reduce the parasitic capacitance between the gate side 14 of the write transistor T2 and the first conductivity type region 1. .

Here, by providing another gate electrode 14-1 (sub-gate electrode) whose potential is fixed in an active state between the gate electrode 14 and the first conductivity type region 1, the change in the potential of the gate electrode 14 is suppressed. The influence on the 1 conductivity type region 11 is almost completely shielded, and the parasitic capacitance between the two is significantly reduced.

Further, the second object is achieved by an interlayer contact structure in which a conductor is provided on the first semiconductor layer, passing through the interlayer insulating film and the second semiconductor layer.

FIG. 1 shows its basic structure. 1st
The second semiconductor layers 1 and 3 are electrically connected to each other via a conductor 4 that can make ohmic contact with them. This structure is realized by piercing the interlayer insulating film 2 from the surface of the second semiconductor layer 3, making a hole until the first semiconductor layer 1 is exposed, and burying the conductor 4 in the hole.

[Effect]

In a three-transistor memory cell, if the conductivity type of the three-dimensionally stacked write transistor T2 is different from that of the two lower layer transistors TI and T3,
It becomes possible to form a stacked OMO3 as a peripheral circuit at the same time as forming a memory cell. At this time, N
No mask process is required to separate channel elements and P-channel elements. This allows us to utilize the element stacking technology introduced to realize ultra-highly integrated memory cells.
It can also be used in peripheral circuits without increasing the number of processes.

In addition, the conductivity type of the transistor is particularly limited, and T2 is set to P
If the channel types, Tl and T3, are N-channel types, it becomes possible to miniaturize the lower layer transistors Tl and T3, reduce the leakage current of the write transistor T2, and improve the withstand voltage against the king phenomenon at the same time. This makes it possible to realize a three-transistor memory cell with a small cell area and excellent memory protection characteristics and reliability.

Furthermore, the information charge storage nodes O and 11 and the reference potential (
increasing the capacitance C9 between the potentials of regions 5 and 18);
In addition, by reducing the parasitic capacitance Cp between the write word line 14 and the write word line 14, it is possible to reduce the noise voltage that causes malfunctions (when the voltage amplitude on the write word line 14 is Vcc, the noise voltage is accumulated due to capacitive coupling). The noise voltage amplitude VN induced at the node is given by Cg + Cp). Lowering VN allows for increased operating margin.

By using the interlayer contact structure shown in FIG. 1(e), the above two problems can be solved without reducing the degree of integration.

First, even if the conductivity types of the second and second semiconductor layers are different from each other, undesirable rectification characteristics can be prevented by using a high melting point metal material such as tahengsten or molybdenum, or a silicide material thereof, as the conductor 4 buried in the hole. ohmic contact can be realized.

Furthermore, even if it is necessary to melt and re-solidify the second semiconductor layer provided on top, undesirable impurities can be re-solidified by performing a series of interlayer contact formation steps up to burying the conductor 4 after melting and re-assimilation. This makes it possible to avoid deterioration in reliability due to distribution, junctions, gate oxide films, etc. However, in this case, it is necessary to set the thickness of the interlayer insulating film 3 to such a thickness that melting of the upper layer does not affect the lower layer.

In addition, using conventional planar aluminum electrode wiring,
Even if an ohmic contact is made between the first and second semiconductor layers, the same effect as in the case shown in Fig. 1 can be obtained, but the major problem with this method is that the area becomes large (Fig. In contrast, the interlayer contact structure according to the present invention does not increase the area compared to the conventional structure using through holes, and it is possible to maintain the degree of integration (Fig. 3). Figure (d)).

〔Example〕

Hereinafter, embodiments of the present invention will be explained with reference to FIGS. 4 to 9. In FIG. ) side silicon wafer. After forming an element isolation region of a thick oxide film 42 on a substrate 41 by selective oxidation, an active region gate oxide film 43 was formed. The oxide film thickness of the element isolation region was 600 nm, and the gate oxide film thickness was 251 m.

Through the gate oxide film 43, the readout and amplification transistors T3. In order to set the threshold voltage of Tl, after performing ion implantation (Boron, In), a polycrystalline silicon film was deposited by chemical vapor deposition, and this was patterned to form two gate electrodes 441 and 442. . B ion is 60keV
Acceleration energy of Te, 1, OX 10”-1n
os/cx# TaLT implant 1uE. With this, the final threshold voltage is about 0.9v (N-channel transistor)
was gotten. Also, the thickness of the polycrystalline silicon film is 310n
m, and the gate length after patterning was 1.5 μm.

Next, arsenic (As) ions are implanted using the gates 441 and 442 as masks to form transistors Tl and T.
n0 type impurity region 451 which becomes the source and drain of No. 3,
452,453 were formed.

As ion is 5×10 with acceleration energy of 80keV
After that, a non-doped silicon dioxide 5iOz film 46 was deposited by chemical vapor deposition under high temperature and low pressure conditions to form an interlayer insulating film, and then chemical vapor deposition was performed again. A polycrystalline silicon film was deposited using a method.The thickness of the non-doped 5iOz film 46 was 0.7 μm.The thickness of the polycrystalline silicon film was 0.3 μm.Laser light was applied to this polycrystalline silicon film. After the entire film was made into a single crystal by irradiation with , it was patterned to form an island-shaped silicon single crystal film 47 [FIG. 4(a)].

After forming a gate oxide film 48 on the surface of the single crystal silicon film 47 by thermal oxidation, in order to set the conductivity type and threshold voltage of the write transistor T2 to be formed on the silicon film 47,
Phosphorus (P) ion implantation was performed. The gate oxide film is 25
nm, p ion implantation was carried out at an acceleration energy of 100 keV. Only OX 1012Lnos/- was performed. This finally resulted in a threshold voltage (P-channel transistor) of approximately -0.9V.

Next, a polycrystalline silicon film is deposited by chemical vapor deposition and patterned to form a gate electrode 49. Using this as a mask, boron (S) ions are implanted to form the source of transistor T2.

P medium impurity regions 501 and 502 which will become drains are formed. The thickness of the polycrystalline silicon film is 310 nm.

The gate length after patterning is 1.5 μm, and the B ion implantation is 5×10”in with an acceleration energy of 60 keV.
I only went to os/-.

After performing high-temperature heat treatment in a nitrogen atmosphere to electrically activate the impurity elements introduced by ion implantation,
Electrical connection is made between the non-layered element formed on the semiconductor substrate 41 and the silicon single crystal film 47 laminated thereon. That is, the oxide films 48 and 46 on the n+ type impurity region 45i
．． 43, and + type impurity region 501. and gate electrode 4
After drilling a hole in the oxide film 48, 46 on the oxide film 42 and the p-type impurity region 502, selective metal deposition is performed on the silicon exposed at the bottom and side surfaces of the hole to form a buried metal pillar 51. Here, a tungsten metal pillar was formed using a method of reducing WFs with H2, and good ohmic contact was achieved with both the n+ and P-type impurity regions. Note that the high-temperature heat treatment in a nitrogen atmosphere was performed at 950°C for 3
The test was carried out for 0 minutes. As a result, the p-type impurity region 5
01°502 junction is between silicon single crystal film 47 and oxide film 4
6, and the junction area effective for junction leakage in the P-doped region 502 could be significantly reduced.

Finally, the interlayer insulating film 52 made of phosphosilicate glass PSG, the contact ball, and the aluminum tcit? i wiring 52.
54 was formed to complete the manufacturing process [Figure 4 (
b)].

In FIG. 4(b), the amplification transistor (N-channel type) Tl has a gate electrode 442. Gate oxide film 43, n
Ten-type impurity regions 452, 453° P-type silicon substrate 41
It is made up of.

In addition, the read transistor (N-channel type) T3 is
Gate electrode 441. Gate oxide film 43°n medium impurity regions 451, 452. By using the p-type silicon substrate 41, the write transistor (P-channel type) T2 includes a gate electrode 49, a gate oxide film 48, and p-type impurity regions 501, 5.
02, connection of the 63 transistors each formed by the n-type wheel crystal silicon substrate 7 is realized by the n÷-type impurity region 452 and the buried tungsten 51. The information '4 product node of the memory cell is formed by regions 442, 502.51, and gate electrodes 441 and 49 act as a read word line and a write word line, respectively.

Aluminum electrode wirings 53 and 54 are a data line and a reference potential line of a memory cell, respectively.

FIG. 5 shows an equivalent circuit diagram of the memory cell according to this embodiment. As described above, the amplification transistor T1 and the read transistor T3 formed on the substrate are of N-channel type, and the write transistor T2 stacked thereon is of P-channel type.

FIG. 6 shows the memory retention state (gate-source voltage Vos
OV) shows the leakage current characteristics of the write transistor T2. In this example, by using a P-channel type element, there is no side channel or back channel influence, and leakage current can be reduced by I.
It was possible to suppress the channel width to about 10-14 A (channel width is 3 μm).

This value is 2
It is nearly an order of magnitude smaller and has a positive effect on memory retention properties. Further, in the P-channel type device, the leakage current does not increase even when the source-drain voltage is higher than that in the N-channel type device. this is.

The P-channel type device has the effect that drain avalanche is less likely to occur.6 When the memory cell whose manufacturing process is shown in this example was integrated into an IK bit array and an operation test was performed, it was found that the power supply Voltage 2.5
v to 7. It was confirmed that it operates stably within the OV range.

In this example, in the manufacturing process shown in Example (1),
This device is characterized in that the threshold voltages of two transistors (gate electrodes 441 and 442) formed on a semiconductor substrate 41 are independently controlled.

That is, boron (B) ion implantation for threshold voltage setting was performed separately at the lower part of the gate electrode 541 and the lower part of the gate electrode 542.

By setting the threshold voltage of the amplification transistor T2 (gate electrode 542) to approximately 2.5V, the storage node (44
Low level (“0”) written to
This makes it possible to achieve stable memory operation even when the write state (write state) is affected by capacitive coupling noise.

χ1 is the rule U. In this embodiment, the amplification transistor T1 serving as the storage node
Fig. 7(a) shows that the gate electrode is embedded in a groove provided on the main surface of the semiconductor substrate.
Specific resistance: 10Ω, p-type (100) silicon wafer 7
A thick oxide film 72 for element isolation and a gate oxide film 73 are grown on the main surface of the polycrystalline silicon gate electrode 74.
After forming n-type impurity regions 75 and 76 using as a mask,
Groove 78 dividing n-shaped impurity region 76 from the main surface side
This figure shows the state in which the oxide film and the silicon substrate are etched. The junction depth of the n-type impurity regions 75 and 76 was 0.2 μm, and the depth of the trench 77 was 2 μm.

Subsequently, a gate oxide film 79 was grown on the side and bottom surfaces of the silicon groove 78 using a thermal oxidation method, and then a polycrystalline silicon film was deposited using a chemical vapor deposition method. This polycrystalline silicon film is buried in the trench and serves as a storage node of the memory cell according to the present invention. That is, an amplification transistor T is formed by using the buried polycrystalline silicon film as a gate electrode, the side and bottom surfaces of the trench 78 as a channel region, and the n-shaped impurity region 76 divided by the trench as a source/drain.
1 is formed.

After that, the same procedure as in Example (1) is carried out, and FIG.
The manufacturing process step was completed in the state shown in ).

In this embodiment, the side and bottom surfaces of the trench 78 contribute to the storage gate capacitance Cg, so the value of C5 can be increased without increasing the cell area. As a result, storage node 84
It was possible to reduce the capacitively coupled noise voltage induced by this method.

This embodiment is characterized in that the aluminum 11-electrode horizontal wiring, which is a reference potential line, overlaps the storage node with a thin insulating film interposed therebetween.

FIG. 8 shows a structure in which the above features are added to the embodiment (3). The manufacturing process steps are exactly the same as in Example (3) until the phosphosilicate glass 86 is formed by chemical vapor deposition.

Thereafter, using a combination of photolithography and dry etching techniques, the phosphosilicate glass 86 and gate oxide film 81 are removed only in the area shown in FIG. It was re-formed in H. The thickness of the thin oxide film 89 was 25 nm. Finally, contact holes and aluminum 11 wires 87 and 88 were formed as shown in the figure to complete the manufacturing process.

In this embodiment, since the overlap region between the storage node 84 and the aluminum electrode wiring 88 with the thin oxide film 89 in between contributes to the storage gate capacitance Cg, it is possible to further increase the value of C without increasing the cell area. Can be done. As a result, the capacitively coupled noise voltage induced in the JM node 84 could be reduced more effectively.

This embodiment is characterized in that a sub-gate electrode connected to a reference potential is provided on the side surface of the gate electrode of the write transistor.

FIG. 9 is a sectional view showing the structure. The manufacturing process steps are exactly the same as in Example (1) until the polycrystalline silicon gate electrode 49 is formed. Thereafter, the surface of the gate electrode 49 is covered with a thin thermal oxide film 59, and a polycrystalline silicon film is again formed by chemical vapor deposition. A wall-shaped sub-gate electrode 60 was formed (FIG. 9(a)). Subsequently, boron (B) ions are implanted using the gate electrode 49 and the sub-gate electrode 60 as masks to form a P-type impurity region 501, and then a ninth Figure (b
The final cross-sectional structure shown in ) was achieved.

In this embodiment, by fixing the sub-gate electrode 60 at a potential of base 4, the parasitic capacitance between the gate electrode 49 (write word line) and the p-type impurity region 501 (storage node) can be significantly reduced. reactor. As a result, the capacitively coupled noise voltage induced from the enlightenment word line to the storage node was reduced, and the operating margin was significantly improved.

Another embodiment of the present invention will be described below with reference to FIGS. 10 and 11.

This embodiment is an example in which the interlayer contact structure of the present invention is applied to a CMO5 type O5 converter using a three-dimensional element stacking technique.

In FIG. 10, the symbol 131 indicates a semiconductor substrate, which is a p-type (100) silicon wafer with a specific resistance of 10Ω. A thick oxide film 1 is formed on this substrate 131 by selective oxidation.
After forming 32 element isolation regions, a gate oxide film 33 was formed in the active region. The oxide film thickness in the element isolation region is 60
The gate oxide film thickness was 25 nm.

In order to control the threshold voltage of the n-channel MOS transistor formed in the semiconductor substrate 131, the gate oxide film 133 is
After boron (F) ion implantation was performed through the ion implantation, a polycrystalline silicon film was deposited by chemical vapor deposition, and this was patterned to form the gate electrode 134. , 0 x 10”
1nos/cn? I just typed it in. This results in approximately 0.
A threshold voltage of 7V was obtained. The thickness of the polycrystalline silicon film is 310 nm, and the gate length after patterning is 1
．． It was 4 μm.

Next, arsenic (As) is applied using the gate electrode 134 as a mask.
Ion implantation is performed to form n+ type impurity regions L35. which will become the source and drain of the MOS transistor. L36 was formed. As ions have an acceleration energy of 80 keV,
OX 1. I typed only O”1nos/ci.

After depositing a non-doped silicon dioxide 5iOz film 137 on the wafer surface using a chemical vapor deposition method under low pressure and high temperature conditions, a polycrystalline silicon film, which will become the second active layer, is again deposited using this as an interlayer insulating film. It was formed by chemical vapor deposition. The thickness of the non-doped 5iOz film was 700 nm. The thickness of the polycrystalline silicon film was 400 nm [first
Figure 0 (,)).

This polycrystalline silicon film was irradiated with laser light to sufficiently grow its crystal grain size, and then patterned to form island-shaped silicon regions.

After forming a gate oxide film 140 using a thermal oxidation method.

p-channel MOS formed in the island-shaped silicon region
Phosphorus (T') ion implantation was performed to control the threshold voltage of the transistor. The gate oxide film thickness is 25 nm, and the P ion is 5 OX with an acceleration energy of 100 keV.
10” I typed only 1nos/ci. As a result,
A threshold voltage of about -0.7V was obtained.

Next, a polycrystalline silicon film is deposited by chemical vapor deposition and patterned to form a gate electrode 141. Using this as a mask, boron (Fl) ions are implanted to form the source and drain. p-type impurity region 142.
43 was formed. The thickness of the polycrystalline silicon film is 3.10n.
m, gate length after pattern Jung is 4 μm, R ion is 5 μm with acceleration energy of 40 keV, OX I
Q “I typed only “i, nos/-”.

After performing high-temperature heat treatment in a nitrogen atmosphere and completely activating the impurity elements introduced by ion implantation,
A gate oxide film 133, 1 is formed on one side of the ten-type impurity region 135.
40, an opening was provided that vertically penetrated the non-doped 5iOz film 137 and the p+ type impurity region 142. The opening was formed using dry etching technology to obtain a finished opening size of approximately 1.5 μm. Tungsten metal was selectively grown on the silicon exposed at the bottom and side surfaces of the opening by chemical vapor deposition, and the opening was filled with tungsten as shown by symbol 44. Selective growth of tungsten was achieved by combining a method of reducing WFe gas with silicon and a method of reducing it with hydrogen [Figure 10(b)].

Finally, an interlayer insulating film made of phosphosilicate glass 45, contact holes, and aluminum electrode wiring 146° 147 were formed to complete the manufacturing process [FIG. 10 (0)].

In FIG. 10(C), tungsten is embedded in the opening of the n0 type impurity region 135.

n-type impurity region 135 on the bottom surface. It was confirmed that good ohmic contact characteristics were exhibited with any of the P-type impurity regions 136 on the side surfaces. The contact resistance value was 1 to 2 x 10-ZΩ·- for both n+/P+. As a result, it was possible to realize a CMO3-type O3 inverter with a minimum area and no worry of latch-up and having good transfer characteristics.

In addition, the code 147 is the power line (V
ccL 136 is ground line (Vss), 134°1
41 corresponds to an input terminal, and 146 corresponds to an output terminal.

1) Description This example is an example in which the interlayer contact structure of the present invention is applied to a three-transistor type MOS dynamic memory cell that enables high integration using a three-dimensional element stacking technique.

In FIG. 11, the symbol 51 indicates a semiconductor substrate, which is a p-type (100) silicon wafer with a specific resistance of 10 Ω·I. A thick oxide film 52 is formed on this substrate 151 by selective oxidation.
After forming element isolation regions, a gate oxide film 153 was formed in the active region.

The oxide film thickness of the element isolation region was 600 nm, and the gate oxide film thickness was 25 nm.

Semiconductor substrate] In order to control the threshold voltage V th of the n-channel MOS transistor formed in the semiconductor substrate 51, boron (R) ions are implanted through the gate oxide film 153, and then a polycrystalline silicon film is deposited by chemical vapor deposition. This was deposited and patterned to form gate m and poles 154 and 155. B ions have an acceleration energy of 60 keV.
OX 10" 1nos/d was implanted. As a result, a threshold voltage of about 0.9V was obtained.The thickness of the polycrystalline silicon film was 31.0 nm, and the gate length after patterning was 2. It was .07Lm.

Next, using the gate electrodes 54 and 55 as a mask, arsenic (A
S) Perform ion implantation to form n10 impurity regions 1.56, 157.1, which will become the source and drain of the MOS transistor.
58 was formed. 5. As ions are accelerated at 80 keV acceleration energy. I drove only OX 10”1nos/d.

After depositing a non-doped silicon dioxide 81 oz film 59 on the wafer surface by chemical vapor deposition under low pressure and high temperature conditions, the polycrystalline silicon layer, which will become the second active layer, is again chemically deposited using this as an interlayer insulating film. It was formed using a vapor deposition method. The thickness of the non-doped 5iOz film was 700 nm. Further, the film thickness of the polycrystalline silicon film was 300 nm.

This polycrystalline silicon film was irradiated with laser light to sufficiently grow its crystal grain size by melting and resolidifying, and then patterned to form island-shaped silicon regions 160. After forming a gate oxide film 161 by thermal oxidation, boron (B) ions were implanted in order to control the threshold voltage of the p-channel MoS transistor formed in the island-shaped silicon region. The gate oxide film thickness is 25 nm, and B ions are accelerated at an acceleration energy of 160 KaV. Ox 1011
4nc) Only B/al was inserted. This results in approximately 0.9
A threshold voltage of V was obtained. - Next, a polycrystalline silicon film is deposited by chemical vapor deposition, and this is patterned to form the gate electrode 162. Using this as a mask, arsenic (As) ions are implanted to form the source and drain. n◆ impurity region 163,
164 was formed.

The film thickness of the polycrystalline silicon film is 310 nm, the gate length after patterning is 2.0 μm, and the As ion is accelerated at 5, OX 10 with an acceleration energy of 80 keV.
/d [Figure 11(a)].

After performing high-temperature heat treatment in a nitrogen atmosphere and completely activating the impurity elements introduced by ion implantation,
A gate oxide film 153.16 is formed on the ten-type impurity region 156.
．． 1, an opening that vertically penetrates the n-type impurity region 163 and the non-doped 5iOz film 159, and also the gate electrode 155.
On top of the gate oxide film 161. n-type impurity region 164
．． Openings were respectively provided that perpendicularly penetrate the non-doped 5iOz film 137. Dry etching technology was used to form the openings.

On the silicon exposed on the bottom and side surfaces of this opening, n0-type polycrystalline silicon was selectively grown by chemical vapor deposition and filled into the opening as shown by symbols 165 and 166. Figure (b)].

Finally, an interlayer insulating film made of phosphosilicate glass 167.

A contact hole and an aluminum electrode wiring 168 were formed to complete the manufacturing process [FIG. 11(C)].

In this case, when the polycrystalline silicon film deposited on the interlayer insulating film 159 is melted and the crystal grain size is grown,
Since the interlayer is not in direct contact with the elements formed in the underlying silicon substrate, the melting process could be optimized without affecting the underlying element characteristics.

Figure 11 shows the three-transistor qMo realized in this example.
s shows an equivalent circuit diagram of a dynamic memory cell. Information is stored in the gate capacitance of an amplification transistor T3, and determined by turning on/off T3. T1 is a write transistor, T2 is a read transistor, and serves as a switch connecting T3 and the data line 71. Of the three transistors! Writing transistor T1. Since this is formed in the silicon thin film on the interlayer insulating film 159, the region for storing information charges is completely separated from the silicon substrate 151, resulting in significantly improved memory retention characteristics and alpha ray soft error resistance. In this example, the leakage current of T1 was able to be suppressed to 1.0-13 A or less, which is largely due to the reduction of the leakage current of T1 made possible by the optimization of the melting process described above.

Note that 168 is a data line, ]-58 is a ground line, 154 and 162 are read and write word lines,
]55 respectively correspond to the gate capacitance of the transistor T3 that stores information charges.

〔Effect of the invention〕

According to the present invention, it is possible to realize a dynamic random access memory cell that has a smaller cell area than a one-transistor, one-capacitor type memory cell, and has excellent memory retention characteristics and long-term reliability. This memory cell is
The minimum accumulated charge required to prevent alpha soft errors is 25 fC, which is sufficiently small, so as microfabrication technology advances, the entire cell can be reduced in a well-balanced manner, to the 0.5 μm level. If this processing technology could be used, a 16 megabit memory chip would be possible. Furthermore, CMO5 using secondary element stacking technology
Since it can be formed using exactly the same process as the circuit, it is possible to efficiently achieve high integration of the entire memory chip, including the peripheral circuitry.

(1) According to the present invention, it is possible to easily realize ohmic contact between two three-dimensionally arranged semiconductor layers without impairing the degree of integration and reliability. This has the effect of significantly improving the I, SI design and pattern layout freedom fj used.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional structural diagram showing an embodiment according to the present invention, FIG. 2 is a circuit diagram and cross-sectional view showing a conventional example, and FIG. 3 is a diagram showing terminal voltages during operation of a memory cell according to the present invention, and FIG. 4 is a sectional view showing an embodiment of the present invention in the order of steps, FIG. 5 is an equivalent circuit diagram of the embodiment in FIG. 4, and FIG. 6 is a leakage current characteristic diagram of a write transistor.
FIG. 7~]...First conductivity type semiconductor substrate, 2, 3.4.
...Second conductivity type region, 8...T3 gate electrode (read word line), 9...Second conductivity type semiconductor film, 10.1
1... First conductivity type region, 14... T2 gate electrode (
17...electrode wiring (data line)
, 18... Electrode wiring (reference potential line), 21... Data line, 22... Write word line, 23... Read word line, 'I']... Amplification transistor, T2...
Write transistor, T3...Read transistor, 41...P-type silicon substrate, 441,442...
Polycrystalline silicon gate electrode, 451, 452, 453.
...n-type impurity region, 47...n-type single crystal silicon film, 49...polycrystalline silicon gate electrode, 501°5
02...P skewer type impurity region, 51...Tungsten embedded, 53...Aluminum electrode wiring, 55...
・Data line, 56...Write word line, 57...
Read word line, 58...Reference potential line, 59...
Oxide film, 60... Polycrystalline silicon sub-gate electrode (reference potential), 71... P-type silicon substrate, 74... Polycrystalline silicon gate electrode, 75.76... N+ type impurity region, 78... ...Silicon groove, 80...N-type spout silicon film, 82...Polycrystalline silicon gate electrode, 8
3.84...p ten-type impurity region, 85...embedded tungsten, 87.88...aluminum oxide 11 electric horizontal wiring, 89...thin oxide film, 11...first semiconductor layer,
12... Interlayer insulating film, 13... Second semiconductor layer, 14
...Conductor buried region, 111...First conductivity type semiconductor substrate, 112...Second conductivity type impurity region, 113,1
18... Gate oxide film, 114.119... Gate electrode, 115... Interlayer insulating film, 116... First conductivity type semiconductor thin film,] 17... Second conductivity type impurity region, 1
21... Semiconductor substrate, 122... First semiconductor layer, 12
4, 127... Interlayer insulating film, 125... Second semiconductor layer, 126... Conductor buried region, 128... Aluminum electrode wiring, 131... N-type semiconductor substrate, 13
3,140...gate oxide film, 134,141...
Polycrystalline silicon gate electrode, 135, 136...n ten impurity regions. ]37...Non-doped Si○2 film, 138...Polycrystalline silicon film, 139...N-type silicon thin film, 142
゜143...p type ten impurity region, 144...tungsten embedded, 145...phosphosilicate glass film, 146
゜147...Aluminum electrode wiring, 151...n
type semiconductor substrate, 153, 161...gate oxide film. 154.155, 162... Polycrystalline silicon gate electrode, 156-158.163.164... n-type semiconductor region, 159... Non-doped S:i0z film, 160
...p-type silicon thin film, 165,166...n-type polycrystalline silicon embedded, 167...phosphosilicate glass film, 168...aluminum electrode wiring, 17]...data line, 172...・Write word line, 173...Read word line, 174...Ground line, 'T'
+ 1...Write transistor, T 1.2...
Read transistor, T13...Amplification transistor. Fig. 1 (Good) Tomi 1 Fig. (b) (C) Tomi 1 Fig. beam (eji/Δ VJ z Fig. (艮) (1o) Y 3 Fig. Tomi 3 Fig. 4 Fig. (Good) 1q (b) 451 447 t3 Yubt 44
Otsu i5JVJ s Figure 5g ￥j 〆 Figure source Shiishi open-circuit tile fo3<Y) ■ 7 Figure (Otsushiri (bl Y q Figure (Mataji No. /θ Figure Kaya /θ Figure ¥:J 11 Mouth irises 11 Figure Figure 1Z

Claims (1)

[Claims] 1. First, second and third semiconductor regions having a second conductivity type are formed from the main surface side in a semiconductor substrate having a first conductivity type, and the first and second semiconductor regions have a second conductivity type. A first conductive layer on the main surface of the semiconductor substrate between two semiconductor regions is in contact with at least mutually opposing ends of the first and second semiconductor regions via a first insulating layer. formed and said second
and a second conductive layer on the main surface of the semiconductor substrate between the third semiconductor regions with a second insulating layer interposed therebetween, the second conductive layer being in contact with at least the opposing ends of the second and third semiconductor regions. A fourth semiconductor region having a first conductivity type is formed on the first, second, and third semiconductor regions and the first and second conductive layers with a third insulating layer interposed therebetween. and,
At least a portion of the fifth semiconductor region having the second conductivity type and the sixth semiconductor region having the first conductivity type are formed in such a manner that they are sequentially juxtaposed and connected in that order, and the fifth semiconductor region on the surface opposite to the semiconductor substrate side, a third conductive layer is in contact with at least mutually opposing ends of the fourth and sixth semiconductor regions via a fourth insulating layer. the first and fourth semiconductor regions are in contact with each other, the second conductive layer and the sixth semiconductor region are in contact with each other, the first and second semiconductor regions, the semiconductor substrate, the A first insulated gate field effect transistor including a first insulating layer and the first conductive layer includes the second and third semiconductor regions, the semiconductor substrate, the second insulating layer, and the first conductive layer. A second insulated gate field effect transistor including a second conductive layer, the fourth, fifth, and sixth semiconductor regions, the fourth insulating layer,
and a third insulated gate field effect transistor including the third conductive layer. 2. The semiconductor memory device according to claim 1, wherein the first and fourth semiconductor regions are in contact with each other via a fourth conductive layer. 3. The semiconductor memory device according to claim 1, wherein the second conductive layer and the sixth semiconductor region are in contact with each other via a fifth conductive layer. 4. A semiconductor memory device according to claims 1 to 3, wherein the first conductivity type is a P type, and the second conductivity type is an N type. 5. In the semiconductor memory device according to claims 1 to 4, the second insulating layer and the second conductive layer are formed in a depth direction from the main surface side of the semiconductor substrate. A semiconductor memory device characterized by being embedded in a groove. 6. In the semiconductor memory device according to claims 1 to 4, the sixth conductive layer includes a fifth insulating layer in either or both of the second conductive layer and the sixth semiconductor region. A semiconductor memory device, characterized in that the sixth conductive layer and the third semiconductor region are formed in such a manner that they are opposed to each other with the sixth conductive layer and the third semiconductor region in contact with each other. 7. In the semiconductor memory device according to claims 1 to 4, the third conductive layer is formed away from the interface between the fifth and sixth semiconductor regions toward the fifth semiconductor region. a seventh conductive layer is formed on the fifth semiconductor region between the third conductive layer and the sixth semiconductor region, with the fourth insulating layer interposed therebetween; , 5th, 6th
the semiconductor region, the fourth insulating layer, and the third and seventh semiconductor regions.
1. A semiconductor memory device comprising a third insulated gate field effect transistor including a conductive layer. 8. In a structure having an interlayer insulating film and a second semiconductor layer on the first semiconductor layer, there is a buried conductor region penetrating through the second semiconductor layer and the interlayer insulating film and in contact with the first semiconductor layer. A semiconductor memory device characterized by: 9. The semiconductor memory device according to claim 1, wherein the conductor buried region has resistive contact characteristics with both the first and second semiconductor layers. 10. In the semiconductor memory device according to claim 1, the conductor buried region is made of tungsten, molybdenum,
A semiconductor memory device characterized in that it is formed of a high melting point metal such as titanium or tantalum, or its silicide, aluminum, or polycrystalline silicon doped with a large amount of impurities.