WO1995019625A1

WO1995019625A1 - Semiconductor device

Info

Publication number: WO1995019625A1
Application number: PCT/JP1995/000041
Authority: WO
Inventors: Tadashi Shibata; Tadahiro Ohmi
Original assignee: Tadashi Shibata; Tadahiro Ohmi
Priority date: 1994-01-18
Filing date: 1995-01-18
Publication date: 1995-07-20
Also published as: JPH07211084A

Abstract

This invention aims at providing a semiconductor device for storing high precision multi-value and analog data by a simple construction and with low power consumption. In a semiconductor device having a plurality of memory cells of multi-value or analog data, the device of the invention includes data output lines for outputting the data of the memory cells, data input lines for transferring the data to the memory cells, data read control signal lines for controlling the data output from the memory cells to the data output lines and data write control signal lines for controlling data write from the data input lines to the memory cells. The memory cell has a first MOS transistor, the gate electrode of the first MOS transistor is connected to the input line through a second MOS transistor, the gate electrode of the second MOS transistor is connected to the data write control signal line, and the source electrode of the first MOS transistor is suitably connected to the data output line.

Description

Specification

Technical field

The present invention relates to a semiconductor device, and more particularly to a memory device that stores multi-valued and analog information.

Background art

In recent years, the degree of integration of semiconductor memories has been increasing year by year, and 16 megabit dynamic memories (DRAMs) are currently being mass-produced. At the research and prototype stage, 64Mbit and 256Mbit DRAMs have already been developed. These memories are called dynamic memories, which store electric charge in a capacitor formed on a semiconductor substrate and express "1" or "0" binary digital information according to the presence or absence of this electric charge. . However, the charge stored in the capacitor is lost due to the reverse leakage current of the PN junction, the subthreshold current of the transistor, or the electron-hole pairs generated in the semiconductor substrate due to the penetration of α particles. The capacitance C _s of the capacitor cannot be made very small, and is required to be about 30 fF or more. Capacitor capacity C,

C _s = e ₀ e _r S / d [F]

It is represented by Here, £ ₀ is the dielectric constant of vacuum (8.85 X 10 " ¹⁴ F / cm), ε ^ is the relative dielectric constant of the inter-electrode insulating film (eg, S i 0. 3.9), and S is the electrode. The area d is the thickness of the insulating film.

According scaling rule, when the plane containing the device dimensions are reduced to IZA, since area S LZA ^2, d is to be IZA, C _e is reduced by LZA, along with high integration of the memory, the signal charges It is steadily decreasing.

Thus, 30 to ensure the C "of f F, for example either using a large kina material ε, such as T a ₂ 0 ₅ as the insulating film, no only means to increase relatively the S. Mr. force, and, the S i 0 ₂ other than the material, with the exception of S i ₃ N ₄ film (£ _r = 7. 5), sufficient use The development of materials with high reliability has been delayed, and it is difficult to put them to practical use. There is a method of obtaining a large surface area by forming a capacitor on an electrode having a three-dimensional structure (trench cano, a stacked capacitor) as a method of relatively increasing S, but the structure is complicated. And there are problems such as difficulty in manufacturing.

Further charge Q _M stored in the memory cell, by taking out from the predetermined cell in the plurality of memory cells of the connected have that data line (bit line) is read out as data of "1" or "0". Now, assuming that the signal voltage written to the memory cell is V _e , V „′ read to the bit line is Vs ^ (C _S ZC _B ) ^V s ( ^C _S << ^C B)

Becomes In other words, with the increase in integration, there was a problem that v _s ' became smaller and smaller as became larger.

One advantageous way to solve these problems is to use a single memory cell,

A multi-valued memory that stores multi-valued data (8 values in this example) such as 0, 1, 2, 3, 4, 5, ... 7 instead of binary digital data of "1" or "0" is there. In this way, one memory cell can store the same information as three memory cells (three bits), so that the memory capacity can be effectively increased without reducing the size of the memory cells. .

Multi-valued memory has more important applications than simply increasing the amount of data per memory cell. It is applied to multivalued information processing and image information processing.

The former is drawing attention as a technology that breaks through the limits of binary and digital information processing. In other words, there is an advantage that the number of elements and the number of wires required for realizing the same logical function can be extremely reduced as compared with the binary digital logic. However, until now there was no effective multi-valued memory, so it was not a generally accepted technology. Until now, multi-valued memory that can be used has been a method of coding multi-valued data into binary data and storing the multi-valued data in a conventional binary memory. In this method, AZD D / A conversion is always required when storing and reading data, and the hardware becomes more complicated. There are problems such as power and memory operation taking a long time. Alternatively, the AZD and DZA converters are connected in series, and the memory that holds the multi-level level in a circuit by feeding back the output to the input is also realized. There is a problem that power consumption increases because data is retained while streaming.

Also, in image processing, it is very important to store multi-valued or analog information as it is and output it as needed, but there is no memory cell that can store analog data with high accuracy. Was.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is an object of the present invention to provide a semiconductor device which has a simple structure, consumes less power, and stores multivalued and analog data with high accuracy. The purpose is. Disclosure of the invention

The present invention relates to a semiconductor device having a plurality of memory cells having a function of storing multi-level data or analog data.

A data output line from which data stored in the memory cell is output, a data input line for transferring data to be stored in the memory cell,

A data read control signal line for controlling data output from the memory cell to the data output line, and a data write control signal line for controlling data write to the memory cell from the data input line;

The memory cell has a first MOS transistor formed on a semiconductor substrate of a first conductivity type;

The gate electrode of the first MOS transistor is connected to the data input line via a second MOS transistor, and the gate electrode of the second MOS transistor is connected to the data write line. The first MOS transistor is connected to a control signal line, and a source electrode of the first MOS transistor is appropriately connected to the data output line. Action According to the configuration of the present invention, a memory device capable of storing and storing multi-valued or analog data with high accuracy and reading out the value as needed can be realized with a simple structure and with low power consumption. High-sensitivity memory, not only can be easily realized, but also multi-valued logic information processing, which is attracting attention as next-generation information processing technology, and high-speed image information processing, which is expected to be applied in various fields It greatly contributes to BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a graph showing a relationship between data of a memory cell and a potential read to a data input / output line.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a micrograph of the test device of the circuit of FIG.

FIG. 5 is a graph showing write / read characteristics.

FIG. 6 is a circuit diagram showing a third embodiment of the present invention.

FIG. 7 is a circuit diagram showing a fourth embodiment of the present invention.

FIG. 8 is a circuit diagram showing a fifth embodiment of the present invention.

FIG. 9 is a circuit diagram showing a sixth embodiment of the present invention.

FIG. 10 is a circuit diagram showing a seventh embodiment of the present invention.

FIG. 11 is a circuit diagram showing an eighth embodiment of the present invention.

FIG. 12 is a circuit diagram showing a ninth embodiment of the present invention.

(Explanation of code)

101, 104, 107 NMOS transistor,

10 2 Drain electrode,

103 source electrode,

1 0 5 Data input / output line,

10 6 NMO S 101 gate electrode,

1 0 8 Charge storage capacitor,

108a, 108b electrodes, 1 09 Sense amplifier,

1 1 3, 1 1 8 switch,

1 1 4 Data write control signal line,

1 15 Data read control signal line,

1 1 6 stray capacitance,

30 1, 303 NMOS transistor,

302 gate electrode,

304 data input / output lines,

305 source electrode,

306 control gate,

307 drain electrode,

308 data read control signal line,

309 gate electrode,

3 1 0 Data write control signal line,

70 1 a, 70 1 b multi-level memory cell,

702 data input / output line,

703 sense amplifier,

704 AZD converter,

705a-705c Inver evening,

706a, 706b neuron MOS inverter,

707 neuron DZA converter using MOS, 80 1 data input line,

802 Data output line

803. 804 switch,

805 multi-valued memory cells,

90 1 a to 90 1 d multi-valued memory cell,

902a ~ 902c data line,

903a ~ 903c, 904a ~ 904c switch, 905a ~ 905c sense amplifier, 1 0 0 1 a to 1 0 0 1 c switch,

1 2 0 1, 1 2 0 2 Multi-value data register,

1 2 0 3 bus line,

1 2 0 4 switch group,

1 2 0 5 Sense amplifier group,

1 2 0 6 Switch group. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, the present invention will be described in detail with reference to examples.

(Example 1)

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. The figure shows one memory cell that holds multi-level or analog data. 101 is, for example, an NMOS transistor whose drain electrode 102 is connected to the power supply voltage V _DD (for example, 5 V), and whose source electrode 103 is connected via the NMOS transistor 104 to data. It is connected to the input / output line 105. Reference numeral 106 denotes a gate electrode of the NMOS 101, which is connected to the data input / output line 105 via the NMOS transistor 107. 108 is the charge storage capacitor C. The one electrode 108a is connected to the gate electrode] 06, and the counter electrode 108b is connected to a DC potential. Although the case of the ground potential is shown here, this may be the power supply potential v _DD or a potential in the middle, for example, VDD, 2, or the like. This capacitor may be, for example, an M 0 S capacitor formed between the semiconductor substrate and the capacitor, or Si 0 ₂ゃ 5 i ₉ N ₄ or oxynitride ゃ T a on a polycrystalline silicon electrode. A capacitor having a crystalline silicon electrode formed through an insulating film such as ₂ _Or may be used. The method of realizing this is not particularly limited.

Next, the operation of this memory cell will be described.

In the explanation, writing and reading of four-valued data are taken as an example, but the same applies to other multi-valued cases. The voltage levels of the quaternary data, 0, 1, 2, 3, are respectively assumed to be, for example, 0 V, V _DD Z 3, 2 V _DD 3, and V _DD, and V _DD is assumed to be, for example, 5 V. Now, the operation of writing data 2, that is, the potential of 2 V _D] 3 to this memory cell Will be described.

First, a signal indicating data 2 is input to the input terminal 110 of the sense amplifier 109 by turning on the switch 111. Then, the sense amplifier outputs a voltage of 2 VDD, 3 to its output terminal 112, and this voltage is transmitted to the data input / output line by turning on the switch 113, and the potential is changed to 2 V _DD Fix to / 3. Next, a positive voltage is applied to the data write control signal line 114 to make the NMOS transistor 107 conductive, thereby charging the capacitor 108.

At this time, the potential V _DM of the wire line 114 needs to be sufficiently high so that the potential V _M of the electrode 108 a (106) becomes equal to the potential of the input / output line 105. . This is because ^V M ^{= V} D ~ ^V T (where V _T is the threshold voltage of NMOS 107 and takes into account the substrate Pier effect). , V _M > v _DD + v _T. For this, for example, a well-known bootstrap circuit or the like may be used. Yotsute thereto, by using a single power supply v _DD, the v _DD by Ri high voltage can be easily generated. Next, by setting _VDM to 0, the transistor 107 is turned off, and the data can be stored in the capacitor CJ in the form of electric charge.

Next, a data read operation will be described. When reading data, first reset the potential of the data input / output line 105 to 0 V. For example, a switch may be attached to the wiring 105 and connected to the ground line. Next, by setting the potential V _DR of the data read control signal line ₁₁₅ to a positive value, the NMOS transistor 104 is turned on, and the source 103 of the NMOS 101 is connected to the data. Connect to I / O line 105. In this case, a current is supplied from the power supply V _DD to the wiring 105 through the transistors ₁₀₁ and 104, and the capacitor C _n 116 is charged. Capacitance C _B is the stray capacitance that Yusuke wiring 1 0 5. With increasing potential VD of the wiring 1 0 5 so as not to turn off the transistor 1 0 4 force, v _DR should be a sufficiently large value, for example, may be set to _{_{_{v Dn> V DD + V T}}} . Here, V _T is the threshold of NMO S 1 0 4, which is a value when the particular substrate bias one v _DD is applied. By setting v _DR in this way using a bootstrap circuit, etc., even when v _B = v _DD , The transistor 104 can be kept conductive. Now, representing the threshold pressure of the transistors 1 0 1 V _TM, the charge of C _B to the potential of the output line 1 05 is _{_{_{V n = V M _ V TM}}} \

This is because when this condition is satisfied, the NMOS 101 is turned off, and the supply of current is stopped. That is, a voltage level corresponding to the data v _M held in the memory cell is output to v _B. Assuming that the decrease in charge during data retention due to leakage etc. is extremely small and can be ignored, and if v _TM = 0 is set, in the example of this explanation, V _B = 2V _DD Z3 The written data can be read as it is.

In practice, V _B = 2 V _DD / 3 is not accurately obtained because of the decrease in charge during the holding period and the increase in the threshold voltage of the NMOS transistor 101 due to the body bias effect. The read potential V _B2 to V _D corresponding to data 2 is

½ ^{= 2 V} DD, ³ - ^ΔΥ Μ- ^AV TM '…)

Becomes Here AV _M represents a decrease in the memory charge, .DELTA..nu _Taumyu represents the increase in V _TM due to the substrate by § scan effect. _{_{That, V TM (V sub = -}} V B2) = V TM (V cub = 0) is + Δν Δν _ΤΜ when expressed as _Taumyu. (However, here, ^V TM (Vsub = 0) = 0V)

Thus, (1) must be restored to data in the original multi-valued data 2 V _DD Z3 of the formula, that is the sense 'amplifier 1 09 is used for that purpose. Functions to be provided in the sensor Suanpu, for example by turning on the switch 1 1 8 to monitor the value of V _B, a predetermined sense level V _s of the value corresponding to the data 2. This function makes the output voltage V _{Qut equal} to the original data, 2 V _DD Z3, when the voltage exceeds V. Specifically, for example, a circuit as shown in the fourth embodiment (FIG. 7) of the present invention may be used. FIG. 2 shows an example of the relationship between the potentials corresponding to the data 0, 1, 2, and 3 written to the memory cells and the potential V „read to the data input / output lines, where V _B1 and V _B2 are respectively Output potential corresponding to data 1 and 2.

For example, the sense level of data 2 is V _s2 , and V _B1 <V _s . It should be designed to satisfy the condition <V _B2 .

Generally, the sense level of each data is

丄 V _si = (i / 3) V _DD -Δν _Μ -ΔΥ _ΤΜ- ^ …… (2)

(i = 1, 2, 3)

Should be determined such that v _B <v _si <v _Bi . The level at which 0 data is sensed is a small positive value, and if it does not exceed this value, 0 V may be output for 109.

As soon as the condition of V _B > V _si is satisfied, V _Qut = (i / 3) V _DD is set immediately, so that the multivalued data that has been accurately restored can be converted to v. Output to _ut and read it out.

During this read operation, the switch 113 may be turned off or turned on. When turned on, v reaches or whether or to each sense level _B, v the value of _B is to be raised to the multi-level data level corresponding to the real, V to a value corresponding to a predetermined V _M _The time when _B rises is shorter than when switch 113 is turned off, and the reading operation can be sped up.

After the value of ^v _Qut is determined, the switches ₁₁₃ are turned on and the write operation is performed, so that the restored data is stored in the memory cell again, and the data is refreshed.

As described above, the operation principle of the multi-valued dynamic memory implemented by the present invention is completely different from that of a conventional dynamic memory of a battery. In other words, instead of directly reading out the stored charge representing the data, the capacitor CJ, the charge is indirectly read out by a source follower circuit using the transistor 101. is there. Since the reading is non-destructive to the data and the current is amplified, the reading voltage does not decrease with the ratio of C / C. The source follower circuit has a capacitive load called CD, so that no DC current flows and power consumption can be reduced sufficiently. You.

In addition, the number of multi-valued levels is determined by the balance between the accuracy of the circuit operation and the accuracy of the manufacturing process.By making these accuracy sufficiently high, it is possible to hold many levels of data. Therefore, a large-capacity memory can be easily realized. Sa Further, it can be applied as a data register or a memory circuit in a multi-valued logic circuit. It can also be used as a memory for holding analog data as it is. In this case, an analog amplifier may be used instead of the 109 sense amplifier. In this way, a multi-level and analog memory with a simple structure, high accuracy, and low power consumption can be realized.

In FIG. 2, curve 20 1 representing the relationship between V _B and V _M is preferably close to a straight line 202 as possible 45 °. To do so, the amount of decrease in charge Δν よ_い may be reduced by first sufficiently reducing the leakage current and the like. For example, in ΡΝ junction created by Urutoraku lean techniques, 1 is the reverse leakage current Chikaraku about 1 0- ¹⁸ A of ΡΝ joining m square, when holding the data of the 8 values C _s of 30 f F, The time when Δν _Μ = 5 OmV is about 100 seconds. Considering that the voltage difference between each level is about 70 OmV, there is no problem at all.

If a refresh cycle is performed at intervals of several hundred milliseconds to several seconds, it can be considered that ΔV _M = 0.

The main factor that determines the difference between V _D and V _¾1 is Δν _、, which is the increase in the threshold value for the substrate bias effect of the NMOS transistor 101. This .DELTA..nu _Taumyu to small fence, for example, transistor 1 0 1 may Shiteyare sufficiently small § click septa concentration New _lambda of Ρ type semiconductor region forming the. For example Ν Α ₌ 1 X 10 ¹⁵ cm hereinafter with them if delta V _TM can almost be ignored.

Alternatively, the P-type semiconductor region forming the transistor 101 may be a P-type well provided in an N-type substrate, and the potential of the well may be connected to be equal to the potential of the source 103 of the transistor 101. Good. In this case, the substrate bias of the transistor 101 becomes 0 V irrespective of the potential of the source 103, so that _AVTM = 0.

In the above embodiment, the闞voltage V _TM of the transistor 101 was 0V, which, v _TM> be 0 v _TM <course be may be zero. By using a depletion-type transistor with v _{TM set to} 0, v _B > v _M can be satisfied. Also, although the description has been given only of the case where the transistors 101, 104, and 107 are NMOS transistors, they may all be PM〇S transistors. No.

In addition, regarding the 4-value data, 0 and 3 data are set to 0 V and 5 V (V _DD ), respectively, but this may have an offset such as 0.5 V and 4.5 V, for example. Further, each level does not necessarily have to be set at an equal voltage interval. These are all matters relating to circuit design, and are not particularly limited by the present invention. This is the same for the function of the 109 sense amplifier.

Further, in FIG. 1, only one memory cell connected to one sense amplifier 109 via the data input / output line 105 is shown, but this is only for the purpose of explanation. Needless to say, a plurality may be connected.

(Example 2)

FIG. 3 shows a second embodiment of the present invention.

In FIG. 3, 301 is an NMOS transistor, and 302 is its gate electrode. The threshold voltage V _TM of the transistor 3 0 1 seen from the gate electrode 3 0 2 is set, for example, V _M = V _DD. The gate electrode 302 is connected to the data input / output line 304 via the NMOS transistor 303. In addition, the source electrode 305 of the NMOS transistor 301 is directly connected to the data input / output line 304. '

Reference numeral 36 denotes a control gate, which is capacitively coupled to the gate electrode 302. The magnitude of the capacitance is represented by C „The coat roll gate 306 and the drain electrode 307 of the transistor 301 are both connected to the data read control signal line 308. The gate electrode 309 of the S transistor 303 is connected to the data write control signal line 310.

Next, the operation of the memory cell will be described. The description will be made by taking as an example the writing and reading of two of the four-value data of 0, 1, 2, and 3, as in the first embodiment.

First, at the time of writing, the potential of the data input / output line is set to 2 V _DDZ3 , the voltage corresponding to data 2.

Then, as in the first embodiment, the electric potential V _M of the signal line 3 1 0 as the _{_{_{V M> V DD + V T}}} , turns on the transistor 3 0 3. At this time, the potential of the signal line 3 08 _VDR is set to 0V. In this case, the potential of the gate electrode 302 becomes equal to the potential of the data input / output line 304.

When turning off the transistor 303 as V _DM = 0 in this state, data in the charge, stored in the capacitor one C _e. This completes the write operation.

Next, a read operation will be described. Reading, after reset first potential V _B of the input and output data line 304 to 0 V, Ru done by pulling only the data read control signal line 308 connected to the cell to be read to V _DD. Current flows from the V _DD through the NMOS transistor 30 1 In this way, the capacitance C _B 3 1 1 of data input and output line 304 is charged, the potential V "rises. This, NMOS transistor 30 to load the Cn 1 is a source follower circuit, and its output v _B is

^V B- ^Φ Ρ- ^Υ ΤΜ …… ( ³⁾

Keep rising until. Here, _VTM is a threshold value in consideration of the substrate bias effect of the NMOS 301, and _Φρ is a potential of the gate electrode 302. Gate electrode

Capacitance between the 302 and the control gate 306 is a C _e, but gate one gate electrode

When all the capacitances other than C _s are represented as C ₀ from the viewpoint of 302, (D _F is φΡ ^{= ν} Μ ⁺ ( ^C Z ^(C 0 ^{+ C} _S )) ' ^V DD …… ( ⁴ )

It is expressed as Here V _M is the potential of the data written to the gate electrode 302, in this example a = 2V _DD / 3.

If C _C : »C ₀ , 0> _F = V _M + V _DD , and from equation (3), the value of V _n is V _B = 2 V _DD / 3, and the written data can be read as it is. .

The description of the operation of the sense amplifier is omitted, but it is the same as in the first embodiment.

Figure 4 is a photomicrograph of a test device in which the circuit shown in Figure 3 was prototyped using a two-layer polysilicon CMOS process. The numbers in the photograph correspond to the numbers in Figure 3. In the photograph, two data input / output lines 304 were separately divided into two parts, and the operation was measured externally as in Fig. 3 when measuring the force. Figure 5 shows the measurement results.

The operation of the 304 is slow because it was measured with a capacitance of about 5 pF, but the actual circuit can be operated at a higher speed because c _B is small. Here, the reason why the threshold voltage of the NMOS transistor 301 is set to V _TM = ^ _DD (5 V) and equal to the power supply voltage is as follows.

When data is read, v _DR is kept at 0 in unselected cells, but v _B rises to a positive potential. This is because the contents of the memory have been read from another selected cell connected to the same data input / output line 304. Now, assuming that the data written in the unselected cell is the data of 3, the potential VM of the gate ₃₀₂ is 5 V. However, since V _TM = 5 V, the transistor 301 does not turn on.

If _VTM is less than 5 V, the transistor 310 turns on and the current flows from the wiring 304 to the signal line 308 which is 0 through the transistor, so that c _B is charged. The time to do it becomes longer. That is, it takes time to read data. Thus, because the transistor 3 0 1 unselected cell is avoided a situation where turning on, the threshold V _TM, it forces preferably larger than the maximum value 5 V of V _M.

_Assuming that _VTM > 5V, the read output voltage becomes smaller than VM, as is apparent from equations (3) and (4). The experimental results in Fig. 5 show such an example. Data, in accordance with 1, 2, 3 to be larger, the decrease of the read data is increasing, because v _TM was large summer by the substrate bias effect. However, such a decrease in read data can be solved without any problem by using the sense amplifier 109 shown in FIG.

As in the second embodiment, when the V _TM = 5 V with respect to the maximum value 5 V of V _M, a slight leakage current is generated in non-selected cells. In order to avoid this, for example, the maximum value of V _M, for example, 4. 0 V not good do it taking less than 5 V to and so on. In this case, _VTM may be smaller than 5 V, for example, 4.5 V. Needless to say, the transistor 301 may be formed in a p-cell in order to eliminate the substrate bias effect, and the potential of the transistor 301 may be connected to the same potential as the source electrode 305.

The determination as high as V _TM = 5 V may be made by applying a DC substrate bias to the substrate.

(Example 3) In the above description, the force of writing data in the state of v _DR = oV. For example, data may be written at V _DR = 5 V. In this case, when data 0 (0 V) is written in the cell, the potential of the gate electrode 302 becomes −5 V when V _DD = 0. Therefore, the NMOS transistor 303 is turned on, and the written data is destroyed.

The third embodiment of the present invention was invented to solve this problem, and FIG. 6 shows a circuit diagram thereof. All are the same as in FIG. 3 except that the transistor 601 is a PMOS transistor, and each part is assigned the same number. If V _M = 5V, the data is retained as the PMOS does not turn on even if the potential of 302 becomes negative. At the time of writing data, V = 0 V and the PMOS 601 may be turned on.

(Example 4)

FIG. 7 shows a fourth embodiment of the present invention.

In the figure, reference numerals 701a and 701b denote multi-level memory cells, which may be, for example, any of FIG. 1, FIG. 3, FIG. 702 is a data input / output line, and 703 is a sense amplifier, an example of which is specifically shown here.

In 703, 704 circuit block Ri Ah with 3 bits Bok of A / D converter converts the analog signal into a digital signal of 3 bits, a circuit for outputting the A _Q, A _v Α _2. Here, A 0 is the least significant bit (LSB).

705 a, 705b, 705 c is Invar evening, their respective inverted voltage _{_{_{V s2, V s4, V s6}}} , i.e. data 2, 4, and equal to the summer in the 6 sense level, V _in is the respective sense level As it goes over, the output of the binary code changes in the order of 1 → 2, 3- → 4, 5-6. Numerals 706a and 706b denote circuits using neuron MOS transistor transistors, and realize the AZD converter circuit together with the members 705a to 705c. The operation of this circuit is well known and is described in the literature (T. Shibata and T. Ohmi, 'Neuron M0¾ binary-logic integrated circuits: Part II, Simplifying techniques of circuit configuration and their practical applications, "IEEE Trans. Electron Devices, Vol. 40, No. 5, pp. 974-979 (1993)). Binary coded output power The sense level for changing from 0 → 1, 2 → 3, 4-5, 6 → 7 is determined by the neuron M〇S invertor 706a, 706b canon. It is possible to freely control by designing the size of these, and it is extremely easy to set these levels to predetermined v _cl , v _s3 , v _s5 , and v _e7 . Since these are known from the above-mentioned literature, the description here is omitted. Numeral 707 denotes a DZA converter using a neuron MOS, which is a circuit for converting a 3-bit multilevel data to analog data in a binary code, and the operation of which is also known in the following literature. (T. Shibata and T. Ohmi, "A functional OS transistor featuring gate-level weighted sum and threshold operations," IEEE Trans. Electron Devices, Vol. 39, No. 6, pp. 1444-1455 (1992)).

That is, as shown in the figure, by connecting in series with the AZD converter and DZA converter, sense up for 8-value data can be realized. In this case, the A / D converter and D / A converter using the neuron MOS are shown because the circuit is greatly simplified. It goes without saying that the AZD D / A converter may be realized using other circuit technologies.

The operation of this circuit is to sense the value of v _in , and sequentially apply the data of the corresponding value level to V. It is a circuit that outputs to _ut . Regardless of whether the switch 708 is used in the open or closed state, this circuit functions as the sense-up described in the description of the first embodiment. More preferably, the switch 708 uses the closed state. That is, by applying feedback to the circuit of 703, the multi-value level can be determined more accurately. NM OS further constituting the DZA converter, using a large transistor current driving force in PMOS, when sensing the level of v _in can lift the level of rapid Niso a predetermined multilevel, faster circuit operation Can be achieved.

Further, even when the switch 709 is opened to disconnect the data input / output line, the sense-up circuit is more convenient because the multi-valued data can be held in a circuit form. An example is possible.

The switch 710 is a switch for inputting a multi-level input signal from the outside to the sense-up. When turning on 110, switch 709 is open or closed. It doesn't matter.

In the present embodiment, the case where the sense-up combining the AZD and DZA converters is used is described, but it goes without saying that any other sense-up may be used.

(Example 5)

In the first to fourth embodiments of the present invention, data input and data output are performed using one data input / output line (105, 304, 702). It goes without saying that data input and output can be performed by opening separate data lines.

FIG. 8 shows a fifth embodiment of the present invention showing such an example. Reference numerals 801 and 802 designate data input lines and output lines, respectively. 803 and 804 are switches for controlling input and output, respectively. Reference numeral 805 denotes a multi-valued memory cell, and any of the cells shown in the first to third embodiments may be used. However, when the cells of the second and third embodiments are used, the switch 804 for controlling the data reading is not necessary and the connection may be made directly. Reading can be performed by setting the potential of the data read control signal line 308 in FIGS. 3 and 6 to V _DD . Figure 8 illustrates this conceptually. For these switches, it is preferable that the gate voltage is made higher than v _DD by using a NMOS in a bootstrap circuit or the like so that analog or multi-level voltage levels can be accurately written and read. Alternatively, a so-called CMOS switch in which NMOS and PMOS are connected in parallel may be used. In this case, the gate voltage may be set to a value equal to or higher than v _{DD by a} bootstrap circuit or the like.

(Example 6)

90 1 a, 90 1 b, 901 c, and 90 1 d are multi-valued memory cells, the contents of which are the same as in FIG. 902a, 902b, and 902c are data lines. For example, 902b is used as a data output line of the cell 901b and at the same time as a data input line of the cell 901c.

This circuit operates as follows. First, switches 903a, 903b, and 903c are closed, and the data of cells 901a, 901b, and 901c are respectively stored. The data is read out to the data lines 902a, 902b, 902c. After that, the switches 903a to 903c are opened and their data are latched in the sense up 905a to 905c. These sense-ups are, for example, those shown in FIG. 7 and the feedback switch 708 is closed. Next, when the data input switches 904a to 904c are closed, these data are stored in the memory cells.

Read them to 901 b, 901 c, 90 Id.

That is, by the above series of operations, the multi-valued data has been moved to all neighboring cells. That is, a multi-valued shift register is realized. This is a circuit that plays an important role in multilevel information processing.

(Example 7)

FIG. 10 is a circuit diagram showing a seventh embodiment of the present invention, which is also a multi-value shift register. However, in this embodiment, the function of data shift is realized by the force using the common input / output line for each cell, the force to put the switches 1001a, 1001b, and 1001c up, and the force to put the switches down. ing.

When data is read from memory cells 1002 a to l 002 c, the switch

Put 1001a to 1001c on top and put the data into the sense amplifiers 1003a to 1003c. Then, at the time of writing, the data can be transferred to the next cell by putting the switch down. When simply refreshing, it is sufficient to perform read and write operations with the switches 1001a to l001c inserted above, so that it can be used both as a memory and as a shift register. It goes without saying that any of the first to third embodiments may be used as the memory cell.

(Example 8)

FIG. 11 is a circuit diagram showing an eighth embodiment of the present invention.Data can be freely exchanged between memory cells by appropriately turning on and off each switch of switch matrices 1101. .

(Example 9)

FIG. 12 shows a ninth embodiment of the present invention. Reference numerals 1201 and 1202 denote multivalued data registers each including four multivalued memory cells. 1203 has four This is, for example, a bus line in a chip of a multilevel microprocessor. Is latched in the sense amplifier group 1 2 0 5 with read to the register A _Q to A multilevel data Chikaraku bus lines 1 2 0 3 ₃ by turning on the Suitsuchi group 1 2 0 4. If the switch group 1 204 is turned off after the switch group 1 204 is turned off, these multi-valued data registers B ^ B g are stored.

As described above, by using the multi-valued memory technology of the present invention, it is very easy to realize a multi-valued microphone mouth processor. In addition, in FIG. 12, each switch group shows only one for each memory cell, but this is only a conceptual configuration, and as in FIGS. This indicates that two are used for reading. In addition, it is needless to say that one switch is unnecessary in the cells shown in FIGS. Industrial applicability

According to the present invention, a memory device capable of storing and storing multi-valued or analog data with high precision and reading out the value as needed can be realized with a simple structure and with low L and power consumption. It becomes possible.

As a result, not only can high-sensitivity memories be easily realized, but also multi-valued logic information processing, which is attracting attention as the next-generation information processing technology, and high-speed image information processing, which is expected to be applied in various fields It greatly contributes to.

Claims

The scope of the claims

1. In a semiconductor device having a plurality of memory cells having a function of storing multi-level data or analog data,

δ a data output line from which data stored in the memory cell is output,

A data input line for transferring data to be stored in the memory cell;

0 the memory cell has a first MOS type transistor formed on a semiconductor substrate of a first conductivity type,

The gate electrode of the first MOS transistor is connected to the data input line via a second MS transistor, and the gate electrode of the second MOS transistor is connected to the data electrode. A semiconductor device connected to a write control signal line, and configured so that a source electrode of the first MOS transistor is appropriately connected to the data output line.

2. The semiconductor device according to claim 1, wherein the data input line and the data output line are configured by the same wiring (data input / output line).

3. The source electrode of the first MOS transistor is connected to the data output line via a thirtieth MOS transistor, and the gate electrode of the third MOS transistor is connected to the source electrode of the third MOS transistor. 3. The semiconductor device according to claim 1, wherein the semiconductor device is connected to the data read control signal line.

4. A control electrode connected directly to the data output line of a source electrode of the first MOS transistor and capacitively coupled to a gate electrode of the first MOS transistor 3. The semiconductor device according to claim 1, wherein the first terminal is connected to a drain electrode of the first MOS transistor and the data read control signal line. 4.

5. The method according to claim 4, wherein, when writing data to the memory cell, the potential of the data read control signal line is held at a value equal to and equal to a power supply voltage. Semiconductor device.

6. The method according to claim 5, wherein the first M〇S transistor is an NMOS transistor, and its inversion threshold voltage is set to be substantially equal to or larger than the power supply voltage. 13. The semiconductor device according to claim 1.

7. The semiconductor device according to claim 4, wherein the second MOS transistor is formed on a semiconductor substrate of a conductivity type opposite to that of the first conductivity type.

8. A semiconductor region of the first conductivity type is formed in a semiconductor substrate of a conductivity type opposite to the first conductivity type as a p-well region separated from each of the plurality of memory cells by a distance L from each other. , '

8. The semiconductor device according to claim 1, wherein each well is electrically connected to a source electrode of the first MOS transistor.

9. At the time of reading data from the memory cell, a temporal change in the potential of the data output line is monitored, and when the potential exceeds a predetermined value, a predetermined potential is output, and the potential is applied to the data input line. 9. The semiconductor device according to claim 1, wherein a circuit for transmitting is included in at least a part.