JPH07192476A - Ferroelectric memory - Google Patents

Abstract

PURPOSE:To obtain a non-volatile ferroelectric memory which is easy to manufacture, has a high SN ratio, and is suitable for increasing the integration density. CONSTITUTION:A reference potential is generated by a reference potential generating section 102 based on a signal potential of logic 1, 0, and stored in a potential storage section 103. In read-out operation, a reference potential is generated in a data line of one side through a potential supplying section 104 based on a stored potential, and information is detected by comparing the reference potential with a signal potential read out in the other data line. In this constitution, since polarization inversion of a dummy cell can be evaded at the time of read-out operation, deterioration caused by fatigue of a film can be suppressed. Also, since a dummy cell having the same structure and size as a memory cell in generating the reference potential, manufacturing is made easy, dispersion of a characteristic is made small, and a highly accurate reference potential can be generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor memory, and more particularly to a structure of a nonvolatile ferroelectric memory suitable for high integration.

[0002]

2. Description of the Related Art A ferroelectric substance, when an electric field of a certain strength is applied, causes polarization in the ferroelectric substance, and the polarization is a residual polarization unless a reverse electric field of a certain strength is applied to invert the polarization. Has the property of being held as. A ferroelectric capacitor using this as a capacitor dielectric film is shown in FIG.
As shown in, there is a hysteresis characteristic between the applied voltage VFE and the accumulated charge QFE.

FIG. 34 is an explanatory diagram showing voltage-charge characteristics of a ferroelectric capacitor. The characteristics of the ferroelectric capacitor will be described based on this figure. When a voltage VM1 of a certain magnitude is applied to the ferroelectric capacitor, the polarization direction of the ferroelectric substance becomes substantially constant along the applied electric field, and the state of the ferroelectric capacitor transits to the state d1. Next, when the applied voltage is set to 0 V, the charge Qr1 for compensating for the residual polarization is obtained.
Remains on the electrode plate, the state of the ferroelectric capacitor becomes the state s1. Further, when a certain voltage -VM0 is applied in the opposite direction to VM1, the polarization is inverted and the state of the ferroelectric capacitor becomes the state d0. After this, the applied voltage is 0
When set to V, the compensation charge −Qr0 remains on the electrode plate and the state s
Transition to 0. That is, when the applied voltage is 0V,
Ferroelectric capacitors can have multiple states.
Therefore, for example, the state s1 is associated with the logic 1 and the state s
Information can be stored by mapping 0s to logical 0s. Since the remanent polarization is retained unless an electric field having a certain strength is applied, this storage method does not require a refresh operation and can form a nonvolatile memory in which information is retained even after the power is turned off.

A ferroelectric capacitor having the above-mentioned characteristics in which information is stored in advance has a voltage of a certain magnitude, for example, VM1.
When the voltage is applied, the apparent capacitance value of the ferroelectric capacitor is different between when the state s1 transits to the state d1 and when the state s0 transits to the state d1. That is, when the state s0 transits to the state d1, a larger amount of charge flows into the ferroelectric capacitor than the transition from the state s1 due to the polarization reversal, and as a result, the apparent capacitance value increases.
That is, when the polarization inversion occurs, the capacitance value becomes equivalently larger than when the polarization inversion does not occur. Information can be read by utilizing this characteristic.

As an example of a non-volatile memory formed by using a ferroelectric capacitor having such characteristics, for example,
Examples include those disclosed in US Pat. No. 4,873,664. The configuration of this memory will be described with reference to FIG. FIG. 35 is a circuit configuration diagram showing a configuration of a conventional ferroelectric memory. In this figure, the ferroelectric capacitor CF
A memory cell MCv1 composed of Ev1 and a transistor TRv1 and a ferroelectric capacitor CFEBv
The memory cell MBv1 constituted by 1 and the transistor TRBv1 is selected by the word line WLv1 and driven by the plate line PLv1 to generate a signal potential on the pair of data lines DLv1 and DBv1. Hereinafter, the operation of generating such a signal potential will be described more specifically.

The pair of data lines DLv1, DBv1 and the plate line PLv1 are set to low level (Low), and the word line W
When Lv1 is set to a high level (High) and the cell transistor is made conductive, the plate line PLv1 is set to H level.
When set to high, the potential of the data line DLv1 becomes High.
And Low potential difference between the ferroelectric capacitor CFEv1
And the parasitic capacitance CDLv1 of the data line DLv1. Similarly, for the potential of the data line DBv1, the potential difference between High and Low is calculated by comparing the parasitic capacitance CDBv of the ferroelectric capacitor CFEBv1 and the data line DBv1.
The voltage is divided by 1 and. In this operation, when the polarization of the ferroelectric capacitor is inverted, the apparent capacitance of the ferroelectric capacitor is increased, so that the signal potential generated on the data line is higher than that when the polarization is not inverted. Therefore, the ferroelectric capacitors CFEv1 and CF
By setting the directions of remnant polarization of EBv1 in mutually opposite directions and writing a logic 1 to one of the memory cells MCv1 and MBv1 and a logic 0 to the other, the pair of data lines DLv1.
1, there is a potential difference between DBv1. This potential difference is sensed by the sense amplifier SAv1 to read information.

The above-mentioned memory uses two memory cells to store 1-bit information, which is disadvantageous in constructing a highly integrated memory. In order to further improve the degree of integration, it is desirable to store 1-bit information in one memory cell. In that case, in order to detect the signal potential generated in the data line by the selected cell, a means for generating a reference potential in the middle of the signal potential corresponding to logic 1 or logic 0 is required in the paired data lines. As one of them,
There is a technique using a dummy cell. As one method of such a dummy cell structure, for example, the method described in the above-mentioned US Pat. No. 4,873,664, or
Examples include those disclosed in JP-A-2-301093. That is, the area of the ferroelectric capacitor of the dummy cell is made different from that of the memory cell, and this is used to generate the reference potential. U.S. Pat. No. 4,873,6
The method disclosed in No. 64 will be described with reference to FIG.

FIG. 36 is a circuit diagram showing the structure of a conventional ferroelectric memory using dummy cells. In the figure, the memory cell MCw1 is selected by the word line WLw1 and driven by the plate line PLw1 to generate a signal potential on the data line DLw1. The dummy cell DMCw1 is selected by the dummy word line DWLw1 and driven by the plate line DPLw1 to generate a reference potential on the data line DDLw1. Here, as disclosed in the above-mentioned US Pat. No. 4,873,664, the area of the ferroelectric capacitor DCFEw1 of the dummy cell DMCw1 is set to the ferroelectric capacitor CF of the memory cell MCw1.
The polarization direction is set to be twice or more larger than that of Ew1 and polarization inversion does not occur when the reference potential is generated. In addition, the ferroelectric capacitor CFEw1
For this, an apparent capacitance at the time of polarization reversal is larger than that at the time of non-inversion of polarization of the ferroelectric capacitor DCFEw1 on the dummy cell side. As a result, the capacitance of the ferroelectric capacitor DCFEw1 on the dummy cell side is larger than the capacitance of the ferroelectric capacitor CFEw1 when the polarization is not inverted and smaller than the capacitance when the polarization is inverted. Therefore, it is possible to generate a potential in the middle of the signal potentials corresponding to logic 1 and logic 0 on the data line DDLw1.

In this technique, the area of the ferroelectric capacitor DCFEw1 on the dummy cell side is set to the ferroelectric capacitor CF.
It is set to be larger than that of Ew1.
As disclosed in 1093, a ferroelectric capacitor D
The same effect can be obtained by setting the area of CFEw1 smaller than that of the ferroelectric capacitor CFEw1 and setting the polarization direction so that polarization inversion always occurs when the reference potential is generated. . Further, as another technique related to the dummy cell configuration, for example, the technique disclosed in Japanese Patent Application Laid-Open No. 2-110893, Japanese Patent Application Laid-Open No. 2-110895, or Japanese Patent Application Laid-Open No. 5-89692 can be cited. That is, the reference potential is generated by connecting two ferroelectric capacitors to the data line and driving them so that one polarization is inverted and the other polarization is not inverted. The method disclosed in Japanese Patent Laid-Open No. 2-110895 will be described with reference to FIG.

FIG. 37 is a circuit diagram showing the structure of a conventional ferroelectric memory for generating a reference potential by utilizing polarization inversion. In the figure, the memory cell MCy1 is selected by the word line WLy1 and generates a signal potential on the data line DLy1. In addition, the dummy cells DMCy1 and DM
Cy2 is selected by the dummy word line DWLy1,
A reference potential is generated on the data line DDLy1. The plate electrode PCy1 of the memory cell MCy1 and the dummy cell D
The plate electrode PLy2 of MCy2 is High and Low.
, And the plate electrode PLy1 of the dummy cell DMCy1 is connected to the Low potential (or High potential). In addition, dummy cells DMCy1 and DMCy2
Ferroelectric capacitors DCFEy1 and DCFEy
The electrode area of 2 is 1/2 of the electrode area of the ferroelectric capacitor CFEy1 included in the memory cell MCy1. Further, the polarization direction of the dummy cell capacitor DCFEy2 is
It is set in advance by applying a high voltage from the reset voltage source VRSy by the reset signal RESETy.

When a signal is generated, the data line DLy1,
The DDLy1 is precharged to the Low potential, and then the word line WLy1 and the dummy word line DWLy1 are driven to connect the memory cell capacitor CFEy1 to the data line DLy.
1 and dummy cell capacitors DCFEy1, DC
FEy2 is connected to the data line DDLy1. At this time, the polarization of the dummy cell capacitor DCFEy2 is inverted, but the polarization of the dummy cell capacitor DCFEy1 is not inverted. Therefore, the dummy cell capacitor DCFEy
1, the sum of the capacities of DCFEy2 is an intermediate value between the capacity of the memory cell capacitor CFEy1 at the time of polarization inversion and the capacity at the time of non-inversion of polarization. By using this, a reference potential for determining the signal potential corresponding to logic 1 and 0 can be generated.

Here, the dummy cell capacitor DCFEy
Instead of providing a circuit for resetting the polarization of No. 2, the data line D as disclosed in JP-A-5-89692.
It is also possible to drive DLy1 to reset the dummy cell. Further, as disclosed in Japanese Patent Application Laid-Open No. 2-110893, a dummy cell is shared by two adjacent pairs of data lines to generate a reference potential by using a dummy cell capacitor having an electrode area equal to that of the memory cell capacitor. You can also This method will be described with reference to FIG.

FIG. 38 is a circuit diagram showing the structure of a conventional ferroelectric memory in which two adjacent pairs of data lines share a dummy cell to generate a reference potential. In this figure,
The electrode areas of the dummy cell capacitors DCFEx1 and DCFEx2 are equal to those of the memory cell capacitors. Further, similarly to FIG. 37, the plate electrode PLx2 is High.
Is connected to the intermediate potential between Low and Low, and the plate electrode PLx1
Is connected to the Low potential (or High potential). Prior to the signal generating operation, a high voltage is applied from the reset voltage source VRSx by the reset signal RESETx,
The polarization direction of the dummy cell capacitor DCFEx2 is set. When the signal is generated, the data line DDLx1,
When the DDLx2 is precharged to the Low potential and then the switches YSWx1 and YSWx2 are made conductive, the reference potential is generated on the data lines DDLx1 and DDLx2.

[0014]

The problems to be solved are the following points which occur in the respective memory configurations using the conventional dummy cells. In the configuration using the first dummy cell, that is, the dummy cell having capacitors having different electrode areas as shown in FIG. 36, the reference potential is based on the capacitance value of either polarization non-inversion or polarization inversion. Since it is determined, it is impossible in principle to generate an intermediate potential using both capacitance values. Therefore, in order to generate a highly accurate reference potential, the capacitance value of the memory cell capacitor at the time of polarization inversion and non-inversion is estimated in advance, and a dummy cell capacitor having a desired capacitance characteristic determined based on this is realized with high accuracy. Must. Since it is difficult to design dummy cells and set process conditions for this purpose, there is a high risk that a stable reference potential cannot be generated due to variations in capacitance characteristics and deviation from the estimated value at the design stage, and the SN ratio and yield decrease. To do. In addition, one polarization of the second dummy cell, that is, two capacitors as shown in FIG. 37 or 38, is inverted,
Regarding the configuration using the dummy cell that does not invert the other polarization, it is possible in principle to generate an intermediate potential between the signal potentials of logic 1 and 0, but the electrode area is ½ of the memory cell capacitor. Alternatively, it is necessary to use a dummy cell having a different structure from the memory cell, such as separating the plate electrodes to provide different plate potentials or providing a reset signal line. Therefore, the dummy cells cannot be formed in the continuous layout pattern of the memory cell array, and the dummy cells have to be separately designed and arranged separately from the memory cell array. Therefore,
As with the configuration using the first dummy cell, it is difficult to design the dummy cell and set process conditions, and it is difficult to obtain a dummy cell capacitor with the same characteristics as the memory cell capacitor, so there is a risk that a stable reference potential cannot be generated. Is high. Moreover, since the access frequency of the dummy cell is higher than that of the memory cell, there is a concern that the dummy cell that causes polarization reversal every read operation may deteriorate with time due to film fatigue. An object of the present invention is to solve these problems of the prior art and to provide a ferroelectric memory which is easy to manufacture, highly reliable, and suitable for high integration.

[0015]

In order to achieve the above object, the ferroelectric memory of the present invention comprises: (1) As shown in FIG. A reference potential generation unit 102 that generates a reference potential based on a signal potential corresponding to “1” and a signal potential corresponding to logic “0”, and a reference potential generated by the reference potential generation unit 102 or the reference potential is reproduced. And a potential storage unit 103 that stores information for storing the information, and a memory cell when the logic “1” or the logic “0” written in the memory cell MC11 of the memory cell array 105 is read after the reference potential generation unit 102 generates the reference potential. A potential for outputting the reference potential reproduced by the potential storage unit 103 or a potential for reproducing this reference potential for detecting the signal potential generated by the MC 11. Characterized by comprising a supply unit 104. (2) In the ferroelectric memory according to (1) above, as shown in FIG.
Reference numeral 02 denotes a first dummy cell RMC1 having the same configuration as the memory cell MC11 and having the same element characteristics.
1 and RMC01, and the logic "1" is applied to one of the first and second dummy cells RMC11 and RMC01.
Is written in the other and a logic "0" is written in the other, and the outputs of the first and second dummy cells RMC11 and RMC01 are short-circuited to generate a reference potential. (3) In the ferroelectric memory described in (2) above, as shown in FIG. 4, the reference potential generation unit 102 includes a pair of first and second data lines DL1 and DB1. , The first dummy cell RMC11 is connected to the first data line DL1, the second dummy cell RMC01 is connected to the second data line DB1, and the first and second dummy cells RMC11 and RMC are connected.
01 and the connected first and second data lines DL1 and D1
It is characterized in that B1 is short-circuited to generate a reference potential. (4) In the ferroelectric memory according to any one of (1) to (3) above, as shown in FIG. 5, the reference potential generation unit 102 includes a plurality of reference potential generation units 102 arranged adjacent to each other on the chip. The potential storage unit 103 includes an adjacent potential averaging unit (data line short-circuit switches SWDS1 and SWDS2) that outputs the average value of the reference potentials generated corresponding to the memory cells. It is characterized in that the average value of the output reference potentials or information for reproducing the average value of the reference potentials is stored. (5) In the ferroelectric memory according to any one of (1) to (4) above, as shown in FIGS.
Reference numeral 2 denotes a separated potential averaging unit (reference potential averaging unit AVR) that outputs an average value of each reference potential generated corresponding to each of a plurality of memory cells that are spaced apart and arranged on the chip.
1), and the potential storage unit 103 is characterized by storing the average value of the reference potential output by the separated potential averaging unit or information for reproducing the average value of the reference potential. (6) In the ferroelectric memory according to any one of (1) to (5) above, as shown in FIG. 9, the reference potential generating unit 102 includes a plurality of memory cells arranged on a chip. A common potential averaging unit (reference potential averaging unit AVR1) that outputs the average value of the reference potentials corresponding to each as a reference potential commonly used for reading all the memory cells arranged on the chip is provided. It is characterized by having. (7) In the ferroelectric memory according to any one of (1) to (5) above, as shown in FIG. 10, the reference potential generator 102 is arranged in each predetermined region on the chip. A common potential averaging unit for each area that outputs an average value of each reference potential generated corresponding to each of a plurality of memory cells as a reference potential commonly used for reading of each memory cell arranged in the same predetermined area (see The potential storage unit 103 is provided with a potential averaging unit AVR1), and the potential storage unit 103 outputs, for each region, the average value of each reference potential output by the common potential averaging unit for each region or information for reproducing the average value of this reference potential. The potential supply unit 104 stores the potential stored in the potential storage unit 1
The average value of the reference potentials stored in 03 or the potential for reproducing the average value of the reference potentials is output for each region. (8) In the ferroelectric memory according to any one of (1) to (7) above, as shown in FIG. 11, the potential storage unit 103 includes a reference potential generation unit 102.
And a potential holding unit MVR having a first capacitor (capacitance storage capacitor CMA) for accumulating a reference potential output by the CPU or a potential for reproducing the reference potential, and a leak characteristic equivalent to that of the first capacitor. The second capacitor (leakage monitoring capacitor CML) that stores a predetermined constant potential when the reference potential of the one capacitor or the potential for reproducing the reference potential and the fluctuation of the potential stored in the second capacitor are A refresh determination unit RFJ having a leak detection unit (comparator DTL) for detection is provided, and when the variation amount of the accumulated potential of the second capacitor detected by the refresh determination unit RFJ reaches a predetermined value, the first Of the reference potential to the capacitor of or the potential to reproduce this reference potential and the potential of the second capacitor. Performs position re accumulation, characterized by refreshing the information. Also, (9) above (1)
In the ferroelectric memory according to any one of (1) to (7), as shown in FIG. 12, the potential storage unit 103 includes an AD conversion unit that converts a reference potential or a potential for reproducing the reference potential into a digital signal. (AD conversion control unit ADC
TL), a latch unit LMD that stores the digital signal converted by the AD conversion unit, and a DA conversion unit (DA converter DAC) that converts the digital signal stored in the latch unit LMD into an analog potential. Characterize. (10) In the ferroelectric memory as described in (9) above, as shown in FIG.
Is a reference potential input control unit (switch SWSL1, SWSL2) for sequentially inputting the reference potential output from the plurality of reference potential generation units 102 or the potential for reproducing the reference potential to the AD conversion unit (AD conversion control unit ADCTL). )When,
An average value calculation unit DCA for calculating an average value of each digital signal corresponding to a plurality of reference potentials sequentially converted by the AD conversion unit or a potential for reproducing the reference potential and outputting the calculated average value to the latch unit LMD. It is characterized by doing. (11) In the ferroelectric memory according to any one of (1) to (10), as shown in FIG. 14, the potential supply unit 104 has a potential having a capacitance sufficiently larger than that of the data line. Supply capacitor (charge supply capacitor C
RS), a potential fluctuation detection unit (comparator DRS) for comparing the accumulated potential of the potential supply capacitor with the reference potential of the potential storage unit 103 or the potential for reproducing the reference potential, and the potential fluctuation detection unit A charging unit (transistor TRS) for charging the potential supply capacitor to a reference potential or a potential for reproducing the reference potential based on the comparison result is provided. In addition, (1
2) In the ferroelectric memory as described in (3) above, FIG.
As shown in FIG. 5, the memory cell array 105 includes memory cells MC1 having the same configuration and the same element characteristics.
1, MC12, MC21, MC22 and first and second dummy cells (dummy cells DMCB1, DMCB2, DM
It is characterized in that it is formed by a layout pattern in which CD1 and DMCD2) are two-dimensionally arranged. Also, (13)
In the ferroelectric memory according to (3) above, as shown in FIG. 18, the data lines DL1 to DL4 and DB1 to DB4 are arranged at least so that adjacent data lines are not simultaneously selected in a read operation. And the unselected data lines DB2 and D2 adjacent to the selected data line DB1 in the read operation.
It is characterized in that the potential of L2 is fixed. In addition, (1
4) In the ferroelectric memory according to any one of (1) to (13) above, as shown in FIG. 23, a plurality of memory cells MH11 and MH12 are commonly connected and the data line DL is connected.
1-2, the first plate electrode having a constant potential intermediate between the highest potential and the lowest potential in the operation amplitudes of DB1 and DB2 and the plurality of dummy cells DMCD1-2 and DMCB1-2 are commonly connected, and at least the selection in the read operation is performed. It is characterized in that the second plate electrodes PLDD and PLBB having a potential higher than or equal to the highest potential or lower than the lowest potential in the operation amplitude of the data line are provided in a period in which the dummy cells thus driven are driven. (15) In the ferroelectric memory according to any one of (1) to (14) above, as shown in FIG. 27, a plurality of data line pairs DL1-DB1, DL2-
An information sensing unit (sense amplifier SA01) that is selectively connected to DB2 and amplifies the potential difference of this data line pair and outputs it as information, and a data line that controls the connection between this information sensing unit and a plurality of data line pairs. Selector (Column selection switch YSW
1, YSW 2) are provided. Also,
(16) In the ferroelectric memory according to (15) above, as shown in FIG. 28, an unselected data line pair DL2-DB2 adjacent to a data line pair DL1-DB1 selected for connection with an information sensing unit. Data line potential fixing unit (precharge circuits TPN1 to TPN1
4) is provided. (17) In the ferroelectric memory according to any one of (1) to (16) above, as shown in FIG. 31, a memory cell array 10
5, a dummy cell DMCB1 that generates a reference potential when reading information, and a dummy plate line potential that generates a potential of the plate electrode of the dummy cell that makes the reference potential generated by this dummy cell equal to the reference potential generated by the reference potential generation unit 102. The potential storage unit 103 stores the potential of the plate electrode of the dummy cell generated by the dummy plate line potential generation unit 107 as information for reproducing the reference potential, and the potential supply unit 104 stores the potential. It is characterized in that the potential of the plate electrode of the dummy cell stored in the storage unit 103 is output.

[0016]

In the present invention, by adopting the configuration of (1) above, during the reference potential generating operation for generating the reference potential,
When a pair of dummy cells in which a logic 0 is written in one side and a logic 1 is written in the other side are used, when reading the information written in the dummy cells, the data lines connected to the respective dummy cells are short-circuited and the data lines are set to logic 0 and logic. A reference potential in the middle of the signal potential corresponding to 1 is generated. Then, this is stored in the potential storage unit. Next, in the read operation, based on the potential information stored in the potential storage unit, the reference potential generated on one of the paired data lines via the potential supply unit,
A signal is detected and information is read by comparison with a signal potential corresponding to logic 0 or logic 1 read from the memory cell connected to the other side. By doing so, it is not necessary to invert the polarization of the dummy cell in the read operation, so that deterioration over time due to fatigue of the ferroelectric film of the dummy cell is reduced, and a highly reliable ferroelectric memory can be obtained. Also, the above (2), (3), and (1
With the configuration of 2), the reference potential intermediate between the signal potentials corresponding to the logic 1 and the logic 0 can be generated without using a dummy cell having a different structure or element size from the memory cell. The reference potential can be generated simply by adding a simple circuit, a dummy cell can be formed in the memory cell array, and the dummy cell can be provided on a layout pattern continuous with the memory cell. This facilitates dummy cell design and process condition setting, improves the uniformity of device characteristics, and makes it possible to generate a highly accurate reference potential.
Further, in the configurations of (4) to (7) above, the reference potential is averaged. As a result, it is possible to generate a more stable reference potential that is resistant to variations in the characteristics of the dummy cells and the like. Further, by adopting the configuration of (8) above,
The reference potential can be stored with a relatively simple circuit. In addition, with the above configurations (9) and (10), the reference potential can be stored as a digital signal,
It is possible to avoid disappearance due to a leak or the like. Further, the potential supply unit can be simply configured by the above (11). Further, with the above configuration (13), since the potential of the adjacent data line is fixed in the read operation, the interference noise due to the parasitic capacitance between the data lines can be reduced. Further, by adopting the configuration of (14), it is not necessary to perform fine processing of the plate electrode as a plate line. Further, as the configurations of (15) and (16), the information sensing unit is shared. As a result, the circuit area can be reduced and only the necessary portion of the memory cell array is operated, so that it is possible to reduce power consumption, noise such as power supply, and the like. Further, in the above configuration (17), the reference potential is generated in the data line via the dummy plate line. As a result, the influence of the fluctuation of the potential supplied from the potential supply section to the memory cell array on the data line potential can be reduced.

[0017]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the configuration of the ferroelectric memory of the present invention according to the present invention. This example illustrates the basic concept of the present invention, and is an example showing a block configuration of a reference potential generation unit that applies a reference potential to a data line during a read operation. In the figure, the reference potential generation unit 101 includes a reference potential generation unit 102,
The potential storage unit 103, the potential supply unit 104, and the controller 106 that controls them are included. The memory cell array 105 also includes a word line WL1, a dummy word line DWB, data lines DL1 and DB1, a memory cell MC11, a dummy cell DMCB1 and a sense amplifier SA1. Dummy cell DMCB1
Are provided in order to balance the capacitances of the data lines DL1 and DB1 and stably perform the amplification operation when the signal is detected by the sense amplifier SA1.

The reference potential generator 102 is in the middle of the signal potential corresponding to the logic 1 or the logic 0 generated in the data line DL1 or the like by the selected memory cell MC11 or the like during the read operation. An electric potential, that is, a reference electric potential is generated. The reference potential can be generated, for example, by generating a signal potential of logic 1 and logic 0 using the memory cell array 105 and short-circuiting the signal potential. The potential storage unit 103 stores the reference potential generated by the reference potential generation unit 102. This storage may be volatile, that is, in such a way that information is lost when the power is turned off. Further, instead of storing the reference potential itself, information such as a potential or a digital value that can reproduce the reference potential in the data line in the read operation may be stored. The potential supply unit 104 applies the reference potential to the data line paired with the data line to which the selected memory cell is connected during the read operation, and thus reproduces the reference potential or the reference potential stored in the potential storage unit 103. Supply a potential for For example, the memory cell MC1
When 1 is selected, the data line DL1 connected to it is
The reference potential is supplied to the data line DB1 which makes a pair with.

As the memory cell MC11, the dummy cell DMCB1, etc., a memory cell for storing information in a non-volatile manner by utilizing the remanent polarization of a ferroelectric substance can be applied.
For example, the configuration shown in FIG. 2 can be applied. FIG. 2 is a circuit configuration diagram showing a configuration example of the memory cell in FIG. In the figure, the memory cell MC11 is a cell transistor T
It is composed of R11 and a ferroelectric capacitor CF11. One of the source and drain terminals of the cell transistor TR11 is
One terminal and the other terminal of the ferroelectric capacitor CF11 are connected to the data line DL1, and the gate terminal is connected to the word line WL1. The other terminal (plate electrode PLC) of the ferroelectric capacitor CF11 is commonly connected to a plurality of memory cells and is also connected to a plate potential supply section (not shown). The ferroelectric capacitor CF11 is formed by sandwiching a ferroelectric film between electrodes.

Examples of ferroelectric materials include lead zirconate titanate (PZT) and barium titanate (BaTi).
Perovskite oxides such as O3) are applicable. The polarization of the ferroelectric capacitor CF11 is controlled by the potential difference between the potential applied to the storage node SN11 by the data line DL1 and the plate electrode PLC. Besides this, the resistance R
F11 represents a resistance representing leakage of the ferroelectric capacitor CF11, and diodes DS11 and DD11 represent source / drain junctions of the cell transistor TR11. It is assumed that the other memory cells and the dummy cell DMCB1 and the like also have the same configuration as the memory cell MC11 and have substantially the same structure and element size.

The flow of the read operation applied to the configuration shown in FIG. 1 will be described with reference to FIG. FIG. 3 is a flowchart showing an operation example of the ferroelectric memory in FIG. 1 according to the present invention. In this example, first, after the power is turned on (step 501), a reference potential is generated (step 502) and stored (step 503). If the read operation is requested here (Yes in step 504), the read operation is started. As an example, in FIG. 1, when the memory cell MC11 is selected, the word line WL1 and the dummy word line DWLB are selectively driven (step 505). As a result, a signal potential corresponding to logic 1 or logic 0 is generated on the data line DL1 (step 506). At this time, the reference potential is supplied from the potential supply unit 104 to the paired data line DB1 (step 507). The difference between the signal potential and the reference potential is detected by the sense amplifier SA1 (step 5).
08) to read the information.

Through this read operation, it is not necessary to invert the polarization of the ferroelectric capacitor of the dummy cell DMCB1 of FIG. On the other hand, when the information of the reference potential stored in the potential storage unit 103 of FIG. 1 needs to be refreshed (Yes determination in step 509), the process returns to step 502 again to generate the reference potential and store it. When it is determined that the refresh is not necessary (No determination in step 509), the standby state is continued until the read request comes. The refresh is required, for example, after the memory is accessed a certain number of times, when the environment such as the supply voltage and the temperature is changed, or when the time elapses, the potential storage unit 103 in FIG. This is the case, for example, when the memory content of is changed or lost.

When there is no access request for a long time, the sleep mode is set, refresh is not performed, and in some cases, power is not supplied to the potential storage unit 103 of FIG. In addition, by returning to step 502 again and providing an operation mode for generating and storing the reference potential, power consumption during standby can be reduced. According to the present embodiment, the read operation can be performed by using the reference potential intermediate between the signal potentials corresponding to the logic 1 and the logic 0 and without causing the film fatigue due to the polarization inversion of the dummy cell capacitor.

Next, a more specific embodiment of the part constituting the above basic concept will be described. FIG. 4 is a circuit configuration diagram showing a second embodiment of the configuration according to the present invention of the ferroelectric memory of the present invention. This example is one example showing the configuration of the reference potential generation unit applicable to the present invention. In the figure, the reference potential generation unit 102 is a memory cell array 105.
Reference potential generating dummy cells RMC11 and RMC01 respectively connected to the data lines DL1 and DB1 included in
And dummy word lines RWL1 and RWL0 for selecting these dummy cells and data line pair DL1-DB1.
A data line short-circuit switch SWDS1 for short-circuiting (a pair of data lines is represented as DL-DB)
And a voltage follower UGB1. The dummy cells RMC11 and RMC01 are used for the memory cell array 1
It is also possible to share it with the dummy cell DMCB1 or the like included in 05.

The reference potential generating operation with this structure is performed as follows. First, the dummy cells RMC11, RM
Write a logic 1 to one of C01 and a logic 0 to the other. This is, for example, the data line DL1 by the sense amplifier SA1.
This can be easily performed by amplifying the potential difference between the data line DB1 and the data line DB1 and using this to write to the dummy cells RMC11 and RMC01. Next, with the data line short circuit switch SWDS1 turned on, the dummy word line RWL
1, RWL0 is selected. Then, the dummy cell RMC1
1, RMC01 is logical 1 from one side, logical 0 from the other side
A signal corresponding to is generated. At this time, the data line pair DL
1-DB1 is short-circuited, so voltage follower U
If the input capacitance of GB1 is sufficiently small, the data line pair D
The potential generated in L1-DB1 is an intermediate potential of the signal potentials corresponding to logic 1 and logic 0. This is used as a reference potential and output via the voltage follower UGB1. By providing the voltage follower UGB1, it is possible to prevent the fluctuation of the reference potential due to the influence of the wiring capacitance and the like.

According to this embodiment, the reference potential can be generated only by adding a simple circuit to the memory cell array. Since the dummy cell used here does not need to have a special structure different from that of the memory cell, the dummy cell can be built in the memory cell array. Therefore, by providing dummy cells on a layout pattern that is continuous with the memory cells, it is possible to easily design the dummy cells and set process conditions, have high uniformity of element characteristics, and generate a highly accurate reference potential.

FIG. 5 is a circuit configuration diagram showing a third embodiment of the configuration according to the present invention of the ferroelectric memory of the present invention.
The present embodiment shows the configuration of the reference potential generation unit applicable to the present invention, and is shown in FIG. 4 in that the reference potential is generated by simultaneously using a plurality of adjacent dummy cells. Different from the embodiment. In FIG. 5, the data line pair D
Data line pair DL2- arranged adjacent to L1-DB1
DB2 has the same array configuration as the data line pair DL1-DB1. That is, in the memory cell array including the memory cell MC12, the dummy cell DMCB2, and the sense amplifier SA2, the reference potential generating dummy cell RMC12,
It is configured by adding RMC02 and a data line short-circuit switch SWDS2.

Each word line and dummy word line are shared with the data line pair DL1-DB1. Data line pair DL1
-A plurality of data line pairs including DB1, DL2-DB2 are
It is commonly connected to the voltage follower UGB1 via the data line short-circuiting switches SWDS1, SWDS2 and the like as the adjacent potential averaging unit of the present invention. In the reference potential generating operation, these data line short circuit switches are turned on at the same time. Therefore, the voltage follower UGB1 is supplied with a potential obtained by averaging the reference potentials generated in the data line pairs DL1-DB1, DL2-DB2 and the like. According to this embodiment,
By using multiple sets of dummy cells at the same time and averaging the reference potential, it is resistant to variations in characteristics of dummy cells, etc.
It is possible to generate a more stable reference potential.

FIG. 6 is a circuit configuration diagram showing a fourth embodiment of the configuration of the ferroelectric memory of the present invention according to the present invention.
The present embodiment shows the configuration of the reference potential generation unit applicable to the present invention, and in that the reference potential is generated by simultaneously using a plurality of sets of dummy cells separated from each other, FIG.
Alternatively, it differs from the embodiment shown in FIG. In FIG. 6, using the same configuration as that shown in FIG. 4 or 5,
k voltage followers UGB1, UGB2, ..., UG
Reference potentials VRR1, VRR2, ..., V given to Bk
RRk is transmitted to the reference potential averaging unit AVR1 as the separated potential averaging unit of the present invention. Reference potential averaging unit AV
R1 outputs the average value VRRA1 of the reference potentials VRR1, VRR2, ..., VRRk.

An example of the configuration of the reference potential averaging unit AVR1 is shown in FIG. Figure 7
FIG. 7 is a circuit configuration diagram showing a first configuration example of the reference potential averaging unit in FIG. 6. In FIG. 7, the reference potential averaging unit AVR1 includes k resistors RB1 and R having a resistance value R.
B2, ..., RBk, and a voltage follower UGBB. Voltage follower UGB1, UGB2
..., reference potentials VRR1, VRR output from UGBk
2, ..., VRRk are resistors RB1, RB2 ,.
Are averaged and output via the voltage follower UGBB. According to this, the reference potential can be averaged using a relatively simple configuration.

Another configuration of the reference potential averaging unit AVR1 is, for example, the one shown in FIG. 8 below. FIG. 8 is a circuit configuration diagram showing a second configuration example of the reference potential averaging unit in FIG. As shown in FIG. 8A, the reference potential averaging unit AVR1 includes a switch SWIN.
1, SWIN2, ..., SWINk and SWG1, SW
G2, SWT, SWRS, and a capacitor CI having a capacitance value C
N, a capacitor COUT having a capacitance value kC, and an operational amplifier O
It is composed of PA1. An example of the operation timing of each switch will be described using the control pulse shown in FIG.

First, the switch SWRS is turned on to discharge the capacitor COUT. Then switch SWIN
1, SWG1 is turned on to charge the capacitor CIN with the reference potential VRR1. Next, the switches SWG2 and SW
When T is turned on, the electric charge charged in the capacitor CIN is transferred to the capacitor COUT. Where capacitor C
Since the capacitance of OUT is k times that of the capacitor CIN, if the gain of the operational amplifier OPA1 is sufficiently large, the capacitor CO
The voltage across the UT is VRR1 / k. Next, the same operation is performed by using the switch SWIN2 instead of the switch SWIN1. Then, VRR2 / k is added to the voltage across the capacitor COUT, and (VRR1 + VRR2) /
k. Hereinafter, the same operation is performed up to the switch SWINk. As a result, the reference potentials VRR1, VRR2, ..., V
The average value VRRA1 of RRk is output. In this configuration, since the output voltage is determined by the relative accuracy of the two capacitors CIN and COUT, k resistors are used.
Compared to the above example, it is less likely to be affected by variations in element characteristics. Further, if the charging time of the capacitor is appropriately lengthened, it is possible to reduce the influence of the wiring resistance on the output value even when the wiring from each voltage follower is long.

An example of the arrangement of each reference potential generating circuit having the above structure on the chip according to the present invention is shown in FIGS.
FIG. 9 is a circuit configuration diagram showing a fifth embodiment of the configuration related to the present invention of the ferroelectric memory of the present invention. In this example,
10 shows a first arrangement example of the reference potential generating circuit in the ferroelectric memory of the present invention on the chip according to the present invention, and in FIG. 9, voltage followers UGB1 and UG are shown.
BGB2, ..., UGB8 are distributed and arranged on the chip MMT. The reference potential generated in each of them is supplied to the reference potential averaging unit AVR1 as the common potential averaging unit of the present invention in the center of the chip. The reference potential averaged by the reference potential averaging unit AVR1 is supplied to the entire chip.
According to this configuration, one reference potential generating section can be shared by the entire chip.

FIG. 10 is a circuit configuration diagram showing a sixth embodiment of the configuration of the ferroelectric memory of the present invention according to the present invention. This embodiment shows a second arrangement example of the reference potential generation circuit in the ferroelectric memory of the present invention on the chip according to the present invention, and in that the reference potential averaging units are arranged in a distributed manner, FIG. Different from the example shown in. In FIG. 10, the chip MMT is divided into four regions MM1 to MM4. On the area MM1, voltage followers UGB1 to UGB4
Are distributed and arranged, and the reference potentials generated in each are supplied to the reference potential averaging unit AVR1 as the region common potential averaging unit of the present invention in the center of the region. The reference potential averaged by the reference potential averaging unit AVR1 is supplied to the area MM1. The other areas MM2 to MM4 have the same configuration. With such a configuration in which the regions are divided, the reference potentials in the adjacent regions can be averaged, and it is particularly effective when the signal potential variation in the chip surface is relatively large. According to this embodiment, the reference potentials can be averaged by using the dummy cells that are located apart from each other on the chip. As a result, the reference potential can be generated even if a defect occurs in a part of the dummy cells in the region.

FIG. 11 is a circuit configuration diagram showing a seventh embodiment of the configuration of the ferroelectric memory of the present invention according to the present invention. The present embodiment shows the configuration of the potential storage section according to the present invention. In FIG. 11, the potential storage section 103 is composed of a potential storage section MVR and a refresh determination section RFJ. The potential storage unit MVR includes a potential storage capacitor CMA as the first capacitor of the present invention and a switch SWM.
It is composed of A. The generated reference potential is charged in the capacitor CMA via the switch SWMA, whereby the reference potential is stored. At the same time, in the refresh determination unit RFJ, the power supply voltage VDD is charged to the leak monitoring capacitor CML as the second capacitor of the present invention via the switch SWML. Capacitor C
It is assumed that the leakage characteristics of the voltage charged in the MA and the voltage charged in the capacitor CML are almost the same.

The charging voltage of the capacitor CML is compared with the reference voltage VRL by the comparator DTL as the leak detecting section of the present invention. The reference voltage VRL is a voltage lower than the power supply voltage VDD by several%, for example. Capacitor C
When the charging voltage of ML drops due to leakage and becomes equal to VRL, it can be considered that the charging voltage of capacitor CMA also drops at almost the same rate. Thereby, the leak of the capacitor CMA can be monitored. The output of the comparator DTL is monitored by the controller 106, and when a voltage drop due to leakage is detected, the reference potential is charged in the capacitor CMA again, and the potential storage unit MVR is refreshed. It is desirable that the time constant of discharge due to leakage be as large as possible so that refresh requests are not frequently made. According to this embodiment, the generated reference potential can be stored using a relatively simple circuit.

FIG. 12 is a circuit configuration diagram showing an eighth embodiment of the configuration related to the present invention of the ferroelectric memory of the present invention. The present embodiment shows the configuration of the potential storage unit applicable to the present invention, and differs from the embodiment shown in FIG. 11 in that the reference potential is stored as a digital value. This Figure 12
In, the potential storage unit 103 includes a latch unit LMD, a DA converter DAC as a DA conversion unit of the present invention, and a comparator CMP. The digital value given to the latch unit LMD is DA converted by the DA converter DAC, and is converted into an analog voltage by the comparator CM.
Given to P. The comparator CMP outputs the comparison result of the reference potential input from the outside and the DA converter DAC. Using this, the AD conversion control unit ADCTL as the AD conversion unit of the present invention of the controller 106 controls the digital value latched by the latch unit LMD.
When the AD conversion of the reference potential is completed by these operations,
The reference potential is stored as a digital value in the latch unit LMD. For the stored reference potential, the digital value latched in the latch unit LMD is converted to D by the DA converter DAC.
It is obtained by A conversion.

FIG. 13 is a circuit configuration diagram showing a ninth embodiment of the configuration of the ferroelectric memory of the present invention according to the present invention. With the configuration of this embodiment, both the reference potential can be averaged and stored. That is, the switches SWSL1 as the reference potential input control unit of the present invention
SWSL2, ... Are switched to sequentially perform AD conversion, and the digital value obtained as a result is stored in the register SRG. This may be input to the average value calculation unit DCA, and the result of calculating the average value may be stored in the latch unit LMD. According to the eighth and ninth embodiments shown in FIGS. 12 and 13, the stored value can be retained without being lost due to a leak or the like. It is also possible to reduce the standby power consumption by turning off the power supplies of blocks other than the latch unit LMD in the standby state.

FIG. 14 is a circuit diagram showing a tenth embodiment of the structure of the ferroelectric memory of the present invention according to the present invention. The present embodiment shows the configuration of the potential supply unit applicable to the present invention. In FIG. 14, the potential storage unit 1 is shown.
The reference potential stored in 03 is applied to the comparator DRS as the potential fluctuation detection unit of the present invention. The output of the comparator DRS controls the charging transistor TRS to charge the charge supply capacitor CRS as the potential supply capacitor of the present invention with the reference potential. In the read operation, the reference potential of the capacitor CRS is supplied to the memory cell array, and the charge lost by the supply is replenished through the transistor TRS. At this time, it is desirable that the capacitance value of the capacitor CRS is large in order to sufficiently lower the output impedance of the potential supply unit and sufficiently supply the charges to the memory cell array. This value can be increased by utilizing wiring capacitance or connecting a ferroelectric capacitor. According to this embodiment, the reference potential can be supplied to the memory cell array with a simple structure.

FIG. 15 is a circuit configuration diagram showing an eleventh embodiment of the configuration of the ferroelectric memory of the present invention according to the present invention. This embodiment shows a configuration of a memory cell array applicable to the present invention. In FIG. 15, the data line DL1 and the data line DB1 form a pair, and a potential difference between them is detected to read out a signal. The data line DL2 and the data line DB2 form a pair. Hereinafter, although the data line pairs having the same configuration are arranged side by side, they are omitted in the figure. The position where the word line WL1 and the data line DL1 intersect is shown in FIG.
Memory cell MC11 having a configuration similar to that shown in FIG.
Are connected. The memory cell MC12 is connected to the intersection of the word line WL1 and the data line DL2. The plate electrodes of the memory cells MC11 and MC12 are connected to the plate line PL1. The memory cell MC21 is provided at a position where the word line WL2 and the data line DB1 intersect.
, And the memory cell MC22 is connected to a position where the word line WL2 and the data line DB2 intersect. The plate electrodes of the memory cells MC21 and MC22 are connected to the plate line PL2.

Similarly, the word lines WLp (p = 1,
2, 3, ..., M) and the data line DLq or DBq (q =
1, 2, ...) At the position intersecting with the memory cell MCpq
Are connected, but omitted in the figure. On the other hand, at a position where the dummy word line DWLD and the data line DLq intersect, a dummy cell DMCDq as a second dummy cell of the present invention is provided.
Are connected. The plate electrode of the dummy cell DMCDq is connected to the dummy plate line PLDD. Further, a dummy cell DMCBq as the first dummy cell of the present invention is connected to a position where the dummy word line DWLB and the data line DBq intersect. The plate electrode of the dummy cell DMCBq is connected to the dummy plate line PLBB.

All memory cells and dummy cells are formed using a common layout pattern and have the same structure and element size. As a result, the device characteristics are almost the same. The sense amplifier SAq is CM
An OS flip-flop is used, which is controlled by the sense amplifier control lines SP and SN, and has a data line pair DLq-DB.
It senses and amplifies the signal generated at q. The precharge circuit TPNq is controlled by the precharge control line PCN, and when not selected, the precharge potential supply line PCV
The potential VSS of SS is supplied to the data line pair DLq-DBq. The reference potential precharge switch SWPRDq is C
Precharge control line PC using MOS switch
Controlled by RD and / PCRD, during the read operation, the reference potential VRD supplied to the precharge potential supply line PCVRD from the potential supply unit 104 shown in FIG. 1 or 14 is supplied to the data line DLq.

Reference potential precharge switch SW
PRBq is a precharge control line PCRB, / PCRB
And the reference potential V during the read operation.
RD is supplied to the data line DBq. The precharge control line / PCRD forms a pair with the precharge control line PCRD, and is driven symmetrically such that when one is High, the other is Low. Similarly, the precharge control line / PCRB is driven symmetrically with the precharge control line PCRB. The data line short circuit switch SWDSq is controlled by the data line short circuit control line DLSH, and the data line pair DLq-
Short and open DBq. Voltage Follower UGB1
Supplies the reference potential generated in the data line pair DL1-DB1 activated in the reference potential generating operation to the potential storage unit 103 shown in FIG. Data line pair DL2-D
The data line short-circuiting switch provided on the data line pair to which the voltage follower is not connected, such as B2, is the data line pair DL1.
A voltage follower such as DB1 is provided to obtain a data line capacitance equivalent to that of the connected data line pair. The column selection switch YSWq is controlled by the column selection line YSq,
Connection between data line pair DLq-DBq and input / output line I / O
Perform separation.

An example of the reference potential generating operation in such a circuit configuration will be described with reference to FIG. FIG. 16 is a timing chart showing an example of a reference potential generating operation in the memory cell array of FIG. First, the standby state will be described. The potential of each word line, dummy word line and plate line is the low potential VSS. The potentials of the sense amplifier control lines SP and SN are VSS, and each sense amplifier is inactive. Furthermore, the potential of the precharge control line PCN is the high potential VDD, and the potential VSS is supplied to each data line pair. Furthermore, the potentials of the precharge control lines PCRD and PCRB are VS.
The potentials of S, / PCRD and / PCRB are VDD, and the reference potential precharge switch is off. Furthermore, the potential of the data line short circuit control line DLSH is VSS and each data line short circuit switch is off. Furthermore, the potential of each column selection line YS1, YS2, ... Is VSS, the column selection switches YSW1, YSW2, ... Are off, and the input / output line I / O and each data line are separated.

Next, the reference potential generating operation will be described.
Here, description will be made focusing on the data lines DL1 and DB1, but the operation of the other data lines is similar to the following. The operation procedure is roughly divided. First, a logic 1 is written in one of the pair of dummy cells and a logic 0 is written in the other (time td1 to td).
3) secondly, a reference potential is generated on the data line (time td4
To td5), thirdly, the polarization direction of the dummy cell capacitor is reset so that the polarization inversion of the dummy cell capacitor does not occur during the read operation (time td6 to td).
8). This will be described in detail below.

First, at time td1, the potential of the precharge control line PCN is set to VSS and the data line pair DL1-
Stop VSS precharge to DB1. Further, the potentials of the dummy word lines DWLD and DWLB are set to VCH, the potentials of the dummy plate lines PLDD and PLBB are set to VDD, the dummy cells DMCD1 and DMCB1 are selected, and the cell transistors are made conductive. Here, the potential VCH is higher than the potential VDD by at least about the threshold voltage of the cell transistor, and the potential VCH is applied to the gate electrode of the transistor.
By applying CH, it is possible to sufficiently transmit a signal potential of about the potential VDD between the source / drain terminals. Further, the potential of the sense amplifier control line SP is set to VDD to activate the sense amplifier SA1.
Then, one of the potentials of the data line pair DL1-DB1 is driven to VDD and the other is driven to VSS due to variations in the characteristics of the transistors forming the sense amplifier SA1 and the other enters a steady state. At this time, the potential difference between VDD and VSS is applied to the dummy cell capacitor connected to the data line on the potential VSS side. The polarization direction set by this is equal to that of the memory cell in which the logic 0 is written.

At time td2, the dummy plate line P
The potentials of LDD and PLBB are set to VSS. At this time, a polarization direction opposite to that of the dummy cell capacitor on the potential VSS side is set to the dummy cell capacitor connected to the data line on the potential VDD side. This direction is equal to that of a memory cell programmed with a logic one. At time td3, the potential of the sense amplifier control line SP is returned to VSS and the sense amplifier SA1 is inactivated. In addition, the potential of the precharge control line PCN is set to VDD and the data line pair DL1-D
The potential of B1 is returned to VSS. Further, the potential of the data line short circuit control line DLSH is set to VDD, and the data line pair DL1-
Short DB1. Next, at time td4, the potential of the precharge control line PCN is set to VSS and the data line pair D
L1-DB1 is put in a floating state. Then, at time td5, the dummy plate lines PLDD, PLBB
Potential of VDD. At this time, the dummy cell DMCD
1, the capacitor of DMCB1 is almost VDD-VSS
Voltage is applied. Then, the polarization of the dummy cell capacitor in which the logic 1 is written is inverted, and the charge ΔQr is accordingly increased.
Flows in. ΔQr is, when sufficient polarization reversal occurs,
As shown in FIG. 34, the charge difference Qr1- for compensating for remanent polarization is shown.
Equal to (-Qr0).

Using this, the reference potential VRR1 generated on the data lines DL1 and DB1 is represented by the following equation, ignoring the noise component.

[Equation 1] In Expression 1, CDL represents the data line capacitance, and CF11
N represents the non-inversion capacitance of the dummy cell capacitor. However, it is assumed that the data lines forming a pair have the same capacitance, and the dummy cell capacitors forming a pair also have the same voltage-charge characteristics.

Here, considering the interference noise due to the parasitic capacitance between the data lines DL1 and DB1 and the peripheral drive lines in the floating state, that is, in the state after the transistors of the precharge circuit TPN1 are cut off. , The reference potential V generated on the data lines DL1 and DB1
RR1N is represented by the following formula.

[Equation 2] In Expression 2, −ΔVPCN is the precharge control line P
The amount of change in the data line potential due to the decrease in the potential of CN is shown. Further, ΔVPLT represents the variation amount of the data line potential due to the rise of the plate line potential due to the parasitic capacitance at the intersection where the dummy cells are connected. Furthermore, ΔVPLB is
The amount of fluctuation of the data line potential due to the rise of the plate line potential due to the parasitic capacitance at the intersection where the dummy cells are not connected is shown. Since all data lines generate the reference potential at the same time,
The parasitic capacitance between the data lines has no effect.

When the reference potential is stored, at time td6, the potential of the data line short-circuit control line DLSH is set to VSS, the data line short-circuit switch is turned off, and the potential of the precharge control line PCN is set to VDD to set the data line. The potential VSS is charged to the pair DL1-DB1. This allows
The polarization of the dummy cell capacitor is reset to logic 0, that is, in the direction in which the polarization is not inverted during the read operation. Then, at time td7, the dummy plate lines PLDD, PDD
The potential of LBB is returned to VSS, and then the potentials of the dummy word lines DWLD and DWLB are returned to VSS at time td8. With the above, the reference potential generating operation is completed.

Next, an example of the read operation of the memory cell array in FIG. 15 will be described with reference to FIG. Figure 1
7 is a timing chart showing an example of a read operation in the memory cell array of FIG. This example shows a read operation when the memory cell MC11 in FIG. 15 is selected. First, at time tr1, the potentials of the word line WL1 and the dummy word line DWLB are set to VCH, the memory cell MC11 and the dummy cell DMCB1 are selected, and the cell transistors are made conductive. Next, at time tr2, the potential of the precharge control line PCN is set to VSS,
The VSS precharge to the data line pair DL1-DB1 is stopped and the floating state is set. Next, at time tr3, the potential of the precharge control line PCRB is set to VDD,
The potential of / PCRB is set to VSS and the data line DB1 is charged with the reference potential VRD.

The reference potential VRD is generated based on the potential VRR1 previously generated in the reference potential generating operation, and is supplied from the potential supply unit 104 shown in FIG. 1 and the like through the precharge potential supply line PCVRD. It is almost equal to VRR1. Further, the potentials of the plate line PL1 and the dummy plate line PLBB are set to VDD. At this time, the capacitor of the memory cell MC11 of FIG.
S voltage is applied. When the logic 0 is written in the memory cell MC11 of FIG. 15, the polarization of the memory cell capacitor is not inverted. Therefore, the signal potential VSD0 generated on the data line DL1 is expressed by the following equation, ignoring the noise component.

[Equation 3] However, the voltage-charge characteristic of the memory cell capacitor is assumed to be equivalent to that of the dummy cell capacitor. The waveform at this time is shown as DL1 (0) in FIG.

On the other hand, when the logic 1 is written in the memory cell MC11 in FIG. 15, the data line D
The signal potential VSD1 of L1 is expressed by the following equation.

[Equation 4] The waveform at this time is shown as DL1 (1) in FIG. Number 1
From Expression 4, the reference potential VRR1 generated in the reference potential generating operation is at the intermediate level between the signal potentials VSD0 and VSD1. Therefore, the reference potential VRD supplied here
Also becomes an intermediate potential between the signal potentials VSD0 and VSD1 and can be detected by comparing with the signal potential.

Here, considering the interference noise due to the parasitic capacitance between the data line DL1 and each driving line in the floating state in the floating state, the signal potential VSD0N and the signal potential VSD0N corresponding to the logic 0 generated on the data line DL1 and Logic 1
The signal potential VSD1N corresponding to is expressed by the following equation.

[Equation 5]

[Equation 6] Here, ΔVDBDL0 and ΔVDBDL1 represent the variation amount of the data line potential due to the reference potential charging to the data line DB1. Since the potentials of the precharge control lines PCRB and / PCRB fluctuate in the opposite directions, noise due to the influence is canceled. From Equations 2, 5 and 6, ΔVDBDL0,
Since the noise component excluding ΔVDBDL1 is the in-phase component, there is no problem in detecting the potential difference.

Next, at time tr4, the potential of the precharge control line PCRB is set to VSS and the potential of / PCRB is set to V.
Returning to DD, the data line DB1 is brought into a floating state. Next, at time tr5, the sense amplifier control line S
The potential of P is set to VDD and the sense amplifier SA1 is activated to amplify the potential difference of the data line pair DL1-DB1. Next, at time tr7, the potential of the plate line PL1 is set to VSS.
Return to. When the logic 1 is read, this operation inverts the polarization of the memory cell capacitor again, and rewriting is performed. The read information is output to the input / output line I / O by setting the potential of the column selection line YS1 to VDD and turning on the column selection switch YSW1 from time tr6 to tr7. During this time, a write signal can be given from the input / output line I / O to write information. Further, by switching the column selection lines and turning on different column selection switches, information of different column addresses can be continuously read.

Next, at time tr8, the potential of the sense amplifier control line SP is returned to VSS to inactivate the sense amplifier SA1, and the potential of the precharge control line PCN is changed to VDD.
Then, the precharge circuit TPN1 is turned on to set the potential of the data line pair DL1-DB1 to VSS. Further, the potential of the dummy plate line PLBB is returned to VSS and the capacitor of the dummy cell DMCB1 is discharged. Next, at time tr9, the potentials of the word line WL1 and the dummy word line DWLB are returned to VSS. With the above, the read operation is completed.

According to this embodiment, the reference potential can be generated and the information can be read by using the memory cell array including the dummy cell having the same element characteristic as the memory cell. Here, since the memory cell and the dummy cell have the same circuit configuration, it is possible to arrange them in a continuous layout pattern by making their structures and element sizes the same. As a result, dummy cell design and process condition setting become easy, and it becomes possible to generate a highly accurate reference potential by using a dummy cell with a small characteristic deviation from the memory cell. Further, the reference potential is generated by using the signal potentials corresponding to logic 1 and logic 0, and the polarization of the dummy cell capacitor is not inverted in the read operation, so that the fatigue of the ferroelectric film due to the concentrated access to the dummy cell can be reduced. .

FIG. 18 is a circuit configuration diagram showing a twelfth embodiment of the configuration of the ferroelectric memory of the present invention according to the present invention. The present embodiment shows a configuration of a memory cell array applicable to the present invention, in which adjacent data line pairs are independently driven, and adjacent data line pairs are partially arranged to intersect. However, this is different from the example shown in FIG. 18, sense amplifier control lines SP1, SN1 control sense amplifiers SA1, SA3, ..., Sense amplifier control lines SP2, SN2 are sense amplifiers SA2, SA4.
Control ... The precharge control line PCN1 supplies the potential VSS of the precharge potential supply line PCVSS to the data line pair DL1-DB1, DL3-DB3, ..., And the precharge control line PCN2 supplies the potential VSS to the data line pair DL.
Supply to 2-DB2, DL4-DB4, ....

The precharge control line PCRD1 supplies the reference potential VRD of the precharge potential supply line PCVRD to the data lines DL1, DL3, ..., And the precharge control line PRD.
CRD2 applies the reference potential VRD to the data lines DL2 and DL.
Supply to 4, ... Also, the precharge control line PCRB1
Supplies the reference potential VRD to the data lines DB1, DB3, ..., And the precharge control line PCRB2 supplies the reference potential VRD.
D is supplied to the data lines DB2, DB4, .... here,
The reference potential precharge switch SWPRD1 etc. is shown in FIG.
5 has the same configuration as that shown in FIG. 5, but is simplified in FIG. By adopting these configurations, it becomes possible to drive every other data line pair and independently control the adjacent data line pairs. In the memory cell array, adjacent data line pairs DL1-DB1 and DL2-D are also provided.
B2 is arranged by interchanging the data lines DB1 and DB2. Similarly, adjacent data line pairs DL3-DB3 and DL
Also in 4-DB4, the data lines DB3 and DB4 are replaced with each other. The same applies to the subsequent data line pairs.

One of the word lines WL1, WL2, WL3, ... And each data line pair has MC11, MC12,
A memory cell such as MC21 is connected. Further, the dummy word line DWLD and the data lines DL1, DL2, DL3, D
A dummy cell such as DMCD1 is connected to the intersection with L4, ...
Dummy cells such as DMCB1 are connected to the intersections of B2, DB3, DB4, .... The dummy cells connected to the dummy word line DWLD include plate lines PLDD and PLD.
Alternately connected to 1. For example, the dummy cell DMCD1
Is connected to the PLDD, and the dummy cell DMCD2 is connected to the PLD.
Connected to 1. The memory cells connected to the word line WL1 are alternately connected to the plate lines PLD1 and PL12. For example, the memory cell MC11 is connected to PL12, and the memory cell MC12 is connected to PLD1.
Similarly, the memory cells connected to the word line WL2 are alternately connected to the plate lines PL12 and PL23, the memory cells connected to the word line WL3 are alternately connected to the plate lines PL23 and PL34, and so on. The dummy cells connected to the dummy word line DWLB are alternately connected to the plate lines PLmB and PLBB.

An example of a planar layout for realizing the above memory cell array configuration is shown in FIG. FIG. 19 is a plan view showing a layout example of the memory cell array in FIG. In FIG. 19, cell transistors are formed in regions where the source / drain regions 6 surrounded by the element isolation regions 2 intersect the word lines 4. One of the source / drain regions of two adjacent cell transistors is commonly connected and connected to the data line 8 at the data line contact DLCT. The other is connected to the lower electrode 12 at each storage node contact STCT. A ferroelectric film is provided between the lower electrode 12 and the plate line 14, and a capacitor is formed in the overlapping portion. Some of the cells forming this memory cell array are used as dummy cells.

FIG. 20 shows an example of a sectional view taken along the line A-AA shown in FIG. 20 is a side sectional view showing a configuration example of a section of the memory cell array in FIG. The procedure for forming the memory cell array will be described with reference to FIG. First, an element isolation region 2 is formed on a semiconductor substrate 1 by a selective oxidation technique, a gate insulating film 3, a word line 4, an interlayer insulating film 5 and a source / drain region 6 are sequentially formed to form a cell transistor. Next, the contact plug 7 is formed on the storage node contact STCT. Next, the data line 8 is formed so as to be connected to the data line contact DLCT portion, and the interlayer insulating film 9 is formed thereon. Further, after the surface is flattened by the insulating film 10, the contact plug 11, the lower electrode 12 and the ferroelectric film 13 are formed. A plate line 14 which also serves as an upper electrode is formed thereon. As the material, for example, p-type silicon is used for the semiconductor substrate 1, n-type silicon is used for the source / drain regions 6, word lines 4, contact plugs 7, n-type polysilicon is used for the data lines 8, and insulating films 2, 3, 5 are used. , 9, 10
For the contact plug 11, tungsten for the contact plug 11, aluminum, tungsten or platinum for the plate line 14, conductive oxide such as platinum or ruthenium oxide for the lower electrode 12, and PZT for the ferroelectric film 13.
Etc. are used.

Next, the reference potential generating operation in the memory cell array of FIG. 18 will be described. FIG. 21 is a timing chart showing an example of reference potential generation operation in the memory cell array of FIG. In this figure, the data line pair DL1
DB1 is driven as in FIG. Therefore, the sense amplifier control line SP1 performs the same operation as the sense amplifier control line SP shown in FIG.
The CN1 operates similarly to the precharge control line PCN shown in FIG. However, the data line pair DL1-DB1
The potential of the data line pair DL2-DB2 adjacent to is maintained at the same VSS as in the standby state. Therefore, the potential of the sense amplifier control line SP2 is VSS, the precharge control line PCN
The potential of 2 is fixed to VDD. By performing such an operation, the driven data line is sandwiched between the data lines fixed to the potential VSS. Therefore, most of the parasitic capacitance between the data lines can be regarded as the ground capacitance, and the interference noise between the data lines can be significantly reduced.

Reference potential VRR generated by this operation
1ND is represented by the following formula.

[Equation 7] Here, VRR1D is a reference potential excluding the interference noise component, and the data line capacitance including the data line capacitance is CDLD.
In other words, it is expressed by the following formula.

[Equation 8] On the other hand, as for the memory cell and the dummy cell connected to the data line pair DL2-DB2 which is not driven, there is no one in which the word line and the plate line are simultaneously selected. Therefore, almost no voltage is applied to the cell capacitor, and there is no possibility that information will be destroyed by polarization reversal.

Next, the read operation of the memory cell array in FIG. 18 will be described. 22 is a timing chart showing an example of a read operation in the memory cell array of FIG. Even in the case shown in this figure, the data line pair D
L1-DB1 is driven in the same manner as in FIG. 17, and the data line pair D
The potential of L2-DB2 is maintained at the same VSS as in the standby state. Therefore, the potential of the sense amplifier control line SP2 is VS
The potentials of S and the precharge control line PCN2 are fixed to VDD. Logic 0 and logic 1 generated by this operation
Signal potentials VSD0ND and VSD1ND corresponding to
Are respectively expressed by the following equations.

[Equation 9]

[Equation 10]

Here, VSD0D and VSD1D are
The signal potentials correspond to logic 0 and logic 1 excluding the interference noise component, respectively, and are represented by the following equations using the CDLD described above.

[Equation 11]

[Equation 12] The precharge control line PCRB1 is driven symmetrically with the pair of precharge control lines / PCRB1 (not shown in FIG. 18) as in FIG. 15, so that noise due to the influence thereof is canceled. From the equations (7), (9) and (10), since the interference noise component is the in-phase component, there is no problem in detecting the potential difference. According to this embodiment, the interference noise due to the parasitic capacitance between the data lines can be significantly reduced, and the operation with higher reliability can be performed. Moreover, since half of the data lines are not driven, power consumption can be reduced.

FIG. 23 is a circuit diagram showing a thirteenth embodiment of the ferroelectric memory of the present invention according to the present invention. The present embodiment shows a configuration of a memory cell array applicable to the present invention, in which the plate electrode of the memory cell is not separated as a plate line and is set to a constant potential in the middle of High and Low, and at the time of standby. It differs from the example shown in FIG. 15 in that the data line potential is the constant potential.
In FIG. 23, the memory cell MH11 connected to the word line WL1 and the data line DL1 and the memory cell MH12 connected to the word line WL1 and the data line DL2 are similar to the memory cell MC11 and the like shown in FIG. A circuit configuration can be applied, and each plate electrode is commonly connected to a voltage source (not shown in the figure) that generates a plate potential VPL. The potential VPL is a constant potential intermediate between the potential VDD and the potential VSS.

Here, the polarization directions of the ferroelectric capacitors of the memory cells MH11, MH12, etc. are VDD and V.
It can be controlled by the potential difference between PL and the potential difference between VPL and VSS. On the other hand, the dummy word line DWLD
, And the dummy cells DMCD1, DMCD2, ... Connected to the plate lines PLDD, the dummy word lines DWLB and the data lines DB1,
Dummy cells DMCB1, DMC connected to DB2, ...
B2, ... Are connected to the plate line PLBB. The precharge circuits TPN1, TPN2, ... Controlled by the precharge control line PCN are connected to the precharge potential supply line PCVPL that supplies the plate potential VPL.
Further, the precharge circuits TPR1, TPR2, ... Controlled by the precharge control line PCRR have the potential VSS.
Is connected to a precharge potential supply line PCVSS for supplying The precharge circuits TPN1, TPN2, ... Are activated during standby, and the precharge circuits TPR1, TPR1
PR2, ... Are used for the VSS precharge operation during the read operation.

A planar layout that realizes such a memory cell array configuration will be described. FIG. 24 is a plan view showing a layout example of the memory cell array in FIG. The layout of FIG. 24 is basically the same as that of FIG.
The same pattern is used, but the plate electrode is not separately processed as a plate line, and the memory cell plate 15
And the dummy plate line 16 are separated from each other.
As a result, the memory cells and the dummy cells can be laid out as a continuous pattern. Further, when an unused cell is inserted between the memory cell portion and the dummy cell portion, there is a margin in terms of plate separation processing accuracy, which is advantageous for device miniaturization.

A method of holding the state and information when the memory cell MH11 or the like is not selected will be described below with reference to the circuit configuration example shown in FIG. First, in order to hold the polarization information of the memory cell in the standby state, the junction leakage current of the reverse biased diode DS11 is supplied through the leakage resistance RF11 and the subthreshold leakage current of the cell transistor TR11, that is, the steady state. , The potential of the storage node SN11 is almost VPL, and the potential difference between the storage node SN11 and the plate electrode PLC at this time causes the ferroelectric capacitor CF
It suffices that information destruction due to polarization inversion 11 does not occur.
The memory cell may be formed using an element having a characteristic capable of maintaining this state.

Here, assuming that the potential of the data line DL1 in the standby state is VPL, the storage node S in the steady state is
The potential of N11 is determined by the ratio of the parallel combined resistance of the leak resistance RF11 and the off resistance Roff of the cell transistor TR11 to the resistance of the diode DS11. Generally, the reverse bias resistance of the diode DS11 can be made sufficiently higher than the above-mentioned parallel combined resistance. In addition, due to noise generated in the word line WL1 in that state, the transistor TR
Even if 11 is turned on, no voltage is applied to the ferroelectric capacitor CF11, so that the noise of the word line becomes strong. Therefore, by holding the standby data line potential at VPL, it becomes easy to retain information.

On the other hand, when the data line DL1 is driven during operation, the off resistance Roff changes to the leak resistance RF11.
Of the ferroelectric capacitor CF, which is sufficiently higher than that of the ferroelectric capacitor CF,
If the time constant for charging 11 is sufficiently larger than the operation time and almost no voltage is applied to the ferroelectric capacitor CF11 during operation, information will not be destroyed. further,
If the leak resistance RF11 is sufficiently higher than the on resistance Ron of the cell transistor TR11, a sufficiently large voltage is applied to the ferroelectric capacitor CF11 during selection. Information is stably held by realizing the element characteristics of the memory cell that satisfy the above-described relationship.

Next, the reference potential generating operation of the memory cell array in FIG. 23 will be described. FIG. 25 is a timing chart showing an example of reference potential generation operation in the memory cell array of FIG. During standby, the potential of the precharge control line PCN is VDD and the potential of PCRR is VSS, and the potential VPL is supplied to each data line pair. Further, since the potential of the sense amplifier control line SP is VSS and the potential of SN is VDD, the transistors of each sense amplifier are not conductive even if the potential of the data line is VPL. Furthermore, the potentials of the plate lines PLDD and PLBB are VSS.
Is. The reference potential generating operation is roughly classified like the example shown in FIG. That is, first, a logical 1 is written in one of the paired dummy cells and a logical 0 is written in the other dummy cell (time tdh1
To tdh3), secondly a reference potential is generated in the data line (time tdh4 to tdh6), and thirdly, the polarization direction of the dummy cell capacitor is reset (time tdh7 to tdh).
8). This will be described in detail below.

First, at time tdh1, the potential of the precharge control line PCN is set to VSS and the data line pair DL1
-Stop VPL precharge to DB1. Further, the potentials of the dummy word lines DWLD and DWLB are set to VCH, the potentials of the dummy plate lines PLDD and PLBB are set to VPL, the dummy cells DMCD1 and DMCB1 are selected, and the cell transistors are turned on. Further, the potential of the sense amplifier control line SP is set to VDD and the potential of SN is set to VSS,
The sense amplifier SA1 is activated. Then, one potential of the data line pair DL1-DB1 is VDD and the other potential is V
It becomes SS and becomes a steady state. At this time, a logic 0 is written in the dummy cell connected to the data line on the potential VSS side, and a logic 1 is written in the dummy cell connected to the data line on the potential VDD side.

Next, at time tdh2, the potential of the sense amplifier control line SP is set to VSS and the potential of SN is set to VDD to deactivate the sense amplifier SA1. In addition, the precharge control line PCN and the data line short circuit control line DL
The potential of SH is set to VDD and the data line pair DL1-DB1
The potential of is returned to VPL and short-circuited. Next, at time tdh3, the potentials of the dummy word lines DWLD and DWLB are set to V
Return to SS and turn off the cell transistor. The states of the dummy cells DMCD1 and DMCB1 at this time are equal to the states of the memory cells storing logic 1 or logic 0. Next, at time tdh4, the potential of the precharge control line PCN is set to VSS, the potential of PCRR is set to VDD, and the potential of the data line pair DL1-DB1 is set to VSS. Next, at time tdh5, the potential of the precharge control line PCRR is set to VSS and the data line pair DL1-DB1 is brought into a floating state. Then, at time tdh6, the potentials of the dummy word lines DWLD and DWLB are set to VCH.
At this time, a voltage of approximately VPL-VSS is applied to the capacitors of the dummy cells DMCD1 and DMCB1.

Reference potential VRR generated by this operation
1NH is represented by the following formula.

[Equation 13] In Expression 13, −ΔVPCRR represents the variation amount of the data line potential due to the potential decrease of the precharge control line PCRR. Further, ΔVWLT represents the variation amount of the data line potential due to the rise of the word line potential due to the parasitic capacitance at the intersection where the dummy cells are connected. Furthermore, ΔVWLB
Represents the variation amount of the data line potential due to the rise of the word line potential due to the parasitic capacitance at the intersection where the dummy cells are not connected. Furthermore, VRR1H is the reference potential excluding the interference noise component, and the charge that flows in with polarization inversion is Δ
If Qrh is given, it is expressed by the following equation.

[Equation 14]

When the reference potential is stored, at time tdh7, the potential of the data line short circuit control line DLSH is set to VSS, the data line short circuit switch is turned off, and the potential of the precharge control line PCN is set to VDD to set the data line pair. DL1-DB1 is charged with the potential VPL. Further, the potentials of the dummy plate lines PLDD and PLBB are returned to VSS. As a result, the polarization of the dummy cell capacitor is reset. Next, at time tdh8, the potentials of the dummy word lines DWLD and DWLB are returned to VSS. With the above, the reference potential generating operation is completed.

Next, the read operation of the memory cell array in FIG. 23 will be described. FIG. 26 is a timing chart showing an example of a read operation in the memory cell array of FIG. In this example, the memory cell MH1 in FIG.
This shows the read operation when 1 is selected. First time tr
At h1, the potential of the precharge control line PCN is set to VS.
S, the potential of the precharge control line PCRR is set to VDD, and the potential of the data line pair DL1-DB1 is precharged to VSS. Next, at time trh2, the potential of the precharge control line PCRR is returned to VSS, and the data line pair D
L1-DB1 is put in a floating state. Then at time t
At rh3, the potentials of the word line WL1 and the dummy word line DWLB are set to VCH, and the memory cells MH11,
The dummy cell DMCB1 is selected to make the cell transistor conductive.

Further, the potential of the precharge control line PCRB is set to VDD, and the data line DB1 is charged with the reference potential VRDH supplied from the potential supply means 104 shown in FIG. Logic 0 and logic 1 generated by this operation
Signal potentials VSD0NH and VSD1NH corresponding to
Are respectively expressed by the following equations.

[Equation 15]

[Equation 16] Here, ΔVDBDL0H and ΔVDBDL1H represent the variation amount of the data line potential due to the reference potential charging to the data line DB1. Further, VSD0H and VSD1H are signal potentials corresponding to logic 0 and logic 1 excluding the interference noise component, and are respectively represented by the following equations.

[Equation 17]

[Equation 18] The precharge control line PCRB is paired with the precharge control line / PCRB (not shown in FIG. 23) as in FIG.
Since it is driven symmetrically with, noise due to the influence is canceled. From Equations 13, 15 and 16, ΔVDBDL0H,
Since the noise component excluding ΔVDBDL1H is the in-phase component, there is no problem in detecting the potential difference. ΔVDB
As for DL0H and ΔVDBDL1H, for example, FIG.
By applying a configuration similar to that, it is possible to remove the effect.

Next, at time trh4, the potential of the precharge control line PCRB is returned to VSS, and the data line DB
Float 1 Next, at time trh5, the potential of the sense amplifier control line SP is set to VDD and SN is set.
Is set to VSS to activate the sense amplifier SA1 to amplify the potential difference between the data line pair DL1-DB1. Rewriting is automatically performed by the amplification. The read information is the column selection line YS at times trh6 to trh7.
The potential of 1 is set to VDD and the column selection switch YSW1 is turned on to output to the input / output line I / O.

Next, at time trh8, the potential of the sense amplifier control line SP is returned to VSS and the potential of SN is returned to VDD to deactivate the sense amplifier SA1, and the potential of the precharge control line PCN is returned to VDD to precharge. Circuit T
PN1 is turned on to return the potential of the data line pair DL1-DB1 to VPL. Next, at time trh9, the potentials of the word line WL1 and the dummy word line DWLB are returned to VSS. With the above, the read operation is completed. in action,
The potential of the dummy plate line PLBB is fixed to VSS. On the other hand, the potential of the data line DB1 is VDD and VS.
It is between S. Therefore, the direction of the voltage applied to the capacitor of the dummy cell DMCB1 does not reverse, and the problem of film fatigue due to polarization reversal does not occur. According to this embodiment, since it is not necessary to perform microfabrication of the plate electrode as a plate line, a large number of plate line driving circuits are not required, and the yield reduction due to plate line processing is suppressed, which is suitable for high integration. A memory cell array can be configured.

FIG. 27 is a circuit diagram showing a fourteenth embodiment of the ferroelectric memory according to the present invention according to the present invention. This embodiment shows a configuration of a memory cell array applicable to the present invention, in which a column selection switch is provided between the memory cell array and the sense circuit, and the sense circuit is shared by a plurality of data line pairs. 23, which is different from the example shown in FIG. 27, the configurations and connections of the memory cells and the dummy cells are the same as those in the example shown in FIG. Precharge circuits TPN1 and TPN2 for supplying the potential VPL
Are separate precharge control lines PCN1 and PCN
Controlled by 2. However, it is not necessary to provide individual control lines for all precharge circuits. For example, the following FIG.
As shown in, it is sufficient that at least the sense amplifier SA01 (sense circuit) as the information sensing unit according to the present invention is shared and the precharge operation of the adjacent data line pair can be independently controlled.

FIG. 28 is a circuit diagram showing a fifteenth embodiment of the ferroelectric memory according to the present invention according to the present invention. As shown in FIG. 28, in order to control the precharge operation of the data line pair which shares the sense amplifier SA01 (sense circuit) and is adjacent, the precharge circuit TPN1 as the data line potential fixing unit of the present invention. , TPN2
TPN3, TPN4, ... Are connected to the precharge control line PCN
It is effective to have a configuration in which the PCN1 and the PCN2 are alternately connected.

The operation of the memory cell array of FIG. 27 according to the present invention will be described below. In FIG. 27, data line pairs DL1-DB1, DL2-DB2, ...
Select the sensing signal line pair DL01-D by SW2, ...
It is connected to B01. Sensing signal line pair DL01-DB01
To the sense amplifier SA01, the potential VSS precharge circuit TPR01, the reference potential VRD precharge switches SWPRD01 and SWPRB01, the data line short-circuit switch SWDS01, and the voltage follower U.
GB01 is a data line pair DL1-DB1, DL2-DB
2, ... is shared. The column selection switch YSW01 is controlled by the column selection line YS01, and the sensing signal line pair DL01.
-Connect and disconnect DB01 and I / O lines.

The reference potential generating operation of the memory cell array in FIG. 27 will be described. FIG. 29 is a timing chart showing an example of reference potential generation operation in the memory cell array of FIG. The example shown in FIG. 29 is that the potential of the unselected data line pair DL2-DB2 adjacent to the selected data line pair DL1-DB1 is fixed to VPL, and the example shown in FIG.
Different from the example shown in. During standby, the potential of the precharge control line PCRR is VDD, and the sensing signal line pair DL
The potential VSS is supplied to 01-DB01. The potentials of the sense amplifier control lines SN and SP are both VSS. The potentials of the other parts are the same as those in the example shown in FIG.

First, at time tdc1, the potential of the precharge control line PCN1 is set to VSS and the data line pair DL
1-Stop VPL precharge to DB1. At the same time, the potential of the precharge control line PCRR is also set to VSS to stop the VSS precharge to the sensing signal line pair DL01-DB01. Also, the dummy word lines DWLD, D
The potential of WLB is set to VCH, the dummy plate line PLDD,
The potential of PLBB is set to VPL and the dummy cell DMCD
1, DMCB1 is selected and the cell transistor is turned on. Further, the potential of the sense amplifier control line SP is set to VDD, the sense amplifier SA1 is activated, and the column selection line Y
The potential of S1 is set to VCH and the sensing signal line pair DL01-D
B01 is connected to the data line pair DL1-DB1.

At this time, one of the data line pairs DL1-DB1 has the potential VSS and the other has the potential VDD, a logic 0 is written in the dummy cell connected to the data line on the potential VSS side, and the dummy line connected to the data line on the potential VDD side writes to the data line on the potential VDD side. Logic 1 is written in the connected dummy cell. Next, at time tdc2,
The potential of the sense amplifier control line SP is set to VSS and the sense amplifier SA1 is deactivated. In addition, the column selection line YS
The potential of 1 is set to VSS and the sensing signal line pair DL01-DB
01 and the data line pair DL1-DB1 are separated. further,
The potentials of the precharge control lines PCN1 and PCRR and the data line short circuit control line DLSH are set to VDD, the potentials of the data line pair DL1-DB1 are set to VPL, and the sensing signal line pair DL0 is set.
The potential of 1-DB01 is returned to VSS and short-circuited. Next, at time tdc3, the dummy word lines DWLD, DWL
The potential of B is returned to VSS and the cell transistor is turned off. The states of the dummy cells DMCD1 and DMCB1 at this time are equal to the states of the memory cells storing logic 1 or logic 0.

Next, at time tdc4, the potential of the precharge control line PCN1 is set to VSS and the potential of the column selection line YS1 is set to VCH, and the precharge potential VSS of the sensing signal line pair DL01-DB01 is set to the data line pair DL1-DB1. Supply to. Next, at time tdc5, the potential of the precharge control line PCRR is set to VSS and the data line pair DL1
-Floating DB1. And time td
At c6, the potentials of the dummy word lines DWLD and DWLB are set to VCH. At this time, the reference potential is generated as described in the description of FIG. However, data line pair D
Since the potential of the data line pair DL2-DB2 adjacent to L1-DB1 is fixed at VPL, the parasitic capacitance between the two can be regarded as a part of the data line-to-ground capacitance.

When the reference potential is stored, the potential of the data line short-circuit control line DLSH is set to VSS at time tdc7 and the data line short-circuit switch is turned off. In addition, the potential of the column selection line YS1 is set to VSS, and the sensing signal line pair DL01
-DB01 and the data line pair DL1-DB1 are separated, and the potentials of the precharge control lines PCN1 and PCRR are set to V
Set to DD, and the potential V is applied to the sensing signal line pair DL01-DB01.
The SS is charged to the potential VPL on the data line pair DL1-DB1. Further, the potentials of the dummy plate lines PLDD and PLBB are returned to VSS. As a result, the polarization of the dummy cell capacitor is reset. Next, at time tdc8, the potentials of the dummy word lines DWLD and DWLB are set to VSS.
Return to.

With the above, the reference potential generating operation is completed. In the above operation, the sensing signal line pair DL01-DB
The potential of the data line pair DL2-DB2 or the like not connected to 01 is fixed to VPL or becomes a floating state after VPL precharge, and the potential of the data line pair DL2-DB2 adjacent to the data line pair DL1-DB1 is fixed to VPL. It Therefore, almost no voltage is applied to the capacitors of the memory cells connected to them, and the word line selection and
Information is not destroyed regardless of non-selection. In particular, in the precharge circuit configuration shown in FIG. 28, the potential of the unselected data line pair adjacent to the selected data line pair can be efficiently fixed by the two precharge control lines PCN1 and PCN2.

Next, the read operation of the memory cell array in FIG. 27 will be described. FIG. 30 is a timing chart showing an example of the read operation in the memory cell array of FIG. In this example, the unselected data line pair DL2-
It differs from the example shown in FIG. 26 in that the potential of DB2 is fixed to VPL. First, at time trc1, the potential of the precharge control line PCN1 is set to VSS, and the column selection line YS1
Potential of VCH is set to VCH, and sensing signal line pair DL01-DB0
1 precharge potential VSS to the data line pair DL1-DB
Precharge to 1. Next, at time trc2, the potential of the precharge control line PCRR is set to VSS, and the data line pair DL1-DB1 is brought into a floating state. Next, at time trc3, the potentials of the word line WL1 and the dummy word line DWLB are set to VCH, and the memory cell MH
11. Select the dummy cell DMCB1 to turn on the cell transistor.

Further, the potential of the precharge control line PCRB is set to VDD and the reference potential is charged to the data line DB1. At this time, a signal potential equivalent to that described in FIG. 26 is generated on the data line DL1. Next, at time trc4,
The potential of the precharge control line PCRB is returned to VSS,
The data line DB1 is put in a floating state. Next, at time trc5, the potential of the sense amplifier control line SP is set to V
It is set to DD and the sense amplifier SA1 is activated to amplify the potential difference of the data line pair DL1-DB1. Rewriting is automatically performed by the amplification. The read information is output to the input / output line I / O by setting the potential of the column selection line YS01 to VDD and turning on the column selection switch YSW01 during the time trc6 to trc7.

Next, at time trc8, the potential of the sense amplifier control line SP is returned to VSS and the sense amplifier SA1
Deactivate. In addition, the potential of the column selection line YS1 is set to VSS.
, The sense signal line pair DL01-DB01 and the data line pair DL1-DB1 are separated, the potentials of the precharge control lines PCN1 and PCRR are set to VDD, and the potential VSS is applied to the sense signal line pair DL01-DB01. Line pair D
L1-DB1 is charged with the potential VPL. Next time trc
9, the word line WL1 and the dummy word line DW
The potential of LB is returned to VSS. With the above, the read operation is completed. During operation, the potential of the dummy plate line PLBB is fixed at VSS, while the potential of the data line DB1 is between VDD and VSS. Therefore, similarly to the example of FIG. 26, the direction of the voltage applied to the capacitor of the dummy cell DMCB1 does not reverse, and the problem of film fatigue due to polarization reversal does not occur.

Further, as described in the example of FIG. 29, the potential of the data line pair DL2-DB2 not connected to the sensing signal line pair DL01-DB01 is fixed to VPL or becomes a floating state after VPL precharge, and particularly Data line pair DL adjacent to line pair DL1-DB1
The potential of 2-DB2 is fixed at VPL. Therefore, almost no voltage is applied to the capacitors of the memory cells connected to them, and information is not destroyed regardless of selection / non-selection of word lines.

According to this embodiment, the circuit area can be reduced and the layout margin of the sense circuit can be relaxed by sharing the sense circuit. In addition to this, since only a necessary portion of the memory cell array is operated, noise such as power consumption and power supply can be significantly reduced. Furthermore, it is possible to reduce unnecessary polarization reversal of the ferroelectric capacitor in the non-selected memory cell, so that it is possible to reduce the characteristic deterioration of the ferroelectric film.

FIG. 31 is a circuit diagram showing a sixteenth embodiment of the ferroelectric memory of the present invention according to the present invention. In the present embodiment, the reference potential is indirectly generated in the data line by adjusting the dummy plate line potential, and this dummy plate line potential is stored as information for reproducing the reference potential. Different from the described embodiment. In FIG. 31, the dummy plate line potential generator 1
Reference numeral 07 includes a pull-up transistor MDD, a pull-down transistor MSS, a comparator CMPR, and a dummy plate line potential control unit PLCTL.

In the memory cell array 105, when the dummy word line DWLB is driven and the dummy cell DMCB1 is selected, the potential of the dummy plate line PLBB is adjusted by the transistors MDD and MSS.
The potential of B1 also changes. The potential of this data line DB1,
The comparator CMPR compares the reference potential generated by the reference potential generator 102 with the reference potential, and obtains the potential of the dummy plate line PLBB where they are equal. In this example,
The potential of the dummy plate line PLBB is adjusted between VCH and VSS, but the adjustment range can be changed by changing the potential of the power supply connected to the pull-up transistor MDD and the pull-down transistor MSS.

When the potential of the dummy plate line PLBB is determined, the potential storage control unit M of the controller 106 is provided.
The potential storage unit 103 is controlled by MCTL to store the dummy plate potential. During the read operation, the dummy plate line potential stored in the potential storage unit 103 is
The potential supply unit 104 supplies the potential to the plate driver PLDRV, and the plate driver PLDRV drives the dummy plate line PLBB. When the circuit similar to that of FIG. 23 is applied to the memory cell array 105, the operation of generating the potential of the dummy plate line will be described using the operation waveform example of FIG.

FIG. 32 is a timing chart showing an example of the dummy plate line potential generation operation of the ferroelectric memory shown in FIG. At time tdd1, the potential of the precharge control line PCN is set to VSS and the potential of PCRR is set to VDD.
Then, the potential of the data line DB1 is set to VSS, and the potentials of the dummy word lines DWLD and DWLB are set to VCH.
At this time, since the potential of the dummy plate line PLBB is VPL, the dummy cell DMCB1 is set to the state storing the logic 0. Next, at time tdd2, the potential of the precharge control line PCRR is set to VSS and the potential of PCN is set to V
The potential of the data line DB1 is returned to VPL by setting to DD, and at time tdd3, the dummy word lines DWLD, DWL
The potential of B is returned to VSS. Next, at time tdd4,
Again, the potential of the precharge control line PCN is set to VSS, PC
The potential of RR is VDD and the potential of data line DB1 is V
The voltage is set to SS, the pull-up transistor MDD is turned on, and the potential of the dummy plate line PLBB is set to VCH. Next, at time tdd5, the precharge control line P
The potential of CRR is set to VSS and the data line DB1 is brought into a floating state.

Next, at time tdd6, the potentials of the dummy word lines DWLD and DWLB are set to VCH. This time,
Since the potential of the dummy plate line PLBB is boosted to VCH, the potential of the data line DB1 becomes higher than the signal potential corresponding to logic 0. That is, if the line noise is ignored, the potential VPU1 represented by the following equation is generated on the data line DB1.

[Formula 19] Next, at time tdd7, the pull-down transistor M
The potential of the dummy plate line PLBB is set to VSS by SS.
Fluctuate toward.

At this time, from the equation (19), the variation amount ΔVDB1 of the data line potential is equal to the variation amount ΔVP of the dummy plate line potential.
It is expressed as follows using LBB.

[Equation 20] The data line capacitance CDL is the capacitance C of the memory cell capacitor.
Since it is several times larger than F11N, ΔVDB1 is ΔVPL
Smaller than BB. The potential of the data line DB1 is compared with the reference potential VRR1 generated by the reference potential generation unit 102 by the comparator CMPR, and when both have substantially the same value (time tdd8), the pull-down transistor MSS is cut off. The dummy plate line potential VRP at this time is
It is stored in the potential storage unit 103.

Next, at time tdd9, the potential of the precharge control line PCN is set to VDD and the potential of the data line DB1 is returned to VPL. In addition, the dummy plate line PLBB
The potential of is also set to VPL. Thereby, the dummy cell DMC
The voltage across the capacitor of B1 is approximately 0V. Finally, at time tdd10, the dummy word lines DWLD,
The potential of DWLB is returned to VSS and the dummy cell transistor is turned off. With the above, the dummy plate line potential generation operation is completed.

Next, the read operation will be described. FIG. 33 is a timing chart showing an example of the read operation of the ferroelectric memory shown in FIG. The read operation is performed by the same procedure as that shown in FIG. 26 except for the generation process of the reference potential VRD. The potential of the dummy plate line PLBB is VPL during standby. Dummy word line DW
Before the potential of LB is driven to VCH, that is, time tr
At d1, the potential of the dummy plate line PLBB is set to the potential VRP stored in the potential storage section. Time t
At rd3, the potential of the dummy word line DWLB is VCH
When driven to, the reference potential VRD is generated on the data line DB1.

At time trd4, the sense amplifier SA
When 1 is activated and the potential difference of the data line pair DL1-DB1 starts to be amplified, the potential of the dummy plate line PLBB is changed to VDD so that the polarization of the capacitor of the dummy cell DMCB1 is not inverted. At time trd7, when the potential of the data line DB1 is returned to VPL, the potential of the dummy plate line PLBB is also set to VPL to discharge the dummy cell capacitor, and then at time trd8, the potential of the dummy word line DWLB is returned to VSS and the dummy cell transistor Turn off.

According to the embodiments shown in FIGS. 31 to 33, the reference potential is generated in the data line via the dummy plate line, so that the potential of the potential supplied from the potential supply unit to the memory cell array changes. The effect is smaller than the method of directly charging the data line with the reference potential. Therefore, the tolerance of the reference potential generator is large, and more reliable read operation is possible.

Although the concept of the present invention has been described above with reference to the embodiments, the basic concept of the present invention, that is, the reference potential generating section, the storage section, and the potential supply section are provided and stored in the storage section in the read operation. The concept of supplying the potential reproduced by the information supplied to the memory cell array from the potential supply unit and applying the reference potential to the data line is not limited to the above embodiment, and for example, a reverse polarity transistor is used. Modifications such as configuring the circuit and inverting the vertical relationship of the voltages may be made. Further, for example, a memory cell and a dummy cell formed only by a ferroelectric capacitor, a sense circuit formed by using a source-coupled differential amplifier, or the like may be used for the memory cell and the dummy cell or the sense circuit. The concept of the present invention is applicable.

[0107]

According to the present invention, it is possible to construct a nonvolatile ferroelectric memory that is easy to manufacture, highly reliable, and suitable for high integration.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a configuration according to the present invention of a ferroelectric memory of the present invention.

FIG. 2 is a circuit configuration diagram showing a configuration example of a memory cell in FIG.

FIG. 3 is a flowchart showing an operation example of the ferroelectric memory in FIG. 1 according to the present invention.

FIG. 4 is a circuit configuration diagram showing a second embodiment of the configuration of the ferroelectric memory of the present invention according to the present invention.

FIG. 5 is a circuit configuration diagram showing a third embodiment of the configuration related to the present invention of the ferroelectric memory of the present invention.

FIG. 6 is a circuit configuration diagram showing a fourth embodiment of the configuration of the ferroelectric memory of the present invention according to the present invention.

7 is a circuit configuration diagram showing a first configuration example of a reference potential averaging unit in FIG.

8 is a circuit configuration diagram showing a second configuration example of the reference potential averaging unit in FIG.

FIG. 9 is a circuit configuration diagram showing a fifth embodiment of the configuration of the ferroelectric memory of the present invention according to the present invention.

FIG. 10 is a circuit configuration diagram showing a sixth embodiment of the configuration of the ferroelectric memory of the present invention according to the present invention.

FIG. 11 is a circuit configuration diagram showing a seventh embodiment of the configuration of the ferroelectric memory of the present invention according to the present invention.

FIG. 12 is a circuit configuration diagram showing an eighth embodiment of the configuration of the ferroelectric memory of the present invention according to the present invention.

FIG. 13 is a circuit configuration diagram showing a ninth embodiment of the configuration of the ferroelectric memory of the present invention according to the present invention.

FIG. 14 is a circuit configuration diagram showing a tenth embodiment of the configuration of the ferroelectric memory of the present invention according to the present invention.

FIG. 15 is a circuit configuration diagram showing an eleventh embodiment of the configuration according to the present invention of the ferroelectric memory of the present invention.

16 is a timing chart showing an example of a reference potential generating operation in the memory cell array of FIG.

17 is a timing chart showing an example of a read operation in the memory cell array of FIG.

FIG. 18 is a circuit configuration diagram showing a twelfth embodiment of the configuration of the ferroelectric memory of the present invention according to the present invention.

19 is a plan view showing a layout example of the memory cell array in FIG.

20 is a side sectional view showing a configuration example of a section of the memory cell array in FIG.

FIG. 21 is a timing chart showing an example of reference potential generation operation in the memory cell array of FIG.

22 is a timing chart showing an example of a read operation in the memory cell array of FIG.

FIG. 23 is a circuit configuration diagram showing a thirteenth embodiment of the configuration of the ferroelectric memory of the present invention according to the present invention.

FIG. 24 is a plan view showing a layout example of the memory cell array in FIG. 23.

FIG. 25 is a timing chart showing an example of reference potential generation operation in the memory cell array of FIG. 23.

FIG. 26 is a timing chart showing an example of a read operation in the memory cell array of FIG.

FIG. 27 is a circuit configuration diagram showing a fourteenth embodiment of the configuration of the ferroelectric memory of the present invention according to the present invention.

FIG. 28 is a circuit configuration diagram showing a fifteenth example of the configuration of the ferroelectric memory according to the present invention according to the present invention.

FIG. 29 is a timing chart showing an example of reference potential generation operation in the memory cell array of FIG. 27.

30 is a timing chart showing an example of a read operation in the memory cell array of FIG. 27.

FIG. 31 is a circuit configuration diagram showing a sixteenth example of the configuration of the ferroelectric memory of the present invention according to the present invention.

32 is a timing chart showing an example of a dummy plate line potential generation operation of the ferroelectric memory in FIG.

33 is a timing chart showing an example of a read operation of the ferroelectric memory shown in FIG.

FIG. 34 is an explanatory diagram showing voltage-charge characteristics of a ferroelectric capacitor.

FIG. 35 is a circuit configuration diagram showing a configuration of a conventional ferroelectric memory.

FIG. 36 is a circuit configuration diagram showing a configuration of a ferroelectric memory using a conventional dummy cell.

FIG. 37 is a circuit configuration diagram showing a configuration of a conventional ferroelectric memory that generates a reference potential by utilizing polarization inversion.

FIG. 38 is a circuit configuration diagram showing a configuration of a conventional ferroelectric memory in which two adjacent pairs of data lines share a dummy cell to generate a reference potential.

[Explanation of symbols]

 1 semiconductor substrate 2 element isolation insulating film 3 gate insulating film 4 word line 5,9 interlayer insulating film 6 source / drain diffusion region 7,11 contact plug 8 data line 10 flattening insulating film 12 lower electrode 13 ferroelectric film 14 plate Line 15 Memory cell plate 16 Dummy plate line 101 Reference potential generation unit 102 Reference potential generation unit 103 Potential storage unit 104 Potential supply unit 105 Memory cell array 106 Controller MC11 Memory cell DMCB1 Dummy cell WL1 Word line DWLB Dummy word line DL1, DB1 Data line SA1 Sense amplifier SWDS1 Data line short circuit switch UGB1 Voltage follower SWPRB1 Reference potential precharge switch TPN1 Precharge circuit YSW1 Column selection switch PL1 Plate line SP, SN sensor Amplifier control line PCN, PCRB, / PCRB Precharge control line PCVSS, PCVRD Precharge potential supply line DLSH Data line Short circuit control line I / O I / O line TR11 Cell transistor CF11 Ferroelectric capacitor STCT Storage node contact part DLCT Data line contact Department.

Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical indication location H01L 27/10 451 7210-4M 21/8247 29/788 29/792 H01L 29/78 371 (72) Inventor Horiguchi Masashi 1-280, Higashi Koigokubo, Kokubunji City, Tokyo (72) Inventor, Jun Central Research Institute, Ltd. Jun Eto 1-280, Higashi Koikeku, Tokyo Kokubunji City, Central Research Laboratory, Hitachi, Ltd. (72) Inventor Masakazu Aoki Tokyo Kokubunji Temple 1-280, Koigokubo, Higashi-shi, Hitachi Central Research Laboratory

Claims (17)

[Claims] 1. A memory cell array comprising a plurality of memory cells for storing a logic "1" or a logic "0" by using polarization of a ferroelectric capacitor, and the logic "1" and the logic "0" of the memory cell. And a reference potential generating means for generating a reference potential in the middle of the signal potential corresponding to the reference potential generating means, and the reference potential generating means generates the reference potential when the logic "1" or logic "0" written in the memory cell is read. In a ferroelectric memory that outputs, as information, either the logic "1" or the logic "0" stored in the memory cell based on the difference between the reference potential and the signal potential generated by the memory cell. The reference potential generating means previously has a signal potential corresponding to the logic “1” and a logic “0”.
Reference potential generating means for generating the reference potential based on the signal potential corresponding to the reference potential, potential storage means for storing the reference potential generated by the reference potential generating means or information for reproducing the reference potential, and the reference potential When the logic "1" or logic "0" written in the memory cell is read after the generation of the reference potential by the potential generation means, the potential storage means reproduces the signal potential generated by the memory cell. 2. A ferroelectric memory, comprising: a potential supplying unit configured to output a generated reference potential or a potential for reproducing the reference potential. 2. The ferroelectric memory according to claim 1, wherein the reference potential generating means includes first and second dummy cells having the same structure as the memory cell and having the same element characteristics. Write a logic "1" to one of the first and second dummy cells and a logic "0" to the other,
A ferroelectric memory, wherein the outputs of the first and second dummy cells are short-circuited to generate the reference potential. 3. The ferroelectric memory according to claim 2, wherein the reference potential generating means is a pair of first and second pair.
Data line, the first dummy cell is connected to the first data line, the second dummy cell is connected to the second data line, and the first and second dummy cells are connected. A ferroelectric memory wherein the first and second data lines are short-circuited to generate the reference potential. 4. The ferroelectric memory according to claim 1, wherein the reference potential generating means is
The semiconductor device further comprises adjacent potential averaging means for outputting an average value of the reference potentials generated corresponding to the plurality of memory cells arranged adjacent to each other on the chip, and the potential storage means includes the adjacent potential average. A ferroelectric memory characterized by storing an average value of the reference potential output by the converting means or information for reproducing the average value of the reference potential. 5. The ferroelectric memory according to claim 1, wherein the reference potential generating means is
A separation potential averaging unit that outputs an average value of each reference potential generated corresponding to each of the plurality of memory cells that are spaced apart and arranged on the chip is provided, and the potential storage unit includes the separation potential. A ferroelectric memory which stores an average value of a reference potential output by an averaging means or information for reproducing the average value of the reference potential. 6. The ferroelectric memory according to claim 1, wherein the reference potential generating means comprises:
The average value of each reference potential generated corresponding to each of the plurality of memory cells arranged on the chip is output as a reference potential commonly used for reading of all the memory cells arranged on the chip. A ferroelectric memory comprising a common potential averaging means. 7. The ferroelectric memory according to claim 1, wherein the reference potential generating means is
An average value of the reference potentials generated corresponding to each of the plurality of memory cells arranged in each predetermined area on the chip is used as a common reference potential for reading the memory cells arranged in the same predetermined area. Area common electric potential averaging means, and the potential storage means reproduces the average value of each reference potential output by the area common potential averaging means or the average value of the reference potentials. Is stored in each of the regions, and the potential supply unit outputs the average value of the reference potentials stored in the potential storage unit or the potential for reproducing the average value of the reference potentials in each of the regions. Ferroelectric memory. 8. The ferroelectric memory according to claim 1, wherein the potential storage means is a reference potential output by the reference potential generating means or a potential for reproducing the reference potential. Potential holding means having a first capacitor for accumulating, and a predetermined potential at the time of accumulating the reference potential of the first capacitor or a potential for reproducing the reference potential having a leak characteristic equivalent to that of the first capacitor. A second capacitor that stores a constant potential; and a refresh determination unit that has a leak detection unit that detects a variation in the potential stored in the second capacitor, and the second capacitor detected by the refresh determination unit When the amount of change in the accumulated potential reaches a predetermined value, the reference potential or the potential for reproducing the reference potential is re-stored in the first capacitor. A ferroelectric memory characterized in that the product and the constant potential are re-accumulated in the second capacitor to refresh information. 9. The ferroelectric memory according to claim 1, wherein the potential storage means converts the reference potential or a potential for reproducing the reference potential into a digital signal. Conversion means, and latch means for storing the digital signal converted by the AD conversion means,
A ferroelectric memory, comprising: a DA conversion means for converting a digital signal stored in the latch means into an analog potential. 10. The ferroelectric memory according to claim 9, wherein the potential storage means AD-converts the reference potential output from a plurality of the reference potential generating means or a potential for reproducing the reference potential. A reference potential input control means for sequentially inputting to the means, and an average value of each digital signal corresponding to the plurality of reference potentials sequentially converted by the AD conversion means or a potential for reproducing the reference potentials. And a mean value calculation means for outputting to the latch means. 11. The ferroelectric memory according to claim 1, wherein the potential supply means is
A potential supply capacitor having a capacitance sufficiently larger than that of the data line, and a potential fluctuation comparing the accumulated potential of the potential supply capacitor with the reference potential of the potential storage means or the potential for reproducing the reference potential. A ferroelectric material comprising: a detection means; and a charging means for charging the potential supply capacitor to the reference potential or a potential for reproducing the reference potential based on a comparison result of the potential variation detection means. memory. 12. The ferroelectric memory according to claim 3, wherein the memory cell array has the same configuration and has the same device characteristics and the first and second memory cells.
2. A ferroelectric memory characterized in that the dummy cells are formed in a layout pattern in which they are two-dimensionally arranged. 13. The ferroelectric memory according to claim 3, wherein the data line is arranged to include at least a section in which adjacent data lines are not simultaneously selected in a read operation, and the read operation is performed. 2. The ferroelectric memory according to claim 1, further comprising means for fixing the potential of at least the unselected data line adjacent to the selected data line. 14. The ferroelectric memory according to claim 1, wherein a plurality of the memory cells are commonly connected, and a constant voltage between a maximum potential and a minimum potential in an operating amplitude of the data line is set. The first plate electrode at a potential and the plurality of dummy cells are commonly connected, and at least during the period in which the selected dummy cell in the read operation is driven, the potential is higher than or equal to the highest potential or lower than or equal to the lowest potential in the operation amplitude of the data line. A ferroelectric memory provided with a certain second plate electrode. 15. The ferroelectric memory according to claim 1, wherein the ferroelectric memory is selectively connected to the plurality of data line pairs, amplifies a potential difference between the data line pairs, and outputs the information as information. 2. A ferroelectric memory, comprising: an information sensing means for controlling; and a data line selecting means for controlling connection between the information sensing means and the plurality of data line pairs. 16. The ferroelectric memory according to claim 15, wherein the potential of an unselected data line pair adjacent to the data line pair selected for connection with the information sensing means is set to:
A ferroelectric memory comprising a data line potential fixing means for fixing the potential to a predetermined potential. 17. The ferroelectric memory according to claim 1, further comprising a dummy cell that generates the reference potential when reading information from the memory cell, and a reference potential generated by the dummy cell. And a dummy plate line potential generating means for generating a potential of the plate electrode of the dummy cell that is made equal to the reference potential generated by the reference potential generating means.
The potential of the plate electrode of the dummy cell generated by the dummy plate line potential generation means is stored as information for reproducing the reference potential, and the potential supply means is the plate electrode of the dummy cell stored in the potential storage means. A ferroelectric memory characterized by outputting the electric potential of the.