JPH0793978A - Semiconductor memory and driving method for semiconductor memory - Google Patents

Abstract

PURPOSE:To obtain a nonvolatile semiconductor memory which is manufactured easily by using a ferroelectric, whose S/N ratio is high and which is suitable for a high degree of integration and to obtain its driving method. CONSTITUTION:Inverted information is stored in dummy cells DMCD, DMCB. When data lines DL, DB are short-circuited by a data-line short circuit means SWDS and the dummy cells DMCD, DMCB are selected, a reference potential in the middle between a signal potential at a logic 1 and that at a logic 0 is generated in the data lines DL, DB. When the data lines DL, DB are separated and a memory cell MC1 is selected, a signal potential is generated in the data line DL. A deference between the signal potential and the reference potential is read out.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor memory and a driving method thereof, and more particularly to a nonvolatile semiconductor memory having a ferroelectric capacitor suitable for high integration.

[0002]

2. Description of the Related Art A ferroelectric substance, when an electric field of a certain strength is applied, causes polarization in the ferroelectric substance, and the polarization is a remanent polarization unless a reverse electric field of a certain strength is applied to invert the polarization. Has the property of being held as. A ferroelectric capacitor using this as a capacitor dielectric film is shown in FIG.
As shown in, there is a hysteresis characteristic between the applied voltage VFE and the accumulated charge QFE. The characteristics of the ferroelectric capacitor will be described with reference to FIG. When a certain voltage VM1 is applied to the ferroelectric capacitor, the polarization direction of the ferroelectric substance becomes substantially constant along the applied electric field,
The state of the ferroelectric capacitor transits to the state d1. Next, when the applied voltage is set to 0 V, the charge Qr that compensates for the residual polarization is generated.
Since 1 remains on the electrode plate, the state of the ferroelectric capacitor becomes the state s1. Further, when a voltage -VM0 having a magnitude opposite to VM1 is applied, the polarization is inverted and the state of the ferroelectric capacitor becomes the state d0. After this, the applied voltage is 0
When set to V, the compensation charge −Qr0 remains on the electrode plate and the state s
Transition to 0. That is, when the applied voltage is 0V, the ferroelectric capacitor can be in a plurality of states. Thus, information can be stored, for example, by associating state s1 with a logic one and state s0 with a logic zero. Remnant polarization is retained unless an electric field of a certain strength is applied. Therefore, according to this storage method,
A non-volatile memory that does not require refresh operation and retains information even after power is turned off can be formed. When a certain amount of voltage, for example, VM1, is applied to the ferroelectric capacitor having the characteristics described above and in which information is stored in advance, the state s1 transits to the state d1 and the state s0 transits to the state d1. In this case, the apparent capacitance value of the ferroelectric capacitor is different. That is, from state s0 to state d1
In the case of the transition to (1), a larger amount of charge flows into the ferroelectric capacitor than the transition from the state s1 due to the polarization reversal, and as a result, the apparent capacitance value increases. That is, when the polarization inversion occurs, the capacitance value becomes equivalently larger than when the polarization inversion does not occur. Information can be read by utilizing this characteristic.

An example of a non-volatile memory formed by using a ferroelectric capacitor having the above characteristics is disclosed in US Pat. No. 4,873,664. The configuration of this memory will be described with reference to FIG. In the figure, a memory cell MCv1 composed of a ferroelectric capacitor CFEv1 and a transistor TRv1, a ferroelectric capacitor CFEBv1 and a transistor TRBv.
The memory cell MBv1 configured by
It is selected by Lv1 and driven by the plate line PLv1 to generate a signal potential on the data line pair DLv1, DBv1. The operation will be described more specifically. DLv
1, DBv1 and PLv1 are set to low level (Low),
When PLv1 is set to High in a state where WLv1 is set to a high level (High) and the cell transistor is made conductive, the potential of DLv1 is obtained by dividing the potential difference between High and Low by CFEv1 and the parasitic capacitance CDLv1 of DLv1. Become. Similarly, the potential of DBv1 is
The potential difference between High and Low is CFEBv1 and DBv
The voltage is divided by one parasitic capacitance CDBv1.
In this operation, when the polarization of the ferroelectric capacitor is inverted, the apparent capacitance of the ferroelectric capacitor is increased, so that the signal potential generated on the data line is higher than that when the polarization is not inverted. Therefore, CFEv1, C
The directions of remanent polarization of FEBv1 are set in the opposite directions,
Writing a logical 1 to one of MCv1 and MBv1 and a logical 0 to the other causes a potential difference between DLv1 and DBv1. This potential difference is sensed by the sense amplifier SAv1 to read information.

The above memory uses one of two memory cells to store 1-bit information, which is disadvantageous in constructing a highly integrated memory. In order to further improve the degree of integration, it is desirable to store 1-bit information in one memory cell. In that case, in order to detect the signal potential generated on the data line by the selected cell, a means for generating a reference potential intermediate between the signal potentials corresponding to logic 1 or logic 0 is required on the paired data lines. As one of them,
A method using a dummy cell may be used. As one method of the dummy cell structure described above, for example, the method described in the above-mentioned U.S. Pat. No. 4,873,664 or the method disclosed in JP-A-2-301093 can be mentioned.
That is, the area of the ferroelectric capacitor of the dummy cell is made different from that of the memory cell, and this is used to generate the reference potential. U.S. Pat. No. 4,873,6
The method disclosed in No. 64 will be described with reference to FIG. In the figure, the memory cell MCw1 is a word line W
It is selected by Lw1 and driven by the plate line PLw1 to generate a signal potential on the data line DLw1. Further, the dummy cell DMCw1 has a dummy word line DWLw.
1 and driven by the plate line DPLw1 to generate a reference potential on the data line DDLw1. Here, as disclosed in US Pat. No. 4,873,664, the ferroelectric capacitor DC of the dummy cell DMCw1 is disclosed.
The area of FEw1 is made twice or more larger than that of the ferroelectric capacitor CFEw1 of the memory cell MCw1, and the polarization direction is set so that polarization inversion does not occur when the reference potential is generated. Further, as the CFEw1, one having an apparent capacity when the polarization is inverted is larger than a capacity when the DCFEw1 is not inverted. As a result, DC
The capacity of FEw1 is larger than the capacity of CFEw1 when the polarization is not inverted and smaller than the capacity when the polarization is inverted. Therefore, the potential in the middle of the signal potentials corresponding to logic 1 and logic 0 can be generated in DDLw1. In the above method, the area of DCFEw1 is set to be larger than that of CFEw1. By setting the polarization direction so that the polarization inversion always occurs,
It is possible to obtain the same effect.

As another method of the dummy cell structure,
For example, Japanese Patent Laid-Open Nos. 2-110893 and 2-1108
And those disclosed in JP-A-5-89692. That is, a reference potential is generated by connecting two ferroelectric capacitors to a data line and driving them so that one polarization is inverted and the other polarization is not inverted. JP-A-2-110895 mentioned above
28 will be described with reference to FIG. In the figure, the memory cell MCy1 is a word line WL.
It is selected by y1 and generates a signal potential on the data line DLy1. In addition, dummy cells DMCy1 and DMCy2
Are selected by the dummy word line DWLy1 and generate a reference potential on the data line DDLy1. Memory cell MC
Plate electrode PCy1 of y1 and dummy cell DMCy
The second plate electrode PLy2 is connected to an intermediate potential between High and Low, and the plate electrode Py of the dummy cell DMCy1 is connected to the plate electrode PLy2.
Ly1 is connected to the Low potential (or High potential). The electrode area of the ferroelectric capacitors DCFEy1 and DCFEy2 included in the dummy cells DMCy1 and DMCy2 is ½ of the electrode area of the ferroelectric capacitor CFEy1 included in the memory cell MCy1. Further, the polarization direction of the dummy cell capacitor DCFEy2 is previously determined by the reset voltage source VRSy by the reset signal RESETy.
It is set by applying a High voltage from. When a signal is generated, the data lines DLy1 and DDLy1 are set to L
precharge to ow potential, then word lines WLy1,
The dummy word line DWLy1 is driven to set the memory cell capacitor CFEy1 to the data line DLy1 and the dummy cell capacitors DCFEy1 and DCFEy2 to the data line D.
Connect to DLy1 respectively. At this time, the polarization of the dummy cell capacitor DCFEy2 is reversed, but DCFEy1
Does not reverse the polarization of. Therefore, the sum of the capacitances of the dummy cell capacitors DCFEy1 and DCFEy2 is an intermediate value between the polarization inversion-time capacitance and the polarization non-inversion-time capacitance of the memory cell capacitor CFEy1. By using this, it is possible to generate a reference potential for determining a signal potential corresponding to logic 1 and 0. Here, instead of providing a circuit for resetting the polarization of the dummy cell capacitor DCFEy2, the data line DDLy1 can be driven to reset the dummy cell, as disclosed in JP-A-5-89692.

Further, as disclosed in Japanese Patent Laid-Open No. 2-110893, by sharing a dummy cell between two pairs of adjacent data lines, the reference potential is set using a dummy cell capacitor having an electrode area equal to that of the memory cell capacitor. It can also be generated. This method will be described with reference to FIG. In the figure, the dummy cell capacitor DC
The electrode area of FEx1 and DCFEx2 is equal to that of the memory cell capacitor. Further, similarly to FIG. 28, the plate electrode PLx2 is connected to an intermediate potential between High and Low, and the plate electrode PLx1 is at a Low potential (or High potential).
h potential). Prior to the signal generating operation, the reset voltage source VRSx is reset by the reset signal RESETx.
From the dummy cell capacitor DCF
The polarization direction of Ex2 is set. Then, at the time of signal generation, the data lines DDLx1 and DDLx2 are precharged to the Low potential, and then the switches YSWx1 and YSWx2.
Is turned on, a reference potential is generated on the data lines DDLx1 and DDLx2.

[0007]

However, the memory configuration using the dummy cell has the following problems. Regarding the configuration using the first dummy cell, that is, the dummy cell having capacitors having different electrode areas as shown in FIG. 27, the reference potential is based on the capacitance value of either polarization non-inversion or polarization inversion. Since it is determined, it is very difficult to generate a highly accurate intermediate potential. In order to generate a highly accurate reference potential, the capacitance value of the memory cell capacitor at the time of polarization inversion and at the time of non-inversion is estimated in advance, and a dummy cell capacitor having a desired capacitance characteristic determined based on this is highly accurately realized. There must be. Since it is difficult to design dummy cells and set process conditions for this purpose, there is a high risk that a stable reference potential cannot be generated due to variations in capacitance characteristics and deviations from the estimated values at the design stage, and the SN ratio and yield decrease. There was a problem in doing it. In addition, the second dummy cell, that is, FIG.
As shown in FIG. 8 or FIG. 29, for a configuration using a dummy cell that inverts one polarization of two capacitors and does not invert the other polarization, generate an intermediate potential between signal potentials of logic 1 and 0. Is possible in principle. However, in order to do so, as shown in FIG. 28, the electrode area of the dummy cell capacitor is set to 1/2 of that of the memory cell capacitor.
Alternatively, as shown in FIG. 29, it is necessary to provide a dummy cell circuit shared by two data lines. Further, a reset signal line must be provided in order to reset the dummy cell after generating the reference potential.
Furthermore, the plate electrodes of the dummy cells must be separated in order to apply different plate potentials. Since the dummy cell having such a structure cannot be formed in a continuous layout pattern of the memory cell array, a dummy cell having a different structure from the memory cell must be separately designed and arranged separately from the memory cell array. Therefore, similarly to the configuration using the first dummy cell, it becomes difficult to design the dummy cell and set the process condition, and it becomes difficult to obtain a dummy cell capacitor having a high relative characteristic accuracy with the memory cell capacitor. There was a problem in that there was a high risk that it could not occur.

An object of the present invention is to provide a nonvolatile semiconductor memory using a ferroelectric material, which is easy to manufacture, has a high SN ratio, and is suitable for high integration, and a driving method thereof.

[0009]

In order to achieve the above object, in the semiconductor memory of the present invention, as shown in FIG. 1, for example, a first dummy cell for storing information of logic 1 or logic 0, such as DMCB, A second dummy cell, for example DMCD, which stores information opposite to that of the first dummy cell is connected to the first dummy cell DMCB, and the memory cell MC1
First data line DB forming a pair with the data line DL for reading the memory cell data of the second dummy cell, for example D
A data line short-circuit means SWDS for short-circuiting the second data line to which the MCD is connected, for example DL, is provided, and the first and second data lines short-circuited by the data line short-circuit means SWDS are logic 1 and logic. A reference potential in the middle of the signal potential of 0 is generated.

Here, the data line for reading the memory cell data and the second data line can be the same or different, and each has its own particular advantage. That is, both the data line for reading the memory cell data and the second data line can be the same, for example, DL in FIG. 1. In this case, the reference potential and the signal potential The timing of occurrence may be different. In this case, there is an advantage that no special means for rewriting the dummy cell is required as described later. On the other hand, for example, as shown in FIG. 18, the first dummy cell DMCB1, the first data line DB1, the second dummy cell DMCB2, the second data line DB2, and the memory cell MC1.
The data line for reading the memory cell data may be different from the second data line so that the data line DL1 for reading one memory cell data is set. In this case, the reference potential and the signal potential can be generated at the same timing, which has the advantage that high-speed access can be performed.

The memory cell array of the present invention is shown in FIG.
As shown in FIG. 3, a cell pattern structure is provided that is two-dimensionally arranged continuously and regularly, and the cell pattern structure includes memory cells and dummy cells having the same structure and the same size cell structure. Characterize. That is,
Like the conventional example, you need cells of different sizes,
There is no need to require different plate potentials.

Alternatively, as the arrangement configuration of the paired data lines, for example, as shown in FIG. 9, the data lines of the fixed potential are operated by partially arranging them with the adjacent data lines of the fixed potential. If the line is provided with an adjacent section, there is an advantage that interference noise between the data lines can be reduced.

Alternatively, as shown in FIG. 13, for example, a data line charging means including a charging circuit TPNd1 and a charging signal line PCVPLd for charging a paired data line in an active state, and the data line charging means are controlled. For example P
A plurality of data line charging control units CNd1 and PCNd2 are provided, and the data line charging unit is controlled by any one of the plurality of data line charging control units, and by the control, the data line pair adjacent to the selected data line pair is not selected. By activating the data line charging means connected to the data line pair and fixing the potential of the adjacent data line pair, interference noise between the data line pairs can be reduced.

Further, in the above description, for example, as described with reference to FIG. 18, that is, the first dummy cell DMCB1, the first data line DB1, the second dummy cell DMCB2, and the second data line. DB2, memory cell M
When the data line for reading the memory cell data and the second data line are different from each other so that the data line DL1 for reading the memory cell data of C11 is provided, rewriting to the first and second dummy cells is performed. It is necessary to provide a dummy cell rewriting means for performing the above. As the dummy cell rewriting means, a logic 1 or a logic 0 is applied to the first dummy cell after the generation of the reference potential and before the end of the memory cell data read operation. Rewriting may be performed, and information reverse to that of the first dummy cell may be rewritten in the second dummy cell.

Alternatively, for example, as shown in FIG. 12, the above-described memory cell array of the present invention and a pair of data lines, such as DLd1-, included in the memory cell array.
Sense circuit SAd that senses the signal read to DBd1
0 and a data line selection means such as YSWd1 for connecting the selected data line to the sense circuit, and the sense circuit SAd0 includes a plurality of data lines DLd1-DB.
It is preferable that the circuit area is reduced by sharing d1, DLd2-DBd2, ....

In such a case, an address structure for selecting a memory cell is provided, and the address structure is, for example, as shown in FIG.
As shown in FIG. 7, a first address A for selecting a memory cell in the memory cell array connected to each sense circuit.
It is preferable to have the configuration of drs1 and the second address Adrs2 for selecting the sense circuit because the number of address pins can be reduced.

Further, in the method of driving the semiconductor memory of the present invention for achieving the above object, for example, in the operation of reading the memory cell data of the memory cell MC1 of the semiconductor memory of FIG. ), The first and second dummy cells DMCB and DMCD in which opposite information is stored are selected, and the first and second data lines DB and DL are short-circuited, and the first and second data lines DB and DL are short-circuited. Process of generating a reference potential on the second data line (101)
A step of electrically separating the first and second data lines (102), and a step of selecting the memory cell MC1 and generating a signal potential on the second data line DL (10).
3), and a step (104) of amplifying the difference between the signal potential and the reference potential and simultaneously storing mutually opposite information in the first and second dummy cells.

In this case, in order to store the opposite information in the first and second dummy cells, the difference between the signal potential and the reference potential is amplified and the first and second dummy cells are selected. All you have to do is

Alternatively, as a method of driving a semiconductor memory of the present invention to achieve the above object, for example, as shown in FIG. 18, particularly FIG.
1 is connected to the third data line DL1 and a step of generating a signal potential on the third data line (202);
The first and second dummy cells DMCB1 and DMCB2 storing mutually opposite information are read to the shorted first and second data lines DB1 and DB2, respectively, and the first and second data lines DB1 and DB1 and DB2 are read. DB
2 is provided with a step (203) of generating a reference potential at the same time, and further, a step (204) of electrically separating the first and second data lines and a difference between the signal potential and the reference potential are amplified. (205) and a step (206) of rewriting the first and second dummy cells DMCB1 and DMCB2.

Here, the first and second dummy cells DM
Rewriting CB1 and DMCB2 (20
As 6), for example, by the circuit configuration as shown in FIG.
A high potential or a low potential may be applied to the first data line DB1 and a low potential or a high potential of the opposite information may be applied to the second data line DB2.

Alternatively, for example, in the circuit configuration as shown in FIG. 20, the process of amplifying the difference between the signal potential and the reference potential includes the signal potential generated in the third data line DL1 and the first data line. The step (206) of amplifying the difference between the reference potentials generated in DB1 and rewriting the above-mentioned first and second dummy cells DMCB1 and DMCB2 includes the third step in which the memory cell MC11 is connected. The potential of the data line DL1 is set to the second data line D
The first and second dummy cells DMCB1 and DMCB2 may be selected while being supplied to B2.

[0022]

Operation: During a read operation, a logic 1 or a logic 0
The first data line connected to the first dummy cell storing the first dummy cell and the second data line connected to the second dummy cell storing the reverse information of the first dummy cell are short-circuited. Then, an intermediate potential between the signal potential corresponding to the logic 1 and the signal potential corresponding to the logic 0 is generated on the first and second data lines. Next, the data line short-circuit means is turned off. Then, the intermediate potential is left on one of the first and second data lines, and a signal potential corresponding to logic 1 or logic 0 is generated on the data line connecting the selected memory cell. That is, if there is a pair configuration such that the first data line connecting the first dummy cell and the data line connecting the selected memory cell form a data line pair, one of the data line pair is It becomes possible to generate an intermediate potential and a signal potential on the other. Therefore, the intermediate potential is used as a reference potential, and the height of the signal potential and the reference potential is sensed and amplified by a sense amplifier, whereby information can be read.

According to this structure and operation, by using the dummy cell having the same structure and the same size as the memory cell,
A reference potential can be generated. At this time, since the structure and size of the memory cell and the dummy cell are the same,
Not only is it easy to design the dummy cell, but it is easy to realize a dummy cell whose element characteristics are almost the same as those of the memory cell and whose characteristic variations are small. This makes it possible to generate a highly accurate reference potential and perform a read operation with a high SN ratio.

When the data line connected to the selected memory cell and the second data line connected to the second dummy cell are the same, the reference potential and the signal potential are generated at the same timing. No, it needs to be done in chronological order. However, in this case, the first and second data lines form a data line pair. Therefore, by amplifying the difference between the signal potential and the reference potential with the sense amplifier, one of the first and second data lines becomes high and the other becomes low. By utilizing this, it becomes possible to rewrite logic 1 to one of the first and second dummy cells and logic 0 to the other without providing a reset signal line.

Since the memory cell and the dummy cell have the same structure and size, both can be formed on a continuous layout pattern. As a result, dummy cell design and process condition setting are easy, relative accuracy is high, and element characteristics with small characteristic variations can be easily obtained, and the area increase due to the dummy cells is slight. Therefore, it is easy to obtain a semiconductor memory that is easy to manufacture, has a high SN ratio, and is suitable for high integration.

If one of the two adjacent data line pairs is replaced with another, and only one data line pair is operated, the operating data line is sandwiched between the data lines whose potential is fixed. Since the read operation is performed in this state, it is strong against interference noise due to the parasitic capacitance between the data lines,
It is possible to perform a highly reliable read operation. In addition, since the number of operating data lines is about half, the power consumption during operation can be reduced.

Further, if the data line pair is selectively connected to the sense circuit and the sense circuit is shared by a plurality of data line pairs, the circuit area can be reduced, and the sense amplifier can be reduced. The layout of the parts has a margin, which is extremely convenient for housing the sense amplifier part, which requires a relatively large area, in a highly integrated circuit.

Further, according to the above configuration, only the necessary portion of the memory cell array is operated,
It is possible to significantly reduce noise such as power consumption and power supply. Moreover, since it is possible to eliminate unnecessary polarization reversal of the ferroelectric capacitor in the unselected memory cell,
It is possible to reduce the characteristic deterioration of the ferroelectric film.

Further, the address configuration is such that the address for selecting the memory cell is fetched in a time division manner, the memory cell in the memory cell array connected to each sense circuit is selected by the first address, and the sense circuit is selected by the second address. If the configuration is performed by address, the number of required address pins can be reduced. Further, while having a configuration in which the sense amplifier is shared, it is possible to easily perform the operation of continuously and rapidly reading the information by changing the address while latching the read information in the sense amplifier.

Furthermore, it is also possible to generate the reference potential and the signal potential at the same time, not in time series. That is, with respect to the two data line pairs, a data line short-circuit means for short-circuiting each one of them is provided, and a dummy cell rewriting means for rewriting the dummy cell is provided. In the read operation, one of the two data line pairs is connected to the selected dummy cell and short-circuited to generate the reference potential. At the same time, the other is connected to the selected memory cell to generate a signal. Next, the data line short-circuit means is turned off and amplification is performed. After that, the dummy cell rewriting means rewrites the selected dummy cell. By applying this configuration and operation, higher speed access becomes possible. Further, the time for which the data line is in the floating state while the reference potential is being generated is shortened, and noise resistance and soft error resistance are improved. As described above, by additionally using a configuration in which a plurality of data line pairs share a sense circuit, the circuit area can be reduced, the layout margin of the sense amplifier section can be relaxed, and the power consumption can be reduced. Is preferred and is preferable.

[0031]

EXAMPLES The present invention will be described below with reference to examples. (Embodiment 1) FIG. 1 is an embodiment showing a basic circuit configuration and an operation flow in the present invention, and is an example showing a circuit configuration for generating a reference potential by short-circuiting a pair of data lines. FIG. 1A shows a basic circuit configuration, and FIG.
Shows the flow of the read operation. Figure 1 (a)
In, the memory cell MC1 is connected to the position where the word line WL1 and the data line DL intersect. Further, the memory cell MC2 is connected to a position where the word line WL2 and the data line DB intersect. Hereinafter, memory cells are connected at positions where a plurality of word lines intersect the data lines DL or DB, but they are omitted in the figure. On the other hand, the dummy word line DW
A dummy cell DMCD is connected to a position where the LD and the data line DL intersect, and a dummy cell DMCB is connected to a position where the dummy word line DWLB and the data line DB intersect. A sense amplifier SA and a data line short circuit switch SWDS are connected between the data lines DL and DB. The memory cells MC1, MC2, ... And the dummy cells DMCD, DMCB may be memory cells that store information in a non-volatile manner by utilizing the remanent polarization of a ferroelectric substance. For example, the configuration shown in FIG. it can. In FIG. 2, the memory cell MC1 includes a cell transistor TR1 and a ferroelectric capacitor CF1. One of the source / drain terminals of the cell transistor TR1 is connected to one terminal of the ferroelectric capacitor CF1, the other is connected to the data line DL, and the gate terminal is connected to the word line WL1.
The other terminal (plate electrode PL1) of the ferroelectric capacitor CF1 is commonly connected to a plate potential supply means (not shown) that generates an intermediate potential between a high level (High) and a low level (Low). The ferroelectric capacitor CF1 is formed by sandwiching a ferroelectric film between electrodes. Examples of ferroelectric materials include lead zirconate titanate (PZT) and barium titanate (BaTiO 3).
3), perovskite oxides such as lithium niobate (LiNbO3) can be applied. The polarization of the ferroelectric capacitor CF1 can be inverted by the difference between High and the plate potential and the difference between the plate potential and Low. In addition, the resistor RF1 is a resistor that represents the leak of the ferroelectric capacitor CF1 and is a diode DS.
1, DD1 represent the source / drain junction of the cell transistor TR1. It is assumed that the other memory cells MC2, ... And the dummy cells DMCD, DMCB also have the same configuration as the memory cell MC1 and have substantially the same structure and element size. Now, returning to FIG. 1, using FIG.
A read operation from the memory cell MC1 in the circuit (a) will be described. In the standby state, the data line short circuit switch SWDS is on. In addition, the dummy cell D
One of MCD and DMCB has logic 1 and the other has logic 0
Is stored. First, the dummy word line D
Select the WLD and DWLB to select the dummy cells DMCD and D
A reference potential is generated on the data lines DL and DB by the MCB (step 101). This reference potential is applied to the data lines DL and DB.
Generate a signal potential of logic 1 on one side and logic 0 on the other side,
It is equal to the potential when this is short-circuited. Here, if the dummy cells DMCD, DMCB have substantially the same element characteristics as the memory cells MC1, MC2, ... And the data lines DL, DB also have substantially the same electrical characteristics, the data lines DL, D
The reference potential generated at B becomes an intermediate potential between the signal potentials of logic 1 and logic 0. Next, the data line short circuit switch S
WDS is turned off (step 102), and data lines DL, DB
Electrically separated. Next, the word line WL1 is selected and a signal potential corresponding to the information stored in the memory cell MC1 is generated on the data line DL (step 103). The potential difference between the signal potential and the reference potential is sensed and amplified by the sense amplifier SA (procedure 104). The data line short-circuit switch SWDS is turned back on (procedure 105), and the read operation is completed. In the above description, the data line short circuit switch SWDS is turned on in step 101,
After generating a signal potential of logic 1 on one of the data lines DL and DB and logic 0 on the other, the switch SWDS is turned on, and D
The reference potential may be generated by short-circuiting L and DB. According to this embodiment, the reference potential can be generated using the dummy cell having the same structure and size as the memory cell. At this time, since the memory cell and the dummy cell have the same structure and size, it is easy to realize a dummy cell having substantially the same element characteristics as those of the memory cell and a small characteristic variation. It is possible to generate and perform a read operation with a high SN ratio.

Next, an embodiment of a more specific memory configuration to which the above basic concept is applied will be described. (Embodiment 2) FIG. 3 is an embodiment showing a block configuration of a memory based on the concept of the present invention. In the figure, MC
ARYa is a memory cell, word line, dummy word line,
A memory cell array including a data line, a precharge circuit, a data line short-circuit switch, and the like. SAGa is a sense circuit group. The memory controller MCTLa receives a control signal from the outside and sends a control signal CTLGa to each part of the memory.
Is generated and the internal address is set to the row address buffer XA.
It is supplied to Ba and the column address buffer YABa.

XABa is a row address buffer, and M
Latch the row address received from CTLa. XD
ECa is a row decoder and selects a word line based on the row address latched by XABa. XDRVa is a word line driver and drives a selected word line. YA
Ba is a column address buffer, which latches the column address received from MCTLa. YDECa is a column decoder, and based on the column address latched by YABa,
Select the data line. YSWGa is a column selection switch group, which connects and disconnects the selected data line and the outside. IDBa is an input data buffer and receives input data from the outside. ODBa is an output data buffer, and includes a main amplifier that amplifies a read signal and an output stage.

Next, the control signal shown in FIG. 3 will be described. The address fetch signals / CS1 and / CS2 control the timing of fetching the address signal Adrs. The write control signal / WE controls the timing of switching the read / write operation mode and fetching the input signal from the data input / output pin DIO. Output control signal /
The OE controls the timing of outputting the read signal to the DIO. The power-down control signal / PWD deals with power-on / off and executes an operation mode in which the potential of each part is set so as not to cause information destruction.

FIG. 4 shows the memory cell array MCAR of FIG.
This is a more specific example of the Ya portion including the sense circuit group SAGa and the column selection switch group YSWGa. In the figure, the word line WLa1 and the data line DLa
For example, a memory cell MCa11 having a configuration similar to that of FIG. Also, the word line WL
The memory cell MCa12 is connected to the intersection of a1 and the data line DLa2. A memory cell MCa21 is provided at a position where the word line WLa2 and the data line DBa1 intersect.
, And the memory cell MCa22 is connected to the intersection of the word line WLa2 and the data line DBa2.
Similarly, the word lines WLap (p = 1, 2, 3, ...
m) and the data line DLaq or DBaq (q = 1, 2,
.) Are connected to the memory cells MCapq. The data lines DLaq and DBaq form a pair, and the potential difference between them is detected to read out the signal. Hereinafter, the data line pair is expressed as DLaq-DBaq. A dummy cell DMCDaq is connected to a position where the dummy word line DWLDa and the data line DLaq intersect, and a dummy cell DMCDaq is connected to the position where the dummy word line DWLBa and the data line DBaq intersect.
Dummy cell DMCBaq is connected. As shown in the figure, if the nodes of adjacent memory cells and data lines are made common, the number of contact holes can be reduced and a high-density cell layout can be achieved. The plate electrodes of the memory cell capacitors and the dummy cell capacitors are commonly connected to a plate potential generating means (not shown). The plate potential VPL is a constant potential intermediate between the potential VDD corresponding to High and the potential VSS corresponding to Low. The sense amplifier SAaq uses a CMOS flip-flop, is controlled by the sense amplifier control lines SPa and SNa, and senses and amplifies a signal generated on the data line pair DLaq-DBaq. The data line short-circuit switch TDSaq is controlled by the data line short-circuit control line DLSa and short-circuits / opens the data line pair DLaq-DBaq. The precharge circuit TPNaq is controlled by the precharge control line PCNa, and when it is not selected, the potential VPL of the precharge potential supply line PCVPLa is set to the data line pair DLaq-DB.
supply to aq. The precharge circuit TRDaq is controlled by the precharge control line PCDa and supplies the potential VSS of the precharge potential supply line PCVSSa to the data line DLaq during the read operation. In addition, the precharge circuit TRBaq has a precharge control line PCBa.
And the potential VSS during the read operation.
Is supplied to the data line DBaq. Column selection switch YSW
The aq is controlled by the column selection line YSaq, and connects / disconnects the data line pair DLaq-DBaq and the input / output line I / Oa.

Next, returning to FIG. 2, a state of the memory cell when not selected and a method of holding information will be described. In order to retain the polarization information of the memory cell during standby,
In the state where the junction leak current of the reverse-biased diode DS1 is supplied through the leak resistance RF1 and the off resistance Roff of the cell transistor TR1, that is, in the steady state, the potential of the node SN1 is almost VPL. It is only necessary that the potential difference of the plate electrode PL1 does not cause information destruction due to polarization reversal of the ferroelectric capacitor CF1. A memory cell is formed using an element having a characteristic capable of maintaining this state.
Here, when the potential of the data line DL in the standby state is VPL, the potential of the node SN1 in the steady state is determined by the ratio of the parallel combined resistance of the leak resistance RF1 and the off resistance Roff to the resistance of the diode DS1. Generally, the reverse bias resistance of the diode DS1 can be made sufficiently higher than the parallel combined resistance described above. Further, even if the transistor TR1 becomes conductive in that state, the ferroelectric capacitor CF
Since no voltage is applied to 1, the noise on the word line becomes strong. Therefore, by holding the standby data line potential at VPL, it becomes easy to retain information. When the data line DL is driven during operation, if the off resistance Roff is sufficiently higher than the leak resistance RF1, or the time constant of charging the ferroelectric capacitor CF1 from the data line DL through the off resistance Roff is the operation time. Big enough compared to
Information is not destroyed if almost no voltage is applied to the ferroelectric capacitor CF1 during operation. further,
If the leak resistance RF1 is sufficiently higher than the on resistance Ron of the cell transistor TR1, a sufficiently large voltage is applied to the ferroelectric capacitor CF1 during selection. Information can be stably held by obtaining the element characteristics that satisfy the above-described relationships.

An example of the read operation of the circuit of FIG. 4 is shown in FIG.
Will be explained. FIG. 5 shows a read operation waveform when the memory cell MCa11 is selected. First, the standby state will be described. The potential of each word line and dummy word line is VSS. The potential of the NMOS side sense amplifier control line SNa is VDD, the potential of the PMOS side sense amplifier control line SPa is VSS, and each sense amplifier is inactive. Furthermore, the potential of the data line short circuit control line DLSa is VDD, and each data line pair is short-circuited. Furthermore, the precharge control line PCD
The potential of a and PCBa is VSS, and the potential of PCNa is VDD.
Therefore, the potential VPL is supplied to each data line pair. Furthermore, the potential of each column selection line YSa1, YSa2, ... Is VSS, and the column selection switches YSWa1, YSWa.
2, ... Are in a non-conductive state, and the input / output line I / Oa and each data line are separated. Furthermore, the data line pair DL
a1-DBa1 connected to the dummy cell DMCDa1,
A logic 1 is written in advance on one side of the DMCBa1 and a logic 0 is written on the other side. Another data line pair DLa2-DBa
The same applies to 2, ...

Next, the read operation will be described. Here, description will be made focusing on the data lines DLa1 and DBa1, but the operation of the other data lines is also the same as the following. When the address capture signal / CS1 falls, the row address is captured in synchronization with this and the read operation is started. First, the dummy cells DMCDa1 and DMCBa1 generate a reference potential on the data line pair DLa1-DBa1. First, at time tra1, the potential of the precharge control line PCNa is set to VSS, the potentials of PCDa and PCBa are set to VDD, and the potentials of the data lines DLa1 and DBa1 are precharged to VSS. Next, at time tra2, the potentials of the precharge control lines PCDa and PCBa are set to V
By setting to SS, all precharge circuits are inactivated, and the data lines DLa1 and DBa1 are brought into a floating state. Next, at time tra3, the dummy word lines DWLDa,
The potential of DWLBa is set to VCH and the dummy cell DMCD
The cell transistors a1 and DMCBa1 are turned on.
However, the potential VCH is higher than the potential VDD by at least the threshold voltage of the cell transistor, and by applying VCH to the gate electrode of the transistor, a signal potential of the potential VDD is sufficiently transmitted between the source and drain terminals. Is what you can do. At this time, the capacitors of the dummy cells DMCDa1 and DMCBa1 are
A voltage of approximately VPL-VSS is applied. Then, one polarization of the dummy cell capacitor is reversed, and accordingly,
The charge ΔQr flows into the dummy cell capacitor whose polarization is inverted. ΔQr is the charge difference Qr1- shown in FIG. 25 for compensating for remanent polarization when sufficient polarization inversion occurs.
Equal to (-Qr0). By using this, the data line DLa
1, reference potential VDBR generated in DBa1 is expressed by the following equation.

[0039]

[Equation 1]

Here, CDL represents the parasitic capacitance of the data line DLa1, and CF1N represents the non-inversion capacitance of the ferroelectric capacitor of the dummy cell DMCDa1. Further, the parasitic capacitance of the data line DBa1 is equal to that of DLa1,
The voltage-charge characteristic of the capacitor of the dummy cell DMCBa1 is equal to that of DMCDa1. Next, the selected memory cell MCa11 generates a signal potential on the data line DLa1. At time tra4, the potential of the data line short circuit control line DLSa is set to VSS, and the data line DLa1
And DBa1 are separated. Next, at time tra5, the potential of the dummy word line DWLDa is set to VSS, the cell transistor of the dummy cell DMCDa1 is cut off, the potential of the precharge control line PCDa is set to VDD, and the potential of the data line DLa1 is precharged to VSS. To do. Next, at time tra6, the potential of the precharge control line PCDa is set to VSS and the data line DLa1 is brought into a floating state. Next, at time tra7,
The potential of the word line WLa1 is set to VCH and the memory cell M
The cell transistor of Ca11 is turned on. Here, when the polarization of the ferroelectric capacitor of the memory cell MCa11 is not inverted, the signal potential VDL0 generated on the data line DLa1 is expressed by the following equation.

[0041]

[Equation 2]

However, the voltage-charge characteristic of the capacitor of the memory cell MCa11 is also equal to that of the dummy cell capacitor. On the other hand, when the polarization is reversed, the data line D
The signal potential VDL1 generated in La1 is expressed by the following equation.

[0043]

[Equation 3]

From the above Equations 1, 2 and 3, the reference potential V
It can be seen that DBR is in the middle of the signal potentials VDL1 and VDL0. The state in which the signal potential VDL1 is generated is DLa1
(1) The state in which the signal potential VDL0 is generated is DLa1
Notated as (0) and shown in the waveform of FIG. The signal amount, that is, the difference between the signal potential VDL1 and the reference potential VDBR and the difference between the reference potential VDBR and the signal potential VDL0 are equal, and the value ΔVR is represented by the following formula.

[0045]

[Equation 4]

If this value is of a size that can be correctly detected by the sense amplifier SAa1, then reading is possible.
At time tra8, sense amplifier control lines SNa and SP
The potential of a is inverted to activate the sense amplifier SAa1, and the potential difference between the data lines DLa1 and DBa1 is amplified.
Here, since the dummy cell DMCDa1 is electrically separated from the data line DLa1 at time tra5,
The load capacitances at both ends of the sense amplifier SAa1 are substantially equal, one is the sum of the capacitances of the data line DLa1 and the memory cell MCa11, and the other is the data line DBa1 and the dummy cell DMCB.
It is the sum of the capacities of a1. As a result, the load capacitance is well balanced and the amplification operation is performed stably. By the amplification, the read information is automatically rewritten in the memory cell MCa11. Further, information opposite to that of the memory cell MCa11 is written in the dummy cell DMCBa1.
When the signal is almost fixed, the potential of the dummy word line DWLDa is set to VCH again at time tra9. Then,
The same information as that of the memory cell MCa11 is written in the dummy cell DMCDa1. Therefore, the dummy cell DMCDa
1, DMCBa1 are written with information opposite to each other, and the reference potential can be generated again in the next read operation without adding the reset operation of the dummy cell after the read operation is completed.

Information is output to the outside by taking in the column address in synchronization with the fall of the address taking-in signal / CS2, and at the time tra10, the column selecting line YSa1.
Is set to VDD, the column selection switch YSWa1 is turned on, and a signal is output to the input / output line I / Oa. Here, a plurality of pieces of information can be continuously read by an operation such as inputting different column addresses and switching the column selection switch. Further, for example, the information output is stopped by the output control signal / OE, and the write control signal /
Information can also be written in the memory cell MCa11 by a procedure such as switching the operation to the write mode by WE and then inputting a write signal from the input / output line I / Oa. The address fetching is stopped in synchronization with the rising edge of the address fetching signal / CS2, and the column selection switch YSWa1 is cut off at time tra11.

The operation of returning the memory to the standby state is started in synchronization with the rising edge of the address fetch signal / CS1. First, at time tra12, the sense amplifier control line SN
The potentials of a and SPa are inverted to deactivate the sense amplifier SAa. Then, the potential of the data line short-circuit control line DLSa is set to VDD, the data line pair DLa1-DBa1 is short-circuited, and the potential of the precharge control line PCNa is set to V.
By setting to DD, the data line pair DLa1-DBa1
The potential of is returned to VPL. As a result, the memory cell MCa
The voltage across the ferroelectric capacitors of 11 and the dummy cells DMCDa1 and DMCBa1 is almost 0V. Therefore, it is possible to discharge charges other than the charge that compensates the residual polarization and stabilize the signal potential and the reference potential generated in the data line in the next read operation.
Finally, at time tra13, the potentials of the word line WLa1 and the dummy word lines DWLDa and DWLBa are set to VS.
The read operation is completed after setting S. Note that, for example, the data line precharge potential at the time of reading is set to VDD,
The potential relationship may be changed as appropriate.

Here, for example, a data line short circuit switch is constructed as shown in FIG. 6A, and the potential of the dummy word line DWLBa is set to the dummy word line DW as shown in FIG. 6B.
Once the voltage is set to VSS together with LDa, the word line WLa1
When the data line is in the floating state, the capacitive coupling noise generated in the data line due to the potential variation of the word line, the dummy word line and the data line short-circuit control line is reduced when the data line is operated again. You can This will be described in detail. When the potentials of the drive lines such as the word lines and the data line short-circuit control lines that intersect the floating data lines change, the data line potentials change via the parasitic capacitance between the drive lines and the data lines. Therefore, the drive lines having different potentials immediately after the floating state and immediately before the start of amplification affect the data line potential immediately before amplification. Parasitic capacitance between word line and data line at intersection where memory cells are connected, parasitic capacitance between word line and data line at intersection where memory cells are not connected, parasitic capacitance at intersection of data line short-circuit control line and data line Are generally different, so that the data line potential fluctuation amount provided by each is also different. The fluctuation amount of the data line potential due to the rise of the drive line potential is calculated by ΔVC.
Let N1, ΔVCN2, and ΔVCN3. In the read operation of FIG. 5, the word line WLa is provided between the times tra6 and tra8 when the data line DLa1 is in the floating state.
The potential of 1 rises. Therefore, the potential variation amount ΔVCNDL1 of the data line DLa1 in this period is represented by the following equation. ΔVCNDL1 = ΔVCN1 ... Goes down. Dummy word line DWL
Since the potentials of Da and the precharge control line PCDa rise and then fall back to the original levels, the data line potential fluctuations caused thereby are offset. From these, the potential variation amount ΔVCNDB1 of the data line DBa1 in this period is expressed by the following equation. ΔVCNDB1 = ΔVCN1 + ΔVCN2-ΔVCN3 (Equation 6) Therefore, the difference ΔVCNDD1 between the right side of Equation 5 and the right side of Equation 6
Is as follows. ΔVCNDD1 = ΔVCN2-ΔVCN3 (Equation 7) The sense amplifier SAa1 has a data line pair DLa1-DBa.
In order to amplify the potential difference of 1, the above ΔVCNDD1 is
It affects the read signal as noise.

As a method of canceling the noise ΔVCN3 included in the equation 7, a method of forming the data line short-circuit switch with a CMOS switch is effective as shown in FIG. 6 (a). In the figure, a data line short circuit switch TDSa1 is provided in parallel with the data line short circuit switch TDSa1. A transistor having a polarity opposite to that of TDSa1 is used for the data line short circuit switch / TDSa1. Similarly, in parallel with the data line short circuit switch TDSa2, the data line short circuit switch / TD
Sa2 is provided. The following data line short-circuit switch has the same configuration. Data line short-circuit switch / TDS
a1, / TDSa2, ... are data line short-circuit control lines / DL
It is controlled by Sa. Data line short-circuit control line / DLSa
As shown in FIG. 6 (b), the potential of is complementary to the potential of the data line short circuit control line DLSa. Therefore, the noise ΔVCN3 generated in the data line due to the potential fluctuation of the data line short circuit control line DLSa is canceled by the data line short circuit control line / DLSa whose potential also fluctuates in the opposite direction at the same time. Here, the data line short-circuiting switches TDSa1, TDSa2, ..., / TDSa1, / so that the absolute values of the noises due to the data line short-circuit control lines DLSa, / DLSa are almost equal.
The noise ΔVCN3 is effectively canceled by determining the element structure and size of TDSa2, ....

Further, as a method of canceling the noise ΔVCN2 contained in the equation 7, as shown in FIG. 6B, the potential of the dummy word line DWLBa is set to the dummy word line DWLDa.
And VCH together with word line WLa1
It is effective to use the method described above. However, other operations are the same as those in FIG. Accordingly, the time tra6 when the data line DLa1 is in the floating state.
During the period from to tra8, the potentials of the word line WLa1 and the dummy word line DWLBa rise. Therefore, the potential variation amount ΔVCNDL2 of the data line DLa1 in this period is represented by the following equation. ΔVCNDL2 = ΔVCN1 + ΔVCN2 (Equation 8) On the other hand, the potential of the word line WLa1 rises during the time tra2 to tra8 when the data line DBa1 is in the floating state. Further, since the potential of the dummy word line DWLBa rises, falls, and rises, the influence of potential fluctuation can be regarded as the same as the one rise of the potential. Therefore, FIG.
Assuming that ΔVCN3 is canceled by using the configuration of FIG.
Is represented by the following formula. ΔVCNDB2 = ΔVCN1 + ΔVCN2 (Equation 9) Therefore, the difference ΔVCNDD2 between the right side of Equation 8 and the right side of Equation 9
Is as follows. ΔVCNDD2 = 0 (Equation 10) From this, the differential component of noise generated in the data line pair due to capacitive coupling with the word line, the dummy word line and the data line short-circuit control line becomes zero. Therefore, the influence of coupling noise on the read operation can be removed.

As the sectional structure of the memory cell array, for example, the one shown in FIG. 7 can be applied. The forming procedure will be described with reference to the drawings. First, the element isolation insulating film 2 is formed on the semiconductor substrate 1 by a selective oxidation technique, and the gate insulating film 3 is formed.
The word line 4 and the dummy word line 24, the interlayer insulating film 5,
Source / drain diffusion regions 6 are sequentially formed to form a cell transistor. Next, the contact plug 7 of the information storage node, the data line 8, and the interlayer insulating film 9 are formed. Further, after the surface is flattened by the insulating film 10, the contact plug 11 of the information storage node and the capacitor lower electrode 1 are formed.
2. Form the ferroelectric film 13. A capacitor upper electrode, that is, a plate electrode 14 is formed thereon. Some cells of the memory cell array formed as described above, that is, cells connected to the dummy word line 24 are used as dummy cells. As the material, for example, p-type silicon is used for the semiconductor substrate 1, n-type silicon is used for the source / drain diffusion regions 6, n-type polysilicon is used for the word line 4 and the dummy word line 24, the contact plug 7, and the data line 8, and insulation is used. Silicon oxide is used for the films 2, 3, 5, 9, and 10, tungsten is used for the contact plug 11, aluminum, tungsten, or platinum is used for the plate electrode 14, and the lower electrode 1 is used.
2 is a conductive oxide such as platinum or ruthenium oxide,
PZT or the like is used for the ferroelectric film 13. In the memory according to the present invention, since all plate potentials can be set to a common constant potential, it is not necessary to provide a step of finely processing plate electrodes as plate lines.

As the plane layout of the memory cell array, for example, the one shown in FIG. 8 can be applied. In the figure, cell transistors are formed at positions where the diffusion layer 6 surrounded by the element isolation region 2 and the word line 4 or the dummy word line 24 also serving as a gate electrode overlap each other. One of the source / drain regions of two adjacent cell transistors is commonly connected and connected to the data line 8 through the data line contact hole 16. The other source / drain region is connected to the capacitor lower electrode 12 via the information storage node contact hole 7, respectively. A ferroelectric film, an upper electrode, etc. are formed on this to form a memory cell array. As shown in the figure, by arranging the memory cells and the dummy cells as a continuous pattern on the common memory cell array region, the element characteristics of the memory cells and the dummy cells are made substantially equal, and it is easy to reduce the characteristic variation. It is possible to generate a highly accurate reference potential.

According to this embodiment, it is possible to construct a memory to which the basic concept described above is applied. At this time, since the memory cell and the dummy cell can be formed in a continuous layout pattern having a common structure, the area increase by the dummy cell is slight. In addition, the dummy cell design and process condition setting are easy, and device characteristics with high relative accuracy can be obtained. As a result, a highly accurate reference potential is obtained, and a read operation with a high SN ratio is possible. Furthermore, since the data can be rewritten to the dummy cell by amplifying the data line potential difference, the reset operation of the dummy cell can be simplified. Furthermore, since the plate potential is a common constant potential, it is possible to suppress an increase in the number of steps and a decrease in yield due to fine processing of the plate electrode, and it is possible to form a memory suitable for high integration.

(Embodiment 3) FIG. 9 is an embodiment showing a memory cell array constructed according to the present invention. In the memory cell array, adjacent data line pairs are partially crossed and arranged. 4 is different from the example shown in FIG. In the figure, adjacent data line pairs DLb1-DBb1 and DLb2
-DBb2 is arranged by interchanging the data lines DBb1 and DBb2 in the memory cell array MCARYb. Similarly, in the adjacent data line pairs DLb3-DBb3 and DLb4-DBb4 as well, the data lines DBb3, D
Bb4 is replaced and arranged. The same applies to the subsequent data line pairs. Word lines WLb1, WLb2
A plurality of memory cells such as MCb11 are connected to one of WLb3, WLb4, ..., WLbm and the data line forming each data line pair. In addition, the dummy word line DW
LDb and data lines DLb1, DLb2, DLb3, DL
A plurality of dummy cells such as DMCDb1 are connected to the intersections with b4, ..., Dummy word line DWLBb and data line D
A plurality of dummy cells such as DMCBb1 are connected to the intersections with Bb1, DBb2, DBb3, DBb4, ....
For example, the configuration shown in FIG. 2 can be applied to the memory cell and the dummy cell. Sense amplifier control lines SPb1, SN
b1 controls the sense amplifiers SAb1, SAb3, ...
The sense amplifier control lines SPb2, SNb2 control the sense amplifiers SAb2, SAb4, .... Sense amplifier SA
A CMOS flip-flop or the like can be applied to b1, ... The data line short circuit control line DLSb1 is a data line pair DL.
Controls short-circuiting / opening of b1-DBb1, DLb3-DBb3, ..., And the data line short-circuit control line DLSb2 controls short-circuiting / opening of the data line pair DLb2-DBb2, DLb4-DBb4 ,. The precharge control line PCNb1 is
The potential VPL of the precharge potential supply line PCVPLb is set to the data line pair DLb1-DBb1, DLb3-DBb3, ...
And the precharge control line PCNb2 is supplied to the potential VP.
L is a data line pair DLb2-DBb2, DLb4-DBb
Supply to 4, ... The precharge control line PCDb1 is
The potential VSS of the precharge potential supply line PCVSSb is supplied to the data lines DLb1, DLb3, ... And the precharge control line PCDb2 supplies the potential VSS to the data line DLb2.
Supply to DLb4, .... Also, the precharge control line P
CBb1 applies the potential VSS to the data lines DBb1 and DBb.
, And the precharge control line PCBb2 supplies the potential VSS to the data lines DBb2, DBb4, .... Column selection lines YSb1, YSb2, YSb3, YSb
4, ... are the connections between each data line pair and the input / output line I / Ob.
Perform separation.

An example of the read operation of the circuit of FIG. 9 is shown in FIG.
It will be described using 0. The operation of FIG. 10 is different from the operation of FIG. 5 in that the read operation is performed based on the same principle as that of FIG. 5, but that every other data line pair is kept in the non-selected state.
Here, a read operation waveform when the memory cell MCb11 is selected is shown. The standby state is the same as the operation in FIG. As for the read operation, the time trb1
-Data line pair DLb1-DBb1 in trb13
And the sense amplifier control lines SPb1 and SN related to this
A series of operations of b1, the data line short-circuit control line DLSb1, and the precharge control lines PCNb1, PCDb1, PCBb1 are the same as the operations at times trb1 to trb13 in FIG. That is, the operations are performed in the order of reference potential generation, data line pair separation, signal potential generation, and amplification to read information. However, the data line pair DLb adjacent to this
2-DBb2 and sense amplifier control line S related thereto
Pb2, SNb2, data line short circuit control line DLSb2 and precharge control line PCNb2, PCDb2, PCB
b2 remains in the same state as during standby even during the read operation (the operation waveforms of PCDb2 and PCBb2 are omitted in FIG. 10). As described with reference to FIG. 9, since the data lines DBb1 and DBb2 are arranged interchangeably in the memory cell array, when the above operation is applied, the operating data lines except the sense circuit and the precharge circuit are The data lines fixed to the constant potential VPL are arranged alternately. The sense circuit / precharge circuit portion is shorter than the memory cell array portion, and the potential of the adjacent data line pair is fixed to VPL. As a result, the interference noise due to the parasitic capacitance between the data lines is greatly reduced. That is, not only is interference noise between adjacent data line pairs reduced, but interference noise between paired data lines is also reduced by operating only one of the data line pairs to generate a signal potential. To be done. As a result, a highly reliable read operation is performed. On the other hand, the memory cell MBb12 is simultaneously selected by the word line WLb1. However, the potential of the data line DBb2 is the same VPL as the plate electrode of the memory cell. Therefore, no voltage is applied to the ferroelectric capacitor of the memory cell MBb12 and polarization inversion does not occur, so that information is retained. Data line pair DLb3-DBb3 and DLb4-D
The same applies to the data line pairs of Bb4 and thereafter. That is, every other pair of data lines operates,
The data line pair in the meantime remains in the standby state. According to this embodiment, since the read operation is performed with the operating data line sandwiched between the data lines whose potentials are fixed, the interference noise due to the adjacent data line pair and the parasitic capacitance between the data line pair is reduced. It is possible to perform a strong and highly reliable read operation. In addition, since the number of operating data lines is about half, the power consumption during operation can be reduced. Note that a data line arrangement different from that of this embodiment may be used as long as the data line arrangement is such that at least a data line whose potential is fixed can be arranged adjacent to the operating data line.

(Embodiment 4) FIG. 11 is an embodiment showing a block configuration of a memory based on the concept of the present invention, in that a column selection switch is provided between a memory cell array and a sense circuit. Different from the example shown in FIG. In the figure, M
CARYd is a memory cell array including memory cells, word lines, dummy word lines, data lines, precharge circuits, and the like. SAGd is a sense circuit group, and includes a sensing signal line connected to the selected data line and a sense amplifier that senses a signal of the sensing signal line. The memory controller MCTLd receives a control signal from the outside and generates a control signal CTLGd to each part of the memory, and also supplies an internal address to the row address buffer XABd and the column address buffer YABd. XABd is a row address buffer, which latches the row address received from MCTLd. XDECd is a row decoder and selects a word line based on the row address latched by XABd. XDR
Vd is a word line driver, which drives a selected word line. YABd is a column address buffer, and MCTLd
Latch the column address received from. YDECd is a column decoder, and selects a data line based on the column address latched by YABd. YSWGd1 is a first column selection switch group, and connects and disconnects the selected data line and the sensing signal line. YSWGd2 is a second column selection switch group, and connects / disconnects the selected sensing signal line and the outside. IDBd is an input data buffer and receives input data from the outside through the data input / output pin DIO. ODBd is an output data buffer, and includes a main amplifier that amplifies a read signal and an output stage. The control signal is the same as in the example shown in FIG.
Are address signals, / CS1 and / CS2 are address fetch signals, / WE is a write control signal, / OE is an output control signal, and / PWD is a power down control signal. By performing column selection in two stages, it is possible to adopt a configuration in which a plurality of data lines share a sense amplifier.

FIG. 12 shows the memory cell array MC of FIG.
This is a more specific example of the ARYd portion including the sense circuit group SAGd and the column selection switch groups YSWGd1 and YSWGd2. In the figure, a memory cell MCd11 having the same configuration as that in FIG. 2, for example, is connected to a position where the word line WLd1 and the data line DLd1 intersect. Further, the memory cell MCd12 is connected to the position where the word line WLd1 and the data line DLd2 intersect. A memory cell MCd21 is connected to a position where the word line WLd2 and the data line DBd1 intersect, and the word line Wd
The memory cell MCd22 is connected to the intersection of Ld2 and the data line DBd2. Similarly, the word line W
Ldp (p = 1, 2, 3, ..., M) and data line DLdq
Or at the position where DBdq (q = 1, 2, ...) Crosses,
Memory cell MCdpq is connected. Data line DLdq
And DBdq form a pair, and detect a potential difference between them to read out a signal. Further, the dummy cell DMCDdq is provided at a position where the dummy word line DWLDd and the data line DLdq intersect.
Are connected, the dummy word line DWLBd and the data line DB
A dummy cell DMCBdq is connected at a position where dq intersects. The precharge circuit TPNdq is controlled by the precharge control line PCNdq, and when not selected, the potential VPL of the precharge potential supply line PCVPLd.
Are supplied to the data line pair DLdq-DBdq. However, the precharge control line does not have to be individually prepared for each precharge circuit, and the control line may be shared by a plurality of precharge circuits. FIG. 13 shows an example thereof, in which the precharge circuit includes precharge control lines PCNd1 and PCNd2.
The adjacent precharge circuits can be controlled independently by alternately connecting to each other. First column selection switch YSWdq
Is controlled by the column selection line YSdq, and the data line pair DL
Connection / disconnection between dq-DBdq and sensing signal line pair DLd0-DBd0 is performed. The sense amplifier SAd0 is controlled by the sense amplifier control lines SPd and SNd, and senses and amplifies the potential difference between the sense signal line pair DLd0-DBd0. The data line short circuit switch TDSd0 has a data line short circuit control line D.
Controlled by LSd, sense signal line pair DLd0-DBd
Short and open 0. Precharge circuit TRDd0
Is controlled by the precharge control line PCDd and supplies the potential VSS of the precharge potential supply line PCVSSd to the sensing signal line DLd0. Also, the precharge circuit TR
Bd0 is controlled by the precharge control line PCBd and supplies the potential VSS to the sensing signal line DBd0. The second column selection switch YSWd0 is controlled by the column selection line YSd0 and connects / disconnects the sensing signal line pair DLd0-DBd0 and the input / output line I / Od.

An example of the read operation of the circuit of FIG. 12 will be described with reference to FIG. The operation of FIG. 14 is different from the operation of FIG. 5 in that the read operation is performed based on the same principle as that of FIG. 5, but only the selected data line pair is operated. Here, a read operation waveform when the memory cell MCd11 is selected is shown. In the standby state, the potential of each word line and the dummy word line is VS, as in the above-described embodiment.
S, the potential of each data line is VPL, and the sense amplifier is inactive. Further, the column selection switches YSWd1, YSWd2,
Are non-conductive, and the sensing signal line pair DLd0-DBd0 and each data line pair are separated. Sensing signal line pair DLd0
-DBd0 is precharged with the potential VSS. Next, the read operation will be described. Time trd1
Basically, the reference potential generating operation in ~ trd3 is almost the same as the operation in time tra1 to tra3 shown in FIG. 5, but the selected data line pair DLd1-DBd
The potential VSS that is precharged to 1 is set to VCH at the potential of the column selection line YSd1 at time trd1, and the sensing signal line pair DLd0-DBd0 and the data line pair DLd1-DB are set.
This is done by connecting with d1. Further, the precharge control line PCNd2 that is not related to the selected data line pair DLd1-DBd1 maintains the same potential VDD as that in the standby state.
After that, the operation from time trd4 to trd11
The operation is substantially the same as the operation at times tra4 to tra11 shown in FIG. That is, the operation is performed in the order of sensing signal line pair separation, signal potential generation, and amplification to read information. At the end of the operation, at time trd12, the potential of the column selection line YSd1 is set to VSS, and the sensing signal line pair DLd0
-DBd0 and the data line pair DLd1-DBd1 are separated, the sensing signal line pair DLd0-DBd0 is set to the potential VSS,
The data line pair DLd1-DBd1 is precharged to the potential VPL. Then, at time trd13, the word line W
The potentials of Ld1 and the dummy word lines DWLDd and DWLBd are set to VSS, and the read operation is completed. Through the above operation, at least the selected data line pair DLd
1-DBd1 adjacent unselected data line pair DLd
2-DBd2 is fixed to the potential VPL through the precharge circuit TPNd2. As a result, the interference noise due to the parasitic capacitance between the data lines is greatly reduced, and a highly reliable read operation is performed. In particular, in the precharge circuit configuration shown in FIG. 13, the potential of the unselected data line pair adjacent to the selected data line pair is fixed to two precharge control lines PCN.
It can be efficiently performed by d1 and PCNd2. In addition to this, as shown in FIG. 9, when one of the two adjacent pairs of data line is replaced with each other, a larger noise reduction effect can be obtained. Further, since the potential of the unselected data line pair is VPL, the information of the word line WLd1 and the dummy word lines DWLDd and DWLBd and the memory cells and dummy cells connected to the unselected data line pair are not destroyed. According to this embodiment, the circuit area can be reduced by sharing the sense amplifier, and the layout margin of the sense amplifier section can be relaxed. In addition to this, since only a necessary portion of the memory cell array is operated, noise such as power consumption and power supply can be significantly reduced. Furthermore, since unnecessary polarization reversal of the ferroelectric capacitor in the unselected memory cell can be eliminated, it is possible to reduce the characteristic deterioration of the ferroelectric film.

(Embodiment 5) FIG. 15 is an embodiment showing a block configuration of a memory based on the concept of the present invention. A column decoder is provided for each of the first column selection switch group and the second column selection switch group. 11 is different from the example shown in FIG. In the figure, the first column address buffer YABd
The column address latched at 1 is the first column decoder YD
ECd1 is supplied to the first column selection switch group YSWG
Control d1. In addition, the second column address buffer YA
The column address latched by Bd2 is supplied to the second column decoder YDECd2, and the second column selection switch group YS.
Control WGd2. In this configuration, since the control line can be arranged in the word line direction from the first column decoder YDECd1, the data line connected to each sense circuit included in the sense circuit group SAGd can be selected by the common control line. .

FIG. 16 shows the memory cell array MC of FIG.
This is a more specific example of the ARYd portion including the sense circuit group SAGd and the column selection switch groups YSWGd1 and YSWGd2. In the figure, the memory mat MMd1 has the same memory cell array configuration as in FIG. However, the precharge control system uses the same configuration as in FIG. Included in the memory mat MMd1,
n sets of data line pairs DLd11-DBd11 to DLd1n
-DBd1n is selectively connected to the sense circuit SUd1 by n column selection lines YSd1 to YSdn. Similarly, n sets of data line pairs DLd21-DBd21 to DLd2n-DBd2n included in the memory mat MMd2.
Are selectively connected to the sense circuit SUd2 by column selection lines YSd1 to YSdn. Similarly, one set of sense circuits is assigned to each of the plurality of memory mats,
The connection / separation of the data line pair selected in each memory mat from the sense circuit is performed by the common column selection line YS.
It is controlled by d1 to YSdn. Not only the column selection lines, but also the word lines WLd1 to WLdm, the dummy word lines DWLDd and DWLBd, the sense amplifier control lines SPd,
SNd, data line short circuit control line DLSd, precharge control lines PCNd1, PCNd2, PCDd, PCBd, and precharge potential supply lines PCVPLd, PCVSS.
Also, d is shared by a plurality of memory mats and sense circuits. Each sense circuit SUd1, SUd2, ...
Selected by the column selection lines YSd01, YSd02, ...
It is connected to the input / output line I / Od. With this configuration, a common control system is used to access one memory cell for each sense circuit. Here, in order to repair the defective data line by providing the spare data line, the column selection line Y
A switching means may be provided between Sd1 to YSdn and the column selection switch. Note that the read operation can be performed in the same manner as in the example shown in FIG. 14 and thus is omitted here.

FIG. 17 is an example showing an address allocation method in a memory having a plurality of memory cell arrays each including one set of sense circuits as shown in FIG. FIG. 17
(A) shows the arrangement of the memory cell array. In the figure, memory mats MM11, MM12, ..., MM21,
MM22, ... Sense circuits SU11, SU1 respectively
, ..., SU21, SU22 ,. FIG. 17 (b)
Is an address signal A fetched by the memory controller MCTLd in synchronization with the address fetch signal / CS1.
The structure of drs1 is shown. The address signal Adrs1 has an s-bit configuration and is input from s address pins A0 to As-1. Of these, address pins A0 to Ar-1
The address AG0 taken in from corresponds to the row address of each memory mat shown in FIG. Further, the address AG fetched from the address pins Ar to As-1
1 corresponds to the column address of each memory mat. By the addresses AG0 and AG1, the memory cells MCS11, MCS12, ..., MCS included in the individual memory mats.
21, MCS22, ... Are respectively selected. FIG. 17
(C) is an address capture signal / C different from / CS1
The structure of the address signal Adrs2 taken into the memory controller MCTLd in synchronization with S2 is shown. The address signal Adrs2 has a u-bit configuration and is input from u address pins A0 to Au-1. In this example, s>
u, and the extra address pins Au to As-1 are don't cares. Of the address signal Adrs2, the address AG2 fetched from the address pins A0 to At-1
Corresponds to the row address of each sense circuit shown in FIG. The address AG3 fetched from the address pins At to Au-1 corresponds to the column address of each sense circuit. The sense circuit SU11 is selected by the addresses AG2 and AG3. According to the present embodiment, the number of required address pins can be reduced as compared with the configuration in which the address is taken in at one timing. Further, while having a configuration in which the sense amplifier is shared, the address can be changed while the read information is latched in the sense amplifier to easily read the information continuously and at high speed, for example, in the static column mode. be able to.

(Embodiment 6) FIG. 18 is an embodiment showing the basic concept of the present invention, in which one data line of each of two adjacent data line pairs is short-circuited to generate a reference potential. This is different from the example shown in FIG. FIG.
18A shows the basic circuit configuration, and FIG. 18B shows the flow of the read operation. In FIG. 18A, the memory cell MC11 is connected at a position where the word line WL1 and the data line DL1 intersect, and the word line WL2
And the data line DB1 intersects with each other, the memory cell MC
21 is connected. Also, the word line WL1 and the data line D
The memory cell MC12 is connected to the position intersecting with L2, and the memory cell MC22 is connected to the position intersecting with the word line WL2 and the data line DB2. Hereinafter, memory cells are connected at positions where a plurality of word lines intersect with the data line DL1 or DB1 and at positions where they intersect the data line DL2 or DB2, but they are omitted in the drawing. On the other hand, the dummy cell DMCD1 is connected at the position where the dummy word line DWLD and the data line DL1 intersect, and the dummy cell DMCD1 is connected at the position where the dummy word line DWLB and the data line DB1 intersect.
Dummy cell DMCB1 is connected. Further, at the position where the dummy word line DWLD and the data line DL2 intersect,
The dummy cell DMCD2 is connected to the dummy word line DW.
A dummy cell DMCB2 is connected at a position where LB intersects with the data line DB2. A sense amplifier SA1 is connected between the data lines DL1 and DB1, and the data line DL
A sense amplifier SA2 is connected between 2 and DB2. A data line short-circuit switch SWDS1 is connected between the data lines DL1 and DL2, and the data lines DB1 and DB2 are connected.
A data line short circuit switch SWDS2 is connected between the two. A dummy cell rewriting circuit RWDC that resets information written in the dummy cell is connected to each data line. The memory cell having the configuration shown in FIG. 2, for example, can be applied to the above memory cell and dummy cell. FIG.
A read operation from the memory cell MC11 in the circuit of FIG. 18A will be described with reference to FIG. During standby, data line short-circuit switches SWDS1 and SWD
S2 is on. In addition, the dummy cells DMCD1, D
It is assumed that one of the MCD2 stores a logic 1 and the other stores a logic 0. Similarly, one of the dummy cells DMCB1 and DMCB2 stores a logic 1 and the other stores a logic 0. First, the data line short circuit switch SWDS1 is turned off (step 201), and the data lines DL1 and DL2 are electrically separated. Next, the word line WL1 is selected and a signal potential corresponding to the information stored in the memory cell MC11 is generated on the data line DL1 (procedure 202). At the same time, the dummy word line DWLB is selected and the dummy cells DMCB1 and DMCB2 are used to select the data lines DB1 and DB1.
A reference potential is generated at 2 (procedure 203). Here, the dummy cells DMCB1 and DMCB2 have substantially the same device characteristics as the memory cell MC11 and the like, and the data lines DB1 and DCB
If B2 also has substantially the same electrical characteristics as DL1 and DL2, the reference potential generated on the data lines DB1 and DB2 is
The potential is almost the middle of the signal potentials of logic 1 and logic 0. Next, the data line short circuit switch SWDS2 is turned off (procedure 204), and the data lines DB1 and DB2 are electrically separated. Next, the potential difference between the data lines DL1 and DB1 is sensed and amplified by the sense amplifier SA1 (step 205). The logic 1 is rewritten to one of the dummy cells DMCB1 and DMCB2 and the logic 0 is rewritten to the other (procedure 206), the data line short-circuit switches SWDS1 and SWDS2 are turned back on (procedure 207), and the read operation is completed.

As a more specific configuration of the dummy cell rewriting circuit RWDC in the circuit of FIG. 18A, the configuration shown in FIG. 19 can be cited, for example. In the figure, the dummy cell rewriting circuit RWDC is shown as a switch SWWD.
1, SWWB1, SWWD2 and SWWB2, and Hi
It is composed of a gh potential supply line PCH and a Low potential supply line PCL. In the procedure 206 shown in FIG. 18B, when the switches SWWB1 and SWWB2 are turned on, the data line DB1 is at the Low potential and the data line DB2 is at the low potential.
Is supplied with a High potential. On the contrary, the data line DL1,
When DL2 is used to generate the reference potential, the switch SW
It is sufficient to turn on WD1 and SWWD2. Thereby, rewriting of the dummy cell can be easily performed. As another configuration of the dummy cell rewriting circuit RWDC in the circuit of FIG. 18A, for example, the configuration shown in FIG. 20 can be cited. In the figure, the dummy cell rewriting circuit RWDC is composed of switches SWSD and SWSB. In step 206 shown in FIG. 18B,
When the switch SWSD is turned on with the sense amplifier SA1 in the active state and SA2 in the inactive state, the sense amplifier S1
The potential opposite to the data line DB1 generated in the data line DL1 and amplified by A1, for example, the potential of the data line DB1 is Lo.
In the case of the w potential, the opposite High potential is supplied to the data line DB2. On the contrary, when the data lines DL1 and DL2 are used for generating the reference potential, the switch SWSB may be turned on. As a result, the dummy cell can be rewritten by using the configuration having a smaller number of elements than the configuration shown in FIG. According to the present embodiment, since the signal potential and the reference potential can be generated at the same time, the time from the start of the read operation to the detection of the signal by amplification is short, and high-speed access is possible compared to the example shown in FIG. .

(Embodiment 7) FIG. 21 is an embodiment showing a memory cell array configuration based on the concept of the present invention, which is a more specific example of the circuit configuration shown in FIG. In the figure, the data line short circuit switch TPSc1
Is controlled by the data line short-circuit control line DLSc0 to short-circuit / open the data line pair DLc1-DBc1. Similarly, the data line short circuit switch TPSc2 is controlled by the data line short circuit control line DLSc0, and the data line pair DLc2-.
Short and open DBc2. Data line short circuit switch T
DSc1 is controlled by the data line short-circuit control line DLSc1 to short-circuit / open the data lines DLc1 and DLc2. Further, the data line short circuit switch TDSc2 is controlled by the data line short circuit control line DLSc2, and the data line DB
Short and open c1 and DBc2. The precharge circuits TPDc1 and TPDc2 that are mainly used during standby are
It is controlled by the precharge control line PNDc and supplies the potential VPL of the precharge potential supply line PCVPLc to the data lines DLc1 and DLc2, respectively. Similarly, the precharge circuits TPBc1 and TPBc2 are controlled by the precharge control line PNBc and supply the potential VPL to the data lines DBc1 and DBc2, respectively. The precharge circuits TRDc1 and TRDc2 and TRBc1 and TRBc2 used at the time of reading are connected to the precharge control line P.
The potential VSS of the precharge potential supply line PCVSSc is controlled by the CRc at the same time and the potential VSS of the precharge potential supply line PCVSSc is changed to the data line DLc
1, DLc2 and DBc1, DBc2. The precharge circuits TWDc1 and TWDc2 used at the time of rewriting the dummy cell are the precharge control lines RW.
The potential VSS is controlled by the data line DLc1
To the potential VDD of the precharge potential supply line PCVDDc
Are supplied to the data line DLc2, respectively. Similarly, the precharge circuits TWBc1 and TWBc2 are controlled by the precharge control line RWBc and supply the potential VSS to the data line DBc1 and the potential VDD to the data line DBc2, respectively. In addition, the arrangement of the memory cells, dummy cells, sense amplifiers, and column selection switches is the same as in the example shown in FIG. That is, the memory cell MCc11 is connected to the intersection of the word line WLc1 and the data line DLc1. In addition, the word line WLc1 and the data line DLc2
A memory cell MCc12 is connected to the intersection of the two. A memory cell MCc21 is connected at a position where the word line WLc2 and the data line DBc1 intersect, and the word line Wc
A memory cell MCc22 is connected to a position where Lc2 and the data line DBc2 intersect. Similarly, the word line W
Lcp (p = 1, 2, 3, ..., M) and data line DLcq
Or at the position where DBcq (q = 1, 2, ...) Crosses,
Memory cell MCcpq is connected. A dummy cell DMCDcq is connected at a position where the dummy word line DWLDc and the data line DLcq intersect, and a dummy cell DMCDcq is connected at a position where the dummy word line DWLBc and the data line DBcq intersect.
Dummy cell DMCBcq is connected. Sense amplifier S
Acq is controlled by sense amplifier control lines SPc and SNc, and senses and amplifies a signal generated on the data line pair DLcq-DBcq. The column selection switch YSWcq is controlled by the column selection line YScq, and the data line pair DLcq-D.
Bcq and input / output line I / Oc are connected / separated.

An example of the read operation of the circuit of FIG. 21 will be described with reference to FIG. FIG. 22 shows the memory cell MCc1.
The read operation waveform when 1 is selected is shown. During standby, the potential of each word line and dummy word line is VS
S, the potential of each data line is VPL. Each sense amplifier is inactive. In addition, each data line short circuit switch is turned on. Furthermore, the dummy cells DMCDc1, D
MCBc1 has logic 0, dummy cells DMCDc2, DM
A logical 1 is written in CBc2 in advance. Next, the read operation will be described. Address capture signal / C
The row address is fetched in synchronization with the fall of S1, and the read operation is started. First, at time trc1, the potentials of the precharge control lines PNDc and PNBc are set to V
The potential of PCRc is set to VDD and the potential of each data line is precharged to VSS. Next, at time trc2, the potential of the precharge control line PCRc is set to VSS, each data line is set in a floating state, and the potentials of the data line short circuit control lines DLSc0 and DLSc1 are set to VS.
S is set to S, and only the data lines DBc1 and DBc2 are short-circuited. Next, at time trc3, the word line WLc1
Of the data lines DLc1 and DLc
2 to generate a signal potential. Read information logic 1,
Corresponding to 0, the generated signal potential is set to DLc1
(1), DLc1 (0) and DLc2 (1), DLc
It is shown in FIG. 22 as 2 (0). At the same time, the potential of the dummy word line DWLBc is also set to VCH and the data line D
A reference potential is generated in Bc1 and DBc2. next,
At time trc4, the data line short circuit control line DLSc2
Is set to VSS to separate the data lines DBc1 and DBc2, and subsequently, at time trc5, each sense amplifier is activated to set the data line pair DLc1-DBc1 and DLc.
The potential difference of c2-DBc2 is amplified. By the amplification, the read information is automatically rewritten in the memory cells MCc11 and MCc12. However, since the information opposite to that of the memory cells MCc11 and MCc12 is written in the dummy cells DMCBc1 and DMCBc2, respectively, the information opposite to that of the DMCBc1 and DMCBc2 is not always written. The output of information to the outside is
The column address is captured in synchronization with the falling edge of the address capture signal / CS2, and at time trc6, the potential of the column selection line YSc1 is set to VDD, the column selection switch YSWc1 is rendered conductive, and a signal is output to the input / output line I / Oc. It is done by doing. Here, it is possible to continuously read out a plurality of pieces of information by inputting different column addresses, or to switch the operation to the write mode, as in the above-described embodiments. The address fetching is stopped in synchronization with the rising edge of the address fetching signal / CS2, and the column selection switch YSWc1 is cut off at time trc7. Address capture signal /
In synchronism with the rising edge of CS1, the dummy cell is reset and the memory is returned to the standby state. First time tr
In c8, deactivate each sense amplifier and
The potentials of the precharge control line PNDc and the data line short circuit control lines DLSc0 and DLSc1 are set to VDD, each data line pair is short-circuited, and the potential is set to VPL. Next, time tr
At c9, the potential of the word line WLc1 is set to VSS and the memory cells MCc11 and MCc12 are returned to the standby state. Next, at time trc10, the potential of the data line short-circuit control line DLSc0 is set to VSS again, the potential of the precharge control line RWBc is set to VCH, and the potential VSS is supplied to the data line DBc1 and the potential VDD is supplied to DBc2. As a result, the dummy cell DMCBc1 has a logic 0.
However, the logic 1 is rewritten in DMCBc2. Next, at time trc11, the potential of the precharge control line RWBc is set to VSS, and the precharge control line PNBc and the data line short circuit control line DLSc0,
The potential of DLSc2 is set to VDD, each data line pair is short-circuited, and the potential is set to VPL. Then, at time trc12, the potential of the dummy word line DWLBc is set to VSS, the dummy cells DMCBc1 and DMCBc2 are returned to the standby state, and the read operation is completed. According to this embodiment,
By simultaneously generating the signal potential and the reference potential, the access time is shortened. In addition, the noise generated in the data line pair due to the capacitive coupling with the word line becomes only the in-phase component, which hardly affects the read operation. Furthermore, since the time for which the data line is in the floating state is shortened, noise immunity and soft error immunity of the read operation are improved.

(Embodiment 8) FIG. 23 is an embodiment showing a memory cell array structure based on the concept of the present invention. The circuit structure shown in FIG. 19 is used and a sense circuit is shared by a plurality of data lines. This is an example of the configuration. In the figure, the memory mat MMe1 has the same memory cell array configuration as in FIG. However, the precharge control system is
A configuration similar to that of FIG. 13 is used. N pairs of data line pairs DLe11-DBe11 to DLe11-DBe11 included in the memory mat MMe1
DLe1n-DBe1n is the n column selection lines YSe11.
~ YSe1n selectively connects to the sense circuit SUe1. A memory cell MCe11 is provided at a position where the word lines WLe11 to WLe1m and the dummy word lines DWLDe1 and DWLBe1 intersect with one of the data line pairs.
1 etc. and the dummy cell DMCBe11 etc. are connected.
The precharge control lines PCNe11 and PCNe12 are 1
Precharge potential supply line PCVP for every other pair of data lines
The potential VPL of Le1 is supplied. Similarly, n pairs of data line pairs DLe21-DB included in the memory mat MMe2 are included.
e21 to DLe2n-DBe2n are column selection lines YSe2.
1 to YSe2n selectively connects to the sense circuit SUe2. The memory cell MCe21 is provided at a position where the word lines WLe21 to WLe2m and the dummy word lines DWLDe2 and DWLBe2 intersect with one of the data line pairs.
1 etc. and the dummy cell DMCBe21 etc. are connected.
The precharge control lines PCNe21 and PCNe22 are set to 1
Precharge potential supply line PCVP for every other pair of data lines
The potential VPL of Le2 is supplied. Sense amplifier control line S
Pe and SNe are sense amplifiers SAe01 and SAe02.
To control. The precharge control line PCRe is a pair of sensing signal lines DLe01-DBe01 and DLe02-DBe02.
Is supplied with the potential VSS of the precharge potential supply line PCVSSe. The precharge control line RWDe supplies the potential VSS to the sensing signal line DLe01 and the potential VDD of the precharge potential supply line PCVDDe to the sensing signal line DLe02. The precharge control line RWBe supplies the potential VSS to the sensing signal line DBe01 and the potential VDD to DBe02. Column selection lines YSe01, YSe02
Is a sense signal line pair DLe01-DBe01, DLe02
-DBe02 is selectively output to the input / output line I / Oe. The data line short-circuit control line DLCe1 is connected to the memory mat M
The connection / separation between Me1 and the sensing signal line DLe02 is controlled, and the data line short circuit control line DBCe1 is connected to the memory mat M.
It controls connection / disconnection between Me1 and the sensing signal line DBe02. The data line short circuit control line DLCe2 controls connection / separation between the memory mat MMe2 and the sensing signal line DLe01, and the data line short circuit control line DBCe2 controls connection / separation between the memory mat MMe2 and the sensing signal line DBe01. To do. Similarly, 2 for each of the two sets of memory mats.
The sets of sense circuits are shared and assigned. In the read operation, one set of data line pairs included in the memory mat MMe1 is connected to the sense circuit SUe1, and one set of data line pairs included in the memory mat MMe2 is connected to the sense circuit SUe2. At the same time, the signal line on the side to which the dummy cell is connected of each signal line pair is short-circuited to generate the reference potential.

An example of the read operation of the circuit of FIG. 23 is shown in FIG.
4 will be described. FIG. 24 shows the memory cell MCe111.
The read operation waveforms when MCe211 and MCe211 are selected are shown. During standby, the potential of each word line and dummy word line is VSS, the potential of each data line is VPL, and the potential of each sensing signal line is VSS. Each sense amplifier is inactive. In addition, each data line short circuit switch is turned on. Furthermore, a logic 0 is written in advance in the dummy cell DMCBe11 and a logic 1 is written in the dummy cell DMCBe21. Next, the read operation will be described. The row address is captured in synchronization with the falling edge of the address capture signal / CS1 and the read operation is started. First, at time tre1, the precharge control line PCNe
11, the potential of PCNe21 to VSS, the column selection line YSe
11, the potential of YSe21 is set to VCH, and the selected data line pair DLe11-DBe11, DLe21-DBe is selected.
The potential of 21 is sensed signal line pair DLe01-DBe01, D
Precharge to the same VSS as Le02-DBe02. Next, at time tre2, the precharge control line P
The potential of CRe is set to VSS and the data line pair DLe11-
DBe11, DLe21-DBe21 are set in a floating state, and data line short-circuit control lines DLCe1, D
The potential of LCe2 is set to VSS and only the data lines DBe11 and DBe21 are short-circuited. Next, at time tre3, the potentials of the word lines WLe11 and WLe21 are set to VC.
It is set to H to generate a signal potential on the data lines DLe11 and DLe21. Corresponding to logic 1 and 0 of the read information, the generated signal potentials are respectively set to DLe11
(1), DLe11 (0) and DLe21 (1), D
It is shown in FIG. 24 as Le21 (0). At the same time,
The potentials of the dummy word lines DWLBe1 and DWLBe2 are also V
CH is set to generate a reference potential on the data lines DBe11 and DBe21. Next, at time tre4, the potentials of the data line short circuit control lines DBCe1 and DBCe2 are set to VS.
S to separate the data lines DBe11 and DBe21,
Then, at time tr5, the sense amplifiers are activated to activate the data line pairs DLe11-DBe11 and DLe2.
The potential difference of 1-DBe21 is amplified. By the amplification, the read information is automatically rewritten in the memory cells MCe111 and MCe211. As for the output of information to the outside, the column address is fetched in synchronization with the fall of the address fetch signal / CS2, the potential of the column selection line YSe01 is set to VDD at the time tr6, and the signal is output to the input / output line I / Oe. It is done by doing. Here, it is possible to continuously read out a plurality of pieces of information by inputting different column addresses, or to switch the operation to the write mode, as in the above-described embodiments. Address acquisition is stopped in synchronization with the rising edge of the address acquisition signal / CS2, and at time t
At re7, the potential of the column selection line YSe01 is set to VSS. In synchronism with the rising edge of the address capture signal / CS1, the dummy cell is reset and the memory is returned to the standby state. First, at time tre8, each sense amplifier is deactivated and the precharge control line PCN
The potentials of e11 and PCNe21 are set to VDD, and the potential of each data line pair is set to VPL. Next, at time tre9, the potentials of the word lines WLe11 and WLe21 are set to VSS, and the memory cells MCe111 and MCe211 are returned to the standby state. Next, at time tre10, the potentials of the precharge control lines PCNe11 and PCNe21 are set to VS again.
S, the potential of the precharge control line RWBe is set to VCH, and the potential VSS is applied to the data line DBe11 by D.
The potential VDD is supplied to Be21. As a result, the logic 0 is rewritten to the dummy cell DMCBe11 and the logic 1 is rewritten to the DMCBe21. Next, time tre
11, the potential of the precharge control line RWBe is set to V
When set to SS, the precharge control line PCNe11,
PCNe21 and data line short circuit control lines DLCe1, D
The potentials of BCe1, DLCe2, and DBCe2 are set to VDD, each data line pair is short-circuited, and the potential is set to VPL. Then, at time tre12, the column selection lines YSe11, Y
The potential of Se21 is set to VSS, the data line pair and the sensing signal line pair are electrically separated, and the dummy word line DWLBe1,
The potential of DWLBe2 is set to VSS and the dummy cell DMC
Be11 and DMCBe21 are returned to the standby state. Further, the potential of the precharge control line PCRe is set to VDD, and the sensing signal line pair DLe01-DBe01, DLe02-DBe.
The potential of 02 is returned to VSS. With the above, the read operation is completed. According to this embodiment, similar to the above embodiment,
The access time is shortened, and the noise resistance and soft error resistance of the read operation are improved. In addition, it is possible to reduce the circuit area by sharing the sense amplifier, relax the layout margin of the sense amplifier section, and reduce noise such as power consumption and power supply.

The concept of the present invention has been described above with reference to the embodiments. The basic concept of the present invention, namely, a data line to which a dummy cell storing a logic 1 is connected, and a data line to which a dummy cell storing a logic 0 is connected. The application of the concept of generating a reference potential intermediate between signal potentials corresponding to logic 1 and logic 0 by using the line and data line short-circuit means is not limited to the above embodiment. For example, by using a configuration in which a plurality of data lines to which dummy cells storing logic 1 are connected and the same number of data lines to which dummy cells storing logic 0 are connected are short-circuited at the same time and the reference potential is averaged. Good. In addition, changes may be made such that a circuit is formed using transistors with opposite polarities, and the vertical relationship of voltages is reversed. Furthermore, the reference potential can be generated by utilizing the concept of the present invention in a memory in which the plate electrode of the memory cell capacitor is driven as a plate line.

[0070]

As described above, according to the present invention, a nonvolatile semiconductor memory that is easy to manufacture, has a high SN ratio, and is suitable for high integration can be constructed.

[Brief description of drawings]

FIG. 1 is a diagram showing a basic circuit configuration of a memory of the present invention and a flow of a read operation.

FIG. 2 is a diagram showing a configuration of a memory cell used in the present invention.

FIG. 3 is a diagram showing a block configuration of a memory of the invention.

FIG. 4 is a diagram showing a circuit configuration of a memory cell array of the present invention.

5 is a diagram showing a read operation waveform of the circuit shown in FIG.

FIG. 6 is a diagram showing a configuration and a read operation waveform of a data line short circuit switch for reducing coupling noise in the memory cell array of the present invention.

FIG. 7 is a diagram showing a cross-sectional structure of a memory cell array of the present invention.

FIG. 8 is a diagram showing a planar layout of a memory cell array of the present invention.

FIG. 9 is a diagram showing a circuit configuration of a memory cell array of the present invention.

10 is a diagram showing read operation waveforms of the circuit shown in FIG.

FIG. 11 is a diagram showing a block configuration of a memory of the invention.

FIG. 12 is a diagram showing a circuit configuration of a memory cell array of the present invention.

FIG. 13 is a diagram showing a precharge circuit configuration used in the memory cell array of the present invention.

14 is a diagram showing a read operation waveform of the circuit of FIG.

FIG. 15 is a diagram showing a block configuration of a memory of the invention.

FIG. 16 is a diagram showing a circuit configuration of a memory cell array of the present invention.

FIG. 17 is a diagram showing an address configuration of a memory of the invention.

FIG. 18 is a diagram showing a basic circuit configuration of a memory of the present invention and a flow of a read operation.

FIG. 19 is a diagram showing a configuration of a dummy cell rewriting circuit of the memory of the present invention.

FIG. 20 is a diagram showing a configuration of a dummy cell rewriting circuit of the memory of the present invention.

FIG. 21 is a diagram showing a circuit configuration of a memory cell array of the present invention.

22 is a diagram showing read operation waveforms of the circuit shown in FIG.

FIG. 23 is a diagram showing a circuit configuration of a memory cell array of the present invention.

24 is a diagram showing read operation waveforms of the circuit shown in FIG.

FIG. 25 is a diagram showing voltage-charge characteristics of a ferroelectric capacitor.

FIG. 26 is a diagram showing a configuration of a conventional ferroelectric memory.

FIG. 27 is a diagram showing a conventional reference potential generating method.

FIG. 28 is a diagram showing a conventional reference potential generating method.

FIG. 29 is a diagram showing a conventional reference potential generating method.

[Explanation of symbols]

MC1, MC2 ... Memory cells DMCD, DM
CB ... Dummy cell SWDS ... Data line short-circuit switch WL1, WL2
... word line DWLD, DWLB ... dummy word line DL, DB ... data line SA ... sense amplifier TR1 ... cell transistor CF1 ... ferroelectric capacitor PL1 ... plate electrode MCARYa ... memory cell array MCTLa ... memory controller XABa ... row address buffer XDECa ... row Decoder XDRVa ... Word line driver YABa ... Column address buffer YDECa ... Column decoder YSWGa ... Column selection switch group SAGa ... Sense circuit group IDBa ... Input data buffer ODBa ... Output data buffer 1 ... Semiconductor substrate 2 ... Element isolation insulating film 3 ... Gate insulation Film 4 ... Word line 5, 9 ... Interlayer insulating film 6 ... Source / drain diffusion region 7, 11 ... Contact plug 8 ... Data line 10 ... Flattening insulating film 12 ... Lower electrode 13 ... Ferroelectric film 14 ... Riseru plate 24 ... dummy word lines

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication location H01L 27/108 (72) Inventor Masakazu Aoki 1-280 Higashi Koigokubo, Kokubunji City, Tokyo Hitachi Central In the laboratory

Claims (14)

[Claims] 1. A memory comprising a plurality of word lines, a plurality of dummy word lines, a pair of data lines, a word line and a data line which intersect each other, and which includes a ferroelectric capacitor. A memory cell array having dummy cells each including a cell and the dummy word line and the data line and including a ferroelectric capacitor, and reading the memory cell data stored in the memory cell. A semiconductor memory that compares a signal potential of a data line to which the memory cell is connected with a reference potential of another data line, a first dummy cell for storing information of logic 1 or logic 0; A second dummy cell that stores information opposite to that of the first dummy cell and a data line that is connected to the first dummy cell and reads the memory cell data are paired. Data line short-circuit means for short-circuiting the one data line and the second data line to which the second dummy cell is connected to each other are provided, and the first and second data lines short-circuited by the data line short-circuit means. A semiconductor memory characterized by generating a reference potential intermediate between signal potentials of logic 1 and logic 0. 2. The semiconductor memory according to claim 1, wherein the data line for reading out the memory cell data and the second data line are the same, and the generation timings of the reference potential and the signal potential are different. A semiconductor memory characterized by: 3. The semiconductor memory according to claim 1, wherein the data line for reading the memory cell data is different from the second data line, and the reference potential and the signal potential are generated at the same timing. A semiconductor memory characterized in that. 4. The semiconductor memory according to claim 1, wherein the memory cell array has a configuration of cell patterns arranged two-dimensionally continuously and regularly, and the configuration of the cell patterns is A semiconductor memory including a memory cell and a dummy cell having the same structure and the same size cell structure. 5. The semiconductor memory according to claim 4, wherein the paired data lines have a section in which an operating data line and a fixed potential data line are adjacent to each other. 6. The semiconductor memory according to claim 4 or 5, wherein data line charging means for charging said pair of data lines in an active state, and a plurality of data line charging means for controlling said data line charging means. The data line charging means is provided with a control means, and the data line charging means is controlled by any one of the plurality of data line charging control means, and by the control, the data connected to an unselected data line pair adjacent to the selected data line pair. A semiconductor memory characterized by activating a line charging means. 7. The semiconductor memory according to claim 3, further comprising dummy cell rewriting means for rewriting to said first and second dummy cells, said dummy cell rewriting means after generating said reference potential. And before the end of the read operation of the memory cell data, the first dummy cell is rewritten with a logic 1 or a logic 0, and the second dummy cell is rewritten with information opposite to that of the first dummy cell. A semiconductor memory characterized by being a thing. 8. The semiconductor memory according to claim 4, wherein the memory cell array and a sense circuit that senses a signal read to a paired data line of the memory cell array are selected. A data line selecting means for connecting the data line to the sense circuit,
A semiconductor memory, wherein the sense circuit is shared by a plurality of pairs of data lines. 9. The semiconductor memory according to claim 8, further comprising an address configuration for selecting a memory cell, the address configuration including a first address for selecting a memory cell in a memory cell array connected to each sense circuit, A semiconductor memory having a second address configuration for selecting the sense circuit. 10. A first dummy cell, a first data line connected to the first dummy cell, a second dummy cell, a second data line connected to the second dummy cell, and A memory cell connected to the first or second data line, and reading the memory cell data stored in the memory cell is performed by using the signal potential of the data line to which the memory cell is connected, In a method for driving a semiconductor memory, which is performed by comparing with a reference potential of a data line, the first and second dummy cells storing mutually opposite information are respectively connected to the shorted first and second data lines. A step of reading and generating a reference potential on the first and second data lines; a step of electrically separating the first and second data lines; a step of selecting the memory cell; Second data line A semiconductor memory comprising: a step of generating a signal potential; and a step of amplifying a difference between the signal potential and the reference potential and simultaneously storing mutually opposite information in the first and second dummy cells. Driving method. 11. The method of driving a semiconductor memory according to claim 10, wherein the step of storing mutually opposite information in the first and second dummy cells amplifies a difference between the signal potential and the reference potential, A method for driving a semiconductor memory, wherein the first and second dummy cells are selected. 12. A first dummy cell, a first data line connected to the first dummy cell, a second dummy cell, a second data line connected to the second dummy cell, and a memory. A semiconductor memory having a cell and reading the memory cell data stored in the memory cell by comparing a signal potential of a data line connected to the memory cell with a reference potential of another data line. In the driving method, the memory cell is connected to a third data line, and a process of generating a signal potential in the third data line, and the first and second dummy cells storing information opposite to each other. At the same time, and a step of reading the shorted first and second data lines respectively to generate a reference potential in the first and second data lines, and further, the first and second data lines To A step of vapor separated, process and method for driving a semiconductor memory, comprising the step of rewriting said first and second dummy cell for amplifying a difference between the signal potential and the reference potential. 13. The method of driving a semiconductor memory according to claim 12, wherein the step of rewriting the first and second dummy cells applies a high potential or a low potential to the first data line, A method for driving a semiconductor memory, characterized in that a low potential or a high potential is applied to the data line. 14. The method of driving a semiconductor memory according to claim 12, wherein the step of amplifying the difference between the signal potential and the reference potential includes the signal potential generated on the third data line and the first potential. The step of rewriting the first and second dummy cells is to amplify the difference between the reference potentials generated in the data lines, and to supply the third data line potentials to the second data lines. , A method for driving a semiconductor memory, wherein the first and second dummy cells are selected.