JP3945498B2 - Memory cell and semiconductor memory device - Google Patents

Description

  The present invention relates to a memory cell using a ferroelectric capacitor as a data holding capacitor, and a semiconductor memory device configured by arranging the memory cells in an array.

Conventionally, as this type of memory cell, one electrode of a ferroelectric capacitor is fixed to a specific potential such as a ground state, and the other electrode can be electrically connected to a plate line or a bit line. (For example, refer to Patent Document 1).
JP-A-5-13774

  By the way, in an image memory configured by arranging such memory cells in an array, normally, when an arbitrary pixel is black, “1” data is held in the memory cell corresponding to the pixel. When it is white, “0” data is held in the memory cell corresponding to the pixel. Therefore, when displaying an inverted image obtained by inverting the black and white portions of a monochrome image on a display or the like, the color data read from the ferroelectric capacitor must be inverted by a logic circuit such as an inverter. There is a problem that the output timing of the inverted image is delayed by the inversion operation in the logic circuit.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above-mentioned unresolved problems of the prior art, and to prevent a delay in the output timing of inverted data and to arrange the memory cells in an array. It is an object to provide a semiconductor memory device configured as described above.

  In order to solve the above-described problem, a memory cell according to the present invention includes a ferroelectric capacitor and a first electrode of the ferroelectric capacitor electrically connected to a plate line and the ferroelectric capacitor. A first connection element group capable of realizing a first state in which the second electrode is electrically connected to the bit line; and the second electrode of the ferroelectric capacitor is electrically connected to the plate line; and A second connection element group capable of realizing a second state in which the first electrode of the ferroelectric capacitor is electrically connected to a bit line; realization of the first state; realization of the second state; And a selection means for selecting a state in which the first and second electrodes are not connected to either the plate line or the bit line, wherein the selection means has a predetermined ferroelectric capacitor. of When holding data by holding a pole state, the first read operation for selecting the realization of the first state and reading the data is selected, and the realization of the second state is selected. The second read operation for reading the inverted data of the data read in the first read operation can be selected.

  Therefore, in the memory cell according to the present invention, when an image memory is arranged in an array, an inverted image obtained by inverting the black and white portions of a monochrome image is displayed on a display or the like. When the first state is selected when the ferroelectric capacitor holds the color data, the second state is selected. When the second state is selected, the first state is selected. By selecting, it is possible to directly read the inverted data of the held color data, and as a result, it is possible to prevent a delay in the output timing of the inverted data.

  In the memory cell according to the present invention, the first connection element group electrically connects a first bit line to the second electrode of the ferroelectric capacitor, and the second connection element The group may electrically connect a second bit line different from the first bit line to the first electrode of the ferroelectric capacitor. Thus, for example, when an image memory is configured by arranging the memory cells in an array, a plurality of ferroelectric capacitors can be electrically connected to the same bit line. When the ferroelectric capacitor is connected to the bit line, a plurality of ferroelectric capacitors can be simultaneously accessed by connecting other ferroelectric capacitors to a bit line different from the bit line.

  Furthermore, in the semiconductor memory device according to the present invention, the first connection element group electrically connects a predetermined bit line to the second electrode of the ferroelectric capacitor, and the second connection element The group may electrically connect the predetermined bit line to the first electrode of the ferroelectric capacitor. By doing so, it is not necessary to provide a peripheral circuit for selecting a bit line connected to each electrode, and the chip area can be reduced.

  In the memory cell according to the present invention, when the same data is repeatedly read from the same ferroelectric capacitor, the selection means for alternately selecting the first state and the second state each time the data is read. You may make it provide. In this way, for example, when an image memory is configured by arranging the memory cells in an array, when the image memory is serially accessed and the same data is repeatedly read from the same ferroelectric capacitor, The polarization inversion occurs in all the ferroelectric capacitors by writing, the number of polarization inversions of all the ferroelectric capacitors can be made almost equal, the degree of deterioration of all the ferroelectric capacitors is made uniform, and the characteristic changes due to the deterioration Can be made uniform for all ferroelectric capacitors.

On the other hand, a semiconductor memory device according to the present invention is characterized in that a plurality of memory cells according to any one of claims 1 to 4 are arranged in an array.
Therefore, in the semiconductor memory device of the present invention, when a reversed image obtained by inverting the black portion and the white portion of a monochrome image is displayed on a display or the like when used for an image memory, the ferroelectric capacitor is used. By connecting the plate line to the electrode to which the bit line was connected when the color data was held, and connecting the bit line to the electrode to which the plate line was connected, Inverted data can be read directly, and a delay in the output timing of the inverted data can be prevented.

In the semiconductor memory device according to the present invention, even if a pair of adjacent memory cell groups among the memory cell groups composed of the plurality of memory cells arranged in the same column share a common plate line. Good. By doing so, the number of plate lines can be reduced, and the chip area can be reduced by reducing the arrangement area of the plate lines.
Furthermore, in the semiconductor memory device according to the present invention, plate lines are individually provided in a pair of adjacent memory cells among the memory cells composed of the plurality of memory cells arranged in the same column. Also good. By doing so, each plate line is connected only to the connection element of one of the adjacent memory cell groups, and the wiring load on the plate line due to the parasitic capacitance of the connection element is approximately halved. As a result, the writing speed and reading speed to the memory cell group can be improved.

Hereinafter, an embodiment of an image memory configured by arranging memory cells of the present invention in an array will be described with reference to the drawings. In the following description, when an arbitrary pixel is black, data “1” is held in the memory cells 5 _nm and 6 _nm corresponding to the pixel, and when the pixel is white, the memory corresponding to the pixel is stored. “0” data is held in the cells 5 _nm and 6 _nm .

<Configuration of Memory Cell of the Present Invention>
FIG. 1 is a schematic configuration diagram of a semiconductor memory device using a memory cell according to the present invention. In the figure, each circuit block and circuit element constituting the semiconductor memory device are formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

In this semiconductor memory device, as shown in FIG. 1A, a memory array region 1 is formed in the center, and a plurality of bit line driving circuits and sense amplifiers are provided above the memory array region 1 in plan view. A bit line (hereinafter also referred to as BL) circuit 2 and a plurality of plate line (hereinafter also referred to as PL) driving circuits 3 are alternately arranged. Hereinafter, it is also referred to as WL.) A drive circuit 4 is provided. The bit line circuit 2, the plate line driving circuit 3, and the word line driving circuit 4 are connected to arbitrary bit lines BL1 _m , BL2 _m , plate line PL _m and word line WL1 in accordance with a control command from a control circuit (not shown). _n and WL2 _n are configured to be driven.

Among these, in the memory array region 1, a plurality of memory cells 5 _nm and 6 _nm (n = 1, 2, m = 1 to 4) are formed in an array. Two types of memory cells 5 _nm and 6 _nm are alternately formed in a horizontal column (hereinafter also referred to as a part) consisting of a plurality of memory cells 5 _nm and 6 _nm formed in an array. ing. Further, a plurality of memory cells 5 _nm and 6 _nm of the same type are formed side by side in a vertical column (hereinafter also referred to as a block).

Of these two types of memory cells 5 _nm and 6 _nm , one of the memory cells (first memory cell) 5 _nm has a ferroelectric material as schematically shown on the left side of the plan view of FIG. A capacitor Q1 _nm is formed at the center. Two bit lines BL1 _m and BL2 _m extending in the vertical direction from the bit line circuit 2 are arranged on the left side in plan view of the ferroelectric capacitor Q1 _nm , and on the right side in plan view, plate line driving is performed. One plate line PL _m extending in the vertical direction from the circuit 3 is arranged, and two word lines WL1 _n and WL2 _n extending in the horizontal direction from the word line driving circuit 4 are arranged on both upper and lower sides in plan view. ing. As shown in FIG. 2, the direction of the voltage applied to the ferroelectric capacitor Q1 _nm is a positive direction when the upper electrode is at a higher potential than the lower electrode, and conversely, the lower electrode is at a higher potential than the upper electrode. The case is negative. The same applies to the direction of the voltage applied to the ferroelectric capacitor Q2 _nm .

Further, as shown in FIG. 1B, one electrode (hereinafter also referred to as an upper electrode) of the ferroelectric capacitor Q1 _nm has a gate connected to the word line WL2 _n and one end connected to the plate line PL. The other end of an N-channel MOS transistor (hereinafter also referred to as NMOS) 7 as a switch connected to _m , and the NMOS 8 as a switch having a gate connected to the word line WL1 _n and one end connected to the bit line BL1 _m Is connected to the other end. The other electrode (hereinafter also referred to as the lower electrode) includes the other end of the NMOS 9 serving as a switch having a gate connected to the word line WL1 _n and one end connected to the plate line PL _m , and the gate connected to the word line. The other end of the NMOS 10 serving as a switch connected to WL2 _n and having one end connected to the bit line BL2 _m is connected.

Then, the word line driving circuit 4 is driven word line WL1 _n, when the word line WL1 _n in gate threshold voltage Vpp is applied, the NMOS 8 to the word line WL1 _n is connected to the gate, NMOS 8 The bit line BL1 _m connected to one end of the ferroelectric capacitor Q1 _nm is electrically connected to the upper electrode of the ferroelectric capacitor Q1 _nm connected to the other end. At the same time, the NMOS 9 whose word line WL1 _n is connected to the gate causes the plate line PL _m connected to one end of the NMOS 9 to be electrically connected to the lower electrode of the ferroelectric capacitor Q1 _nm connected to the other end. Connected. Here, the gate threshold voltage Vpp is a voltage at which the NMOSs 8 to 14 become conductive.

Similarly, the word line driving circuit 4 is driven word line WL2 _n, when the word line WL2 _n in gate threshold voltage Vpp is applied, by NMOS10 to the word line WL2 _n is connected to the gate The bit line BL2 _m connected to one end of the NMOS ₁₀ is electrically connected to the lower electrode of the ferroelectric capacitor Q1 _nm connected to the other end. At the same time, the plate line PL _m connected to one end of the NMOS 7 is electrically connected to the upper electrode of the ferroelectric capacitor Q1 _nm connected to the other end by the NMOS 7 whose word line WL2 _n is connected to the gate. Connected.

Thus, in the semiconductor memory device of this embodiment, an arbitrary plate line PL _m and the ferroelectric capacitor Q1 _nm can be electrically connected via the NMOSs 7 and 9. Therefore, for example, to prevent the case where data is read from only one ferroelectric capacitor Q1 _nm, the potential of the plate line PL _m other ferroelectric capacitors Q1 _nm to not read the data from being output it can, also, to reduce the wiring load of the plate line PL _m, it is possible to improve the writing speed and reading speed of the data.

  Incidentally, in a so-called 1-transistor 1-capacitor (hereinafter also referred to as 1T1C) type memory cell, for example, when reading data from only one ferroelectric capacitor, other ferroelectrics that do not read data are used. The plate line potential is also output to the body capacitor. Therefore, it is necessary to rewrite data to all the ferroelectric capacitors connected to the same plate line, and the wiring load on the plate line becomes large, and the data writing speed and reading speed are slow. turn into.

In addition, since one memory cell 5 _nm is formed by one ferroelectric capacitor Q1 _nm , a two-transistor two capacitor (hereinafter also referred to as 2T2C) in which one memory cell is formed by two ferroelectric capacitors. The area of the memory cell 5 _nm can be reduced and the chip area can be reduced as compared with the) type memory cell. Further, for example, by miniaturizing the transistor process and integrating the NMOSs 7 to 10 in the area of the ferroelectric capacitor Q1 _nm , the size of the memory cell area can be halved compared to the 2T2C type memory cell.

By reducing the areas of the memory cells 5 _nm and 6 _nm , the area of the redundant memory cell can be reduced, and the chip area can be further reduced. By the way, in the 2T2C type memory cell, one memory cell is composed of two ferroelectric capacitors. Therefore, the redundant memory cell must also be composed of two ferroelectric capacitors. As a result, the chip area becomes larger.

On the other hand, of the two types of memory cells 5 _nm and 6 _nm , the other memory cell (second memory cell) 6 _nm has a ferroelectric material as schematically shown on the right side in a plan view of FIG. A capacitor Q2 _nm is formed in the center. Two bit lines BL3 _m and BL4 _m extending in the vertical direction from the bit line circuit 2 are arranged on the right side of the ferroelectric capacitor Q2 _nm in plan view, and adjacent to the left side in plan view. 1 a common plate line PL _m (first memory cell 5 _nm in plan view on the left) the memory cell 5 _nm is disposed, on the upper and lower sides in plan view, the first memory cell 5 _nm and the common word line WL1 to the adjacent _n and WL2 _n are arranged.

As described above, in the present embodiment, the plate line PL _m is set between a pair of adjacent memory cells among a plurality of memory cells 5 _nm and 6 _nm arranged in the same block. Standardized. Therefore, it is possible to reduce the number of plate lines PL _m, to reduce the layout area of the plate line PL _m, it is possible to reduce the chip area.
Incidentally, in a 1T1C type memory cell in which a plate line is individually arranged for each memory cell, the number of plate lines is increased, and the arrangement area of the plate lines is increased. As a result, the chip area is increased. End up. In addition, when the number of plate lines increases, when the wiring pitch of the plate lines is small, the coupling capacity between adjacent plate lines decreases the speed of the plate lines or increases the noise propagation path, thereby increasing the memory cell. There is a risk that the data held in the memory will be destroyed.

Further, one electrode (hereinafter also referred to as an upper electrode) of the ferroelectric capacitor Q2 _nm is connected to the NMOS 11 as a switch having a gate connected to the word line WL2 _n and one end connected to the plate line PL _m . The other end is connected to the other end of the NMOS 12 as a switch having a gate connected to the word line WL1 _n and one end connected to the bit line BL3 _m . The other electrode (hereinafter also referred to as a lower electrode) has a gate connected to the word line WL1 _n and one end connected to the plate line PL _m and the other end of the NMOS 13 as a switch, and the gate connected to the word line. The other end of the NMOS 14 as a switch connected to WL2 _n and having one end connected to the bit line BL4 _m is connected.

Then, the word line driving circuit 4 is driven word line WL1 _n, when the word line WL1 _n in gate threshold voltage Vpp is applied, the NMOS 12 of the word line WL1 _n is connected to the gate, NMOS 12 The bit line BL3 _m connected to one end of the ferroelectric capacitor Q2 _nm is electrically connected to the upper electrode of the ferroelectric capacitor Q2 _nm connected to the other end. At the same time, the NMOS 13 whose word line WL1 _n is connected to the gate causes the plate line PL _m connected to one end of the NMOS 13 to be electrically connected to the lower electrode of the ferroelectric capacitor Q2 _nm connected to the other end. Connected.

Similarly, the word line driving circuit 4 is driven word line WL2 _n, when the word line WL2 _n in gate threshold voltage Vpp is applied, by NMOS14 to the word line WL2 _n is connected to the gate The bit line BL4 _m connected to one end of the NMOS 14 is connected to the lower electrode of the ferroelectric capacitor Q2 _nm connected to the other end. At the same time, the NMOS 11 having the word line WL2 _n connected to the gate causes the plate line PL _m connected to one end of the NMOS 11 to be electrically connected to the upper electrode of the ferroelectric capacitor Q2 _nm connected to the other end. Connected.

<Write>
Next, a procedure for writing data to the ferroelectric capacitors Q1 _nm and Q2 _nm will be described.
First, when “1” data is written in an arbitrary ferroelectric capacitor Q1 _nm or Q2 _nm , first, the word line driving circuit 4 gates the potential of the word line WL1 _n corresponding to the ferroelectric capacitor Q1 _nm or Q2 _nm. The threshold voltage is Vpp. Then, the ferroelectric capacitors Q1 _nm are connected to the other ends of the bit lines BL1 _m and BL3 _m connected to one end of the NMOSs 8 and 12 by the NMOSs 8 and 12 to which the word line WL1 _n is connected to the gate. And electrically connected to the upper electrode of Q2 _nm . At the same time, the plate line PL _m connected to one end of the NMOS 9 and 13 is connected to the ferroelectric capacitor Q1 _nm connected to the other end by the NMOS 9 and 13 connected to the gate of the word line WL1 _n. It is electrically connected to the lower electrode of Q2 _nm .

Next, the potential of the bit line BL1 _m or BL3 _m corresponding to (connected to) the arbitrary ferroelectric capacitor Q1 _nm or Q2 _nm is set to “0” in the bit line circuit 2, and the other bit lines The potentials of BL1 _m and BL3 _m are set to half the write voltage Vcc (hereinafter also referred to as non-selection voltage) 1/2 Vcc. At the same time, the potential of the plate line PL _m corresponding to the arbitrary ferroelectric capacitor Q1 _nm or Q2 _nm is set to the writing voltage Vcc by the plate line driving circuit 3, and the potentials of the other plate lines PL _m are not selected. The use voltage is 1/2 Vcc. The write voltage Vcc is sufficiently larger than the coercive voltage that causes polarization inversion in the ferroelectric capacitors Q1 _nm and Q2 _nm , and the non-selection voltage ½ Vcc is an anti-voltage that causes the polarization inversion. The voltage is sufficiently smaller than the voltage.

Then, the potential of the upper electrode of the arbitrary ferroelectric capacitor Q1 _nm or Q2 _nm is set to “0”, the potential of the lower electrode is set to the writing voltage Vcc, and negative writing is performed on the ferroelectric capacitor Q1 _nm or Q2 _nm. By applying the use voltage −Vcc, “1” data is written in the ferroelectric capacitor Q1 _nm or Q2 _nm . On the other hand, it corresponds to the word line WL1 _n corresponding to the arbitrary ferroelectric capacitor Q1 _nm or Q2 _nm , the non-corresponding bit line BL1 _m , BL3 _m , and the ferroelectric capacitor Q1 _nm or Q2 _nm ( ferroelectric capacitors Q1 _nm and Q2 _nm which connections are) the plate line PL _m is connected, a positive or negative non-select voltage 1 / 2Vcc, since -1 / 2Vcc only be applied, the original polarization State is maintained. Further, the In the any of the ferroelectric capacitors Q1 _nm or Q2 _nm in the non-corresponding word lines WL1 _n ferroelectric capacitors Q1 _nm and Q2 _nm that is connected, the voltage applied between the electrodes is " The same electric potential of “0” is maintained and the original polarization state is maintained.

On the other hand, any strong when writing "0" data in the ferroelectric capacitor Q1 _nm or Q2 _nm, the gate of the first potential of the word line WL1 _n corresponding to the ferroelectric capacitor Q1 _nm or Q2 _nm in word line driving circuit 4 The threshold voltage is Vpp. Then, the ferroelectric capacitors Q1 _nm are connected to the other ends of the bit lines BL1 _m and BL3 _m connected to one end of the NMOSs 8 and 12 by the NMOSs 8 and 12 to which the word line WL1 _n is connected to the gate. And electrically connected to the upper electrode of Q2 _nm . At the same time, the plate line PL _m connected to one end of the NMOS 9 and 13 is connected to the ferroelectric capacitor Q1 _nm connected to the other end by the NMOS 9 and 13 connected to the gate of the word line WL1 _n. It is electrically connected to the lower electrode of Q2 _nm .

Next, the potential of the bit line BL1 _n or BL3 _m corresponding to (connected to) the arbitrary ferroelectric capacitor Q1 _nm or Q2 _nm is set as the write voltage Vcc in the bit line circuit 2, and other bits The potentials of the lines BL1 _n and BL3 _m are set to the non-selection voltage 1 / 2Vcc. At the same time, the potential of the plate line PL _m corresponding to the arbitrary ferroelectric capacitor Q1 _nm or Q2 _nm is set to “0” by the plate line driving circuit 3, and the potentials of the other plate lines PL _m are not selected. The voltage is 1/2 Vcc.

Then, the potential of the upper electrode of the arbitrary ferroelectric capacitor Q1 _nm or Q2 _nm is set as the writing voltage Vcc, the potential of the lower electrode is set to “0”, and positive writing is performed in the ferroelectric capacitor Q1 _nm or Q2 _nm. By applying the application voltage Vcc, “0” data is written in the ferroelectric capacitor Q1 _nm or Q2 _nm . On the other hand, the word line WL1 _n corresponding to the arbitrary ferroelectric capacitor Q1 _nm or Q2 _nm , the non-corresponding bit line BL1 _m , corresponding to (connected to) the ferroelectric capacitor Q1 _nm or Q2 _nm. The ferroelectric capacitors Q1 _nm and Q2 _nm to which the plate line PL _m is connected are applied with only positive or negative non-selection voltages 1 / 2Vcc and -1 / 2Vcc, so that the original polarization state is maintained. Is done. Further, the In the any of the ferroelectric capacitors Q1 _nm or Q2 _nm in the non-corresponding word lines WL1 _n ferroelectric capacitors Q1 _nm and Q2 _nm that is connected, the voltage applied between the electrodes is " The same electric potential of “0” is maintained and the original polarization state is maintained.

<Normal reading>
Next, a procedure for reading data from the ferroelectric capacitors Q1 _nm and Q2 _nm will be described.
When data is read from an arbitrary ferroelectric capacitor Q1 _nm or Q2 _{nm as} it is, the potential of the bit line BL1 _m or BL3 _m corresponding to the ferroelectric capacitor Q1 _nm or Q2 _nm is first written in the bit line circuit 2 The voltage Vcc is set, and the potentials of the other bit lines BL1 _m and BL3 _m are set to the non-selection voltage 1/2 Vcc. At the same time, the potential of the plate line PL _n corresponding to the arbitrary ferroelectric capacitor Q1 _nm or Q2 _nm is set to “0” by the plate line driving circuit 3, and the potentials of the other plate lines PL _m are not selected. The voltage is 1/2 Vcc.

Next, the potential of the word line WL1 _n corresponding to the arbitrary ferroelectric capacitor Q1 _nm or Q2 _nm is set to the gate threshold voltage Vpp by the word line driving circuit 4. Then, the ferroelectric capacitors Q1 _nm are connected to the other ends of the bit lines BL1 _m and BL3 _m connected to one end of the NMOSs 8 and 12 by the NMOSs 8 and 12 to which the word line WL1 _n is connected to the gate. And electrically connected to the upper electrode of Q2 _nm . At the same time, the plate line PL _m connected to one end of the NMOS 9 and 13 is connected to the ferroelectric capacitor Q1 _nm connected to the other end by the NMOS 9 and 13 connected to the gate of the word line WL1 _n. It is electrically connected to the lower electrode of Q2 _nm .

Then, the potential of the upper electrode of the arbitrary ferroelectric capacitor Q1 _nm or Q2 _nm is set as the writing voltage Vcc, the potential of the lower electrode is set to “0”, and positive writing is performed in the ferroelectric capacitor Q1 _nm or Q2 _nm. by applying the use voltage Vcc, the ferroelectric capacitor Q1 _nm or to charge up the bit line BL1 _m or BL3 _m by charge transfer Q2 _nm, and "0 to the ferroelectric capacitors Q1 _nm or Q2 _nm "Write the data. Here, when “1” data is held in the ferroelectric capacitor Q1 _nm or Q2 _nm , a relatively large charge transfer occurs due to the polarization inversion, and the bit line BL1 _m or BL3 _m is relatively large. The potential VH is charged up. Further, when “0” data is held, since the polarization is not reversed, only a relatively small charge transfer occurs, and a relatively small potential VL is charged to the bit line BL1 _m or BL3 _m .

Next, it is determined whether or not the charged up potential is higher than a reference potential (a potential set between VH and VL). When the potential is larger than the reference potential, the potential is amplified to the write voltage Vcc by the sense amplifier of the bit line circuit 2 connected to the bit line BL1 _m or BL3 _m, and is smaller than the reference potential. In this case, the potential is set to “0”. That is, when “0” data is read from the ferroelectric capacitor Q1 _nm or Q2 _nm , the write voltage Vcc is output from the bit line circuit 2 and “1” data is read. "0" potential is output.

Incidentally, when a "1" data is read from the ferroelectric capacitors Q1 _nm or Q2 _nm is the first potential of the strong word line WL1 corresponding to the dielectric capacitor Q1 _nm or Q2 _{nm n} in word line driving circuit 4 The gate threshold voltage is Vpp. Next, the potential of the bit line BL1 _m or BL3 _m corresponding to the ferroelectric capacitor Q1 _nm or Q2 _nm is set to “0” in the bit line circuit 2 and the other bit lines BL1 _m and BL3 _m are not selected. The use voltage is 1/2 Vcc. At the same time, the potential of the plate line PL _m corresponding to the ferroelectric capacitor Q1 _nm or Q2 _nm is set to the writing voltage Vcc by the plate line driving circuit 3, and the other plate line PL _{m is set} to the non-selection voltage 1 /. 2Vcc. Then, by applying a negative write voltage Vcc to the ferroelectric capacitors Q1 _nm or Q2 _nm, writes "1" data to the ferroelectric capacitor Q1 _nm or Q2 _nm.

<Reading inverted data>
On the other hand, when reading inverted data from an arbitrary ferroelectric capacitor Q1 _nm or Q2 _nm , first, the potential of the bit line BL2 _m or BL4 _m corresponding to the ferroelectric capacitor Q1 _nm or Q2 _nm is set in the bit line circuit 2. The write voltage Vcc is set, and the potentials of the other bit lines BL2 _m and BL4 _m are set to the non-selection voltage 1/2 Vcc. At the same time, the potential of the plate line PL _m corresponding to the arbitrary ferroelectric capacitor Q1 _nm or Q2 _nm is set to “0” by the plate line driving circuit 3, and the potentials of the other plate lines PL _m are not selected. The voltage is 1/2 Vcc.

Next, the potential of the word line WL2 _n corresponding to the arbitrary ferroelectric capacitor Q1 _nm or Q2 _nm is set to the gate threshold voltage Vpp by the word line driving circuit 4. The ferroelectric capacitors Q1 _nm are connected to the other ends of the bit lines BL2 _m and BL4 _m connected to one end of the NMOSs 10 and 14 by the NMOSs 10 and 14 to which the word line WL2 _n is connected to the gate. And electrically connected to the lower electrode of Q2 _nm . At the same time, the plate line PL _m connected to one end of the NMOS 7 and 11 is connected to the ferroelectric capacitor Q1 _nm connected to the other end by the NMOS 7 and 11 connected to the gate of the word line WL2 _n. It is electrically connected to the upper electrode of Q2 _nm .

Then, the potential of the lower electrode of the arbitrary ferroelectric capacitor Q1 _nm or Q2 _nm is set as the writing voltage Vcc, the potential of the upper electrode is set to “0”, and negative writing is performed on the ferroelectric capacitor Q1 _nm or Q2 _nm. By applying the voltage −Vcc, the bit line BL2 _m or BL4 _m is charged up by the charge transfer of the ferroelectric capacitor Q1 _nm or Q2 _nm , and the ferroelectric capacitor Q1 _nm or Q2 _nm has “ 1 ”Write data. Here, when “0” data is held in the ferroelectric capacitor Q1 _nm or Q2 _nm , a relatively large charge transfer occurs due to the polarization inversion, and the bit line BL2 _m or BL4 _m is relatively large. The potential VH is charged up. Further, when “1” data is held, since the polarization is not reversed, only a relatively small charge transfer occurs, and a relatively small potential VL is charged to the bit line BL2 _m or BL4 _m .

Next, as in normal reading, it is determined whether or not the charged-up potential is larger than the reference potential. When the voltage is larger than the reference potential, the voltage is amplified to the write voltage Vcc by the sense amplifier of the bit line circuit 2 connected to the bit line BL2 _m or BL4 _m, and is smaller than the reference potential. In this case, the voltage is set to “0”. That is, when “1” data is read from the ferroelectric capacitor Q1 _nm or Q2 _nm , the write voltage Vcc is output from the bit line circuit 2 and “0” data is read. "0" potential is output.

When “0” data is read from the ferroelectric capacitor Q1 _nm or Q2 _nm , the word line drive circuit 4 first sets the potential of the word line WL2 _n corresponding to the ferroelectric capacitors Q1 _nm and Q2 _nm. The gate threshold voltage is Vpp. Next, the potential of the bit line BL2 _m or BL4 _m corresponding to the ferroelectric capacitor Q1 _nm or Q2 _nm is set to “0” in the bit line circuit 2 and the other bit lines BL2 _m and BL4 _m are not selected. The use voltage is 1/2 Vcc. At the same time, the potential of the plate line PL _m corresponding to the ferroelectric capacitor Q1 _nm or Q2 _nm is set to the writing voltage Vcc by the plate line driving circuit 3, and the other plate line PL _{m is set} to the non-selection voltage 1 /. 2Vcc. Then, by applying a positive write voltage Vcc to the ferroelectric capacitors Q1 _nm or Q2 _nm, writes "0" data to the ferroelectric capacitor Q1 _nm or Q2 _nm.

As described above, in the semiconductor memory device of the present embodiment, the upper electrodes of the arbitrary ferroelectric capacitors Q1 _nm and Q2 _nm are electrically connected to the plate line PL _m and the lower electrode is connected to the bit line BL1. _{m to} BL4 _m , and the lower electrodes of the arbitrary ferroelectric capacitors Q1 _nm and Q2 _nm are electrically connected to the plate line PL _m , and the upper electrode is electrically connected to the bit line. And a state in which the upper and lower electrodes of the arbitrary ferroelectric capacitors Q1 _nm and Q2 _nm are not connected to the plate line PL _m and any of the bit lines BL1 _{m to} BL4 _m can be selected. It was. When displaying an inverted image obtained by inverting the black and white portions of the monochrome image on a display or the like, the bit lines BL1 _m and BL3 _m are stored when the color data is held in the ferroelectric capacitors Q1 _nm and Q2 _nm. There connect the connected plate line electrode had PL _m, the plate line PL _m is to be connected to bit lines BL2 _m, BL4 _m to electrodes is connected. Therefore, the inverted data of the color data held in the ferroelectric capacitors Q1 _nm and Q2 _nm can be read as it is, and as a result, the output timing delay of the inverted data can be prevented.

  Incidentally, in the method of configuring an image memory by arranging 1T1C or 2T2C type memory cells in an array, when displaying an inverted image obtained by inverting the black and white portions of a monochrome image on a display or the like, ferroelectricity is used. The color data read from the body capacitor must be inverted by a logic circuit such as an inverter. As a result, the output timing of the inverted image is delayed by the inversion operation of the logic circuit. In addition, the method of inverting color data using two 1T1C type memory cells or the method of inverting color data read from a memory cell in a peripheral circuit increases the area of the memory cell and the area of the peripheral circuit. The chip area becomes large.

Also, the NMOS 8 and 12 can electrically connect the bit lines BL1 _m and BL3 _m to the upper electrodes of the ferroelectric capacitors Q1 _nm and Q2 _nm , and the NMOS 10 and 14 can connect the bit lines BL2 _m and BL4 _m to the lower electrodes. Can be electrically connected. Therefore, for example, when there are a plurality of ferroelectric capacitors Q1 _nm and Q2 _nm that can be electrically connected to the same bit lines BL1 _{m to} BL4 _m , the arbitrary ferroelectric capacitors Q1 _nm and Q2 _nm when connected to the bit line BL1 _m ~BL4 _m is other ferroelectric capacitors Q1 _nm, the Q2 _nm be to connect to the bit line BL1 _m ~BL4 _m different bit line BL1 _m ~BL4 _m, more The ferroelectric capacitors Q1 _nm and Q2 _nm can be simultaneously accessed.

In addition, the plate line PL _m is shared by the adjacent first memory cell 5 _nm and second memory cell 6 _nm . Therefore, it is possible to simultaneously read data from the adjacent first memory cell 5 _nm and second memory cell 6 _nm while preventing an increase in the chip area. For example, when serial access is made to the image memory, The speed can be doubled.
By the way, in the method of increasing the apparent access speed by providing a cache memory such as a serial access memory, the access speed can be increased, but the area of the cache memory increases and the chip area increases. End up. Further, in the method of increasing the access speed by doubling the memory cell capacity of the 1T1C type memory cell, the area of the memory cell increases and the chip area increases.

As described above, the NMOSs 7, 10, 11, and 14 in FIG. 1 constitute the first connection element described in the claims, and similarly, the NMOSs 8, 9, 12, and 13 in FIG. 1 constitute the second connection element. The upper electrodes of the ferroelectric capacitors Q1 _nm and Q2 _nm in FIG. 1 constitute a first electrode, and the lower electrodes of the ferroelectric capacitors Q1 _nm and Q2 _nm in FIG. 1 constitute a second electrode. 1 bit lines BL2 _m and BL4 _m constitute a first bit line, and bit lines BL1 _m and BL3 _m in FIG. 1 constitute a second bit line.

Further, the above embodiment shows an example of the memory cell and the semiconductor memory device of the present invention, and the configuration thereof is not limited.
For example, in the above-described embodiment, the example in which the plate line PL _m is shared by the adjacent first memory cell 5 _nm and the second memory cell 6 _nm is shown, but the present invention is not limited to this. For example, the plate lines PL1 _m and PL2 _m may be individually provided in a pair of adjacent memory cells among the memory cells composed of the memory cells 5 _nm and 6 _nm arranged in the same block. That is, as shown in FIG. 3, two plate lines PL1 _m and PL2 _m are extended in the vertical direction from each plate line drive circuit 3, and the NMOS 7 of the first memory cell 5 _nm is extended to the extended plate line PL1 _m . , connect one end of the 9, may be connected to NMOS11,13 end of the second memory cell 6 _nm to the plate line PL2 _m. If that way, each plate line PL1 _m, PL2 _m, of the adjacent memory cells 5 _nm, 6 _nm, is only NMOS7,9 or 11, 13 of one of the memory cells 5 _nm or 6 _nm is connected The wiring loads of the plate lines PL1 _m and PL2 _m due to the junction capacitances of the NMOSs 7, 9 or 11 and 13 can be reduced to almost half, and as a result, the writing speed and the reading speed can be improved. At that time, in order to prevent an increase in coupling capacitance, it is preferable to form the adjacent plate lines PL1 _m and PL2 _m in different layers on the semiconductor substrate.

In addition, two bit lines BL1 _m , BL2 _m or BL3 _m , BL4 _m are provided for one memory cell 5 _nm or 6 _nm , and a bit is formed on the lower electrodes of the ferroelectric capacitors Q1 _nm and Q2 _nm with NMOS 10 and 14. An example in which the lines BL2 _m and BL4 _m can be electrically connected and the bit lines BL1 _m and BL3 _m can be electrically connected to the upper electrodes of the ferroelectric capacitors Q1 _nm and Q2 _nm by the NMOSs 8 and 12 is shown. However, it is not limited to this. For example, one bit line BL1 _m or BL3 _m is provided for one memory cell 5 _nm or 6 _nm , and bit lines are formed on both electrodes of the ferroelectric capacitor Q1 _nm or Q2 _nm with NMOSs 8, 10 or 12, 14 the BL _m may be electrically connected. That is, as shown in FIG. 4, one bit line BL1 _m , BL3 _m is extended from each bit line driving circuit 2 to one memory cell 5 _nm , 6 _nm in the vertical direction, and the bit line BL1 _m One end of the NMOS 8 and 10 of the first memory cell 5 _nm may be connected, and one end of the NMOS 12 and 14 of the second memory cell 6 _nm may be connected to the bit line BL3 _m . By doing so, it is unnecessary to provide a peripheral circuit for selecting the bit line BL _m, it is possible to reduce the chip area.

Furthermore, when reading data from the ferroelectric capacitors Q1 _nm and Q2 _nm , the bit lines BL1 _m and BL3 _m are connected to the upper electrode, and the plate line PL _m is connected to the lower electrode. However, it is not limited to this. For example, connected to each of the read, the first state of connecting to and lower electrode connected to the plate line PL _m to the upper electrode bit lines BL1 _m, BL3 _m, the bit line BL1 _m, BL3 _m to the upper electrode and as the second state of connecting the plate line PL _m in the lower electrode is alternately selected, and may control the BL circuit 2, PL drive circuit 3 and the WL driver circuit 4. By doing so, for example, when data read from the ferroelectric capacitors Q1 _nm and Q2 _nm is rewritten, it is possible to cause polarization inversion in the ferroelectric capacitors Q1 _nm and Q2 _nm. The deterioration characteristics due to can be made almost equal for all the ferroelectric capacitors Q1 _nm and Q2 _nm .

By the way, when reading data from the ferroelectric capacitors Q1 _nm and Q2 _nm , the method in which the bit lines BL1 _m and BL3 _m are always connected to the upper electrode and the plate line PL _m is connected to the lower electrode is ferroelectric. capacitors Q1 _nm, when rewriting the data read from Q2 _nm, "0" ferroelectric capacitor Q1 _nm which data is read, it can not be poled in Q2 _nm. Therefore, deterioration characteristics due to polarization inversion differ depending on the ferroelectric capacitors Q1 _nm and Q2 _nm , and variations occur in the potentials VH and VL charged up to the bit lines BL1 _m and BL3 _m. The read margin must be set large.

In the above embodiment, the example in which the memory cell of the present invention is arranged in an array to configure the image memory is shown, but the present invention is not limited to this. For example, a device memory for performing addition or subtraction of binary numbers may be configured. By doing so, inverted data, that is, one's complement can be easily obtained, so that subtraction of binary numbers can be easily performed.
Incidentally, in the method of obtaining a one's complement using two 1T1C type memory cells or the method of obtaining the one's complement by inverting data read from a 1T1C type memory cell in a peripheral circuit, the area of the memory cell As a result, the area of the peripheral circuit increases, and as a result, the chip area increases.

It is a block diagram which shows one Embodiment of the memory cell of this invention. It is a figure for demonstrating the characteristic of the ferroelectric capacitor of FIG. It is a block diagram which shows the modification of the memory cell of this invention. It is a block diagram which shows the modification of the memory cell of this invention.

Explanation of symbols

BL1 _m, BL2 _m, BL3 _m, BL4 _m are bit lines, PL _m, PL1 _m, PL2 _m are plate lines, WL1 _n, WL2 _n are word lines, 1 is a memory cell array, 2 is a bit line circuit, 3 is Plate line drive circuit, 4 is a word line drive circuit, 5 _nm is a first memory cell, 6 _nm is a second memory cell, 7, 9, 11, and 13 are NMOS (first connection elements), 8, 10, 12, 14 is NMOS (second connection element), Q1 _nm, Q2 _nm are ferroelectric capacitors

Claims (7)

A first ferroelectric capacitor and a first electrode of the ferroelectric capacitor are electrically connected to the plate line, and a second electrode of the ferroelectric capacitor is electrically connected to the bit line. A first connection element group capable of realizing a state, and the second electrode of the ferroelectric capacitor electrically connected to a plate line, and the first electrode of the ferroelectric capacitor electrically connected to a bit line A second connection element group capable of realizing a second state connected to the first state, realization of the first state, realization of the second state, and the first and second electrodes serving as the plate line and the bit. Selecting means for selecting the realization of a state not connected to any of the lines,
The selecting means selects a realization of the first state and reads the data when the ferroelectric capacitor holds data by holding a predetermined polarization state; And a memory cell, wherein the second read operation for reading the inverted data of the data read in the first read operation by selecting the realization of the second state can be selected.   The first connection element group electrically connects a first bit line to the second electrode of the ferroelectric capacitor, and the second connection element group includes the first connection element group of the ferroelectric capacitor. 2. The memory cell according to claim 1, wherein a second bit line different from the first bit line is electrically connected to the electrode.   The first connection element group electrically connects a predetermined bit line to the second electrode of the ferroelectric capacitor, and the second connection element group includes the first electrode of the ferroelectric capacitor. 2. The memory cell according to claim 1, wherein the predetermined bit line is electrically connected to the memory cell.   4. When the same data is repeatedly read out from the same ferroelectric capacitor, selection means for alternately selecting the first state and the second state each time the data is read out is provided. The memory cell according to any one of the above.   5. A semiconductor memory device comprising a plurality of memory cells according to claim 1 arranged in an array.   6. The semiconductor memory device according to claim 5, wherein a plate line is shared by a pair of adjacent memory cell groups among the memory cell groups composed of the plurality of memory cells arranged in the same column.   6. The semiconductor memory device according to claim 5, wherein a plate line is individually provided in a pair of adjacent memory cells among the memory cells composed of the plurality of memory cells arranged in the same column. .

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