JP2001351386A - Semiconductor memory and its operation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce largely the bit cost keeping the constitution of so to speak gain cell as it is. SOLUTION: This method is an operation method of a semiconductor memory having a write-in transistor Q1, plural memory cells MC having a read-out transistor Q2 of which a gate is connected to a first impurity region being a source or a drain of the write-in transistor Q1 and a gate is a storage node SN, write-in word lines WWL to which a gate of the write-in transistor Q1 is connected in the direction of word, bit lines BL to which a second impurity region being sources or drains of both transistors Q1, Q2 are connected in the direction of bit, and a read-out word line RWL capacity-coupled with the storage node SN, voltage of the write-in word line WWL and voltage of the bit line BL are controlled, voltage of ternary or more is written in plural storage nodes SN in plural memory cells MC and held.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has a memory cell called a so-called gain cell, and stores data held in the memory cell by a bit line without lowering the amplitude by supplying a charge through a read transistor. And a method of operating the same.

[0002]

2. Description of the Related Art In a DRAM that holds a signal voltage by the capacity of a capacitor and stores information according to the held signal voltage, memory cells have been increasingly miniaturized in recent years as the capacity has increased. . The miniaturization of the memory cell causes a decrease in the capacitance of the capacitor. As a result, the amplitude of the read signal is reduced, and it is becoming difficult to secure the stability of operation at the time of reading and to guarantee the accuracy of the read data. For this reason, a so-called gain cell, which holds a signal voltage at the gate of a read transistor and outputs a signal voltage to a bit line without causing a decrease in amplitude due to charge supply via the read transistor during reading, has been receiving attention.

The gain cell (memory cell MC) has a write transistor Q as shown in FIGS.
1, a read transistor Q2 and a capacitor (CAP or C). The write transistor Q1 has its gate connected to the write word line WWL, and is connected between the storage node SN and the bit line BL. The read transistor Q2 has a gate connected to the storage node SN and a source connected to the bit line BL. In FIG. 2, the drain of the read transistor Q2 is connected to the read word line RWL, and in FIG. 3, the drain of the read transistor Q2 is connected to the supply line of the power supply voltage V _CC . These read transistors Q2
Need only be biased at the time of reading. Therefore, in FIG. 2, the number of wires is reduced by using the supply line of the power supply voltage V _cc for applying the drain bias of the read transistor Q2 and the read word line RWL together.

A capacitor (CAP or C) is provided for capacitively coupling the read word line RWL to the storage node SN. In FIG. 3, for example, MIM (Metal
-Insulator-Metal), the capacitor C is provided. In FIG. 2, the capacitor C can be configured using the parasitic capacitance Cp between the gate and the drain of the read transistor Q2. Therefore, the actual number of elements of the memory cell of FIG. 2 can be smaller than that of FIG.

In writing, one of binary voltages corresponding to write data "1" and "0" is set to the bit line BL, and the write word line WWL is driven to turn on the write transistor Q1. Thereby, the bit line voltage is transmitted to storage node SN. Thereafter, when the write transistor Q1 is turned off, the storage node SN is in an electrically floating state, so that the bit line voltage is held as storage data in the storage node SN. The threshold voltage is set so that the read transistor Q2 does not turn on in this storage state. For example, the voltage corresponding to the storage data “1” is 0.75 V, and the storage data “0”
Is 0 V, the threshold voltage VthQ2 of the read transistor Q2 is set to about 0.9 V so that the read transistor Q2 is not turned on even by the voltage 0.75V of the storage data "1".

In reading, the bit line is set to a floating state at 0 V, and the voltage of the read word line RWL is raised to a high level. Thereby, the voltage of storage node SN rises due to capacitive coupling via capacitor CAP or C. In boosting the storage node SN, the boosted voltage of the storage data “1” is higher than the threshold voltage VthQ2 of the read transistor Q2, and the storage data “0”
Is determined in advance so that the boosted voltage becomes lower than the threshold voltage VthQ2. Therefore, when the storage data is “1”, the read transistor Q2 is turned on, and the bit line BL outputs the voltage VBLh obtained by subtracting the threshold voltage VthQ2 from the boosted voltage of the storage data “1”.
To rise. On the other hand, when the storage data is “0”, the read transistor Q2 does not turn on, so that the bit line voltage is maintained at 0V. By amplifying the bit line voltage difference by a sense amplifier, binary storage data is detected and read.

In a one-transistor, one-capacitor DRAM, the bit line voltage changes at the time of reading due to the discharge of the charge stored in the capacitor. Therefore, if the load capacitance of the bit line is large, only a slight bit line voltage change can be obtained. . On the other hand, in the above-described gain cell, the electric charge that causes a voltage change on the bit line BL at the time of reading is stored in the power supply voltage V.
_It is supplied from the _CC supply line or the read word line RWL. Therefore, even when the load capacitance of the bit line BL is large, the bit line BL rapidly changes to the relatively large voltage VBLh. Therefore, the gain cell has advantages that the read operation is stable, noise-resistant, and hard to malfunction as compared with the DRAM cell.

Further, the capacitor CA in the gain cell
Since P and C are used for boosting the storage node SN, their capacitance values can be smaller than the capacitors of the DRAM cells. Therefore, unlike a capacitor of a DRAM cell, it is not necessary to form a lower electrode in a complicated shape or introduce a capacitor dielectric film having a high dielectric constant in order to increase the capacitance value of the gain cell. And the compatibility with the logic process is high.

[0009]

However, the conventional gain cell requires two transistors for writing and reading, so that the cell area is large, which is required to increase the capacity of the semiconductor memory and reduce the bit cost. Was an obstacle.

Since the two-transistor structure is necessary for the stable operation of the gain cell, there has been an attempt to reduce the cell area by using one of the TFTs and stacking the TFT on the other bulk transistor. However, T
Since the FT-type and bulk-type transistors are formed in separate steps, this means that the gain cell is formed by a simple manufacturing process to reduce the manufacturing cost, and the significance of adopting the gain cell is to ensure consistency with the logic process. Will be impaired.

An object of the present invention is to provide a semiconductor memory device having a memory cell including two transistors called a so-called gain cell and capable of greatly reducing bit cost while keeping the memory cell configuration as it is, and an operation method thereof. It is in.

[0012]

According to a first aspect of the present invention, there is provided a method of operating a semiconductor memory device, comprising: a writing transistor; and a gate connected to a first impurity region having a gate serving as a source or a drain of the writing transistor. , A plurality of memory cells having a read transistor serving as a storage node, a write word line in which the gates of the write transistor are connected in a word line direction, and a second impurity serving as a source or a drain of the write transistor and the read transistor. An operation method of a semiconductor memory device having a bit line having regions connected in a bit line direction and a read word line capacitively coupled to the storage node, wherein a voltage of the write word line and a voltage of the bit line are controlled. And a plurality of storage nodes in the plurality of memory cells It is held write voltage above.

In the present invention, at the time of writing, one of the four or more voltages is set to the bit line, and a constant write word line voltage is applied to the write word line to turn on the write transistor. The set voltage of the bit line is transmitted to the storage node through the conductive write transistor. Alternatively, at the time of writing, a constant voltage is set to the bit line, a write word line voltage corresponding to a voltage to be written to the storage node is applied to the write word line, and the write transistor is turned on. A voltage obtained by subtracting the threshold voltage of the writing transistor from the voltage is set in the storage node.

In the former write method, the maximum value of the voltage set on the bit line is a voltage value obtained by subtracting the threshold voltage of the write transistor from the write word line voltage and the threshold voltage of the read transistor. Less than. The maximum value of the voltage written to the storage node in the latter writing method is smaller than both the constant voltage set for the bit line and the threshold voltage of the read transistor. In the latter writing method, the voltage of the bit line is set such that a constant write bit line voltage is applied to a bit line to which a memory cell to be operated is connected, and a ground voltage is applied to other bit lines. Further, writing may be performed a plurality of times while switching the write word line voltage so that the voltage value gradually decreases, and a voltage of four or more values may be written to a plurality of memory cells connected to the same word line.

In the present invention, at the time of reading, the bit line is floated at the ground voltage, a read word line voltage is applied to the read word line to boost the storage node voltage, and the read transistor is turned on or off. The voltage corresponding to the boosted voltage of the storage node is caused to appear on the bit line and read. In this case, the read word line voltage is a constant voltage that allows the four or more voltages corresponding to all the four or more voltages held in the storage node to appear on the bit line. For example,
The read word line voltage is within a range where the read transistor is kept off when the voltage of the storage node is boosted from the minimum value of the four or more voltages, and is turned on when the voltage is boosted from another voltage value. Is a constant voltage.

Alternatively, the read word line voltage is gradually increased stepwise and applied a plurality of times, and each time the voltage is applied, a voltage corresponding to the storage node voltage is displayed one by one on the bit line and read.

In the first memory cell in which the operation method of the present invention is preferable, the read word line is coupled to the storage node via a capacitor provided for each memory cell, and the first impurity of the read transistor is connected to the storage node. The region is connected to the power supply line. Alternatively, a first impurity region of the read transistor is connected to the read word line, and the read word line is connected to the storage node via a parasitic capacitance (and a capacitance element) in the read transistor. The bit line may be common for writing and reading, or may be provided separately. In the latter case, the bit line comprises a write bit line connecting the second impurity region of the write transistor in the bit line direction and a read bit line connecting the second impurity region of the read transistor in the bit line direction.

In the method of operating a semiconductor memory device according to the first aspect of the present invention, two or more bits of data are written in one memory cell by any of the above-described methods. The written data of 2 bits or more is read. In particular, in reading, the stored data is converted from the gate voltage of the reading transistor to the source voltage and appears on the bit line while maintaining the steepness of the voltage value distribution among the plurality of memory cells. This is because the charge supply of the bit line voltage change is performed from the read word line or the power supply voltage supply line, so that the bit line voltage at the time of readout decreases the signal voltage due to the bit line load capacitance and the variation of the bit line load capacitance. Because it is hardly affected by Therefore, in the present invention, the difference between the maximum voltage value and the minimum voltage value of the bit line voltage at the time of reading is large, and therefore, it is easy to relatively increase each voltage step width and increase the number of storage bits per cell. It is.

A semiconductor memory device according to a second aspect of the present invention includes a write transistor and a read transistor whose gate is connected to a first impurity region serving as a source or drain of the write transistor and whose gate serves as a storage node. A plurality of memory cells, a write word line in which gates of the write transistors are connected in a word line direction, and a second source or drain of the write transistor and the read transistor.
A bit line in which an impurity region is connected in a bit line direction, and a semiconductor memory device having a read word line capacitively coupled to the storage node, wherein a voltage of the bit line and a voltage of the write word line are controlled, There is further provided a control circuit for writing a voltage of four or more values to a plurality of storage nodes in the plurality of memory cells.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a block diagram showing a main part of a memory cell array of a semiconductor memory device according to first and second embodiments of the present invention and peripheral circuits thereof.

As shown in FIG. 1, the memory cell array
M × n (m, n: any natural number) memory cells MC11, MC12,..., MC2 arranged in a matrix
,..., MCmn. In the memory cell array, each memory cell group in the same row is connected to the same write word line WWLj (j = 1, 2,..., N) and read word line RWLj, and each memory cell group in the same column is connected to the same bit line BLi ( i = 1, 2,..., m). A reference cell R is provided for each bit line BLi.
Ci, a sense amplifier SAi, and a circuit for initializing a bit line voltage, for example, a discharge circuit DCHi are connected to each other.

The reference cells RC1, RC2,..., RCm are:
It is commonly connected to a reference write word line RWWL and a reference read word line RRWL in the word line direction.
Each of the reference cells RC1, RC2,..., RCm has a bit complementary line / BL1, / BL2 in the bit line direction.
.., / BLm. Bit supplementary line / BL1,
/ BL2,..., / BLm are bit lines BL1,
BL2,..., BLm.

The sense amplifier SAi is connected to the bit line BLi
, And a corresponding bit line consisting of a complementary bit line / BLi. The sense amplifier SAi is activated by sense amplifier drive lines SPL and SNL in the word line direction. The discharge circuit DCHi is connected to the control line E
Q controls.

A bit line drive circuit BLD is connected to all bit line pairs. This bit line drive circuit BLD
Includes a switch that separates a bit line selected according to a column selection signal from a subsequent input / output circuit or the like and sets the bit line to a floating state at the time of reading. Further, in the present embodiment (first embodiment), the bit line drive circuit BLD applies any one of four or more voltages according to the number of bits of the stored data to the selected bit line at the time of writing. Including a configuration for switching to another voltage as needed. The bit line drive circuit BLD applies a constant voltage to the bit line at the time of writing in a second embodiment described later.

A word line driving circuit WLD is connected to the write word lines WWL1,..., The read word lines RWL1,..., The reference write word line RWWL, and the reference read word line RRWL. At the time of writing, reading, or refreshing, a word line is selected by the word line drive circuit WLD, and a write word line voltage is applied to the selected write word line, or a read word line voltage is applied to the selected read word line. Is done. In the present embodiment (first embodiment), the write word line voltage applied by the word line drive circuit WLD is a constant voltage. However, in the second embodiment described later, four words corresponding to the number of bits of storage data at the time of writing are used. Any voltage equal to or higher than the value is applied to the selected write word line WWL, and is switched to another voltage as needed.

FIGS. 2 and 3 show circuit examples of the memory cell. Note that the reference cell has the same basic configuration as the memory cell. The memory cell MC shown in FIG. 2 includes a write transistor Q1, a read transistor Q2, and a capacitor C.

The write transistor Q1 has a gate connected to the write word line WWL and one of a source and a drain connected to the bit line BL. The read transistor Q2 has a gate connected to the other of the source and the drain of the write transistor Q1, and a source connected to the bit line B.
L, and the drain is connected to the read word line RWL. Capacitor C is formed of, for example, a capacitive element having a MOS structure or a parasitic capacitance Cp between the gate and drain of read transistor Q2. When the capacitor is composed of a capacitance element, the parasitic capacitance Cp of the transistor is connected in parallel to the capacitance element (external capacitance element Cex1) on the equivalent circuit shown in FIG. This external capacitance element Cex1
Is connected to a connection midpoint between the read transistor Q2 and the write transistor Q1, and the other electrode is connected to the read word line RWL. The gate of the read transistor Q2 capacitively coupled to the read word line RWL in this manner becomes the storage node SN of the memory cell MC.

Hereinafter, write and read operations will be described by taking as an example the case of writing two bits, that is, a quaternary voltage, to the storage node SN. In the following description, the memory cell configuration shown in FIG. 2 is assumed. FIGS. 5 and 6 are timing charts showing voltage changes at the common connection line and the storage node of the memory cells. FIG. 5 shows a write operation and FIG. 6 shows a read operation.

The write operation is performed collectively on a plurality of memory cells arranged on the same row. First, after all the bit lines BL are discharged by the above-described discharge circuit DCH, the above-mentioned bit line driving circuit BLD
4 bits for each bit line according to the logic of the storage data to be written
A voltage at any level of the value is set. As shown in FIG. 5C, for example, the bit line setting voltage is 0 V when the storage data is "00", 0.25 V when the storage data is "01", and 0.5 V when the storage data is "10". And 0.75 V when the stored data is "11". The write transistor Q1 and the read transistor Q
The threshold voltage of No. 2 is higher than the maximum value of the four values of 0.75 V, for example, 0.9 V.

The voltage of the read word line RWL is
As shown in (B), it is maintained at 0 V during the write operation. On the other hand, as shown in FIG. 5A, the write word line WWL rises from a low level (for example, 0 V) to a high level (for example, 2 V) at a stage where the bit line voltage is stabilized after setting. . The drive voltage 2V of the write word line WWL is such that the voltage value 1.1V obtained by subtracting the threshold voltage 0.9V of the write transistor Q1 from the voltage is higher than the maximum value 0.75V of the above four values. Is decided. As a result, most of the write transistors Q1 in the word line direction are turned on, and FIG.
As shown in (D), the bit line setting voltage is transmitted to storage node SN as it is.

Thereafter, as shown in FIG. 5A, the write word line WWL is returned from 2 V to 0 V, the storage node SN enters an electrically floating state, and the write operation ends. At this time, the threshold voltage of the read transistor Q2 is 0.9 V, and the maximum value of the stored data is 0.7.
Since the voltage is higher than 5V, the read transistor Q2 does not turn on, and thereafter the storage data holding state is maintained.

The read operation is also performed collectively on a plurality of memory cells arranged on the same row. As shown in FIG. 6A, the write word line WWL is maintained throughout the read period.
Is maintained at the low level, and the write transistor Q1 maintains the off state. First, under the control of the control line EQ, the discharge circuit DCH discharges all the bit lines BL to set the ground potential to 0V. Thereafter, the bit line drive circuit BLD sets all the bit lines BL to a floating state.

As shown in FIG. 6B, a high-level read word line voltage, for example, 1.5 V is applied to the read word line RWL. When the read word line voltage is applied, the gate capacitance Vp of the read transistor Q2 is changed by the coupling capacitance Cp between the gate and the drain of the read transistor Q2.
g (storage node voltage) is raised. At this time, the boost amount of the gate voltage Vg depends on the magnitude of the coupling capacitance Cp. The voltage applied to the read word line RWL is distributed to the coupling capacitance Cp and other transistor parasitic capacitances.
At this time, the higher the capacitance ratio (coupling capacitance coefficient) of the coupling capacitance Cp to the total capacitance, the larger the boost amount of the gate voltage Vg. To increase the coupling capacitance coefficient, an external capacitance element Cex1 may be added as shown in FIG. When the voltage applied to the read word line RWL is different from the drain voltage of the read transistor Q2 and the coupling capacitance coefficient is desired to be set arbitrarily, the memory cell configuration shown in FIG. 3 can be adopted. Now, assuming that the coupling capacitance coefficient is 0.67, 1 V (= 1.5 V × 0.67) is added to the voltage of the storage node SN. Therefore, the voltage of the storage node SN is 1.75 V, 1.5 V, 1.25 V, and 1.0 V in order from the higher storage data as shown in FIG.

On the other hand, 1.5 V is applied between the source and the drain of the read transistor Q2, and the voltage between the source and the gate is 0.9 V or more (threshold voltage or more). All the read transistors Q2 of the connected memory cells are turned on. As a result, charges are supplied from the read word line RWL, and the voltage of each bit line BL increases. When the bit line voltage increases to some extent, the read-out transistor Q2 shifts to the cutoff state because the voltage between the source and the gate of the read transistor Q2 decreases. The source voltage (bit line voltage) that shifts to the cutoff state depends on the gate voltage Vg (the boosted voltage of the storage node SN). That is, when the bit line voltage rises to a voltage obtained by subtracting the threshold voltage of the read transistor Q2 from the boosted voltage of the storage node SN, each read transistor Q2 is cut off. Therefore,
As shown in FIG. 6C, the bit line voltage when the storage data is “11” is 0.85 (= 1.75−0.9) V. Similarly, when the storage data is “10”, the bit line voltage is 0.6 (= 1.5−0.9) V, and the storage data “01”
Is 0.35 (= 1.25-0.
9) V, the bit line voltage when the storage data is “00” is 0.1 (= 1.0−0.9) V.

As described above, in the present embodiment, a bit line voltage corresponding to the stored data can be obtained by one reading.
Thereafter, when the bit line voltage is stabilized, the sense amplifier SA
Is activated to perform reading. At this time, since the step of changing the bit line voltage is 0.25 V, which is the same as that of the stored data, the bit line voltage difference can be amplified by a normal sense amplifier.

Second Embodiment The second embodiment relates to another operation method of the semiconductor memory device. In the second embodiment, FIGS. 1 to 4 can be applied as they are. However, in the semiconductor memory device according to the present embodiment, an input / output circuit, not shown in FIG.
In the case of bit storage, it includes at least three column registers and an output circuit that determines a column register in which “1” is temporarily stored and outputs the determination result as 2-bit storage data.

FIGS. 7 and 8 are timing charts showing a voltage change in a common connection line of a memory cell and a storage node in the operation method of the semiconductor memory device according to the second embodiment. FIG. 7 shows a write operation and FIG. 8 shows a read operation. FIG. 9 shows the transition of the storage node voltage at the time of writing and at each reading stage. In the second embodiment, as shown in FIG. 7, writing to a plurality of memory cells arranged in the same row is achieved through three writing operations. Also, the storage data written in the same row is
As shown in FIG. 8, data is read through three read operations. In the following description, the write transistor Q
The threshold voltages of the first transistor 1 and the read transistor Q2 are both set to 0.875V.

In writing, first, all the bit lines BL
Is discharged by the above-described discharge circuit DCH. After that, the bit line BL to which the memory cell to which the storage data "11" is to be written is connected to 0 V by the bit line driving circuit BLD as shown in FIG.
To a predetermined voltage, for example, 1.5V. When the bit line voltage is stabilized, as shown in FIG. 7A, the write word line WWL is raised from 0V to a first-stage voltage, for example, 1.625V. As a result, the write transistor Q1 of the memory cell to which the storage data “11” is to be written is turned on, and as shown in FIG. 7C, the threshold voltage of the write transistor Q1 is changed from the first stage write word line voltage of 1.625V. A voltage of 0.875 V was subtracted.
The voltage of 75 V (first storage node voltage) is applied to storage node SN
Appear in. After that, the write word line WWL is changed to 1.6.
When the voltage is returned from 25 V to 0 V, the first-stage writing is completed. Note that the threshold voltage of the read transistor Q2, 0.875V, is higher than the first storage node voltage, 0.75V, so that the read transistor Q2 does not turn on.

In the second stage of writing, the storage data "1"
Bit line B to which a memory cell to which 0 "is to be written is connected.
L is raised from 0V to 1.5V. When the bit line voltage is stabilized, the write word line WWL is set to a second stage voltage lower than the first stage voltage of 1.625 V, for example, 1.3.
Start up from 0V to 75V. As a result, the write transistor Q1 of the memory cell into which the storage data "10" is to be written is turned on, and the threshold voltage 0.875V of the write transistor Q1 is subtracted from the second write word line voltage 1.375V of 0.5V. (Second storage node voltage) appears at storage node SN. At this time, the write transistor Q1 of the “11” write cell
0.625 (1.375-0.7)
5) Since only the voltage of V is applied, the write transistor Q1 of the "11" write cell is not turned on. Thereafter, when the write word line WWL is returned from 1.375 V to 0 V, the second-stage write is completed. The threshold voltage of 0.875 V of the read transistor Q2 is
Since the storage node voltage is higher than 0.5 V, the read transistor Q2 of the “10” write cell does not turn on.

In the third stage of writing, the storage data "0"
Bit line B to which a memory cell to which 1 "is to be written is connected.
L is raised from 0V to 1.5V. When the bit line voltage becomes stable, the write word line WWL is raised from 0V to a third stage voltage lower than the second stage voltage 1.375V, for example, 1.125V. As a result, the write transistor Q1 of the memory cell to which the storage data "01" is to be written is turned on, and the threshold voltage 0.875V of the write transistor Q1 is subtracted from the third write word line voltage 1.125V of 0.25V. Voltage (third
Storage node voltage) appears at storage node SN. In addition,
At this time, 0.375 (= 1.125) is applied to the gate and source of the write transistor Q1 of the “11” write cell.
−0.75) V, and only a voltage of 0.625 (= 1.125−0.5) V is applied to the gate and source of the write transistor Q1 of the “10” write cell. The write transistors Q1 of these already written cells are not turned on. Thereafter, when the write word line WWL is returned from 1.125 V to 0 V, the third stage of writing is completed. Since the threshold voltage 0.875V of the read transistor Q2 is higher than the third storage node voltage 0.25V, the read transistor Q2 of the "01" write cell does not turn on.

The storage node voltage of the memory cell not selected by the above-described first to third-stage writing is set to the initial value of 0V.
And this 0 V becomes the fourth storage node voltage. As shown in the first section (write) at the left end of FIG.
The first to fourth storage node voltages 0.75 V, 0.5 V, 0.
25V and 0V are distributed in a voltage range lower than the threshold voltage of 0.875 V of the read transistor Q2,
The data is held in each memory cell without turning on the read transistor Q2.

Next, the read operation will be described. In reading, first, the discharge circuit DCH discharges all the bit lines BL under the control of the control line EQ,
Set to ground potential 0V. Thereafter, the bit line drive circuit BLD sets all the bit lines BL to a floating state. Further, the bit line driving circuit BLD has a bit complementary line /
For example, 0.0625 V is set to BL.

As shown in FIG. 8A, the word line drive circuit WLD applies a first-stage voltage to the read word line RWL.
For example, 0.375 V is applied. When the read word line voltage is applied, the above-mentioned capacitive coupling coefficient is set to 0.
Assuming that the storage node SN is 67, 0.25 (= 0.375 × 0.67) V is added to the first to fourth storage node voltages. That is, the first storage node voltage is 0.75 V
To 1.0 V, the second storage node voltage from 0.5 V to 0.75 V, the third storage node voltage from 0.25 V to 0.5 V, and the fourth storage node voltage from 0 V to 0.
It rises to 25V. As a result, as shown in the second section (first reading stage) of FIG. 9, only the first storage node voltage of the “11” write cell exceeds the threshold voltage of the read transistor Q2 of 0.875 V, and “11” Only the read transistor Q2 of the write cell turns on. When the gate voltage of the read transistor Q2 is higher than the threshold voltage, a voltage obtained by subtracting the threshold voltage from the gate voltage appears at the source. Accordingly, 0.125 (= 1.0−0.87) is applied to the bit line BL of the “11” write cell.
5) V appears. After that, all the sense amplifiers SA are activated. The sense amplifier SA has a reference bit line voltage of 0.
With reference to 0625V, "11" having a higher voltage
Supply voltage V _CC (1.5 only the bit lines of the write cells
V). The amplified voltage is temporarily stored at a predetermined address of the first column register at the bit line end.

In the subsequent second stage, as shown in FIG. 8A, the word line driving circuit WLD reads the read word line RWL.
To the second stage voltage higher than the first stage, for example 0.75
V is applied. As a result, in the storage node SN,
0.5 (= 0.75 × 0.67) for the fourth storage node voltage
V is added. That is, when the first storage node voltage is 0.
From 75V to 1.25V, the second storage node voltage is 0.5
From V to 1.0V, the third storage node voltage increases from 0.25V to 0.75V, and the fourth storage node voltage increases from 0V to 0.5V. As a result, as shown in the third section (read second stage) of FIG. 9, the first storage node voltage of the “11” write cell and the second storage node voltage of the “10” write cell
The storage node voltage exceeds the threshold voltage of read transistor Q2, 0.875V. This turns on each read transistor Q2 of the “10” write cell.
However, "11" because the bit line write cell is amplified already to the supply voltage V _CC, not on not applied enough voltage to the source and the drain of the read transistor Q2. Therefore, the bit line B of the "10" write cell
0.125 (= 1.0−0.875) V appears in L. After that, all the sense amplifiers SA are activated. The sense amplifier SA amplifies only the bit line of the “10” write cell having a higher voltage than the reference bit line voltage 0.0625 V to the power supply voltage V _CC (1.5 V). The amplified voltage is temporarily stored in a predetermined address of the second column register at the bit line end.

In the subsequent third stage, as shown in FIG. 8A, the word line drive circuit WLD reads the read word line RWL.
, A third stage voltage higher than the second stage, e.g.
125 V is applied. Thereby, in the storage node SN,
0.75 (= 1.125 ×
0.67) V is added. That is, the first storage node voltage changes from 0.75 V to 1.5 V, the second storage node voltage changes from 0.5 V to 1.25 V, the third storage node voltage changes from 0.25 V to 1.0 V, and The storage node voltage increases from 0V to 0.75V. As a result, as shown in the fourth section (readout third stage) of FIG. 9, the three storage node voltages other than the fourth storage node voltage of the “00” write cell become the threshold voltage 0.
Exceeds 875V. This turns on each read transistor Q2 of the “01” write cell. However,
Since the bit line of the “11” write cell and the bit line of the “10” write cell have already been amplified to the power supply voltage V _CC , the source and drain of the read transistor Q2 are not sufficiently turned on and do not turn on. Therefore, "0
0.125 (=)
1.0-0.875) V appears. After that, all the sense amplifiers SA are activated. The sense amplifier SA amplifies only the bit line of the “01” write cell having a higher voltage than the reference bit line voltage 0.0625 V to the power supply voltage V _CC (1.5 V). The amplified voltage is temporarily stored in a predetermined address of the third column register at the end of the bit line.

[0046] After the above operation, the output circuits in the input and output circuits, each predetermined address corresponding to the memory cell address of the first to third column register in the word line direction, "1" (the power supply voltage V _CC) Examine the memory location of. For example, at a certain address, when "1" is stored only in the first column register, the storage data is determined to be "11", and when "1" is stored only in the second column register, the storage data is determined. Is determined to be “10”, and when “1” is stored only in the third column register, the storage data is “0”.
It is determined as “1”, and all column registers are “0”.
In the case of storage, it is determined that the storage data is “00”. Such a determination is performed for all addresses, and the determination result is output to a data bus or the like as one page of 2-bit storage information, thereby completing the page read operation.

The refresh operation is an operation for restoring the stored data attenuated by the leak current of the write transistor Q1 in the off state or the like. FIG. 10 shows the voltage application timing of the refresh operation. The refresh operation is basically a read operation and a write operation that are repeated for each stage in this order. In the first stage, when reading is performed on the “11” write cell, only the bit line voltage of the “11” write cell rises to the power supply voltage of 1.5 V as described above. Then, this 1.5V
When 1.625 V is applied to the write word line WWL using this voltage as the set value of the bit line voltage, 0.75 V is newly written in the “11” write cell. Similarly,
In the second stage, the "10" write cell is read and written back, and in the third stage, the "01" write cell is read and written back.

In this refresh operation, a change in the bit line voltage at the time of reading is determined by a sensing reference voltage (for example,
0.0625 V), the stored data can be restored. In the semiconductor memory device according to the second embodiment, a malfunction can be effectively prevented by periodically interrupting the refresh operation before the stored data including the noise margin attenuates and normal data detection becomes impossible. .

Third Embodiment In the third embodiment, the basic write operation is the same as in the first embodiment. In the third embodiment, by dividing the bit line BL and the bit auxiliary line / BL, it is possible to reliably read and write back 2-bit storage data in one reference cell by utilizing the difference in load capacity. Present the method. FIGS. 11 and 12 show a configuration of a main part connected to one bit line pair in the semiconductor memory device according to the present embodiment. Note that FIG. 11 and FIG. 12 do not show separate bit line pairs, but show complementary circuits connected to one bit line pair.

The bit line pair BL, / BL is divided into four regions, that is, a region A, a region B, a region C, and a region D via the transfer gate T1 or T2.
Specifically, bit line pair BL, / BL has a load capacity (for example, proportional to the wiring length) of 2/6 of all bit lines, bit line pair BLa, / BLa in region A, and bit line pair BL, / BL Bit line pair BL in region B having 1/6 load capacitance
b, / BLb, a pair of bit lines BLc and / BLc in a region C having a load capacitance of 2/6 of all bit lines, and a pair of bit lines BL in a region D having a load capacitance of 1/6 of all bit lines.
d and / BLd. Bit lines BLb and B
Transfer gate T1 between Lc and between bit supplementary lines / BLb and / BLc is controlled by signal TG1. Further, between the bit lines BLa and BLb, the bit complementary line / B
Transfer gate T2 between La and / BLb, between bit lines BLc and BLd, and between bit auxiliary lines / BLc and / BLd are controlled by signal TG2.

Bit lines BLa, BLb, BLc in four regions
And BLd, a plurality of memory cells MC are connected as in FIG. In FIG. 11, only one memory cell MC is shown in the region A as a representative. As shown in FIG. 2, the memory cell MC includes a write transistor Q1, a read transistor Q2, and a capacitor C connected between the gate and the drain of the read transistor Q2. As described above, the gate of the write transistor Q1 is driven by the write word line WWL, and the drain of the read transistor Q2 is driven by the read word line RWL.

On the other hand, two reference cells RC are connected to the bit line side and the bit auxiliary line side, respectively, two in the area A and the area B and two in the area C and the area D. In FIG. 11, the area B
A reference cell RC having the same configuration as the memory cell of FIG. 2 is connected to the bit complement line / BLb, and the reference cell in the region D is not shown. The gate of the write transistor Q1 of the reference cell RC is driven by the reference write word line RWWL, and the drain of the read transistor Q2 is driven by the reference read word line RRWL.

On both sides of the divided portions of the area A and the area B, and
Sense amplifiers SA1 or SA2 are connected to a total of four locations on both sides of the divided areas of the area C and the area D. The sense amplifier SA1 has a load capacity of 2/6 of the entire region, that is, between the bit line pair BLa and / BLa in the region A,
Further, it is connected between the bit line pair BLc and / BLc in the region C. Further, the sense amplifier SA2 has a bit line pair B in the region side where the load capacitance is 1/6 of the whole, that is, in the region B.
Lb, / BLb, and bit line pair BL in region D
d, / BLd.

At a division point between the area A and the area B, a connection node between the sense amplifier SA1 and the bit line BLa;
A coupling capacitor Cc is connected between the sense amplifier SA2 and a connection node with the bit supplementary line / BLb. Similarly,
A coupling capacitor Cc is connected between a connection node between the sense amplifier SA1 and the bit line BLb and a connection node between the sense amplifier SA2 and the bit line BLb. Also,
In the division between the region C and the region D, the sense amplifier S
Between a connection node of A1 with the bit line BLc and a connection node of the sense amplifier SA2 with the bit auxiliary line / BLd,
The coupling capacitance Cc is connected. Similarly, a coupling capacitance Cc is connected between a connection node of sense amplifier SA1 with bit complement line / BLc and a connection node of sense amplifier SA2 with bit line BLd.

As shown in FIG. 12, areas A, B,
One column switch is connected between each pair of bit lines C and D. In FIG. 12, a column switch C is provided between a bit line BLa in a region A and a complementary bit line / BLa.
Sa is connected, and a column switch CSc is connected between the bit line BLc and the bit auxiliary line / BLc in the region C. Each column switch CSa, CSc is composed of two transistors T3 and T4. Transistor T
3 is connected between the bit line BLa and the supply line of the I / O voltage DQa, and between the bit line BLc and the supply line of the I / O voltage DQc. The transistor T4 is connected between the bit auxiliary line / BLa and the supply line of the I / O voltage / DQa,
Further, it is connected between the bit auxiliary line / BLc and the supply line of the I / O voltage / DQc. Transistors T3 and T4
Are driven by a column selection signal CSL.

Here, in FIG. 11, each capacitance of the bit line BL and the bit supplementary line / BL is set to 200 fF, and 1/6 of the unit capacitance (33.3 fF) is described as Cb1. Bit lines BLa, BLc and bit supplementary line / BL
a and / BLc have a load capacity in which two unit capacitors Cb1 are connected in parallel, and the bit lines BLb and BLd and the bit supplementary lines / BLb and / BLd have a load capacity corresponding to the unit capacity Cb1.

Writing is performed in the same manner as in the first embodiment.
In a state where a predetermined voltage is applied to the bit line BL by the bit line driving circuit BLD, the write word line WWL is driven to a high level to turn on the write transistor Q1,
The bit line setting voltage is transmitted to storage node SN. By turning the write word line WWL back to the low level and turning off the write transistor Q1, any one of four values is stored in the storage node SN as shown in FIG.

In a similar manner, a predetermined voltage of 0.375 V is written to reference cell RC. This write voltage may be set by the bit line drive circuit BLD. Here, a method of setting the bit line voltage using the difference in the load capacitance of the bit line will be described below. FIG. 13 shows this reference cell RC.
5 is a timing chart at the time of writing.

First, the signal TG2 is at a high level (1.5
V), the signal TG1 is at a low level (0 V). Therefore, the transfer gate T2 between the region A and the region B is turned on, and the bit lines BLa and BLb and the bit auxiliary lines / BLa and /
BLb is connected. Further, the transfer gate T2 between the region C and the region D is turned on, and the bit lines BLc and BLc are turned on.
d, bit auxiliary lines / BLc and / BLd are connected.
The transfer gate T1 between the region B and the region C is off.

Next, the column selection signal CSL output from a column decoder (not shown) rises from 0 V to 1.5 V as shown in FIG. This allows
The column switch CSa provided in the region A is turned on, and as shown in FIG.
For example, 0.75 V corresponding to _CC / 2 is the bit auxiliary line / BL
a, / BLb. On the other hand, the column selection signal CS
The column switch CSc in the area C receiving L also turns on, and as shown in FIG.
V is transmitted to bit auxiliary lines / BLc and / BLd. After that, as shown in FIG. 13A, the signal TG1 rises from a low level to a high level. As a result, the transfer gate T1 between the region B and the region C is turned on, and all the bit auxiliary lines divided in the middle are connected. Areas A and B
0.75V on the side and 0V on the areas C and D are averaged,
As shown in FIGS. 13D and 13E, the bit supplementary line voltage is 0.375 V (V _CC / 4).

As shown in FIG. 13C, when the reference write word line RWWL is driven by, for example, 2 V, the write transistor Q1 of the reference cell RC is turned on, and the bit auxiliary line voltage 0.375 V is written to the storage node RSN. It is.

In reading of the reference cell RC,
The reference read word line RRWL is connected to the power supply voltage V _CC (1.5
V). Assuming that the above-described capacitance coupling ratio is 0.67, the storage node RSN of the reference cell RC is 1 (= 1.5 ×
0.67) V rises to 1.375V. Further, the read transistor Q2 is turned on. If the threshold voltage is 0.9V, 0.475V obtained by subtracting 0.9V from 1.375V appears on the bit auxiliary line / BL.

Next, the bit auxiliary line voltage of 0.475 V
Reading and writing back of the memory cell MC based on only the reference will be described. FIG. 14 shows the storage data “10”.
6 is a timing chart at the time of reading and writing back (at a storage node voltage of 0.5 V).

First, the transfer gate control signal T
G1 and TG2 are set to 1.5V to connect all bit lines BL and all bit auxiliary lines / BL, and the potential is set to 0V to be in a floating state. Further, as shown in FIG. 14A, the signal TG1 is returned from 1.5 V to 0 V, the transfer gate T1 is turned off, and the bit line and the bit auxiliary line are divided in the middle. In this state, in order to read the memory cells MC in the area A and the reference cells RC in the area B, FIG.
As shown in (C), the read word line RWL and the reference read word line RRWL are raised from 0V to 1.5V. As shown in FIG. 6C and described above, 0.6 V appears on the bit lines BLa and BLb (FIG. 14D,
(F)), the above-described reference voltage 0.475 V appears on the bit supplementary lines / BLa and / BLb (FIG. 14E,
(G)).

At this stage, as shown in FIG. 14B, the signal TG2 is returned from 1.5 V to 0 V, the transfer gate T2 is turned off, and the bit lines BLa and BL between the region A and the region B are turned off.
Lb and the bit supplementary lines / BLa and / BLb are divided. Further, the read word line RWL and the reference read word line RRWL also fall. Then, the sense amplifier SA1 in the region A is activated. As a result, FIG.
As shown in FIG. 14D, the voltage of the bit line BLa rises from 0.6 V to the power supply voltage V _CC (1.5 V), and as shown in FIG. Drops to 0V. At this time, the voltage 1.
5V becomes the MSB (most significant bit) of the read data, and is read by a path (not shown). In this case, since the bit line BLa is at a high level of 1.5 V, the MSB of the read data is determined to be “1”.

On the other hand, the region A by the sense amplifier SA1
Of the bit line pair BLa, / BLa is transmitted to the bit line pair BLb, / BLb in the region B via the coupling capacitance Cc. Specifically, the voltage change amount ΔV (/ BLb) of the bit auxiliary line / BLb is the voltage change amount ΔV of the bit line BLa.
(BLa) multiplied by the capacitance ratio of the capacitor, and is expressed by the following equation (1).

ΔV (/ BLb) = ΔV (BLa) × Cc / (Cb1 + Cc) (1) = (1.5V−0.6V) × 8.3fF / (33.3fF + 8.3fF) = 0.18V The coupling capacitance Cc was assumed to be 8.3 fF.

The bit auxiliary line / BLb is originally 0.475 V
Therefore, this 0.18 V is added, and FIG.
The voltage eventually becomes 0.655 V as shown in (G). Similarly, the voltage fluctuation of the bit line BLb is 0.095V. However, since the voltage of the bit auxiliary line / BLa has dropped due to sensing, the bit line BLb has dropped from the original voltage of 0.6 V by the amount of the voltage fluctuation, and FIG.
As shown in (F), the voltage eventually becomes 0.505V. in this way,
The amplification of the sense amplifier SA1 in the area A reverses the magnitude relationship between the potentials of the bit line pairs in the area B.

For this reason, when the sense amplifier SA2 is activated next, as shown in FIG.
Of the bit auxiliary line / BLb rises to 1.5V as shown in FIG. 14 (G). At this time, the voltage of 0 V of the bit line BLb is set to L of the read data.
It becomes SB (least significant bit) and is read by a path (not shown). In this case, since the bit line BLb is at a low level of 0 V, the LSB of the read data is determined to be “0”. As described above, the MSB is “1” and the LSB is “0”, and the stored data “10” is read.

Subsequently, the stored data is rewritten by redistribution of the bit line charges. First, as shown in FIG. 14B, the signal TG2 is raised from 0 V to 1.5 V, whereby the bit line BLa in the area A and the bit line BL in the area B are raised.
b is connected. At this time, since the bit line BLa is at 1.5 V and the bit line BLb is at 0 V, the bit line BLa
Charge flows into Lb. Since the load capacitance ratio between the bit lines BLa and BLb is 2: 1, the bit line voltage after equalization is 2/3 of 1.5 V, and FIG.
As shown in (F), the bit lines BLa and BLb both change to 1.0V.

Next, as shown in FIG. 14A, the signal TG1 is raised from 0V to 1.5V, whereby the bit lines BLa and BLb in the areas A and B are set to 0V in the areas C and D.
Bit lines BLc and BLd in the floating state
Connect with At this time, the 1.0 V bit lines BLa, BL
Charges flow into the bit lines BLc and BLd from the b side.
Since the load capacity ratio between the two is 1 to 1, FIG.
As shown in (D), (F) and (H), the bit line voltage after equalization is 0.5 V, which is half of 1.0 V.

The bit line voltage of 0.5 V corresponds to FIG.
“10” in (C) is a voltage value when writing. Therefore, next, the write word line WWL is changed from 0V to 2V.
, 0.5 V corresponding to the storage data “10” is written to the storage node SN.

The above is the reading and writing back of the storage data "10", but the other "11", "01" and "0"
The same operation is performed in the case of 0 ". The voltage change of the bit line pair BLb, / BLb before and after the activation of the sense amplifier SA1 in the operation including other storage data is shown in FIG.
5 collectively.

In the case of "11" in FIG. 15A, the read bit line BL before the sense amplifier SA1 is turned on is read.
The voltages of a and BLb are 0.85 V from FIG. When the sense amplifier SA1 is turned on, the bit line BLa
Rises from 0.85V by 1.5V and 0.65V.
This bit line voltage 1.5V is the MSB of the stored data.
Read as "1". On the other hand, this bit line BLa
Is the same as the capacitance ratio (about 0.2) of the above equation (1).
At the bit auxiliary line / BLb, and the bit auxiliary line / BLb
Rises from the original 0.475V by 0.13V and eventually reaches 0.605V. In addition, the voltage of the bit supplementary line / BLa drops from the original 0.475V to 0V by 0.475V. This voltage drop is transmitted to the bit line BLb at the same capacitance ratio (approximately 0.2) as in the above equation (1),
b drops by 0.095V from the original 0.85V,
In the end, it becomes 0.755V. After that, the sense amplifier SA2
Is activated, the bit line B is added to the bit line BLa.
Lb also becomes 1.5V. The voltage 1.
5V is read as LSB "1" of the stored data.

As described above, in the case of "11", the bit line B
La and BLb maintain a high level with respect to bit complementary lines / BLa and / BLb before and after activation of sense amplifier SA1. That is, after the activation of the sense amplifier SA1 and also after the activation of the sense amplifier SA2, the inversion of the voltage relationship does not occur in the bit line pair.

In the write-back operation of "11", the voltage remains at 1.5 V even if the transfer gate T2 is turned on and the bit lines BLa and BLb are connected. The bit line voltage of .5V is reduced by half to 0.75V. Since this voltage is the bit line setting voltage at the time of writing “11” in FIG. 5C, writing back of “11” can be subsequently performed.

In the case of "01" in FIG. 15C, the read bit line BL before the sense amplifier SA1 is turned on is read.
The voltages of a and BLb are 0.35 V from FIG. When the sense amplifier SA1 is turned on, the bit line BLa
Drop from 0.35V by 0V and 0.35V. The bit line voltage 0V is read as the MSB “0” of the stored data. On the other hand, the voltage drop of the bit line BLa is reduced by the bit auxiliary line / BL at the same capacitance ratio (about 0.2) as in the above equation (1).
b, the bit complement / BLb is the original 0.475
It drops by 0.07V from V, and eventually becomes 0.405V. Also, the voltage of the bit supplementary line / BLa is 0.47
It rises from 5V to 1.5V by 1.025V. This voltage rise is transmitted to the bit line BLb at the same capacitance ratio (approximately 0.2) as in the equation (1), and the bit line BLb rises by 0.205 V from the original 0.35 V, and eventually becomes 0.55 V.
It becomes 5V. Thereafter, when the sense amplifier SA2 is activated, the bit line BLb becomes 1.5V. This bit line B
The voltage 1.5 V of Lb is read as LSB "1" of the stored data.

As described above, in the case of "01", before the activation of the sense amplifier SA1, the bit lines BLa and BLb are at the low level with respect to the bit complementary lines / BLa and / BLb.
After the activation of sense amplifier SA1, bit line BLb attains a high level with respect to bit auxiliary line / BLb. That is, before and after the activation of the sense amplifier SA1, the voltage relationship of the bit line pair is reversed.

In the write-back of "01", the bit line BLa is at 0 V and the bit line BLb is at 1.5 V before the transfer gate T2 is turned on to connect the bit lines BLa and BLb. The load capacitance ratio between the bit lines BLa and BLb is 2: 1. Therefore, when the transfer gate T2 is turned on, the charge is supplied to the BLb side where the load capacitance ratio is half, so that the bit lines BLa and BL
The voltage of b rises only to 0.5V which is 1/3 of 1.5V. Next, when the transfer gate T1 is connected, the bit line voltage of 0.5V is halved to 0.25V. This voltage is the bit line setting voltage at the time of writing “01” in FIG.
Can be written back.

In the case of "00" in FIG. 15D, the read bit line BL before turning on the sense amplifier SA1 is read.
The voltages of a and BLb are 0.1 V from FIG.
When the sense amplifier SA1 is turned on, the bit line BLa drops from 0.1V to 0V by 0.1V. The bit line voltage 0V is read as the MSB “0” of the stored data. On the other hand, the voltage drop of the bit line BLa is reduced by the bit auxiliary line / BL at the same capacitance ratio (about 0.2) as in the above equation (1).
b, the bit complement / BLb is the original 0.475
The voltage drops by 0.02 V from V, and eventually becomes 0.455 V. Also, the voltage of the bit supplementary line / BLa is 0.47
It rises from 5V to 1.5V by 1.025V. This voltage rise is transmitted to the bit line BLb at the same capacitance ratio (approximately 0.2) as in the above equation (1).
It rises by 0.205V from 1V, and eventually reaches 0.305V. Thereafter, when the sense amplifier SA2 is activated, the bit line BLb becomes 0V. The voltage 0 V of the bit line BLb is read as the LSB “0” of the stored data.

As described above, in the case of "00", the bit line B
La and BLb maintain a low level with respect to bit complementary lines / BLa and / BLb before and after activation of sense amplifier SA1. That is, after the activation of the sense amplifier SA1 and also after the activation of the sense amplifier SA2, the inversion of the voltage relationship does not occur in the bit line pair.

In the writing back of "00", even if the transfer gate T2 is turned on and then the transfer gate T1 is turned on, the voltages of the bit lines BLa and BLb remain at 0V. This voltage is the bit line setting voltage at the time of writing “00” in FIG.
0 "can be written back.

As described above, in the third embodiment, the bit supplementary lines / BLa, / BLb are read by reading the reference cell RC.
Using one reference voltage of 0.475 V set as described above, it is possible to sequentially read and write back four-valued storage data. At this time, as shown in FIG. 15, the voltage difference between the pair of bit lines did not fall below 0.125 V, and sufficient amplification was possible with a normal sense amplifier.

The above is a description of the case where the memory cell MC shown in FIG.
Writing, reading and writing back of bit storage data have been described, but the same operation can be performed in the case of 3 bits or more. The same operation can be performed for the memory cell of FIG. Further, as shown in FIGS. 16 and 17, a bit line BL is connected to a write bit line WBL to which a write transistor Q1 is connected and a read bit line RBL to which a read transistor Q2 is connected.
The bit line drive circuit BLD can separately write, read, and write back stored data of 2 bits or more for the memory cell configured from the BL.

[0084]

According to the semiconductor memory device of the present invention,
It has a write transistor and a read transistor,
It has become possible to write and read two or more bits of storage data into a memory cell that can be read to a bit line without causing a decrease in the amplitude of the storage data due to the supply of charge through the read transistor. For this reason, the bit cost could be significantly reduced without increasing the memory cell area.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main part of a memory cell array of a semiconductor memory device according to an embodiment of the present invention and peripheral circuits thereof.

FIG. 2 is a circuit diagram of a memory cell according to an embodiment of the present invention.

FIG. 3 is a circuit diagram of another memory cell according to the embodiment of the present invention.

FIG. 4 is an equivalent circuit diagram in the case where a capacitor includes an external capacitance element in the memory cell of FIG. 2;

FIG. 5 is a timing chart showing a write operation of the semiconductor memory device according to the first embodiment.

FIG. 6 is a timing chart illustrating a read operation of the semiconductor memory device according to the first embodiment.

FIG. 7 is a timing chart illustrating a write operation of the semiconductor memory device according to the second embodiment.

FIG. 8 is a timing chart illustrating a read operation of the semiconductor memory device according to the second embodiment.

FIG. 9 is a graph showing a transition of a storage node voltage at the time of writing and at each reading stage of the semiconductor memory device according to the second embodiment.

FIG. 10 is a timing chart showing a refresh operation of the semiconductor memory device according to the second embodiment.

FIG. 11 is a circuit diagram showing a configuration of a main part connected to one bit line pair in a semiconductor memory device according to a third embodiment.

FIG. 12 is a circuit diagram complementary to FIG. 11, showing another configuration of a main part connected to one bit line pair in the semiconductor memory device according to the third embodiment.

FIG. 13 is a timing chart showing a write operation of a reference cell of the semiconductor memory device according to the third embodiment.

FIG. 14 is a timing chart showing read and write-back operations of “10” storage data for a memory cell of the semiconductor memory device according to the third embodiment.

FIG. 15 is a diagram showing a voltage change of a bit line pair before and after activation of a first sense amplifier in reading and writing back of quaternary storage data from and to memory cells of a semiconductor memory device according to a third embodiment. .

FIG. 16 is a circuit diagram showing a configuration example of a memory cell to which the present invention can be applied.

FIG. 17 is a circuit diagram showing another configuration example of a memory cell to which the present invention can be applied;

[Explanation of symbols]

Q1: write transistor, Q2: read transistor, C, CAP: capacitor, Cp: parasitic capacitance, Cex
1 ... external capacitance element, Cc ... coupling capacitance, Cb1 ... unit load capacitance, MC ... memory cell, RC ... reference cell, SA, SA
1, SA2: sense amplifier, DCH: discharge circuit, T1, T2: transfer gate, CSa, CSc
... column switch, T3, T4 ... transistor in column switch, WWL ... write word line, RWL ... read word line, RWWL ... reference write word line, RRW
L: Reference read word line, BL, BLa, BLb, B
Lc, BLd: bit line, / BL, / BLa, / BL
b, / BLc, / BLd ... bit supplementary lines, SPL, SNL
... Sense amplifier drive voltage supply line, EQ ... Control line, SN ...
Storage node, RSN: Reference storage node, TG1, TG2
... Transfer gate control signal, CSL ... Column selection signal, DQa, DQc, / DQa, /DQc...I/O voltage.

Claims (18)

[Claims] A first transistor having a gate serving as a source or a drain of the first transistor;
A plurality of memory cells each having a read transistor connected to the impurity region and having the gate serving as a storage node; a write word line in which the gate of the write transistor is connected in a word line direction; sources of the write transistor and the read transistor Alternatively, there is provided an operation method of a semiconductor memory device having a bit line in which a second impurity region serving as a drain is connected in a bit line direction and a read word line capacitively coupled to the storage node, wherein the voltage of the write word line is An operation method of a semiconductor memory device which controls a voltage of a bit line and writes and holds a voltage of four or more values in a plurality of storage nodes in the plurality of memory cells. 2. The method according to claim 1, wherein at the time of writing, one of the four or more voltages is set to the bit line, a constant write word line voltage is applied to the write word line, and the write transistor is turned on. 2. The method of operating a semiconductor memory device according to claim 1, wherein a set voltage of said bit line is transmitted to said storage node through said write transistor. 3. The maximum value of the voltage set on the bit line is:
3. The operating method of a semiconductor memory device according to claim 2, wherein both a voltage value obtained by subtracting a threshold voltage of said write transistor from said write word line voltage and a threshold voltage of said read transistor are smaller. 4. When writing, a constant voltage is set to the bit line, a write word line voltage corresponding to a voltage to be written to the storage node is applied to the write word line, and the write transistor is turned on. 2. The method according to claim 1, wherein a voltage obtained by subtracting a threshold voltage of the write transistor from a write word line voltage is set in the storage node. 5. A method according to claim 4, wherein a maximum value of a voltage written to said storage node is smaller than both a constant voltage set to said bit line and a threshold voltage of said read transistor. 6. A method according to claim 1, wherein a voltage of said bit line is applied to a bit line to which a memory cell to be operated is connected by applying a constant write bit line voltage and applying a ground voltage to other bit lines. 5. The semiconductor according to claim 4, wherein writing is performed a plurality of times while switching the write word line voltage so that the voltage value gradually decreases, and a voltage of four or more values is written to a plurality of memory cells connected to the same word line. An operation method of a storage device. 7. At the time of reading, the bit line is floated at a ground voltage, a read word line voltage is applied to the read word line to boost the storage node voltage, and the read transistor is turned on or off.
2. The method according to claim 1, wherein a voltage corresponding to the boosted voltage of the storage node is caused to appear on the bit line and read out. 8. A read word line voltage corresponding to all four or more voltages held in the storage node.
8. The method according to claim 7, wherein the voltage is a constant voltage capable of appearing on the bit line. 9. The read word line voltage, wherein the read transistor maintains an off state when the voltage of the storage node is boosted from the minimum value of the four or more voltages,
9. The operation method of a semiconductor memory device according to claim 8, wherein the constant voltage is within a range that is turned on when the voltage is increased from another voltage value. 10. A read word line voltage which is gradually increased stepwise and applied a plurality of times, and each time the voltage is applied, a voltage corresponding to the storage node voltage appears one by one on the bit line and is read. Item 8. An operation method of the semiconductor memory device according to Item 7. 11. The read word line is coupled to the storage node via a capacitor provided for each memory cell, and the first impurity region of the read transistor is connected to a power supply voltage line. The operation method of the semiconductor memory device described in the above. 12. The read transistor according to claim 1, wherein the first impurity region of the read transistor is connected to the read word line, and the read word line is connected to the storage node via a parasitic capacitance in the read transistor.
The operation method of the semiconductor memory device described in the above. 13. The read transistor according to claim 1, wherein a first impurity region of the read transistor is connected to the read word line, and the read word line is coupled to the storage node via a parasitic capacitance and a capacitance element in the read transistor. The operation method of the semiconductor memory device described in the above. 14. The bit line comprises a write bit line connecting the second impurity region of the write transistor in the bit line direction and a read bit line connecting the second impurity region of the read transistor in the bit line direction. 2. The method of operating a semiconductor memory device according to claim 1, wherein the method comprises: 15. A memory cell comprising: a write transistor; a plurality of memory cells each including a read transistor having a gate connected to a first impurity region serving as a source or a drain of the write transistor and having a gate serving as a storage node; A write word line having a gate connected in a word line direction, a bit line having a second impurity region serving as a source or a drain of the write transistor and the read transistor connected in a bit line direction, and a read word capacitively coupled to the storage node A control circuit that controls a voltage of the bit line and a voltage of the write word line, and writes a voltage of four or more values to a plurality of storage nodes in the plurality of memory cells. A semiconductor memory device further provided. 16. The read word line is coupled to the storage node via a capacitor provided for each of the memory cells, and a first impurity region of the read transistor is connected to a power supply voltage line. 13. The semiconductor memory device according to claim 1. 17. The read transistor according to claim 1, wherein a first impurity region of the read transistor is connected to the read word line, and the read word line is coupled to the storage node via a parasitic capacitance in the read transistor.
6. The semiconductor memory device according to 5. 18. The read transistor according to claim 15, wherein a first impurity region of the read transistor is connected to the read word line, and the read word line is coupled to the storage node via a parasitic capacitance and a capacitance element in the read transistor. 13. The semiconductor memory device according to claim 1.