CN103026416A

CN103026416A - Semiconductor device

Info

Publication number: CN103026416A
Application number: CN2011800388581A
Authority: CN
Inventors: 长塚修平; 松崎隆德; 井上广树; 加藤清
Original assignee: Semiconductor Energy Laboratory Co Ltd
Current assignee: Semiconductor Energy Laboratory Co Ltd
Priority date: 2010-08-06
Filing date: 2011-07-19
Publication date: 2013-04-03
Anticipated expiration: 2031-07-19
Also published as: US8837232B2; TW201209830A; CN103026416B; KR20180130595A; KR101925159B1; TWI549131B; US8488394B2; JP2015172993A; US20130301367A1; KR102006586B1; WO2012017844A1; JP6133928B2; KR20130098312A; US20120033510A1; JP2017139050A; JP5748602B2; JP2012256401A

Abstract

An object is to provide a semiconductor device with a novel structure, which can hold stored data even when power is not supplied and which has an unlimited number of write cycles. The semiconductor device is formed using a memory cell including a wide band gap semiconductor such as an oxide semiconductor. The semiconductor device includes a potential change circuit having a function of outputting a potential lower than a reference potential for reading data from the memory cell. When the wide band gap semiconductor which allows a sufficient reduction in off-state current of a transistor included in the memory cell is used, a semiconductor device which can hold data for a long period can be provided.

Description

Semiconductor device

Technical field

The present invention relates to a kind of semiconductor device of semiconductor element and driving method of semiconductor device of utilizing.

Background technology

Utilize the memory storage of semiconductor element broadly to be divided into two classes: even when electric power supply stops, losing the volatile storage of having stored data and the Nonvolatile memory devices that when not providing electric power, also keeps having stored data.

A typical case of volatile storage is dynamic RAM (DRAM).DRAM stores data, and its mode is the transistor of selecting to be included in the memory element, and with charge storage in capacitor.

From the DRAM reading out data time, according to above-mentioned principle, the electric charge in the capacitor is lost, thereby needs another write operation during each reading out data.Data are shorter during keeping, even this is because when not selecting transistor, because the leakage current (off state current (off-state current)) between the source electrode under the cut-off state and the drain electrode etc. and electric charge are from/the cause that flows through to the transistor of formation memory element.For this reason, need another write operation (refresh operation) at predetermined space, and be difficult to fully reduce power consumption.In addition, lose when electric power supply stops owing to storing data, thus the another kind of memory storage of magnetic material or optical material need to be utilized, in order to keep for a long time data.

Another example of volatile storage is static RAM (SRAM).SRAM is by using the circuit such as trigger (flip-flop) to keep storing data, and thereby need not refresh operation, this is better than DRAM.But because the circuit of use such as trigger, the cost of every memory capacity is high.In addition, as among the DRAM, the storage data among the SRAM are lost when electric power supply stops.

A typical case of Nonvolatile memory devices is flash memory.Flash memory comprises gate electrode in the transistor and the floating boom between the channel formation region, and stores data in the floating boom by electric charge is remained on.Therefore, the advantage of flash memory is, extremely grows (semipermanent) during the data maintenance, and does not need the required refresh operation of volatile storage (for example referring to patent documentation 1).

But the gate insulator that is included in the memory element is deteriorated because of the tunnel current that generates in the write operation, so memory element becomes after the write operation of predetermined quantity and can't work.In order to reduce the impact of this problem, for example, adopt a kind of method, wherein make the quantity homogenising of the write operation of memory element, but need complicated peripheral circuit to realize this method.Even when adopting this method, also can't solve the basic problem in serviceable life.In other words, flash memory is not suitable for the application of frequent rewrite data.

In addition, need high voltage, so as in floating boom iunjected charge or remove electric charge, and need to be used for generating high-tension circuit.In addition, need the long period to inject or remove electric charge, and be not easy to write at a relatively high speed or wipe.

[list of references]

[patent documentation 1] Japanese Patent Application Publication No.S57-105889.

Summary of the invention

In view of the above problems, the purpose of a mode of the present invention provides a kind of semiconductor device with novel structure, even this semiconductor device also can keep having stored data when not providing electric power, and has the write cycle of unlimited amount.

In a mode of the present invention, semiconductor device with the material that can fully reduce transistorized off state current for example the semi-conductive oxide semiconductor material of wide energy gap form.When use can fully reduce the semiconductor material of transistorized off state current, semiconductor device can keep data between longer-term.

For example, a mode of the present invention is a kind of semiconductor device, and this semiconductor device comprises the storage unit of using wide energy gap semiconductor to form.This semiconductor device comprises having in order to export the electric potential transfer circuit of the function of the current potential lower than reference potential from the storage unit reading information.

More specifically, for example can adopt following structure.

A mode of the present invention is a kind of semiconductor device, comprising: the memory cell array that comprises m * n storage unit; The first driving circuit; The second driving circuit; Potential generation circuit; Bit line; Source electrode line; And gate line.One of storage unit comprises: the first transistor that comprises first grid electrode, the first source electrode, the first drain electrode and the first channel formation region; And the transistor seconds that comprises second gate electrode, the second source electrode, the second drain electrode and the second channel formation region.The first channel formation region comprises the semiconductor material different from the second channel formation region.The first driving circuit storage unit each row in comprise the K position latch section, have the write circuit of the multiplexer of K position.Write circuit is connected to the latch section of potential generation circuit, K position.

In addition, a mode of the present invention is a kind of semiconductor device, comprising: the memory cell array that comprises m * n storage unit; The first driving circuit; The second driving circuit; The counter of K position (K is natural number); Potential generation circuit; Bit line; Source electrode line; And gate line.One of storage unit comprises: the first transistor that comprises first grid electrode, the first source electrode, the first drain electrode and the first channel formation region; And the transistor seconds that comprises second gate electrode, the second source electrode, the second drain electrode and the second channel formation region.The first channel formation region comprises the semiconductor material different from the second channel formation region.The first driving circuit comprises latch section, the reading circuit of K position in each row of storage unit.The counter of K position is connected to reading circuit, and reading circuit is connected to the latch section of K position.

In addition, a mode of the present invention is a kind of semiconductor device, comprising: the memory cell array that comprises m * n storage unit; The first driving circuit; The second driving circuit; The counter of K position (K is natural number); Potential generation circuit; Bit line; Source electrode line; And gate line.One of storage unit comprises: the first transistor that comprises first grid electrode, the first source electrode, the first drain electrode and the first channel formation region; And the transistor seconds that comprises second gate electrode, the second source electrode, the second drain electrode and the second channel formation region.The first channel formation region comprises the semiconductor material different from the second channel formation region.The first driving circuit in each row of storage unit, comprise the K position latch section, have write circuit and the reading circuit of the multiplexer of K position.The counter of K position is connected to reading circuit, and the latch section of K position is connected to write circuit, reading circuit.

In above-mentioned half, source electrode line can be connected to the first source electrode, and bit line can be connected to the first drain electrode and the second drain electrode, and gate line can be connected to the second gate electrode, and first grid electrode can be connected to the second source electrode.

In addition, above-mentioned in, the first transistor can be the p channel transistor, transistor seconds can be the n channel transistor.Perhaps, above-mentioned in, the first transistor can be the n channel transistor, transistor seconds can be the n channel transistor.

In above-mentioned, the second channel formation region of transistor seconds can use oxide semiconductor to form.

In above-mentioned, can be connected in parallel between bit line and source electrode line comprises a plurality of storage unit of one of storage unit.Perhaps, can between bit line and source electrode line, be connected in series a plurality of storage unit that comprise one of storage unit.

In above-mentioned, reading circuit can comprise load, sensor amplifier and NAND circuit, sensor amplifier can be connected to an input of NAND circuit, and the storer read line can be connected to another input of NAND circuit, and the latch section of K position can be connected to the output of NAND circuit.

In above-mentioned, potential generation circuit can be connected to each of the first driving circuit and the second driving circuit.

In above-mentioned, the counter of K position can be electrically connected to the input of the latch section of K position.

Note, although above-mentioned transistor comprises oxide semiconductor sometimes, the present invention is not limited thereto.Can use can realize can be with the off state current characteristic of oxide semiconductor the material of suitable off state current characteristic, for example wide gap material such as silit (its energy gap Eg is greater than the semiconductor material of 3 eV specifically).

Note, in this instructions etc. such as " on " or D score term not necessarily represent an assembly " directly " be placed on another assembly " on " or D score.For example, " gate electrode on the gate insulator " can be illustrated in the situation that another kind of assembly is arranged between gate insulator and the gate electrode.Such as " on " and D score term only be used for the convenience that illustrates.

In addition, the function of limiter assembly not of the term such as " electrode " or " wiring " in this instructions etc.For example, " electrode " sometimes can be as the part of " wiring ", and vice versa.Moreover term " electrode " or " wiring " can comprise the situation that a plurality of " electrodes " or " wiring " form according to integration mode.

When using the transistor of opposite polarity or when direction of current flow changes in circuit operation, the function of " source electrode " and " drain electrode " is mutually transposing sometimes.Therefore, term " source electrode " and " drain electrode " can be changed mutually in this instructions etc.

Note, the term " electrical connection " in this instructions etc. comprises that assembly passes through the situation that " having the object of any Electricity Functional " connects.Electric signal has no particular limits for " object with any Electricity Functional ", as long as can transmit between the assembly that connects by this object and receive.

The example of " object with any Electricity Functional " is electrode and wiring, is again the on-off element such as transistor, resistor, inductor, capacitor and element with various functions.

Because it is minimum to comprise the transistorized off state current of oxide semiconductor, so can keep extremely long-time by using this transistor will store data.In other words, can fully reduce power consumption, because no longer need refresh operation, perhaps the frequency of refresh operation can be reduced to extremely low.Even when electric power (note, current potential is preferably fixed) is not provided, also can keep for a long time storing data.

In addition, do not need the high voltage that writes for data according to semiconductor device of the present invention, and do not have the deteriorated problem of element.For example, different from conventional nonvolatile memory, do not need to inject and extract electronics from floating boom to floating boom, and thereby can not occur fully such as the problem gate insulator deteriorated.That is to say, for the not restriction of number of times as the rewriting of the problem of conventional nonvolatile memory, and greatly improve its reliability according to semiconductor device of the present invention.Moreover, because by transistorized conducting state or cut-off state data writing, so can be easy to realize high speed operation.In addition, do not need operation for obliterated data.

Because comprising the transistor of the material beyond the oxide semiconductor can operate with abundant high speed, so when it combined with the transistor that comprises oxide semiconductor, semiconductor device can operate (for example data read) with abundant high speed.In addition, the transistor that comprises the material beyond the oxide semiconductor can successfully be realized the various circuit (for example logical circuit or driving circuit) that need at full speed operate.

Therefore, can by provide comprise the material beyond the oxide semiconductor transistor (in other words, the transistor that can operate with abundant high speed) and the transistor (in other words, its off state current fully little transistor) that comprises oxide semiconductor realize having the semiconductor device of novel feature.

Description of drawings

Figure 1A 1, Figure 1A 2, Figure 1B and Fig. 1 C are the circuit diagrams of semiconductor device;

Fig. 2 is the block diagram of semiconductor device;

Fig. 3 A is the block diagram of semiconductor device, and Fig. 3 B and Fig. 3 C are the circuit diagrams of semiconductor device;

Fig. 4 is the circuit diagram of semiconductor device;

Fig. 5 is the circuit diagram of semiconductor device;

Fig. 6 is the block diagram of semiconductor device;

Fig. 7 is the circuit diagram of semiconductor device;

Fig. 8 is the circuit diagram of semiconductor device;

Fig. 9 A, Fig. 9 B1, Fig. 9 B2, Fig. 9 B3, Fig. 9 B4 and Fig. 9 B5 are the circuit diagrams of semiconductor device;

Figure 10 is the circuit diagram of semiconductor device;

Figure 11 is sequential chart;

Figure 12 is sequential chart;

Figure 13 is sequential chart;

Figure 14 is the circuit diagram of semiconductor device;

Figure 15 is sequential chart;

Figure 16 is sequential chart;

Figure 17 A is the sectional view of semiconductor device, and Figure 17 B is the planimetric map of semiconductor device;

Figure 18 A to Figure 18 G is the sectional view of the manufacturing process of SOI substrate;

Figure 19 A to Figure 19 E is the sectional view of the manufacturing process of semiconductor device;

Figure 20 A to Figure 20 D is the sectional view of the manufacturing process of semiconductor device;

Figure 21 A to Figure 21 D is the sectional view of the manufacturing process of semiconductor device;

Figure 22 A to Figure 22 C is the sectional view of the manufacturing process of semiconductor device;

Figure 23 A to Figure 23 F is the figure of electronic equipment;

Figure 24 is the block diagram of semiconductor device;

Figure 25 is the block diagram of semiconductor device;

Figure 26 A and Figure 26 B are the sectional views of semiconductor device;

Figure 27 A to Figure 27 C is the sectional view of the manufacturing process of semiconductor device;

Figure 28 A to Figure 28 C is the sectional view of semiconductor device;

Figure 29 A to Figure 29 E is respectively the figure of the structure of explanation oxide material;

Figure 30 A to Figure 30 C is the figure of the structure of explanation oxide material;

Figure 31 A to Figure 31 C is the figure of the structure of explanation oxide material;

Figure 32 is the dependent figure of gate voltage that illustrates by the mobility that calculates;

Figure 33 A to Figure 33 C illustrates by the leakage current that calculates and the dependent figure of gate voltage of mobility;

Figure 34 A to Figure 34 C illustrates by the leakage current that calculates and the dependent figure of gate voltage of mobility;

Figure 35 A to Figure 35 C illustrates by the leakage current that calculates and the dependent figure of gate voltage of mobility;

Figure 36 A and Figure 36 B are respectively the figure that explanation is used for the transistorized cross section structure of calculating;

Figure 37 A to Figure 37 C is respectively the figure that transistorized characteristic is shown;

Figure 38 A and Figure 38 B are respectively the figure that transistorized characteristic is shown;

Figure 39 A and Figure 39 B are respectively the figure that transistorized characteristic is shown;

Figure 40 is the figure that transistorized characteristic is shown;

Figure 41 A and Figure 41 B are the figure that transistorized characteristic is shown;

Figure 42 is the figure that the XRD spectrum of oxide material is shown;

Figure 43 is the figure that transistorized characteristic is shown;

Figure 44 A is the planimetric map of semiconductor device, and Figure 44 B is the sectional view of semiconductor device;

Figure 45 A is the planimetric map of semiconductor device, and Figure 45 B is the sectional view of semiconductor device.

Embodiment

Embodiments of the present invention are described below with reference to accompanying drawings.Note, the present invention is not limited to following description, and those skilled in the art's easy to understand, and pattern of the present invention and details can be revised by variety of way, and do not deviate from its spirit and scope.Therefore, the present invention is not appreciated that the description that is confined in the following embodiment.

Note, the position of each assembly shown in the accompanying drawing etc., size, scope etc. do not have Precise Representation in some cases for easy to understand.Therefore, the present invention not necessarily is confined to disclosed position, size, scope etc. in accompanying drawing etc.

In this instructions etc., use ordinal number such as " first ", " second " and " the 3rd " in order to avoid obscuring between the assembly, and these terms number of limiter assembly not necessarily.

Embodiment 1

In the present embodiment, with reference to Figure 1A 1, Figure 1A 2, Figure 1B and Fig. 1 C basic circuit structure and operation according to the semiconductor device of a mode of the present invention are described.Note, in each of circuit diagram, sometimes on the transistor next door with " OS ", comprise oxide semiconductor in order to represent this transistor.

＜basic circuit 〉

At first with reference to Figure 1A 1, Figure 1A 2, Figure 1B and Fig. 1 C the most basic circuit structure and operation thereof are described.In the semiconductor device shown in Figure 1A 1, the source electrode (or drain electrode) of bit line BL, transistor 160, the source electrode (or drain electrode) of transistor 162 are electrically connected to each other.Source electrode line SL is electrically connected to the drain electrode (or source electrode) of transistor 160.Gate lines G L is electrically connected to the gate electrode of transistor 162.The drain electrode of the gate electrode of transistor 160 and transistor 162 (or source electrode) is electrically connected to an electrode of capacitor 164.Electric capacity line CL is electrically connected to another electrode of capacitor 164.Note, can adopt following structure: the source electrode (or drain electrode) of transistor 160 is not electrically connected each other with the source electrode (or drain electrode) of transistor 162, and they are electrically connected to respectively other wirings.

Here, for example, comprise the transistor of oxide semiconductor as transistor 162.The transistor that comprises oxide semiconductor has the characteristic of minimum off state current.Therefore, the current potential of the gate electrode of transistor 160 can keep extremely long-time by making transistor 162 cut-offs.The providing of capacitor 164 be convenient to keep to give transistor 160 gate electrode electric charge and read and store data.

Note, the semiconductor material of transistor 160 is not particularly limited.Aspect the speed that improves reading out data, preferably for example use the transistor with high switching speed, such as the transistor that uses monocrystalline silicon.In the situation of using the p channel transistor shown in Figure 1A 1, Figure 1A 2 and Figure 1B as transistor 160.In the situation of using the n channel transistor shown in Fig. 1 C as transistor 160.

In addition, can omit capacitor 164 as shown in Figure 1B.

Semiconductor device utilization shown in Figure 1A 1 can keep the characteristic of current potential of the gate electrode of transistor 160, thus write as described as follows, maintenance and reading out data.

Writing and keep data of description at first.At first, be the current potential that makes transistor 162 conductings with the potential setting of gate lines G L, and transistor 162 conductings.Therefore, the current potential of bit line BL is offered the node (being also referred to as the FG of floating boom section) of an electrode of the gate electrode of the drain electrode (or source electrode) that is electrically connected on transistor 162, transistor 160 and capacitor 164.That is to say, predetermined charge is offered the FG of floating boom section (writing).Here, apply and provide two kinds of electric charges of different potentials (hereinafter, to provide the electric charge of electronegative potential to be called charge Q _L, and provide the electric charge of noble potential to be called charge Q _H) one of them.Note, can apply provides three kinds of different potentials or more kinds of electric charge, in order to improve memory capacity.After this, be the current potential that makes transistor 162 cut-offs with the potential setting of gate lines G L, and transistor 162 cut-offs.Therefore, keep offering the electric charge (maintenance) of the FG of floating boom section.

Because the off state current of transistor 162 is minimum, so the electric charge of the gate electrode of transistor 160 is kept for a long time.

Next reading data of description.By provide suitable potential (reading potential) to electric capacity line CL under the state that predetermined potential (constant potential) is provided to source electrode line SL, the current potential of bit line BL changes according to the quantity of electric charge that keeps at the FG of floating boom section.In other words, the conductance of transistor 160 is controlled by the electric charge in the gate electrode that remains on transistor 160 (may also be referred to as the FG of floating boom section).

Generally speaking, when transistor 160 is the p channel transistor, with Q _HGive apparent threshold threshold voltage (the apparent threshold voltage) V in the situation of gate electrode of transistor 160 _{Th_H}Be lower than with Q _LGive the apparent threshold threshold voltage V in the situation of gate electrode of transistor 160 _{Th_L}For example, in writing, provide Q _LSituation under, when the current potential of electric capacity line CL is V ₀(V _{Th_H}With V _{Th_L}Between the current potential of centre) time, transistor 160 conductings.Q is provided in writing _HSituation under, even when the current potential of electric capacity line CL be V ₀The time, transistor 160 is remain off also.Therefore, can read the data that keep by the current potential of measuring bit line BL.

Next with the rewriting of data of description.The rewriting of data according to the writing and keep similar mode to carry out of data.In other words, be the current potential that makes transistor 162 conductings with the potential setting of gate lines G L, and transistor 162 conductings.Therefore, the current potential (current potential of relevant new data) with bit line BL offers the FG of floating boom section.After this, be the current potential that makes transistor 162 cut-offs with the potential setting of electric capacity line CL, and transistor 162 cut-offs.The electric charge of relevant new data is offered the FG of floating boom section and remain among the FG of floating boom section.

In the semiconductor device according to a mode of the present invention, can write direct rewrite data by aforesaid another data.Therefore, high-tension electric charge from floating boom such as the use that need to not need in flash memory etc. extracts, and thereby can suppress the reduction of the operating speed that causes because of erase operation.In other words, can realize the high speed operation of semiconductor device.

As an example, the following specifically describes current potential VDD or earthing potential GND are offered the method that writes, keeps, reads in the situation of the FG of floating boom section.In the following description, the data that keep when current potential VDD is offered the FG of floating boom section are called data " 1 ", and the data that keep when earthing potential GND is offered the FG of floating boom section are called data " 0 ".Note, the relation that offers between the current potential of the FG of floating boom section is not limited to this.

When data writing, be GND with the potential setting of source electrode line SL, be GND with the potential setting of electric capacity line CL, be VDD with the potential setting of gate lines G L, and transistor 162 conductings.When data " 0 " were written to the FG of floating boom section, GND offered bit line BL.When data " 1 " are written to the FG of floating boom section, the current potential of bit line BL can be set as VDD, and the current potential of gate lines G L can be set as VDD+Vth_OS, so the current potential of the FG of floating boom section is not reduced to the voltage that equates with the threshold voltage (Vth_OS) of transistor 162.

When keeping data, be GND with the potential setting of gate lines G L, and transistor 162 cut-offs.In order to suppress transistor 160 by p channel transistor generation current and power consumption is same current potential with the current potential of bit line BL and the potential setting of source electrode line SL in bit line BL and source electrode line SL.Noting, as long as the current potential of bit line BL and the current potential of source electrode line SL are same current potential, can be VDD or GND with the potential setting of electric capacity line CL just.

Note, above-mentioned " same current potential " comprises " roughly same current potential ".In other words, above-mentioned purpose is for suppressing to be created in the electric current among bit line BL and the source electrode line SL by the potential difference (PD) between abundant reduction bit line BL and the source electrode line SL, therefore comprise " roughly same current potential ", this current potential is to compare the current potential etc. that fully (for example, one of percentage is following) reduces power consumption with the situation that current potential with source electrode line SL is fixed as GND etc.In addition, the potential error that causes because of cloth line resistance etc. is fully permissible.

When reading out data, be GND with the potential setting of gate lines G L, be GND with the potential setting of electric capacity line CL, be VDD or the current potential lower than VDD (below be called VSL) with the potential setting of source electrode line SL.Here, in the situation that data " 1 " are written to floating gate portion FG, transistor 160 cut-offs of p channel transistor, and the current potential of the bit line BL when reading beginning is held or rises.Note, keeping or rising of the current potential of bit line BL relies on the reading circuit that is connected in bit line BL.In the situation that data " 0 " are written to the FG of floating boom section, transistor 160 conductings, the current potential of bit line BL becomes current potential VDD or the VSL same with the current potential of source electrode line SL.Thereby, according to the current potential of bit line BL, can read the data " 1 " or the data " 0 " that remain on the FG of floating boom section.

Note, remain on (namely at current potential VDD, data " 1 " are written to) in the situation among the FG of floating boom section, potential setting with source electrode line SL when reading is VDD, thereby the grid of transistor 160 and the voltage between the source electrode (below, be called Vgsp) become Vgsp=VDD-VDD=0V, and Vgsp is higher than the threshold voltage of transistor 160, (below, be called Vthp), so transistor 160 cut-offs of p channel transistor.Here, even the current potential that remains among the FG of floating boom section is lower than in the situation of VDD because be written in that current potential among the FG of floating boom section is lower than VDD, satisfy Vgsp=(VDD-|Vthp| because the cut-off of transistor 160 when the current potential of the FG of floating boom section is greater than or equal to VDD-|Vthp|)-VDD=-|Vthp|=Vthp, also therefore normal reading out data " 1 ".Yet, be lower than in the situation of VDD-|Vthp| at the current potential of the FG of floating boom section, be lower than Vthp because Vgsp is set as, so transistor 160 conductings, what therefore read is not data " 1 " but data " 0 ", this just causes misreading.In other words, in the situation that data writing " 1 ", the lower limit of current potential that can reading out data is lower than the current potential VDD of source electrode line SL | Vthp|, i.e. VDD-|Vthp|.On the other hand, when when reading the potential setting of source electrode line SL being VSL, as mentioned above, the lower limit of current potential that can reading out data " 1 " is lower than the current potential VSL of source electrode line SL | Vthp|, i.e. VSL-|Vthp|.Here, because current potential VSL is lower than current potential VDD, VSL-|Vthp| is lower than VDD-|Vthp|.In other words, when the potential setting with source electrode line SL was VSL, the lower limit of current potential that can reading out data " 1 " was lower.Therefore, VSL is better than VDD as the current potential of source electrode line SL, and this is because the wider cause of scope of current potential that can reading out data " 1 ".Noting, is in the situation of VSL in the potential setting with source electrode line SL, when VDD is written to the FG of floating boom section Vgsp become VDD-VSL＞Vthp (because VDD＞VSL), therefore can no problem ground so that transistor 160 cut-offs.

The node (FG of floating boom section) that is electrically connected with an electrode of the gate electrode of drain electrode (or source electrode), transistor 160 of transistor 162 and capacitor 164 here, has the function similar to the transistorized floating boom of floating boom that is used for non-volatile memory device.When transistor 162 cut-off, the FG of floating boom section can be counted as embedding in the insulator, and thereby electric charge remain among the FG of floating boom section.The off state current that comprises the transistor 162 of oxide semiconductor is less than or equal to 1/100000 of the transistorized off state current that comprises silicon semiconductor etc.; The loss of the electric charge that gathers among the FG of floating boom section that therefore leakage current in the transistor 162 causes is insignificant.That is to say, comprise the transistor 162 of oxide semiconductor by utilization, can realize not providing electric power also can keep the Nonvolatile memory devices of data.

For example, (1 zA (narrow general holder ampere (zeptoampere)) is 1 * 10 when room temperature (25 ℃) plays the off state current of transistor 162 to be less than or equal to 10 zA ^-21A) and the capacitance of capacitor 164 when being approximately 10 fF, data can keep 10 ⁴Second or longer time.Much less, the retention time is depended on transistor characteristic and capacitance.

In addition, in the semiconductor device according to a mode of the present invention, do not have the deteriorated problem of gate insulator (tunnel insulator film), this problem is pointed out in conventional floating boom transistor.That is to say, can solve the deteriorated problem of the gate insulator that causes to floating boom because of electronic injection of the problem of being counted as.This means, the quantity to write cycle on the principle does not limit.In addition, do not need to write and wipe required high voltage in the conventional floating boom transistor.

Assembly the transistor in the semiconductor device of Figure 1A 1 can be counted as comprising the resistor shown in Figure 1A 2 and capacitor.That is to say, in Figure 1A 2, transistor 160 and capacitor 164 respectively are counted as comprising resistor and capacitor.R1 and C1 represent respectively resistance value and the capacitance of capacitor 164.Resistance R 1 is corresponding to the resistance value that is included in the insulation course in the capacitor 164.R2 and C2 represent respectively resistance value and the capacitance of transistor 160.The resistance value of the gate insulator of resistance value R2 during corresponding to transistor 160 conducting.Capacitor C 2 is corresponding to so-called grid capacitance (electric capacity that forms between gate electrode and source electrode or drain electrode and the electric capacity that forms between gate electrode and channel formation region).

Fully little and R1 and R2 satisfy under the condition of R1 〉=ROS, R2 〉=ROS at the grid leakage current of transistor 162, when ROS is source electrode under the state of transistor 162 cut-off and the resistance between the drain electrode when (being called again effective resistance), mainly by the off state current of transistor 162 determine electric charge keep during (be called again data maintenance during).

On the other hand, when not satisfying above-mentioned condition, during being difficult to guarantee fully keep, even the off state current of transistor 162 is fully little.This is because the leakage current (for example being created on the leakage current between source electrode and the gate electrode) except the off state current of transistor 162 is large.Therefore, can say, preferably satisfy the relation of R1 〉=ROS and R2 〉=ROS according to the semiconductor device of present embodiment.

On the other hand, preferably, satisfy C1 〉=C2.This be because, if resistance C1 is large, then when the current potential of the FG of floating boom section is controlled by electric capacity line CL, the current potential of electric capacity line CL can be offered effectively the FG of floating boom section, and can make the difference between the current potential (for example reading potential and non-reading potential) that offers electric capacity line CL less.

As mentioned above, when satisfying above-mentioned relation, can realize preferred semiconductor device.Note, R1 and R2 are by the insulation course control of gate insulator and the capacitor 164 of transistor 160.Same relation is applicable to C1 and C2.Therefore, the material of gate insulator, thickness etc. preferably suitably are arranged to satisfy above-mentioned relation.

In the described semiconductor device of present embodiment, the FG of floating boom section has the function similar to the transistorized floating boom of floating boom in flash memory etc., but the FG of floating boom section of present embodiment has different from the floating boom in flash memory etc. in essence features.

In flash memory, because it is high to be applied to the current potential of control gate, affect the floating boom of adjacent cells so need the suitable distance between the holding unit in order to prevent this current potential.This is one of highly integrated factor that hinders by semiconductor device.This factor is owing to the ultimate principle of flash memory, and wherein tunnel current flows through by applying high electric field.

By contrast, operate by the transistor that switch comprises oxide semiconductor according to the semiconductor device of present embodiment, and do not use the above-mentioned principle of the charge injection that tunnel current carries out.That is to say, different from flash memory, do not need the high electric field for charge injection.Therefore, do not need to consider from the impact on adjacent cells of the high electric field of control gate, and this is convenient to highly integrated.

In addition, also be than the advantage part of flash memory, do not need high electric field, and do not need large peripheral circuit (for example booster circuit (booster circuit)).For example, in the situation of the data that write two-stage (), in each storage unit, be applied to ceiling voltage according to the storage unit of present embodiment (be applied to simultaneously between the maximum potential of terminal of storage unit and the potential minimum poor) and can be less than or equal to 5 V, be preferably lower than or equal 3 V.

In the relative dielectric constant ε r1 that is included in the insulation course in the capacitor 164 situation different from the relative dielectric constant ε r2 of insulation course in being included in transistor 160, satisfy 2 * S2 more than or equal to S1(2 * S2 〉=S1) with the area S1 that is included in the insulation course in the capacitor 164 and the area S2 of insulation course that is included in the gate capacitor of transistor 160, preferred S2 is more than or equal to S1(S2 〉=S1) time, and C1 easily becomes more than or equal to C2.In other words, can be easy to make C1 more than or equal to C2, make simultaneously the area that is included in the insulation course in the capacitor 164 little.Specifically, for example, the stacked insulation course for being included in capacitor 164 of the film that the high-k material of use such as hafnia forms or the high-k material of use such as hafnia the film that forms and the film that uses oxide semiconductor to form, so that ε r1 can be arranged to more than or equal to 10, be preferably more than or equal 15, and be used to form the insulation course of gate capacitor when the film that uses monox to form, so that ε r2 can be arranged to 3 to 4.

The combination of this class formation make can realize according to the semiconductor device of a mode of the present invention further higher integrated.

＜example application 〉

Next, more specifically circuit structure and the operation thereof of having used the circuit shown in Figure 1A 1, Figure 1A 2, Figure 1B and Fig. 1 C described with reference to the accompanying drawings.Describing in the present embodiment makes a storage unit keep the so-called multivalued storage of a plurality of states.

Fig. 2 is an example of the block diagram of semiconductor device.The feature of the block diagram of semiconductor device shown in Figure 2 relates to the write operation of driving circuit.Semiconductor device shown in Figure 2 is to keep 2 in a storage unit ^KThe multivalued storage of value (K is the integer more than 1), and have memory cell array 201, column drive circuit 202, horizontal drive circuit 203 and the potential generation circuit 207 that comprises a plurality of storage unit.

That memory cell array 201 has is a plurality of (for example, m) gate lines G L and a plurality of (for example, m) electric capacity line CL, a plurality of (for example, n) bit line BL, source electrode line SL(are not shown) and be configured to rectangular a plurality of storage unit 170.

As storage unit 170, the storage unit shown in can application drawing 1A1.In addition, as storage unit 170, can use the storage unit shown in Figure 1B.In the case, can omit electric capacity line CL.Moreover, as storage unit 170, the storage unit shown in can application drawing 1C.

Potential generation circuit 207 is by being provided a plurality of simulation current potential VW(1) to VW(2 ^K) 2 ^KIndividual power lead VW is connected to column drive circuit 202.Potential generation circuit 207 produces a plurality of simulation current potential VW(1) to VW(2 ^K) and output to column drive circuit 202.

Column address signal line CA, input data signal line DIN, outputting data signals line DOUT and control signal wire CE etc. are connected to column drive circuit 202.In column drive circuit 202, be provided with latch section and the write circuit of K position by each row of storage unit 170.Latch group 226(1) to 226(n) be connected respectively to write circuit 224(1 by K latch output signal line) to 224(n).Column drive circuit 202 control bit line BL and source electrode line SL also are connected to memory cell array 201 by bit line BL and source electrode line SL.

Write circuit 224(1) to 224(n) be connected to K latch output signal line and be provided the simulation current potential VW(1 that exports from potential generation circuit 207) to VW(2 ^K) 2 ^KIndividual power lead VW.Write circuit 224(1) to 224(n) have respectively a multiplexer 335(1) to 335(n).Latch group 226(1 based on the K position) to 226(n) output signal, multiplexer 335(1) to 335(n) respectively from a plurality of simulation current potential VW(1 of potential generation circuit 207 output) to VW(2 ^K) current potential of middle selection.Then, can carry out under the state of write operation write circuit 224(1) to 224(n) output is by multiplexer 335(1) to 335(n) current potential selected.

Row address signal line RA and control signal wire CE etc. are connected to horizontal drive circuit 203.Horizontal drive circuit 203 control gate polar curve GL and electric capacity line CL also are connected to memory cell array 201 by gate lines G L and electric capacity line CL.

The latch group 226(1 of the K position will be stored in row then, will be described) to 226(n) in data be written to simultaneously the method for the storage unit in the delegation.

In horizontal drive circuit 203, High current potential (below, be called the H current potential) is offered control line CE, and horizontal drive circuit 203 can be operated, and row address signal is input to row address signal line RA, and select row by the row address signal appointment.The signal of indication write state is input to the control line CE of appointment, and the current potential that will be used for writing offers electric capacity line CL in the selected row and electric capacity line CL and the gate lines G L in gate lines G L and the non-selection row.At the storage unit 170(1 with structure shown in Figure 2,1) to 170(m, n) in, the current potential of electric capacity line CL in the selected row and the current potential of gate lines G L become respectively the Low current potential (below, be called the L current potential) and current potential VH, and the current potential of the current potential of the electric capacity line CL in the non-selection row and gate lines G L becomes respectively current potential VH and L current potential.

In column drive circuit 202, the H current potential is offered control line CE, and column drive circuit 202 can be operated.The signal of indication write state is input to the control line CE of appointment, thus the write circuit 224(1 in each row) to 224(n) each will be from a plurality of simulation current potential VW(1) to VW(2 ^K) in one of the current potential selected output to bit line BL(1) to BL(n).This current potential is based on the latch group 226(1 from the K position) to 226(n) output signal by being included in write circuit 224(1) to 224(n) and in multiplexer 335(1) to 335(n) select.

Consequently, the write circuit 224(1 from row) to 224(n) the simulation current potential of output offers the FG of floating boom section of the storage unit in the row of being selected by horizontal drive circuit 203 by bit line BL.

Then, in horizontal drive circuit 203, to indicate the signal of the end of write state to be input to the control line CE of appointment, and the current potential that will be used for finishing to write offer electric capacity line CL and the electric capacity line CL in gate lines G L and the non-selection row and each of gate lines G L that is selected in the row.In the storage unit 170 with structure shown in Figure 2, be the L current potential with the potential setting that is selected the gate lines G L in the row.Consequently, transistor 162 cut-offs that the storage unit in the selected row has, and keep the electric charge of savings in the FG of floating boom section.Be the L current potential with the potential setting of the electric capacity line CL in the non-selection row.Thus, storage unit 170(1,1) to 170(m, n) write operation finish.

As mentioned above, in semiconductor device shown in Figure 2, can simultaneously many-valued data be written to storage unit in the delegation.

Note, as an example, can be VDD with the H potential setting, and can be GND with the L potential setting.

Because semiconductor device shown in Figure 2 has bit line BL that storage unit has and the FG of floating boom section by transistor 162 structures connected to one another, so current potential directly can be offered the FG of floating boom section of savings electric charge in write operation.Consequently, can carry out at a high speed write operation to each storage unit.Especially, compare with the wiring method that as the floating boom transistor of non-volatile memory device, uses minimum tunnel current to carry out charge injection, can control the current potential of the floating boom FG of section with short period and high precision, and can carry out write operation.

In addition, in semiconductor device shown in Figure 2, offer all write circuit 224(1 in the row by a plurality of simulation current potentials that will in potential generation circuit 207, produce) to 224(n), the therefore write circuit 224(1 in the row) to 224(n) each can select independently current potential corresponding to data writing from a plurality of simulation current potentials.Consequently, many-valued data once and at a high speed can be written to storage unit in the delegation.

Note, as be used as the floating boom transistor of non-volatile memory device by using minimum tunnel current iunjected charge to come need to change the write time according to data writing in the situation of data writing.That is, when writing the few data of charge injection amount, need to write with the short period, when writing the many data of charge injection amount, need to write with the long period.Consequently, need to repeatedly write, and this causes the operation of complexity and low speed.On the other hand, semiconductor device shown in Figure 2 can once and at a high speed be written to many-valued data the storage unit in the delegation, and irrelevant with data writing.

In addition, to 2 ^KThe storer of value writes in the method for data, can make to be contained in 2 in the storage unit ^KThe data of value are corresponding to the latch section of K position, and can reduce the circuit scale of semiconductor device shown in Figure 2.For example, in the situation of the data that storage 4 is worth, utilize the structure of the latch section with 2.Especially, to 2 ^KIn the method for data writing of the storer of value, be stored in 2 in the storage unit making ^KEach data of value are contained in the situation corresponding to a latch, need 2 ^KThe latch section of position.Compare with such structure, can reduce circuit scale.

Note, the structure of the NOR type memory cell array with the storage unit shown in Figure 1A 1 is shown as example in the present embodiment, wherein the source electrode of the source electrode of transistor 160 or drain electrode and transistor 162 or drain electrode are connected in parallel by bit line BL, yet a mode of the present invention is not limited to this structure.Source electrode or the drain electrode of the source electrode of transistor 160 or drain electrode and transistor 162 can be connected to different wirings.Shown in Fig. 1 C, the transistor 160 that is included in the storage unit can be the n channel transistor.In addition, as shown in Figure 5, can adopt the NAND type memory cell array that the storage unit series connection is connected.

This be because in semiconductor device shown in Figure 2 write circuit 224(1 in the row) to 224(n) can from a plurality of simulation current potentials, select independently corresponding to the current potential of data writing the cause with the structure-irrelevant of storage unit.This is still because as long as 162 gate lines G L are connected to the cause that the FG of floating boom section just can directly offer the FG of floating boom section with current potential and can carry out writing at a high speed by transistor in storage unit.

Note, in the present embodiment, input data signal line DIN and outputting data signals line DOUT are connected to column drive circuit 202, yet the present invention is not limited to this.Also can connect input/output data signal wire DINOUT.

Figure 24 is another example of the block diagram of semiconductor device.The feature of the block diagram of semiconductor device shown in Figure 24 relates to the read operation of driving circuit.Semiconductor device shown in Figure 24 is to keep 2 in a storage unit ^KThe multivalued storage of value (K is the integer more than 1) state, and have the counter 206 of the memory cell array 201, column drive circuit 202, horizontal drive circuit 203, potential generation circuit 207 and the K position that comprise a plurality of storage unit.

Memory cell array 201 has a plurality of gate lines G L and a plurality of electric capacity line CL, a plurality of bit line BL, source electrode line SL and is configured to rectangular a plurality of storage unit 170.

The counter 206 of K position is with K count signal COUNT(1) to COUNT(K) output to column drive circuit 202 and potential generation circuit 207.The counter 206 of K position is connected to column drive circuit 202 and potential generation circuit 207 by K count signal line.

K count signal COUNT(1) to COUNT(K) be imported into potential generation circuit 207, and potential generation circuit 207 will be simulated current potential and be outputed to horizontal drive circuit 203.Potential generation circuit 207 produces the simulation current potential according to the value change of count signal.Potential generation circuit 207 is connected to horizontal drive circuit 203 by the variable power supply line VR that is provided the simulation current potential.

Column address signal line CA, input data signal line DIN, outputting data signals line DOUT and control signal wire CE etc. are connected to column drive circuit 202.In column drive circuit 202, be provided with latch section and the reading circuit of K position by each row of storage unit 170.Latch group 226(1) to 226(n) be connected respectively to reading circuit 225(1 by K latch input signal line) to 225(n).Column drive circuit 202 control bit line BL and source electrode line SL also are connected to memory cell array 201 by bit line BL and source electrode line SL.

Storage unit 170 is connected to reading circuit 225(1 by bit line BL) to 225(n) as load.Reading circuit 225(1) to 225(n) comprise K output signal line.Can carry out under the state of read operation reading circuit 225(1) to 225(n) each output when pull-up resistor is high, become the H current potential and when pull-up resistor hangs down, become the internal signal of L current potential.In addition, when internal signal is the H current potential, reading circuit 225(1) to 225(n) will be from K count signal COUNT(1 of counter 206 input of K position) to COUNT(K) offer output signal line, and when internal signal was the L current potential, output signal line became high impedance status.Latch group 226(1) to 226(n) storage is fed to the data of K latch input signal line.

Then, the storage unit of describing from desirable row is read the latch group 226(1 of many-valued data and the K position in each row) to 226(n) middle method of storing data.

In horizontal drive circuit 203, the H current potential is offered control line CE, and horizontal drive circuit 203 can be operated, row address signal is input to row address signal line RA, and selects the row by the row address signal appointment.The signal of indication reading state is input to the control line CE of appointment, and the current potential that will be used for reading offers electric capacity line CL and the electric capacity line CL in gate lines G L and the non-selection row and each of gate lines G L in the selected row.In the storage unit 170(1 with structure shown in Figure 24,1) to 170(n, m) in, will offer from the simulation current potential of potential generation circuit 207 output the electric capacity line CL the selected row, and current potential VH will be offered electric capacity line CL in the non-selection row.The L current potential is offered gate lines G L.

In column drive circuit 202, the H current potential is offered control line CE, and column drive circuit 202 can be operated.The signal of indication reading state is input to the control line CE of appointment, thus the reading circuit 225(1 in the row) to 225(n) become can reading out data state.Current potential VSR is offered source electrode line SL.

In addition, the counter in during read K position count down to " 2 from " 0 " ^K-1 ".When the value of counter is that " i " (i is 0 to 2 ^K-1) time, potential generation circuit 207 produces and output simulation current potential VR(i).In the present embodiment, the value of counter is larger, and the simulation current potential that is produced is lower.That is, VR(i)＞VR(i+1) (i is 0 to 2 ^K-2).Consequently, according to the value of counter, will simulate current potential VR(0 from height) to low simulation current potential VR(2 ^K-1) offers in order the electric capacity line CL that is selected in the row.

When the potential change of electric capacity line CL, the current potential of the FG of floating boom section changes by capacitive coupling.The current potential of the electric capacity line CL that needs in order to make transistor 160 conductings is known as the threshold voltage of storage unit.In the present embodiment, because transistor 160 is p channel transistors, transistor 160 cut-offs when the current potential of electric capacity line CL is higher than the threshold voltage of storage unit, and transistor 160 conductings when the current potential of electric capacity line CL hangs down than the threshold voltage of storage unit.The threshold voltage of storage unit is difference according to being stored in data in the storage unit.Data in being stored in storage unit are that j(j is 0 to 2 ^K-1) time, the threshold voltage of storage unit is Vth(i).

Potential generation circuit 207 produces and satisfies VR(i)＞Vth(i) (i is 0 to 2 ^K-1) and Vth(i)＞VR(i+1) (i is 0 to 2 ^K-2) VR(i).That is, produce that to be higher than storage data j(j be i to 2 ^KThe threshold voltage of storage unit-1) and to be lower than storage data j(j be 0 to i-1) the current potential of threshold voltage of storage unit, as VR(i).

When the current potential of electric capacity line CL reduced with the value of counter and is lower than the threshold voltage of selecteed storage unit, transistor 160 changed to conducting from cut-off state.Reading circuit 225(1 in the row) to 225(n) pull-up resistor when the transistor 160 in the storage unit of respective column changes to conducting from cut-off state, change to low pull-up resistor from high capacity resistance.

When pull-up resistor is high, reading circuit 225(1) to 225(n) export from K count signal COUNT(1 of counter 206 inputs of K position) to COUNT(K).Then, from reading circuit 225(1) to 225(n) the value of count signal of output signal be stored in the latch section of K position.On the other hand, when pull-up resistor is low, reading circuit 225(1) to 225(n) output signal line become high impedance status.At this moment, be stored in the latch group 226(1 of K position) to 226(n) in data be held.The value of the counter when consequently, the current potential of electric capacity line CL is lower than the threshold voltage of storage unit is stored in K position latch group 226(1) to 226(n) in.That is, when reading the storage unit of storage data " i ", data " i " are stored in the latch section.

As mentioned above, in semiconductor device shown in Figure 24, can the storage unit from desirable row read many-valued data.

Note, as an example, H current potential, L current potential and current potential VSR can be VDD, GND and VDD respectively.

From 2 ^KIn the method for the memory read data of value, can make to be stored in 2 in the storage unit ^KThe data of value are corresponding to the latch section of K position, and can reduce the circuit scale of semiconductor device shown in Figure 24.For example, in the situation of the data that storage 4 is worth, adopt the structure of the latch section that comprises 2.Especially, from 2 ^KIn the method for memory read data of value, make be stored in the storage unit each 2 ^KIn the situation of data corresponding to a latch of value, need 2 ^KIndividual latch.Compare with such structure, can reduce circuit scale.

Note, the structure of the NOR type memory cell array that comprises the storage unit shown in Figure 1A 1 is shown as example in the present embodiment, wherein the source electrode of the source electrode of transistor 160 or drain electrode and transistor 162 or drain electrode are connected in parallel by bit line BL, yet a mode of the present invention is not limited to this structure.Source electrode or the drain electrode of the source electrode of transistor 160 or drain electrode and transistor 162 can be connected to different wirings.Shown in Fig. 1 C, the transistor 160 that is included in the storage unit can be the n channel transistor.In addition, as shown in Figure 4, can adopt NAND type memory cell array, wherein the storage unit series connection connects.

This is because following cause: in semiconductor device shown in Figure 24, the reading circuit 225(1 in the row) to 225(n) the value of each counter when pull-up resistor is changed be stored in the latch section, and with the structure-irrelevant of storage unit.This or because following cause: the state of storage unit (transistor 160 be conducting state or cut-off state) can be controlled by the value of the counter 206 of K position.

Note, in the present embodiment, the counter 206 in during read K position count down to " 2 from " 0 " ^K-1 ", however a mode of the present invention is not limited to this.The counter 206 of K position can be from " 2 ^K-1 " count down to " 0 ".In addition, in the present embodiment, height is simulated current potential to low simulation current potential offer in order the electric capacity line CL that is selected in the row, yet a mode of the present invention is not limited to this.Also can offer in order the electric capacity line CL that is selected in the row with hanging down the paramount simulation current potential of simulation current potential.In addition, in the present embodiment, the threshold voltage vt h(j of the data that storage unit is stored " j ") be higher than the threshold voltage vt h(j+1 of the data " j+1 " that storage unit stores), however a mode of the present invention is not limited to this.The threshold voltage vt h(j of the data that storage unit is stored " j ") can be lower than the threshold voltage vt h(j+1 of the data " j+1 " that storage unit stores).

Figure 25 is an example of the block diagram of semiconductor device.The feature of the block diagram of semiconductor device shown in Figure 25 relates to write operation and the read operation of driving circuit.Semiconductor device shown in Figure 25 is to keep 2 in a storage unit ^KThe multivalued storage of value (K is the integer more than 1) state, and have the counter 206 of the memory cell array 201, column drive circuit 202, horizontal drive circuit 203, potential generation circuit 207 and the K position that comprise a plurality of storage unit.

Potential generation circuit 207 produces a plurality of simulation current potential VW(1) to VW(2 ^K), and output to column drive circuit 202.Potential generation circuit 207 is by being provided simulation current potential VW(1) to VW(2 ^K) 2 ^KIndividual power lead is connected to column drive circuit 202.K count signal COUNT(1) to COUNT(K) be imported into potential generation circuit 207, and potential generation circuit 207 will be simulated current potential and be outputed to horizontal drive circuit 203.Potential generation circuit 207 produces the simulation current potential according to the value change of count signal.Potential generation circuit 207 is connected to horizontal drive circuit 203 by the power lead that is provided the simulation current potential.

Column address signal line CA, input data signal line DIN, outputting data signals line DOUT and control signal wire CE etc. are connected to column drive circuit 202.In column drive circuit 202, be provided with latch section, write circuit and the reading circuit of K position by each row of storage unit 170.Latch group 226(1) to 226(n) be connected respectively to write circuit 224(1 by K latch output signal line) to 224(n) and reading circuit 225(1) to 225(n).Column drive circuit 202 control bit line BL and source electrode line SL also are connected to memory cell array 201 by bit line BL and source electrode line SL.

Write circuit 224(1) to 224(n) be connected to K latch output signal line and be provided the simulation current potential VW(1 that exports from potential generation circuit 207) to VW(2 ^K) 2 ^KIndividual power lead VW.Write circuit 224(1) to 224(n) comprise respectively multiplexer 335(1) to 335(n).Latch group 226(1 based on the K position) to 226(n) output signal, multiplexer 335(1) to 335(n) each a plurality of simulation current potential VW(1 from potential generation circuit 207 output) to VW(2 ^K) current potential of middle selection.Can carry out under the state of write operation write circuit 224(1) to 224(n) output is by multiplexer 335(1) to 335(n) current potential selected.

Then, because will be stored in the latch group 226(1 of the K position in the row) to 226(n) in the data method that is written to simultaneously the storage unit in the delegation identical with the method for work of semiconductor device shown in Figure 2, so the description thereof will be omitted.

Because the storage unit from desirable row reads the latch group 226(1 of many-valued data and the K position in row) to 226(n) in the method for storage data identical with the method for work of semiconductor device shown in Figure 24, so the description thereof will be omitted.

Because semiconductor device shown in Figure 25 has bit line BL that storage unit has and the FG of floating boom section by transistor 162 structures connected to one another, so current potential directly can be offered the FG of floating boom section of savings electric charge in write operation.Consequently, can carry out at a high speed write operation to each storage unit.Especially, compare with the wiring method that as the floating boom transistor of non-volatile memory device, uses minimum tunnel current to carry out charge injection, can control the current potential of the floating boom FG of section with short period and high precision, and can carry out write operation.

In addition, in semiconductor device shown in Figure 25, offer all write circuit 224(1 in the row by a plurality of simulation current potentials that will in potential generation circuit 207, produce) to 224(n), the write circuit 224(1 in each row thus) to 224(n) can select independently current potential corresponding to data writing from a plurality of simulation current potentials.Consequently, many-valued data once and at a high speed can be written to storage unit in the delegation.

Note, as be used as the floating boom transistor of non-volatile memory device by using minimum tunnel current iunjected charge to come need to change the write time according to data writing in the situation of data writing.That is, when writing the few data of charge injection amount, need to write with the short period, when writing the many data of charge injection amount, need to write with the long period.Consequently, need to repeatedly write, and this causes the operation of complexity and low speed.On the other hand, semiconductor device shown in Figure 25 can once and at a high speed be written to many-valued data the storage unit in the delegation, and irrelevant with data writing.

In addition, to 2 ^KThe storer of value writes and from the method for its reading out data, can make to be stored in 2 in the storage unit ^KThe data of value are corresponding to the latch section of K position, and can reduce the circuit scale of semiconductor device shown in Figure 25.Especially, because be written to the data of storage unit and be stored in the latch cicuit of same K position from the data that storage unit reads, so can reduce circuit scale.For example, in the situation of the data that storage 4 is worth, utilize the structure of the latch section with 2.

To 2 ^KThe storer of value writes in the method for data, make be stored in the storage unit each 2 ^KIn the situation of data corresponding to a latch of value, need 2 ^KThe latch section of position.Perhaps, from 2 ^KIn the method for memory read data of value, make be stored in the storage unit each 2 ^KIn the situation of data corresponding to a latch of value, need 2 ^KThe latch section of position.Even be written to the data of storage unit and all be the data of K position from the data that storage unit reads, when data mode does not need to form respectively as the latch section of the K position of read operation with as the latch section of the K position of write operation simultaneously, so circuit scale becomes large.Circuit scale with semiconductor device of structure shown in Figure 25 is compared and can be reduced with in these structures any.

Note, in the present embodiment, as shown in Figure 4, the structure of the NOR type memory cell array that comprises the storage unit shown in Figure 1A 1 is shown as example, wherein the source electrode of the source electrode of transistor 160 or drain electrode and transistor 162 or drain electrode are connected in parallel by bit line BL, yet a mode of the present invention is not limited to this structure.Source electrode or the drain electrode of the source electrode of transistor 160 or drain electrode and transistor 162 can be connected to different wirings.Shown in Fig. 1 C, the transistor 160 that comprises storage unit can be the n channel transistor.In addition, as shown in Figure 5, can adopt NAND type memory cell array, wherein the storage unit series connection connects.

This be because in semiconductor device shown in Figure 25 write circuit 224(1 in the row) to 224(n) can from a plurality of simulation current potentials, select independently corresponding to the current potential of data writing the cause with the structure-irrelevant of storage unit.This or because as long as 162 gate lines G L are connected to that the FG of floating boom section just can directly offer the FG of floating boom section with current potential and the cause that can write at a high speed by transistor in storage unit.

In addition, this is because following cause: in semiconductor device shown in Figure 25, the reading circuit 225(1 in the row) to 225(n) the value of each counter when pull-up resistor is changed be stored in the latch section, and with the structure-irrelevant of storage unit.This or because following cause: the state of storage unit (transistor 160 be conducting state or cut-off state) can be controlled by the value of the counter 206 of K position.

Note, in the present embodiment, the counter 206 in during read K position count down to " 2 from " 0 " ^K-1 ", however a mode of the present invention is not limited to this.The counter 206 of K position can be from " 2 ^K-1 " count down to " 0 ".In addition, in the present embodiment, height is simulated current potential to low simulation current potential offer in order the electric capacity line CL that is selected in the row, yet a mode of the present invention is not limited to this.Can offer in order the electric capacity line CL that is selected in the row with hanging down the paramount simulation current potential of simulation current potential.In addition, in the present embodiment, the threshold voltage vt h(j of the data that storage unit is stored " j ") be higher than the threshold voltage vt h(j+1 of the data " j+1 " that storage unit stores), however a mode of the present invention is not limited to this.The threshold voltage vt h(j of the data that storage unit is stored " j ") can be lower than the threshold voltage vt h(j+1 of the data " j+1 " that storage unit stores).

Then, will the structure of the semiconductor device of using foregoing circuit be described.

Particularly, illustrate and comprise 8 input/output data signal wire I/O and a storage unit is write or reads 4 (16 values (2 from it ⁴The circuit structure of data value)) is as example.In addition, except as otherwise noted, the H current potential illustrates VDD, and the L current potential illustrates GND.

Fig. 3 A is an example of the block diagram of semiconductor device.Semiconductor device shown in Fig. 3 A has memory cell array 201, column drive circuit 202, horizontal drive circuit 203, controller 204, counter 206, I/O control circuit 205 and the potential generation circuit 207 that comprises a plurality of storage unit 170.

Memory cell array 201 is connected to control bit line BL and the column drive circuit 202 of source electrode line SL and the horizontal drive circuit 203 of control gate polar curve GL and electric capacity line CL.Column drive circuit 202 is connected to potential generation circuit 207, counter 206 and I/O control circuit 205.Horizontal drive circuit 203 is connected to potential generation circuit 207.Potential generation circuit 207 is connected to counter 206.These circuit except memory cell array 201 are connected to controller 204.

I/O control circuit 205 is connected to 8 input/output data signal wire I/O1 to I/O8, and is connected to column drive circuit 202 by input data signal line DIN1 to DIN8 and outputting data signals line DOUT1 to DOUT8.I/O control circuit 205 is by controller 204 controls.For example, when the H current potential was input to I/O control circuit 205 by the control line that is connected with controller 204, the signal of 8 input/output data signal wire I/O1 to I/O8 was input to I/O control circuit 205.8 input/output data signal wire I/O1 to I/O8 are electrically connected to respectively 8 input data signal line DIN1 to DIN8, and the signal of 8 outputting data signals line DOUT1 to DOUT8 is outputed to column drive circuit 202.Add, when the L current potential was input to I/O control circuit 205 by the control line that is connected with controller 204, the signal of 8 outputting data signals line DOUT1 to DOUT8 was input to I/O control circuit 205 from column drive circuit 202.8 outputting data signals line DOUT1 to DOUT8 are electrically connected to respectively 8 input/output data signal wire I/O1 to I/O8, and the signal of 8 outputting data signals line DOUT1 to DOUT8 is outputed to input/output data signal wire I/O1 to I/O8.

Counter 206 is connected to column drive circuit 202 and potential generation circuit 207 by count signal line COUNT0 to COUNT3.Counter 206 is by controller 204 control, and the data of 4 count signal line COUNT0 to COUNT3 are outputed to column drive circuit 202 and potential generation circuit 207.

Potential generation circuit 207 is connected to column drive circuit 202 and is connected to horizontal drive circuit 203 by variable power supply line VR by analog power pressure-wire V1 to V16 and stabilized power source line VREAD.Potential generation circuit 207 is by controller 204 controls.Potential generation circuit 207 with the Voltage-output of the voltage of high power supply voltage VH, analog power pressure-wire V1 to V16 and stabilized power source line VREAD to column drive circuit 202.Potential generation circuit 207 will be owing to the data of count signal line COUNT0 to COUNT3 voltage and the high power supply voltage VH of the variable power supply line VR of variation in voltage output to horizontal drive circuit 203.In the present embodiment, the pass between the voltage of analog power pressure-wire V1 to V16 is V1＜V2＜V3＜V4＜V5＜V6＜V7＜V8＜V9＜V10＜V11＜V12＜V13＜V14＜V15＜V16＜VH.The voltage of analog power pressure-wire V1 is GND.The data of count signal line COUNT0 to COUNT3 are less, and the voltage of variable power supply line VR is larger.Note, variable power supply line VR is by controller 204 controls.Variable power supply line VR output is corresponding to the voltage of the data of count signal line COUNT0 to COUNT3 when read operation.In other cases, variable power supply line VR output L current potential.

As the storage unit 170 shown in Fig. 3 B, the storage unit shown in can application drawing 1A1.In addition, as storage unit 170, can use the storage unit shown in Figure 1B.In addition, shown in Fig. 3 C, like that, can omit electric capacity line CL.Moreover, as storage unit 170, the storage unit shown in can application drawing 1C.

The structure of memory cell array 201 then, is described with reference to Fig. 4 and Fig. 5.

Fig. 4 illustrates the example of memory cell array 201.Memory cell array 201 shown in Figure 4 comprises m gate lines G L, m electric capacity line CL, a n bit line BL, (n/8) individual source electrode line SL and a plurality of storage unit 170.Here, storage unit 170 is configured to the rectangular of capable (on the longitudinal direction) * n row of m (on transverse direction).Here, 8 array storage units 170 are set and a source electrode line SL is set by every.Therefore, compare with the situation that in each row, is provided with a source electrode line SL, can reduce the quantity of wiring.In addition, can save the area of memory cell array 201.Certainly, n source electrode line SL can be arranged in the memory cell array shown in Figure 4 201.

N bit line BL and (n/8) individual source electrode line SL be connected to bit line and the source line driving circuit 221 in the column drive circuit 202 of being included in shown in Fig. 3 A.M gate lines G L and m electric capacity line CL are connected to gate line and the electric capacity line drive circuit 231 in the horizontal drive circuit 203 of being included in shown in Fig. 3 A.

Fig. 5 illustrates another example of memory cell array 201.Memory cell array 201 shown in Figure 5 comprises selects line G(1), m gate lines G L, m electric capacity line CL, a n bit line BL, source electrode line SL and a plurality of storage unit 170.Here, storage unit 170 is configured to the rectangular of capable (on the longitudinal direction) * n row of m (on transverse direction).

N bit line BL and source electrode line SL are connected to bit line and the source line driving circuit 221 in the column drive circuit 202 of being included in shown in Fig. 3 A.Select line G(1), a m gate lines G L and m electric capacity line CL be connected to gate line and the electric capacity line drive circuit 231 in the horizontal drive circuit 203 of being included in shown in Fig. 3 A.

Then, with reference to Fig. 6 the structure that the row that are connected to memory cell array 201 drive the moving circuit 202 of device is described.

In Fig. 6, column drive circuit 202 comprises bit line, source line driving circuit 221 and column decoder 222.Bit line and source line driving circuit 221 comprise selector switch 229.In bit line and source line driving circuit 221, selector switch 228, latch group 226(are also referred to as latch section), write circuit 224, reading circuit 225 and

analog switch

223a, 223b be included in each row of storage unit.Impact damper 230 arranges 8 array storage units and arranges by every.Storer read signal line PRE is connected to source electrode line SL by impact damper 230.

Column decoder 222 is connected to selector switch 229.Selector switch 229 is connected to selector switch 228.Selector switch 228 is connected to latch group 226.Latch group 226 is connected to the write circuit 224 that reading circuit 225 separately reaches separately.For example, the reading circuit 225(1 in the first row) be connected to bit line BL(1 by analog switch 223a), the write circuit 224(1 in the first row) be connected to bit line BL(1 by analog switch 223b).Reading circuit 225(n in the n row) be connected to bit line BL(n by analog switch 223a), the write circuit 224(n in the n row) be connected to bit line BL(n by analog switch 223b).

Column decoder 222 is connected with Nc individual (2 ^Nc* 2 ³=n) column address signal line CA and control line CE.Column decoder 222 is connected to selector switch 229 by (n/8) individual column decoding signal wire.With Nc individual (2 ^Nc* 2 ³=n) data and the control signal CE of column address signal line CA are input to column decoder 222, and column decoder 222 outputs to data (n/8) individual column decoding signal wire.When control line CE is set as the H current potential, corresponding to Nc individual (2 ^Nc* 2 ³=n) data of column address signal line CA will to only have the data setting of (n/8) individual column decoding signal wire be the H current potential.When control line CE is set as the L current potential, be the L current potential with the data setting of all column decoding signal wires, and with Nc (2 ^Nc* 2 ³=n) the data independence of column address signal line CA.

(n/8) individual column decoding signal wire, input data signal line DIN1 to DIN8, outputting data signals line DOUT1 to DOUT8, input select signal line DI1(1) to DI8(n) and output select signal wire DO1(1) to DO8(n) be connected to selector switch 229.Because (n/8) data of individual column decoding signal wire, input data signal line DIN1 to DIN8 and input select signal line DI1(1) to DI8(n) 8 line conductings.Identical therewith, outputting data signals line DOUT1 to DOUT8 selects signal wire DO1(1 with output) to DO8(n) 8 line conductings.For example, when the potential setting with the 5th column decoding signal wire is the H current potential, input data signal line DIN1 to DIN8 and input select signal line DI1(5) to DI8(5) conducting, and outputting data signals line DOUT1 to DOUT8 selects signal wire DO1(5 with output) to DO8(5) conducting.In the case, other input select signal lines and other output select signal wire to be in quick condition with respect to input data signal line DIN1 to DIN8 and outputting data signals line DOUT1 to DOUT8.When the potential setting with all column decoding signal wires is the L current potential, all input select signal line DI1(1) to DI8(n) and output selection signal wire DO1(1) to DO8(n) be in quick condition with respect to input data signal line DIN1 to DIN8 and outputting data signals line DOUT1 to DOUT8.

Selector switch 228 and latch group's 226 detailed structure is described with reference to Fig. 7.

Selector switch 228(1) be connected to input select signal line DI1(1), output selects signal wire DO1(1), writing address signal wire BA_W1 to BA_W4, reading address signal line BA_R1 to BA_R4, latch input signal line I(1,1) to I(4,1) and latch output signal line O(1,1) to O(4,1).Identical therewith, selector switch 228(8) be connected to input select signal line DI8(1), output selects signal wire DO8(1), writing address signal wire BA_W1 to BA_W4, reading address signal line BA_R1 to BA_R4, latch input signal line I(1,8) to I(4,8) and latch output signal line O(1,8) to O(4,8).Moreover, selector switch 228(n) be connected to input select signal line DI8(n/8), output selects signal wire DO8(n/8), writing address signal wire BA_W1 to BA_W4, reading address signal line BA_R1 to BA_R4, latch input signal line I(1, n) to I(4, n) and latch output signal line O(1, n) to O(4, n).

Writing address signal wire BA_W1 to BA_W4 is corresponding to selector switch 228(1) to 228(n) in latch input signal line I(1,1) to I(4, n).When the data setting with writing address signal wire BA_W1 is the H current potential, selector switch 228(1) the latch input signal line I(1 in, 1) the latch input signal line I(1, selector switch 228(8), 8) and selector switch 228(n) in latch input signal line I(1, n) be electrically connected to respectively input select signal line DI1(1), input select signal line DI8(1) and input select signal line DI8(n/8).Reading address signal line BA_R1 to BA_R4 is corresponding to selector switch 228(1) to 228(n) in latch output signal line O(1,1) to O(4, n).When the data setting with reading address signal line BA_R1 is the H current potential, selector switch 228(1) the latch output signal line O(1 in, 1) the latch output signal line O(1, selector switch 228(8), 8) and selector switch 228(n) in latch output signal line O(1, n) be electrically connected to respectively output and select signal wire DO1(1), output selects signal wire DO8(1) and output select signal wire DO8(n/8).Only have one to be set as the H current potential in the data of the data of writing address signal wire BA_W1 to BA_W4 and reading address signal line BA_R1 to BA_R4, and no matter the combination of these signal wires as, what a plurality of writing address signal wire and reading address signal line are not set as the H current potential simultaneously.When the data setting with the data of all writing address signal wire BA_W1 to BA_W4 and reading address signal line BA_R1 to BA_R4 is the L current potential, selector switch 228(1) to 228(n) in latch input signal line I(1,1) to I(4, n) and latch output signal line O(1,1) to O(4, n) with respect to input select signal line DI1(1) to DI8(n/8) and output select signal wire DO1(1) to DO8(n/8) be in quick condition.

Latch group 226 quantity equals the columns of storage unit.Latch group 226(1) comprise latch 227(1,1) to latch 227(4,1) four latchs.Latch 227(1,1) to latch 227(4,1) be connected respectively to latch input signal line I(1,1) to I(4,1) and be connected respectively to latch output signal line O(1,1) and to O(4,1).For example, latch input signal line I(1,1) and latch output signal line O(1,1) be connected to latch 227(1,1), and latch input signal line I(4,1) and latch output signal line O(4,1) be connected to latch 227(4,1).

Identical therewith, latch group 226(8) comprise latch 227(1,8) to latch 227(4,8) four latchs.Moreover, latch group 226(n) comprise latch 227(1, n) to latch 227(4, n) and four latchs.

When the data by utilizing writing address signal wire BA_W1 to BA_W4 and the data of column decoding signal wire, latch input signal line I(1,1) to I(4, when n) being electrically connected to input data signal line DIN1 to DIN8, latch 227(1,1) to latch 227(4, n) data of storage input data signal line DIN1 to DIN8.When latch input signal line I(1,1) to I(4, n) when being in quick condition with respect to input data signal line DIN1 to DIN8, latch 227(1,1) to latch 227(4, n) be stored in latch 227(1 before remaining on it, 1) to latch 227(4, n) in data.Latch output signal line O(1,1) to O(4, n) by utilizing latch input signal line I(1,1) to I(4, n) output remains on latch 227(1,1) to latch 227(4, n) and in data.

Particularly, when the integer that with x(x is 1 to n/8) when the column decoding signal wire is set as the H current potential and writing address signal wire BA_W2 is set as the H current potential, input data signal line DIN1 to DIN8 is electrically connected to latch and selects signal wire DI1(x) to DI8(x) and selector switch 228(8x-7) to selector switch 228(8x) in latch input signal line I(2,8x-7) to I(2,8x), and the data of input data signal line DIN1 to DIN8 are stored in latch group 226(8x-7) to 226(8x) in latch 227(2,8x-7) to latch 227(2,8x) in.

Latch output signal line O(1,1) to O(4,1), storer writes control signal wire PWE and analog power pressure-wire V1 to V16 is connected to write circuit 224(1).Write circuit 224(1) is connected to bit line BL(1 by analog switch 223b).

Fig. 8 illustrates an example of write circuit.Write circuit shown in Figure 8 comprises NAND circuit 321, level translator 322 and 4 s' multiplexer 336.In each row, 4

NAND circuit

321 and 4 level translators 322 are set.Storer write control signal wire PWE be connected to NAND circuit 321 each input and the latch output signal line O(1 of latch 227,1) to O(4,1) be connected to the input of NAND circuit 321.Level translator 322 is connected to each output of NAND circuit 321.In addition, level translator 322 is connected to 4 multiplexer 336.4 multiplexer 336 is connected to bit line BL by analog switch 223b.

In write circuit shown in Figure 8, when the data setting that storer is write control signal wire PWE is the L current potential, from the voltage of 4 multiplexers 336 output analog power pressure-wire V1, and with latch output signal line O(1,1) data independence to O(4,1).When the data setting that storer is write control signal wire PWE is the H current potential, according to latch output signal line O(1,1) to O(4,1) data, be converted from the voltage of 4 multiplexers 336 output.In the present embodiment, be in the situation of H current potential at the data setting that storer is write control signal wire PWE, from the following voltage of 4 multiplexers 336 output: when latch output signal line O(1,1) to O(4,1) data when being " 0h ", V1; " 1h ", V2; " 2h ", V3; " 3h ", V4; " 4h ", V5; " 5h ", V6; " 6h ", V7; " 7h ", V8; " 8h ", V9; " 9h ", V10; " Ah ", V11; " Bh ", V12; " Ch ", V13; " Dh ", V14; " Eh ", V15; And " Fh ", V16.

Fig. 9 A illustrates an example of reading circuit.Reading circuit shown in Fig. 9 A comprises load 323, sensor amplifier 324 and NAND circuit 325.Sensor amplifier 324 is connected to an input of NAND circuit 325, and storer read signal line PRE is connected to another input of NAND circuit 325.Sensor amplifier 324 is connected to load 323, and sensor amplifier 324 is connected to bit line BL by analog switch 223a.Latch input signal line I(1,1) to I(4,1) and count signal line COUNT0 to COUNT3 be connected to the output of NAND circuit 325.Note, the situation that the reading circuit shown in Fig. 9 A is connected to the storage unit of first row is shown.

Fig. 9 B1 to Fig. 9 B5 illustrates the concrete example of load 323.Shown in Fig. 9 B1, stabilized power source line VREAD can be connected to the gate terminal of n channel transistor.Shown in Fig. 9 B2, load 323 can be resistor.Shown in Fig. 9 B3, stabilized power source line VREAD can be connected to the gate terminal of p channel transistor.Shown in Fig. 9 B4, load 323 comprises the gate terminal of n channel transistor, and the gate terminal of this n channel transistor is connected in the source terminal of this n channel transistor and the drain terminal.Shown in Fig. 9 B5, load 323 comprises the gate terminal of p channel transistor, and the gate terminal of this p channel transistor is connected in the source terminal of this p channel transistor and the drain terminal.

In the reading circuit shown in Fig. 9 A, sensor amplifier 324 is judged the voltage of the bit line BL of cutting apart to produce by the resistance of load 323 and p channel transistor.When the data setting with storer read signal line PRE is the H current potential, by the output of sensor amplifier 324, count signal line COUNT0 to COUNT3 and latch input signal line I(1,1) to I(4,1) conducting or be in quick condition.When the data setting with storer read signal line PRE is the L current potential, latch input signal line I(1,1) to I(4,1) be in quick condition with respect to count signal line COUNT0 to COUNT3, and irrelevant with the output of sensor amplifier 324.

As shown in Figure 6, analog switch 223a connects reading circuit 225 and storage unit, and analog switch 223b connects write circuit 224 and storage unit.Analog switch 223a and 223b are connected to that the noble potential storer reads control signal wire PREH and counter-rotating noble potential storer reads control signal wire PREHB.Analog switch 223a and 223b read control signal wire PREH by the noble potential storer and counter-rotating noble potential storer reads control signal wire PREHB control.The data that the noble potential storer reads control signal wire PREH are to be the signal that voltage VH obtains by the H potential setting with the data of storer read signal line PRE.The data that counter-rotating noble potential storer reads control signal wire PREHB are the reverse signal that the noble potential storer reads the data of control signal wire PREH.When the data setting that the noble potential storer is read control signal wire PREH is voltage VH, and the noble potential storer that will the reverse data setting that reads control signal wire PREHB is when being the L current potential, and bit line BL is connected to reading circuit 225.When the data setting that the noble potential storer is read control signal wire PREH is the L current potential, and the noble potential storer that will the reverse data setting that reads control signal wire PREHB is when being voltage VH, and bit line BL is connected to write circuit 224.

Storer read signal line PRE and source electrode line SL(1) to SL(n/8) be connected to impact damper shown in Figure 6 230.All source electrode line SL(1) to SL(n/8) the output signal same with the signal of storer read signal line PRE respectively.

Then, with reference to Figure 10 the horizontal drive circuit 203 that is connected to memory cell array 201 is described.

In Figure 10, horizontal drive circuit 203 comprises line decoder 232.In horizontal drive circuit 203, NAND circuit 331, NAND circuit 333, level translator 332, level translator 334 and multiplexer MUX are included in each row of storage unit.Mr individual (2 ^MrBe m) row address line RA, control line CE and column decoding signal wire R_a(1) to R_a(m) be connected to line decoder 232.Column decoding signal wire R_a(1) be connected to an input of NAND circuit 331, and line storage write control signal line PWE_R is connected to another input.Level translator 332 is connected to the output of NAND circuit 331.Level translator 332 is connected to the gate lines G L of storage unit.Column decoding line R_a(1) be connected to an input of NAND circuit 333, and control line CE is connected to another input.Level translator 334 is connected to the output of NAND circuit 333.Multiplexer MUX is connected to level translator 334, variable power supply line VR, pressure-wire VH and electric capacity line CL.

In line decoder 232, when the data setting with control line CE is the H current potential, will be according to the data of row address signal line RA and from m row decoding line R_a(1) to R_a(m) data setting that only has a row decoding line selected is the H current potential.When the data setting with control line CE is the L current potential, be the L current potential with the data setting of all row decoding lines, and with the data independence of row address signal line RA.

Being the H current potential with the data setting of line storage write control signal line PWE_R, will be voltage VH corresponding to the data setting of the gate lines G L in the storage unit of selecteed row decoding line thus.Be the L current potential with the data setting of the gate lines G L in other storage unit.As the data corresponding to the electric capacity line CL in the storage unit of selecteed row decoding line, export the current potential of the data of variable power supply line VR from multiplexer MUX.To the data of the electric capacity line CL in other storage unit, from multiplexer MUX output voltage V H.

Be the L current potential with the data setting of line storage write control signal line PWE_R, the data setting with the gate lines G L in all storage unit is the L current potential thus.As the data corresponding to the electric capacity line CL in the storage unit of selecteed row decoding line, export the current potential of the data of variable power supply line VR from multiplexer MUX.To the data of the electric capacity line CL in other storage unit, from multiplexer MUX output voltage V H.

Figure 11 to Figure 16 illustrates the sequential chart according to a mode of the present invention.Figure 11 illustrates the data from input data signal line DIN1 to DIN8 is stored in n the sequential among the latch group.Figure 12 illustrates and will be stored in n the data among the latch group and be written to the sequential of storage unit.Figure 13 illustrates from the storage unit reading out data and stores data in n the sequential the latch group.Figure 16 illustrates and will be stored in n the data among the latch group and output to the sequential of outputting data signals line DOUT1 to DOUT8.

Figure 11 illustrates the data from input data signal line DIN1 to DIN8 is stored in sequential among the latch group.At first, determine the data of column address conductor CA and the data of input data signal line DIN1 to DIN8, and be the H current potential with the data setting of control line CE.Thus, a column decoding signal wire is selected.In Figure 11, under the prerequisite of the data that write successively column address conductor CA from " 00h ", describe.

Then, be the H current potential with the data setting of writing address signal wire BA_W1, latch (1,1) to the input of latch (1,8) is electrically connected to input data signal line DIN1 to DIN8 thus, and the data of input data signal line DIN1 to DIN8 are written into.When writing data into latch (1,1) to latch (1,8), be the L current potential by the data setting with writing address signal wire BA_W1, and the storage data.

Then, change the data of input data signal line DIN1 to DIN8.Then, be the H current potential with the data setting of writing address signal wire BA_W2, the data of input data signal line DIN1 to DIN8 are written to latch (2,1) to latch (2,8).When writing data into latch (2,1) to latch (2,8), be the L current potential by the data setting with writing address signal wire BA_W2, and the storage data.Same therewith, BA_W4 carries out this operation to the writing address signal wire.

In this operation, when becoming the L current potential, the data of all writing address signal wire BA_W1 to BA_W4 need to change the data of column address conductor CA and the data of input data signal line DIN1 to DIN8, to prevent wrong writing.A series of operation is continued until that the combination of data of the data of all column address conductor CA and writing address signal wire BA_W1 to BA_W4 is selected, and the data of input data signal line DIN1 to DIN8 are stored among all latch groups.

After the data with input data signal line DIN1 to DIN8 are stored among all latch groups, the data that are stored among the latch group are written to storage unit.Figure 12 illustrates and will be stored in data among the latch group and be written to the sequential of storage unit.

At first, in horizontal drive circuit, determine the data of row address signal line RA.Because the data of control line CE become the H current potential in the time of in storing data in the latch group, so a row decoding signal is selected when determining the data of row address signal line RA.In the present embodiment, the data of the row address signal line RA situation for " 00h " is described.Electric capacity line CL(1 corresponding to selecteed row decoding signal wire) data become the L current potential, and the data of the electric capacity line CL in other row become current potential VH.

Then, the data of line storage write control signal line PWE_R become the H current potential, and corresponding to the gate lines G L(1 of selecteed row decoding signal wire) data become current potential VH.

Then, in column drive circuit 202, the data that storer writes control signal wire PWE become the H current potential.The data that storer writes control signal wire PWE become the H current potential, and the voltage that is stored in the analog power pressure-wire V1 to V16 of the data the latch group corresponding to the write circuit from column drive circuit 202 thus is output.At this moment, the analog switch in the column drive circuit 202 reads each output and the bit line BL(1 that control signal wire PREHB is connected to write circuit by utilizing the noble potential storer to read control signal wire PREH and counter-rotating noble potential storer) to BL(n).Thus, with the Voltage-output of analog power pressure-wire V1 to V16 to bit line BL(1) to BL(n).In the present embodiment, the data in being stored in the latch group are " 0h ", the voltage of corresponding V1; " 1h ", V2; " 2h ", V3; " 3h ", V4; " 4h ", V5; " 5h ", V6; " 6h ", V7; " 7h ", V8; " 8h ", V9; " 9h ", V10; " Ah ", V11; " Bh ", V12; " Ch ", V13; " Dh ", V14; " Eh ", V15; And " Fh ", V16.

At this moment, in horizontal drive circuit, will be from each bit line BL(1) to BL(n) voltage of the voltage V1 to V16 of output is written to and is connected with gate lines G L(1) and the FG of floating boom section of storage unit.

Then, the data of line storage write control signal line PWE_R become the L current potential, and gate lines G L(1) data become the L current potential.At this moment, with gate lines G L(1) data of the storage unit that is connected are held.

Then, in column drive circuit, the data that storer writes control signal wire PWE become the L current potential, and the voltage (GND in Figure 12) of analog power pressure-wire V1 is outputed to bit line BL(1) to BL(n).At last, the data of control line CE become the L current potential in horizontal drive circuit, thus electric capacity line CL(1) to CL(m) data become the L current potential.By above-mentioned steps, to the write operation end of storage unit.

Figure 13 illustrates from the storage unit reading out data and stores data in sequential the latch group.

At first, in horizontal drive circuit, determine the data of row address line RA, and be the H current potential with the data setting of control line CE, select thus the row of the storer that reads.In the present embodiment, the data at row address line RA are to describe under the prerequisite of " 00h ".The Voltage-output of the variable voltage line VR that will provide from potential generation circuit at this moment, is to selecteed electric capacity line CL(1) data.The voltage of variable voltage line VR changes according to the data of count signal line COUNT0 to COUNT3.In the case, the data of count signal line COUNT0 to COUNT3 are less, and the voltage of variable voltage line VR is higher.The H current potential is offered the data of other electric capacity lines CL.

Then, in column drive circuit, the data setting that storer is read control signal wire PRE is the H current potential.At this moment, to read the data of control signal wire PREH be to read the signal of the identical sequential of data of control signal wire PRE with storer to the noble potential storer.Device is read in noble potential storage, and to get the H current potential of data of control signal wire PREH higher than the data that storer reads control signal wire PRE.The data that counter-rotating noble potential storer reads control signal wire PREHB are reverse signals that the noble potential storer reads the data of control signal wire PREH.The data of source electrode line SL are to read the signal of control signal wire PRE by the storer that impact damper 230 obtains.

Bit line BL(1) to BL(n) read control signal wire PREHB and be electrically connected to reading circuit by utilizing the noble potential storer to read control signal wire PREH and counter-rotating noble potential storer.Thus, because decision bit line BL(1 is cut apart in the load of reading circuit with the resistance of the p channel transistor in the storage unit) to BL(n) current potential.

Then, according to the data of count signal line COUNT0 to COUNT3, count down to " Fh " from " 0h ".Electric capacity line CL(1) voltage of the variable voltage line VR that changes according to the data of count signal line COUNT0 to COUNT3 of output.As shown in figure 13, the value along with count signal line COUNT0 to COUNT3 increases the lower voltage of variable voltage line VR.

Figure 14 and Figure 15 illustrate the more specific description of read operation.Figure 14 represents reading circuit and storage unit.Figure 15 illustrates the sequential chart of Figure 14.

In Figure 15, as electric capacity line CL(1) potential change the time, the current potential of the FG of floating boom section is owing to capacitive coupling changes.Since the current potential of the FG of floating boom section, the resistance value change between the source electrode of p channel transistor and the drain electrode, and because the load 323 of reading circuit is cut apart the potential change of bit line BL with the resistance of p channel transistor.

The change of the resistance value of the p channel transistor 160 in the storage unit 170, and bit line BL(1) to BL(n) current potential surpass certain value, the output of the sensor amplifier in the reading circuit 324 switches to the L current potential from the H current potential thus.Thus, as shown in figure 15, the output of SA_OUT switches to the L current potential from the H current potential similarly, therefore determines to be stored in the value of the count signal line COUNT0 to COUNT3 among the latch group in the column drive circuit.

According to the storage data, namely remain on the voltage among the FG of floating boom section of each storage unit, bit line BL(1) to BL(n) with electric capacity line CL(1) between relation change.Thus, by data, the electric capacity line CL(1 of count signal line COUNT0 to COUNT3) current potential and bit line BL(1) to BL(n) and current potential corresponding stored unit in the current potential of the FG of floating boom section change, can realize reading of many-valued storage.

Figure 16 illustrates and will be stored in data among the latch group and output to the sequential of outputting data signals line DOUT1 to DOUT8.

Be " 00h " with the data setting of column address conductor CA.So be maintained the H current potential because data are stored in the data of control line CE among the latch group, a column decoding signal wire is selected thus.Then, the data setting with reading address signal line BA_R1 is the H current potential.Therefore, being stored in latch (1,1) to the data communication device in the latch (1,8) crosses the latch output signal line and outputs to outputting data signals line DOUT1 to DOUT8.

Then, after reading address signal line BA_R2 is set as the H current potential, be the H current potential with the data setting of reading address signal line BA_R2, and be stored in latch (2,1) data communication device to the latch (2,8) is crossed the latch output signal line and is outputed to outputting data signals line DOUT1 to DOUT8.Same therewith, reading address signal line BA_R3 and reading address signal line BA_R4 are carried out this operation.

When changing the data of column address conductor CA, be the L current potential with the data setting of all reading address signal line BA_R1 to BA_R4.When reading the data that are stored among the latch group, control successively the data of reading address signal line BA_R1 to BA_R4.

As mentioned above, 2 ⁴The value storer each row in comprise 4 latch section and 4 multiplexer, and in 4 multiplexer from current potential V(1) to V(2 ⁴) select a current potential and export, multi-value data once and at a high speed can be written to thus the storage unit in the delegation, the result shortens the write time.

In addition, 2 ⁴The value storer comprises that the output of 4 counter and 4 s' counter is connected to the input of 4 latch section in each row, can reduce thus the size of reading circuit, therefore can save the area of storage peripheral circuit.

In the present embodiment, illustrate a storage unit is write or reads 4 (16 values (2 from it ⁴Value)) the circuit structure of data is as example, yet a mode of the present invention also can be applied to a storage unit is write or reads K position (2 from it ^KThe circuit structure of data value).Note, can be applied to write or read the circuit structure of the data of 2 values.

2 ^KThe value storer each row in comprise the latch section of K position and the multiplexer of K position, and in the multiplexer of K position from current potential V(1) to V(2 ^K) select a current potential and export, multi-value data once and at a high speed can be written to thus the storage unit in the delegation, the result shortens the write time.

In addition, 2 ^KThe value storer comprises that the output of the counter of the counter of K position and K position is connected to the input of the latch section of the K position in each row, can reduce the size of reading circuit, therefore can save the area of storage peripheral circuit.

Structure shown in the present embodiment and method etc. can be with the structure shown in other embodiments and method etc. suitably make up arbitrarily.

Embodiment 2

In the present embodiment, describe according to the structure of the semiconductor device of a mode of disclosed invention and the manufacture method of this semiconductor device with reference to Figure 17 A and Figure 17 B, Figure 18 A to Figure 18 G, Figure 19 A to Figure 19 E, Figure 20 A to Figure 20 D, Figure 21 A to Figure 21 D and Figure 22 A to Figure 22 C.

The cross section structure of＜semiconductor device and planar structure 〉

Figure 17 A and Figure 17 B illustrate an example of the structure of semiconductor device.Figure 17 A illustrates the cross section of semiconductor device, and Figure 17 B illustrates the plane of semiconductor device.Here, Figure 17 A is corresponding to the cross section along line A1-A2 and the line B1-B2 of Figure 17 B.Semiconductor device shown in Figure 17 A and Figure 17 B comprises the transistor 160 that wherein comprises the first semiconductor material and comprises the transistor 162 that wherein comprises the second semiconductor material on top in the bottom.Here preferably, the first semiconductor material is mutually different with the second semiconductor material.For example, the semiconductor material except oxide semiconductor can be used as the first semiconductor material, and oxide semiconductor can be used as the second semiconductor material.Semiconductor material except oxide semiconductor can be such as silicon, germanium, SiGe, silit, gallium arsenide etc., and single crystal semiconductor preferably.In addition, can use organic semiconducting materials etc.The transistor that comprises this semiconductor material except oxide semiconductor can be easy at full speed operate.On the other hand, the transistor that comprises oxide semiconductor keeps electric charge because of its characteristic between can growing.Semiconductor device shown in Figure 17 A and Figure 17 B can be used as storage unit.

Note, the technical characterictic of disclosed invention is to use in transistor 162 can be in order to the semiconductor material such as oxide semiconductor of abundant reduction off state current, in order to keep data.Therefore, do not need and to be confined to above those that provide such as the material of semiconductor device, actual conditions the structure.

Transistor 160 among Figure 17 A and Figure 17 B comprises: channel formation region 134 is arranged in the semiconductor layer on the Semiconductor substrate 500; Impurity range 132 (being called again source region and drain region) is provided with channel formation region 134 therebetween; Gate insulator 122a is arranged on the channel formation region 134; And gate electrode 128a, be arranged on the gate insulator 122a, so that overlapping with channel formation region 134.Note, for convenience's sake, its source electrode and drain electrode in the accompanying drawings unshowned transistor can be called transistor.In addition, in this case, in the description of transistorized connection, source region and source electrode nominal are made " source electrode ", and drain region and drain electrode nominal are made " drain electrode ".That is to say, in this manual, term " source electrode " can comprise the source region.

In addition, conductive layer 128b is connected to the impurity range 126 in the semiconductor layer that is arranged on the Semiconductor substrate 500.Here, conductive layer 128b is as source electrode or the drain electrode of transistor 160.In addition, impurity range 130 is arranged between impurity range 132 and the impurity range 126.In addition, insulation course 136, insulation course 138 and insulation course 140 are set also, so that covering transistor 160.Note, higher integrated in order to realize, transistor 160 preferably has the not structure of the side wall insulating layer shown in Figure 17 A and Figure 17 B.On the other hand, when paying attention to the characteristic of transistor 160, side wall insulating layer can be arranged on the side of gate electrode 128a, and the impurity range 132 that comprises the zone with different impurities concentration can be set.

Transistor 162 among Figure 17 A and Figure 17 B comprises: oxide semiconductor layer 144, be arranged on insulation course 140 grades, and source electrode (or drain electrode) 142a and drain electrode (or source electrode) 142b is electrically connected to oxide semiconductor layer 144; Gate insulator 146, capping oxide semiconductor layer 144, source electrode 142a and drain electrode 142b; And gate electrode 148a, be arranged on the gate insulator 146, so that overlapping with oxide semiconductor layer 144.

Here, preferably by abundant removal such as hydrogen impurity or oxygen fully is provided, make oxide semiconductor layer 144 highly purified.Specifically, to be less than or equal to be 5 * 10 to the hydrogen concentration of oxide semiconductor layer 144 ¹⁹Atom/cm ³, be preferably lower than or equal 5 * 10 ¹⁸Atom/cm ³, more preferably be less than or equal to 5 * 10 ¹⁷Atom/cm ³Note, the hydrogen concentration of oxide semiconductor layer 144 is measured by secondary ion mass spectrum analytic approach (SIMS).The defect level that comes energy gap highly purified and that wherein cause because of oxygen defect by abundant reduction hydrogen concentration by the oxide semiconductor layer 144 that oxygen fully is provided reduces in, carrier concentration is lower than 1 * 10 ¹²/ cm ³, be preferably lower than 1 * 10 ¹¹/ cm ³, more preferably be lower than 1.45 * 10 ¹⁰/ cm ³For example, to be less than or equal to 100 zA (1 zA (narrow general holder ampere) be 1 * 10 to the off state current under the room temperature (25 ℃) (here for per unit channel width (1 μ m)) ^-21A), be preferably lower than or equal 10 zA.Like this, become the oxide semiconductor of i type (intrinsic) oxide semiconductor or essence i type oxide semiconductor by use, can access the transistor 162 with extremely favourable off state current characteristic.

Note, be processed into island so that the oxide semiconductor layer 144 of the leakage current between the element that suppresses to cause because of miniaturization can adopt the oxide semiconductor layer 144 that is not processed into island although the transistor 162 among Figure 17 A and Figure 17 B comprises.In the situation that oxide semiconductor layer is not processed into island, can prevent the pollution of the oxide semiconductor layer 144 that causes because of the etching in processing.

Capacitor 164 among Figure 17 A and Figure 17 B comprises drain electrode 142b, gate insulator 146 and conductive layer 148b.That is to say, drain electrode 142b is as an electrode of capacitor 164, and conductive layer 148b is as another electrode of capacitor 164.By this structure, can fully guarantee electric capacity.In addition, by stacked oxide semiconductor layer 144 and gate insulator 146, can fully guarantee the insulating property (properties) between drain electrode 142b and the conductive layer 148b.Moreover, in the situation that do not need capacitor, can omit capacitor 164.

In the present embodiment, transistor 162 and capacitor 164 are set, so that overlapping with at least a portion of transistor 160.By adopting this plane figure, can realize high integrated.For example, given minimum feature size is F, and then the shared area of storage unit can be 15F ²To 25F ²

Insulation course 150 is arranged on transistor 162 and the capacitor 164.Wiring 154 is set in the opening that forms in gate insulator 146 and insulation course 150.Wiring 154 is the wirings that connect a storage unit and another storage unit, and corresponding to the bit line BL among Fig. 2.Wiring 154 is connected to impurity range 126 by source electrode 142a and conductive layer 128b.Compare from the structure that source region in the transistor 160 wherein or the source electrode 142a in drain region and the transistor 162 are connected to different wirings, said structure allows the minimizing of wiring quantity.Therefore, the integrated level of semiconductor device can improve.

By conductive layer 128b is set, the position that impurity range 126 is connected with source electrode 142a and source electrode 142a can be overlapped with wiring 154 positions that are connected.By this plane figure, can prevent that the element area from increasing because of the contact region.In other words, the integrated level of semiconductor device can improve.

The manufacture method of＜SOI substrate 〉

Next with reference to Figure 18 A to Figure 18 G example for the manufacture of the manufacture method of the SOI substrate of above-mentioned semiconductor device is described.

At first, prepare Semiconductor substrate 500 (referring to Figure 18 A) for base substrate (base substrate).As Semiconductor substrate 500, can use the Semiconductor substrate such as monocrystalline substrate or monocrystalline germanium substrate.In addition, as Semiconductor substrate, can use solar energy level silicon (SOG-Si) substrate etc.In addition, can use the poly semiconductor substrate.In the situation that use SOG-Si substrate, poly semiconductor substrate etc., and to compare in the situation of using monocrystalline substrate etc., manufacturing cost can reduce.

Note, replace Semiconductor substrate 500, can use the various glass substrate for electronics industry, such as alumina silicate glass, aluminium borosilicate glass and barium borosilicate glass; Quartz substrate; Ceramic substrate; And Sapphire Substrate.In addition, can use wherein silicon nitride and aluminium nitride as its principal ingredient and its thermal expansivity ceramic substrate near the thermal expansivity of silicon.

The surface of Semiconductor substrate 500 is preferably cleaned in advance.Specifically, preferably adopt hydrochloric acid/hydrogen peroxide mixture (HPM), sulfuric acid/hydrogen peroxide mixture (SPM), ammoniacal liquor hydrogen peroxide mixture (APM), dilute hydrofluoric acid (DHF) etc. to come clean semiconductor substrate 500.

Prepare subsequently bonded substrate.Here, single crystal semiconductor substrate 510 is as bonded substrate (referring to Figure 18 B).Note, although its crystallinity be the substrate of monocrystalline here as bonded substrate, the crystallinity of bonded substrate not necessarily is confined to monocrystalline.

For example, as single crystal semiconductor substrate 510, can use and adopt the formed single crystal semiconductor substrate of 14 family's elements, for example monocrystalline substrate, monocrystalline germanium substrate or single-crystal silicon Germanium substrate.In addition, can use the compound semiconductor substrate that adopts gallium arsenide, indium phosphide etc.The typical case of market sale silicon substrate is circular silicon substrate, and its diameter is that 5 inches (125 millimeters), diameters are that 6 inches (150 millimeters), diameters are that 8 inches (200 millimeters), diameters are that 12 inches (300 millimeters) and diameter are 16 inches (400 millimeters).Note, the shape of single crystal semiconductor substrate 510 is not limited to circle, and single crystal semiconductor substrate 510 can be the substrate that has been processed into such as rectangular shape etc.In addition, single crystal semiconductor substrate 510 can (CZ) method or floating region (FZ) method form by vertical pulling (Czochralski).

Oxide film 512 forms (referring to Figure 18 C) on the surface of single crystal semiconductor substrate 510.Consider to remove and pollute, preferably, before forming oxide film 512, adopt the surface of the cleaning single crystal semiconductor substrate 510 such as hydrochloric acid/hydrogen peroxide mixture (HPM), sulfuric acid/hydrogen peroxide mixture (SPM), ammoniacal liquor hydrogen peroxide mixture (APM), dilute hydrofluoric acid (DHF), FPM (mixed solution of hydrofluorite, aquae hydrogenii dioxidi and pure water).Can alternately discharge dilute hydrofluoric acid and Ozone Water cleans.

Oxide film 512 can adopt individual layer or the lamination such as silicon oxide film, oxygen silicon nitride membrane etc. to form.As the method that is used to form oxide film 512, can use thermal oxidation process, CVD method, sputtering method etc.When oxide film 512 formed by the CVD method, silicon oxide film preferably used such as tetraethoxy-silicane (being abbreviated as TEOS) (chemical molecular formula Si (OC ₂H ₅) ₄) and so on organosilane form, make it possible to realize favourable joint.

In the present embodiment, form oxide film 512 (here for SiO by single crystal semiconductor substrate 510 being carried out thermal oxidation _xFilm).Thermal oxidation is preferably carried out in the oxidizing atmosphere of having added halogen.

For example, the thermal oxidation of single crystal semiconductor substrate 510 is carried out in the oxidizing atmosphere of having added chlorine (Cl), can form thus by the oxide film 512 of oxychlorination.In this case, oxide film 512 is the films that comprise the chlorine atom.By this oxychlorination, be hunted down as the heavy metal (for example Fe, Cr, Ni or Mo) of external impurity, and the chloride of metal is formed and then moves to the outside; Therefore, can reduce the pollution of single crystal semiconductor substrate 510.

Note, the halogen atom that comprises in the oxide film 512 is not limited to the chlorine atom.Fluorine atom can be included in the oxide film 512.As the method for the fluorine oxidation on the surface of single crystal semiconductor substrate 510, can use wherein be immersed in single crystal semiconductor substrate 510 in the HF solution and then in oxidizing atmosphere through the method for thermal oxidation, wherein adding NF ₃Oxidizing atmosphere in carry out method of thermal oxidation etc.

Subsequently, ion accelerates by electric field, is irradiated to single crystal semiconductor substrate 510, and is added, and forms the wherein destroyed embrittlement district 514 (referring to Figure 18 D) of crystal structure with predetermined depth thus in single crystal semiconductor substrate 510.

The incident angle etc. that forms kinetic energy, quality, electric charge or ion that the degree of depth in embrittlement district 514 can be by ion is adjusted.Embrittlement district 514 is in the degree of depth formation roughly the same with the average depth of penetration of ion.The thickness of the single-crystal semiconductor layer that therefore, separates from single crystal semiconductor substrate 510 can adopt the degree of depth of adding the ion place to adjust.For example, average depth of penetration can be controlled to so that the thickness of single-crystal semiconductor layer is approximately 10 nm to 500 nm, is preferably 50 nm to 200 nm.

Can adopt ion doping equipment or ion implantation device to carry out ion exposure processes.As the typical case of ion doping equipment, there is non-mass separation type equipment, wherein carry out the plasma excitation of process gas, and all ionic speciess that pass through to generate come irradiation object.In this equipment, object adopts the ionic species of the plasma that does not have mass separation to shine.On the contrary, ion implantation device is mass separation equipment.In ion implantation device, carry out the mass separation of the ionic species of plasma, and adopt the ionic species with predetermined quality to come irradiation object.

In the present embodiment, the example that ion doping equipment wherein is used for hydrogen is added single crystal semiconductor substrate 510 is described.Comprise the gas of hydrogen as source gas.For the ion that is used for irradiation, H ₃ ⁺Ratio preferably be set as height.Specifically, preferably, H ₃ ⁺Ratio with respect to H ⁺, H ₂ ⁺And H ₃ ⁺Total amount be set as and be greater than or equal to 50% (more preferably being greater than or equal to 80%).Pass through H ₃ ⁺At high proportion, the efficient of ion exposure can improve.

Note, ion to be added is not limited to hydrogen ion.Can add helium ion etc.In addition, ion to be added is not limited to a kind of ion, but can add different kinds of ions.For example, in the situation that adopt simultaneously hydrogen and helium to shine with ion doping equipment, with adopt hydrogen to compare with the situation that helium shines by different step, can reduce step number, and the surfaceness of the single-crystal semiconductor layer that can suppress to form after a while.

Note, when adopting ion doping equipment to form embrittlement district 514, also can add heavy metal; But ion exposure is undertaken by the oxide film 512 that comprises halogen atom, can prevent thus the pollution of the single crystal semiconductor substrate 510 that causes because of heavy metal.

Then, Semiconductor substrate 500 and single crystal semiconductor substrate 510 are arranged to toward each other, and make in its situation that oxide film 512 is arranged betwixt mutually closely attached.Therefore, Semiconductor substrate 500 and single crystal semiconductor substrate 510 be bonded with each other (referring to Figure 18 E).Note, oxide film or nitride film can form on the surface of the single crystal semiconductor substrate 510 that engages with Semiconductor substrate 500.

When engaging, preferably, will be more than or equal to 0.001 N/cm ²But be less than or equal to 100 N/cm ²Pressure, for example more than or equal to 1 N/cm ²But be less than or equal to 20 N/cm ²Pressure be applied to part of Semiconductor substrate 500 or a part of single crystal semiconductor substrate 510.Make composition surface mutually near and when exerting pressure to be arranged to mutual close contact, the part that being bonded between Semiconductor substrate 500 and the oxide film 512 carried out close contact generates, and joint expands to almost whole area naturally.Carry out under this effect that is bonded on Van der Waals for or Hydrogenbond, and can at room temperature carry out.

Note, before single crystal semiconductor substrate 510 and Semiconductor substrate 500 were bonded with each other, surface treatment was preferably passed through on the surface that will be bonded with each other.Surface treatment can improve the bond strength at the interface between single crystal semiconductor substrate 510 and the Semiconductor substrate 500.

As surface treatment, can use the combination of wet processed, dry process or wet processed and dry process.In addition, wet processed can be used from different wet type treatment combinations, and perhaps dry process can be used from different dry type treatment combinations.

Note, the thermal treatment that is used for the raising bond strength can be carried out after engaging.This thermal treatment is carried out under the temperature of the separation that 514 places, embrittlement district do not occur (for example, be greater than or equal to room temperature but be lower than 400 ℃ temperature).In addition, the joint of Semiconductor substrate 500 and oxide film 512 can carry out in to its heating with the temperature within this scope.Thermal treatment can use diffusion furnace, the heating furnace such as resistance-heated furnace, rapid thermal annealing (RTA) equipment, microwave heating equipment etc. to carry out.Note, the said temperature condition is an example, and a mode of disclosed invention is not appreciated that and is confined to this example.

Subsequently, heat-treat, in order to distinguish from single crystal semiconductor substrate 510 in embrittlement, single-crystal semiconductor layer 516 forms in Semiconductor substrate 500 thus, and oxide film 512 (Figure 18 F) is set therebetween.

Note, the heat treated temperature in wishing to separate is low as far as possible.This is because when the temperature in separating is low, can suppress the generation of roughness on the surface of single-crystal semiconductor layer 516.Specifically, the heat treated temperature in the separation can be greater than or equal to 300 ℃ but be less than or equal to 600 ℃, and thermal treatment is more effective when temperature is less than or equal to 500 ℃ (being greater than or equal to 400 ℃).

Note, after separating single crystal semiconductor substrate 510, single-crystal semiconductor layer 516 can pass through in the thermal treatment that is greater than or equal to 500 ℃ temperature, so that the concentration of remaining hydrogen is reduced in the single-crystal semiconductor layer 516.

Subsequently, adopt laser to shine the surface of single-crystal semiconductor layer 516, form thus that its surface planarity is improved and the single-crystal semiconductor layer 518 (referring to Figure 18 G) that is reduced of defective wherein.Note, replace Ear Mucosa Treated by He Ne Laser Irradiation to process, can heat-treat.

Although in the present embodiment, the treatment with irradiation of employing laser is right after for separating of the thermal treatment of single-crystal semiconductor layer 516 carries out afterwards, and a mode of the present invention is not appreciated that and is confined to this.After for the thermal treatment of cutting apart single-crystal semiconductor layer 516, carry out comprising for the surface of removing single-crystal semiconductor layer 516 etch processes in the zone of many defectives, then can carry out Ear Mucosa Treated by He Ne Laser Irradiation and process.In addition, Ear Mucosa Treated by He Ne Laser Irradiation carries out after processing and can being improved at the surface planarity of single-crystal semiconductor layer 516.Note, etch processes can be Wet-type etching or dry-etching.In addition, in the present embodiment, after the irradiation of adopting as mentioned above laser, can reduce the step of the thickness of single-crystal semiconductor layer 516.In order to reduce the thickness of single-crystal semiconductor layer 516, can adopt any or both of dry-etching and Wet-type etching.

By above-mentioned steps, can access the SOI substrate (referring to Figure 18 G) that comprises the single-crystal semiconductor layer 518 with advantageous feature.

The manufacture method of＜semiconductor device 〉

Next with reference to Figure 19 A to Figure 19 E, Figure 20 A to Figure 20 D, Figure 21 A to Figure 21 D and Figure 22 A to Figure 22 C the method for making the semiconductor device that uses above-mentioned SOI substrate is described.

Transistorized manufacture method in the＜bottom 〉

At first with reference to Figure 19 A to Figure 19 E and Figure 20 A to Figure 20 D method for the manufacture of the transistor 160 in the bottom is described.Note, Figure 19 A to Figure 19 E and Figure 20 A to Figure 20 D illustrate the part by the formed SOI substrate of method shown in Figure 18 A to Figure 18 G, and are the transistorized cross section artworks that illustrates in the bottom shown in Figure 17 A.

At first, single-crystal semiconductor layer 518 is patterned into island, so that form semiconductor layer 120 (referring to Figure 19 A).Note, before or after this step, can add semiconductor layer with giving the conductive impurity element of N-shaped or giving the conductive impurity element of p-type, in order to control transistorized threshold voltage.As in the semi-conductive situation, phosphorus, arsenic etc. can be as giving N-shaped conductive impurity element at silicon.On the other hand, boron, aluminium, gallium etc. can be as giving p-type conductive impurity element.

Subsequently, insulation course 122 forms so that cover semiconductor layer 120 (referring to Figure 19 B).Insulation course 122 will be gate insulator after a while.For example, can by the surface of semiconductor layer 120 being heat-treated (thermal oxidation, hot nitrogen treatment etc.), form insulation course 122.Can replace thermal treatment to use high-density plasma to process.For example, can carry out high-density plasma with any mixed gas of rare gas such as He, Ar, Kr or Xe and oxygen, nitrogen oxide, ammonia, nitrogen or hydrogen processes.Much less, can pass through CVD method, sputtering method etc., form insulation course.Insulation course 122 preferably has the monox of comprising, silicon oxynitride, silicon nitride, hafnia, aluminium oxide, tantalum oxide, yttria, hafnium silicate (HfSi _xO _y(x＞0, y＞0)), added the hafnium silicate (HfSi of nitrogen _xO _y(x＞0, y＞0)), added the hafnium (HfAl of nitrogen _xO _y(x＞0, y＞0)) etc. any single layer structure or stepped construction.The thickness of insulation course 122 for example can be more than or equal to 1 nm but is less than or equal to 100 nm, is preferably more than or equals 10 nm but be less than or equal to 50 nm.The monolayer insulating layer that comprises monox here, forms by the plasma CVD method.

Subsequently, mask 124 forms at insulation course 122, and will give a kind of impurity element adding semiconductor layer 120 of conduction type, so that form impurity range 126 (referring to Figure 19 C).Note,, after adding impurity element, remove mask 124 here.

Subsequently, mask forms at insulation course 122, and partly removes the zone with the overlapping insulation course 122 of impurity range 126, so that form gate insulator 122a (referring to Figure 19 D).The part of insulation course 122 can be removed by the etching such as Wet-type etching or dry-etching.

Subsequently, the conductive layer that is used to form gate electrode (comprise and use the layer formed wiring identical with gate electrode) forms and the process processing at gate insulator 122a, so that form gate electrode 128a and conductive layer 128b (referring to Figure 19 E).

The conductive layer that is used for gate electrode 128a and conductive layer 128b can use the metal material such as aluminium, copper, titanium, tantalum or tungsten to form.The layer that comprises conductive material can use the semiconductor material such as polysilicon to form.The method that is used to form the layer that comprises conductive material is not specifically limited, and can adopts various film formation methods such as evaporation coating method, CVD method, sputtering method, spin coating method.Conductive layer can be processed by carrying out etching with Etching mask.

Subsequently, add semiconductor layer by using gate electrode 128a and conductive layer 128b as the impurity element that mask will give a kind of conduction type, so that form channel formation region 134, impurity range 132 and impurity range 130 (referring to Figure 20 A)., add the impurity element such as boron (B) here, in order to form the p channel transistor.In the situation that form the n channel transistor, for example add the impurity element such as phosphorus (P) or arsenic (As).Here, the concentration of impurity element to be added can suitably be set.In addition, after adding impurity element, carry out the thermal treatment for activation.Here, the concentration in the impurity range increases according to following order: impurity range 126, impurity range 132 and impurity range 130.

Subsequently, insulation course 136, insulation course 138 and insulation course 140 form so that cover gate insulation course 122a, gate electrode 128a and conductive layer 128b (referring to Figure 20 B).

Insulation course 136, insulation course 138 and insulation course 140 can form with the material that comprises the inorganic insulating material such as monox, silicon oxynitride, silicon oxynitride, silicon nitride or aluminium oxide.Insulation course 136, insulation course 138 and insulation course 140 particularly preferably use low-k (low-k) material to form because since the electric capacity that overlapped electrodes or wiring cause can fully reduce.Note, insulation course 136, insulation course 138 and insulation course 140 can be any the formed porous dielectric layers that uses these materials.Because porous dielectric layer is compared with intensive insulation course and is had low-k, so the electric capacity that causes because of electrode or wiring can further reduce.In addition, insulation course 136, insulation course 138 and insulation course 140 can use the organic insulation such as polyimide or acrylic acid to form.In the present embodiment, the situation that silicon oxynitride will be used for insulation course 136, silicon oxynitride is used for insulation course 138 and monox is used for insulation course 140 is described.Adopt the stepped construction of insulation course 136, insulation course 138 and insulation course 140 here; But a mode of disclosed invention is not limited to this.Also can use single layer structure, two-layer stepped construction or four layers or more multi-layered stepped construction.

Subsequently, insulation course 138 and insulation course 140 are processed or etch processes through chemically mechanical polishing (CMP), so that insulation course 138 and insulation course 140 flatten (referring to Figure 20 C).Here, carry out CMP and process, until part is exposed insulation course 138.When silicon oxynitride is used for insulation course 138 and monox when being used for insulation course 140, insulation course 138 stops thing as etching.

Subsequently, insulation course 138 and insulation course 140 are processed or etch processes through CMP, so that expose the upper surface (referring to Figure 20 D) of gate electrode 128a and conductive layer 128b., carry out etching here, until part is exposed gate electrode 128a and conductive layer 128b.For etch processes, preferably carry out dry-etching, but can carry out Wet-type etching.Expose in the step of gate electrode 128a and conductive layer 128b in part, in order to improve the characteristic of the transistor 162 that forms after a while, the surface of insulation course 136, insulation course 138 and insulation course 140 is flattened.

By above-mentioned steps, can form the transistor 160 (referring to Figure 20 D) in the bottom.

Note, before or after above-mentioned steps, can be used to form the step of supplemantary electrode, wiring, semiconductor layer or insulation course.For example, wherein the Miltilayer wiring structure of stacked insulation course and conductive layer makes it possible to provide the high-integrated semiconductor device as wire structures.

Transistorized manufacture method in the＜top 〉

Next with reference to Figure 21 A to Figure 21 D and Figure 22 A to Figure 22 C method for the manufacture of the transistor 162 in the top is described.

At first, oxide semiconductor layer forms at gate electrode 128a, conductive layer 128b, insulation course 136, insulation course 138, insulation course 140 etc., and through processing, so that form oxide semiconductor layer 144 (referring to Figure 21 A).Note, before forming oxide semiconductor layer, can be in insulation course 136, insulation course 138 and insulation course 140 formation as the insulation course of substrate (base).Insulation course can form by the PVD method such as sputtering method or the CVD method such as the plasma CVD method.

Oxide semiconductor to be used preferably comprises indium (In) or zinc (Zn) at least.Specifically, preferably comprise In and Zn.Stabilizing agent as for reducing the deviation of the transistorized electrical specification of using oxide semiconductor preferably also comprises gallium (Ga).Preferably comprise tin (Sn) as stabilizing agent.Preferably comprise hafnium (Hf) as stabilizing agent.Preferably comprise aluminium (Al) as stabilizing agent.

As another kind of stabilizing agent, can comprise one or more lanthanide series such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb) or lutetium (Lu).

Material as being used for oxide semiconductor layer can use following material: quaternary metallic oxide such as In-Sn-Ga-Zn-O class material, In-Hf-Ga-Zn-O class material, In-Al-Ga-Zn-O class material, In-Sn-Al-Zn-O class material, In-Sn-Hf-Zn-O class material, In-Hf-Al-Zn-O class material; Ternary metal oxide is such as In-Ga-Zn-O class material, In-Sn-Zn-O class material, In-Al-Zn-O class material, Sn-Ga-Zn-O class material, Al-Ga-Zn-O class material, Sn-Al-Zn-O class material, In-Hf-Zn-O class material, In-La-Zn-O class material, In-Ce-Zn-O class material, In-Pr-Zn-O class material, In-Nd-Zn-O class material, In-Sm-Zn-O class material, In-Eu-Zn-O class material, In-Gd-Zn-O class material, In-Tb-Zn-O class material, In-Dy-Zn-O class material, In-Ho-Zn-O class material, In-Er-Zn-O class material, In-Tm-Zn-O class material, In-Yb-Zn-O class material, In-Lu-Zn-O class material; Binary metal oxide such as In-Zn-O class material, Sn-Zn-O class material, Al-Zn-O class material, Zn-Mg-O class material, Sn-Mg-O class material, In-Mg-O class material, In-Ga-O class material; In-O class material; Sn-O class material; Zn-O class material; Deng.In addition, above-mentioned material can comprise SiO ₂Here, for example, In-Ga-Zn-O class material means the oxidation film that contains indium (In), gallium (Ga), zinc (Zn), and its ratio of components is not specifically limited.In addition, In-Ga-Zn-O class material can comprise In, Ga and Zn element in addition.

In addition, as oxide semiconductor, can use by Formula I nMO ₃(ZnO) _m(m＞0) expressed material.Here, M represents from the selected a kind of metallic element of Ga, Al, Fe, Mn and Co or Determination of multiple metal elements.For example, M can be Ga, Ga and Al, Ga and Mn, Ga and Co etc.In addition, as oxide semiconductor, can use by Formula I n ₃SnO ₅(ZnO) _n(n＞0, n is integer) expressed material.

For example, can use atomic ratio In:Ga:Zn=1:1:1 (=1/3:1/3:1/3) or In:Ga:Zn=2:2:1 (=2/5:2/5:1/5) In-Ga-Zn-O class material or its composition are in any of the oxide above-mentioned composition near.In addition, can use atomic ratio In:Sn:Zn=1:1:1 (=1/3:1/3:1/3), In:Sn:Zn=2:1:3 (=1/3:1/6:1/2) or In:Sn:Zn=2:1:5 (=1/4:1/8:5/8) In-Sn-Zn-O class material or its composition are in any of the oxide above-mentioned composition near.

But a mode of the present invention is not limited to this, can use the material with suitable composition according to required characteristic of semiconductor (for example mobility, threshold voltage and deviation).In addition, in order to obtain required characteristic of semiconductor, preferred, the atomic ratio of carrier density, impurity concentration, defect concentration, metallic element and oxygen, interatomic disance, density etc. are arranged to appropriate value.

For example, in the situation that use In-Sn-Zn-O class material can become more readily available high mobility.But, even in the situation that also can increase mobility by defect concentration in the reduction block with In-Ga-Zn-O class material.

Note, for example, express " composition that comprises the oxide of In, Ga and Zn with atomic ratio In:Ga:Zn=a:b:c (a+b+c=1) is in atomic ratio In:Ga:Zn=A:B:C (A+B+C=1) and comprises near the oxide of In, Ga and Zn " and represent that a, b and c satisfy following relationship: (a-A) ²+ (b-B) ²+ (c-C) ²≤ r ², and for example, r can be 0.05.Same situation is applicable to other oxide.

Oxide semiconductor can be monocrystalline or on-monocrystalline.Under latter event, oxide semiconductor can be amorphous or polycrystalline.In addition, oxide semiconductor can have non crystalline structure or amorphous (non-amorphous) structure that comprises the part with crystallinity.

In amorphous oxide semiconductor, flat surfaces can become more readily available so that when transistor when making with oxide semiconductor, interface scattering can reduce, and higher mobility can become more readily available.

In having the oxide semiconductor of crystallinity, defective can further reduce in the block, and when surface flatness is improved, can access the mobility higher than amorphous oxide semiconductor layer.In order to improve surface flatness, oxide semiconductor preferably forms at flat surfaces.Specifically, oxide semiconductor can be less than or equal to 1 nm at average surface roughness (Ra), preferably is less than or equal to 0.3 nm, the surface that more preferably is less than or equal to 0.1 nm forms.

Note, Ra expands to obtain by the three-dimensional by the center line average roughness of JIS B0601 definition, in order to be applied to the plane.Ra can be expressed as " mean value of the absolute value of the deviation on the surface from the reference surface to the appointment ", and is defined by following formula.

[formula 1]

In following formula, S ₀Represent that the area on plane to be measured is (by coordinate (x ₁, y ₁), (x ₁, y ₂), (x ₂, y ₁) and (x ₂, y ₂) four represented rectangle regions that point defines), and Z ₀The average height that represents plane to be measured.Ra can adopt atomic force microscope (AFM) to measure.

The thickness of oxide semiconductor layer is preferably more than or equal to 3 nm but is less than or equal to 30 nm.This is because transistor may normal conducting when oxide semiconductor layer blocked up (for example thickness is more than or equal to 50 nm).

Oxide semiconductor layer preferably forms by the method that the impurity such as hydrogen, water, hydroxyl or hydride wherein is difficult for entering oxide semiconductor layer.For example, can use sputtering method etc.

As In-Ga-Zn-O class target, for example can use ratio of components to be In ₂O ₃: Ga ₂O ₃: the ZnO=1:1:1[mol ratio] target.Note, do not need target material and ratio of components are confined to the above.For example, can use ratio of components to be In ₂O ₃: Ga ₂O ₃: the ZnO=1:1:2[mol ratio] target.

As the target of In-Zn-O class material, use the target of following ratio of components: ratio of components is In:Zn=50:1 to 1:2 (In in the mol ratio in the atomic ratio ₂O ₃: ZnO=25:1 to 1:4), be preferably 20:1 to 1:1 (In in the mol ratio in the atomic ratio ₂O ₃: ZnO=10:1 to 1:2), more preferably be 15:1 to 1.5:1 (In in the mol ratio in the atomic ratio ₂O ₃: ZnO=15:2 to 3:4).For example, when being used to form the semi-conductive target of In-Zn-O type oxide and having that ratio of components is In:Zn:O=X:Y:Z in the atomic ratio, satisfy and concern Z＞1.5X+Y.

In addition, In-Sn-Zn-O class material also can be called ITZO, and uses and have that ratio of components is the oxide target of In:Sn:Zn=1:2:2, In:Sn:Zn=2:1:3, In:Sn:Zn=1:1:1, In:Sn:Zn=20:45:35 etc. in the atomic ratio.

The relative density of oxide target is greater than or equal to 90% but be less than or equal to 100%, is preferably to be greater than or equal to 95% but be less than or equal to 99.9%.This is the target that has high relative density because of by use, and formed oxide semiconductor layer can be fine and close film.

It can be the mixed atmosphere of rare gas (being generally argon) atmosphere, oxygen atmosphere or rare gas and oxygen that film forms atmosphere.Be preferred from the atmosphere of the high-pure gas of wherein having removed the impurity such as hydrogen, water, hydroxyl or hydride, think to prevent that hydrogen, water, hydroxyl, hydride etc. from entering oxide semiconductor layer.

In the present embodiment, use In-Ga-Zn-O type oxide target to form oxide semiconductor layer by sputtering method.

At first, substrate placed remain on the film formation chamber that reduces under the pressure, and to substrate heating, so that reaching, underlayer temperature is higher than 200 ℃ but be less than or equal to 500 ℃, preferably be higher than 300 ℃ but be less than or equal to 500 ℃, more preferably be greater than or equal to 350 ℃ but be less than or equal to 450 ℃ temperature.

Then, the high-pure gas of wherein fully having removed the impurity such as hydrogen, water, hydroxyl or hydride is introduced from wherein removing the film formation chamber of residual moisture, and oxide semiconductor layer is by using target to form at substrate.In order to remove moisture residual in the film formation chamber, desirably use the entrapment vacuum pump such as cryopump, ionic pump or titanium sublimation pump.In addition, rejected unit can be the turbopump that is provided with cold-trap.In adopting the emptying film formation chamber of cryopump, for example, impurity removal such as hydrogen, water, hydroxyl or the hydride (compound that preferably comprises in addition carbon atom) can reduce the concentration of the impurity such as hydrogen, water, hydroxyl or hydride in the oxide semiconductor layer that forms in the film formation chamber thus.

In the situation that underlayer temperature low (for example 100 ℃ or lower) between depositional stage, the material that comprises hydrogen atom might enter oxide semiconductor; Therefore, preferably with the temperature within the above-mentioned scope substrate is heated.When forming when oxide semiconductor layer in the situation that with this temperature heated substrate, underlayer temperature increases, so that hydrogen bond cut off by heat, and the material that comprises hydrogen atom unlikely enters oxide semiconductor layer.Therefore, oxide semiconductor layer is in the situation that form with the said temperature heated substrate, and the concentration of the impurity such as hydrogen, water, hydroxyl or hydride can fully reduce in the oxide semiconductor layer thus.In addition, the damage that causes because of sputter can reduce.

An example as the film formation condition, adopt following condition: the distance between substrate and the target is 60 mm, and pressure is 0.4 Pa, and direct current (DC) power supply is 0.5 kW, underlayer temperature is 400 ℃, and film formation atmosphere is oxygen atmosphere (ratio of oxygen flow rate is 100%).Note, pulse dc power is preferred, because can reduce the flour (being called again particle or dust) that film forms middle generation, and film thickness can be uniform.

Note, before forming oxide semiconductor layer by sputtering method, preferably by wherein introducing the reverse sputtering of argon gas and generation plasma, remove the flour (being called again particle or dust) on the formation surface that invests oxide semiconductor layer.Thereby reverse sputtering refers to and a kind ofly voltage is applied to substrate side in order to generate the method that plasma is revised the surface near substrate.Note, the gases such as nitrogen, helium, oxygen can be used to replace argon.

Can by after oxide semiconductor layer forms, carrying out etching when the mask with anticipated shape, process oxide semiconductor layer.Mask can form by the method such as photoetching or ink ejecting method.The etching of oxide semiconductor layer can be dry-etching or Wet-type etching.Much less, use capable of being combined they both.

After this, can heat-treat to oxide semiconductor layer 144 (the first thermal treatment).The material that comprises hydrogen atom in the oxide semiconductor layer 144 is further removed in thermal treatment; Therefore can improve the structure of oxide semiconductor layer 144 and can reduce defect level in the energy gap.Under inert gas atmosphere to be greater than or equal to 250 ℃ but be less than or equal to 700 ℃, preferably be greater than or equal to 450 ℃ but be less than or equal to 600 ℃ or the temperature that is lower than the strain point of substrate and heat-treat.Inert gas atmosphere preferably comprises nitrogen or rare gas (such as helium, neon or argon) as its principal ingredient but does not comprise the atmosphere of water, hydrogen etc.For example, nitrogen in the introducing heat treating equipment or the purity of the rare gas such as helium, neon or argon are greater than or equal to 6 N (99.9999%), preferably are greater than or equal to 7 N (99.99999%) (namely, impurity concentration is less than or equal to 1 ppm, is preferably lower than or equals 0.1 ppm).

Thermal treatment can be carried out in the following manner: for example, object introduce is used the electric furnace of stratie etc., and under blanket of nitrogen with 450 ℃ of heating one hour.Oxide semiconductor layer 144 during heating treatment is not exposed to air, makes it possible to entering of anti-sealing and hydrogen.

Above-mentioned thermal treatment has the effect of removing hydrogen, water etc., and can be called processed, dehydrogenation processing etc.Thermal treatment can be carried out on following opportunity, for example before oxide semiconductor layer is processed into island or after forming gate insulator.This processed or dehydrogenation are processed can carry out one or many.

Subsequently, the conductive layer (being included in the wiring that forms in the layer identical with drain electrode with the source electrode) that is used to form source electrode and drain electrode forms and the process processing at oxide semiconductor layer 144, so that form source electrode 142a and drain electrode 142b (referring to Figure 21 B).

Conductive layer can form by PVD method or CVD method.As the material that is used for conductive layer, can use the element from aluminium, chromium, copper, tantalum, titanium, molybdenum and tungsten, chosen, comprise any these elements as the alloy of composition etc.In addition, can use one or more materials of from manganese, magnesium, zirconium, beryllium, neodymium and scandium, choosing.

Conductive layer can have single layer structure or comprise two-layer or more multi-layered stepped construction.For example, conductive layer can have titanium film or titanium nitride film single layer structure, comprise the single layer structure of the aluminium film of silicon, wherein titanium film be layered in double-layer structure on the aluminium film, wherein titanium film be layered on the titanium nitride film double-layer structure or wherein titanium film, aluminium film and titanium film according to the three-decker of this sequential cascade.Note, the advantage of conductive layer with single layer structure of titanium film or titanium nitride film is, it can be easy to be processed into have ramp shaped source electrode 142a and the drain electrode 142b of (tpaered shape).

In addition, conductive layer can form with conducting metal oxide.As conducting metal oxide, can use indium oxide (In ₂O ₃), tin oxide (SnO ₂), zinc paste (ZnO), indium oxide-tin oxide alloy (In ₂O ₃-SnO ₂, sometimes be abbreviated as ITO), indium oxide-oxide zinc-oxide alloy (In ₂O ₃-ZnO) or wherein comprise any these metal oxide materials of silicon or monox.

Conductive layer preferably is etched into so that source electrode 142a and the drain electrode 142b that will form have the slope shape end.Here, the oblique angle for example is preferably more than or equals 30 ° but be less than or equal to 60 °.Carry out etching, so that the end of source electrode 142a and drain electrode 142b becomes slope shape, can improve thus the covering by the gate insulator 146 that forms after a while, and can prevent from disconnecting.

Distance between transistorized channel length (L) in the top is divided by the lower edge portion of source electrode 142a and drain electrode 142b is determined.Note, for being used to form in the exposure that forms the mask that uses in the transistorized situation of channel length (L) less than 25 nm, preferably use its wavelength to be as short as several nanometers to the extreme ultraviolet line of tens nanometer.In passing through the exposure of extreme ultraviolet, resolution is high, and depth of focus is large.Owing to these reasons, the transistorized channel length (L) that will form after a while can be in more than or equal to 10 nm but be less than or equal within the scope of 1000 nm (1 μ m), and circuit can operate at a relatively high speed.In addition, miniaturization can realize the low power consumption of semiconductor device.

As from Figure 21 B in a different example, the oxide conducting layer can be used as the source region and the drain region is arranging between oxide semiconductor layer 144 and the source electrode and between oxide semiconductor layer 144 and the drain electrode.

For example, can by forming oxide conductive film at oxide semiconductor layer 144, forming conductive layer and in same lithography step, process oxide conductive film and conductive layer at oxide conductive film, form oxide conducting layer, source electrode 142a and drain electrode 142b as source region and drain region.

In addition, form the lamination of oxide semiconductor film and oxide conductive film, and in same lithography step, process the shape of the lamination of oxide semiconductor film and oxide conductive film, so that form oxide semiconductor layer 144 and the oxide conductive film of island.After forming source electrode 142a and drain electrode 142b, come etching island oxide conductive film with source electrode 142a and drain electrode 142b as mask, make it possible to form the oxide conducting layer as source region and drain region.

Note, when the etching carried out for the treatment of the shape of oxide conducting layer, suitably adjust etching condition (for example concentration of the type of etchant, etchant and etching period), in order to prevent the over etching of oxide semiconductor layer.

The material of oxide conducting layer preferably comprises zinc paste as composition, and does not preferably comprise indium oxide.For this oxide conducting layer, can use zinc paste, zinc oxide aluminum, nitrogen zinc oxide aluminum, zinc-gallium oxide etc.

When the oxide conducting layer arranged between oxide semiconductor layer and source and drain electrode, source region and drain region can have than low resistance, and transistor can high speed operation.

By the structure of oxide semiconductor layer 144, oxide conducting layer and use metal material formed source electrode and drain electrode, transistorized withstand voltage can further improve.

For the frequency characteristic that improves peripheral circuit (driving circuit) is used for the source region with the oxide conducting layer and the drain region is effective.This is can reduce contact resistance because metal electrode (for example molybdenum or tungsten) and oxide semiconductor layer contact to contact to compare with the oxide conducting layer with metal electrode (for example molybdenum or tungsten).Can reduce contact resistance by the oxide conducting layer is inserted between oxide semiconductor layer and source and the drain electrode; Therefore, the frequency characteristic of peripheral circuit (driving circuit) can be improved.

Subsequently, gate insulator 146 forms so that cover source electrode 142a and drain electrode 142b, and contacts (referring to Figure 21 C) with the part of oxide semiconductor layer 144.

Can pass through CVD method, sputtering method etc., form gate insulator 146.In addition, gate insulator 146 preferably forms so that comprise monox, silicon nitride, silicon oxynitride, gallium oxide, aluminium oxide, tantalum oxide, hafnia, yttria, hafnium silicate (HfSi _xO _y(x＞0, y＞0)), added the hafnium silicate (HfSi of nitrogen _xO _y(x＞0, y＞0)), added the hafnium (HfAl of nitrogen _xO _y(x＞0, y＞0)) etc.Gate insulator 146 can have single layer structure or wherein in conjunction with the stepped construction of these elements.Thickness is not specifically limited; But in the situation that make the semiconductor device miniaturization, preferably thickness is little, in order to guarantee transistorized operation.For example, in the situation that use monox, thickness can be set as more than or equal to 1 nm but be less than or equal to 100 nm, is preferably more than or equals 10 nm but be less than or equal to 50 nm.

When gate insulator is thinner as mentioned above, cause the gate leakage problem that causes because of tunnel effect etc.In order to solve gate leakage problem, such as hafnia, tantalum oxide, yttria, hafnium silicate (HfSi _xO _y(x＞0, y＞0)), added the hafnium silicate (HfSi of nitrogen _xO _y(x＞0, y＞0)) or added the hafnium (HfAl of nitrogen _xO _y(x＞0, y＞0)) and so on high-k (high-k) material be preferably used for gate insulator 146.Be used for gate insulator 146 by the high-k material and might guarantee electrical specification, and increase thickness, so that sup.G leaks.Note, can adopt the film that comprises the high-k material and comprise any stepped construction of film of monox, silicon nitride, silicon oxynitride, silicon oxynitride, aluminium oxide etc.

In addition, the insulation course (in the present embodiment, gate insulator 146) that is contacted with oxide semiconductor layer 144 can use the insulating material that comprises 13 family's elements and oxygen to form.More oxide semiconductor material comprises 13 family's elements, and the collocation that comprises the insulating material of 13 family's elements and oxide semiconductor is good.Therefore be used for the insulation course that contacts with oxide semiconductor layer when the insulating material that will comprise 13 family's elements, can keep and oxide semiconductor layer between the good state at interface.

The insulating material that comprises 13 family's elements here, refers to the insulating material of one or more elements that comprise 13 families.As the insulating material that comprises 13 family's elements, enumerate gallium oxide, aluminium oxide, oxidation gallium aluminium, gallium oxide aluminium etc.Here, the oxidation gallium aluminium refers to the amount material larger than gallium of aluminium in the atomic percent wherein, and gallium oxide aluminium refers to the amount of gallium in the atomic percent wherein more than or equal to the material of the amount of aluminium.

For example, form with the situation that comprises the gate insulator that the Gallium oxide semiconductor layer contacts under, comprise the material of gallium oxide for gate insulator, so that the property preservation at the interface between oxide semiconductor layer and the gate insulator is favourable.In addition, when oxide semiconductor layer is arranged to be in contact with one another with the insulation course that comprises gallium oxide, can be reduced in the accumulation of the hydrogen at the interface between oxide semiconductor layer and the insulation course.Note, be used for to access similar effects in the situation of insulation course belonging to the Constitution Elements of oxide semiconductor element mutually of the same clan.For example, be effective by forming insulation course with the material that comprises aluminium oxide.Aluminium oxide is difficult for permeable.Therefore, preferably enter at anti-sealing and use the material that comprises aluminium oxide aspect the oxide semiconductor layer.

The insulating material of the insulation course that contacts with oxide semiconductor layer 144 preferably mixes to comprise the higher oxygen of ratio stoichiometric composition by the thermal treatment under the oxygen atmosphere or oxygen." oxygen doping " refers to oxygen added in the block.Note, use term " block " not only to add film surface in order to illustrate oxygen, but also add film inside.In addition, " oxygen doping " comprises " oxygen plasma doping ", and the oxygen that wherein will be made as plasma adds block.Oxygen mixes and can carry out with ion injection method or ion doping method.

For example, in the situation that the insulation course that contacts with oxide semiconductor layer 144 forms with gallium oxide, the composition of gallium oxide can mix to be set to Ga by the thermal treatment under the oxygen atmosphere or oxygen ₂O _x(x=3+ α, 0＜α＜1).In the situation that the insulation course that contacts with oxide semiconductor layer 144 forms with aluminium oxide, the composition of aluminium oxide can mix to be set to Al by the thermal treatment under the oxygen atmosphere or oxygen ₂O _x(x=3+ α, 0＜α＜1).In the situation that the insulation course use gallium oxide aluminium (perhaps oxidation gallium aluminium) that contacts with oxide semiconductor layer 144 forms, the composition of gallium oxide aluminium (perhaps oxidation gallium aluminium) can mix to be set to Ga by the thermal treatment under the oxygen atmosphere or oxygen _xAl _2-xO _{3+ α}(0＜x＜2,0＜α＜1).

By oxygen doping treatment etc., can form the insulation course in zone higher in the ratio stoichiometric composition that comprises oxygen wherein.When the insulation course that comprises this zone contacts with oxide semiconductor layer, the oxygen that excessively exists in the insulation course is offered oxide semiconductor layer, and can reduce the oxygen defect at the interface in the oxide semiconductor layer or between oxide semiconductor layer and the insulation course.

Note, replace gate insulator 146, the insulation course that comprises zone higher in the ratio stoichiometric composition of oxygen wherein can be used for the insulation course as the basilar memebrane of oxide semiconductor layer 144, perhaps can be used for gate insulator 146 and base insulating layer.

After forming gate insulator 146, the second thermal treatment is preferably carried out in inert gas atmosphere or oxygen atmosphere.Heat treated temperature is greater than or equal to 200 ℃ but be less than or equal to 450 ℃, preferably is greater than or equal to 250 ℃ but be less than or equal to 350 ℃.For example, thermal treatment can be carried out 1 hour with 250 ℃ in blanket of nitrogen.The second thermal treatment can reduce the deviation of transistorized electrical specification.In addition, in the oxygen containing situation of gate insulator 146 bags, oxygen can be offered oxide semiconductor layer 144 with the oxygen defect in the compensation oxide semiconductor layer 144.

Note, although in the present embodiment, the second thermal treatment is carried out after forming gate insulator 146, and be not limited to this second heat treated opportunity.For example, the second thermal treatment can be carried out after forming gate electrode.In addition, the second thermal treatment can be followed the first thermal treatment and carries out, and the first thermal treatment can double as the second thermal treatment, and perhaps the second thermal treatment can double as the first thermal treatment.

As mentioned above, by carrying out at least a in the first thermal treatment and the second thermal treatment, oxide semiconductor layer 144 can highly purified one-tenth so that comprise material comprising the least possible hydrogen atom.

Subsequently, the conductive layer (comprise and use the layer formed wiring identical with gate electrode) that is used to form gate electrode is formed and the process processing, so that form gate electrode 148a and conductive layer 148b (referring to Figure 21 D).

Gate electrode 148a and conductive layer 148b can or comprise any these materials with the metal material such as molybdenum, titanium, tantalum, tungsten, aluminium, copper, neodymium or scandium and form as the alloy material of principal ingredient.Note, gate electrode 148a and conductive layer 148b can have single layer structure or stepped construction.

Subsequently, insulation course 150 forms (referring to Figure 22 A) at gate insulator 146, gate electrode 148a and conductive layer 148b.Can pass through PVD method, CVD method etc., form insulation course 150.Insulation course 150 can form with the material that comprises the inorganic insulating material such as monox, silicon oxynitride, silicon nitride, hafnia, gallium oxide or aluminium oxide.Note, for insulation course 150, can preferably use the material with low-k, perhaps preferably adopt to have the structure (for example porous structure) of low-k.This is because by reducing the low-k of insulation course 150, the electric capacity that generates between wiring and the electrode can reduce and increase operating speed.Note, although in the present embodiment, insulation course 150 has single layer structure, and a mode of disclosed invention is not limited to this structure.Insulation course 150 can have and comprises two-layer or more multi-layered stepped construction.

Subsequently, in gate insulator 146 and insulation course 150, form the opening that reaches source electrode 142a.After this, be connected to the wiring 154 of source electrode 142a in insulation course 150 formation (referring to Figure 22 B).Opening forms by the selective etch with mask etc.

Conductive layer forms by PVD method or CVD method, and then carries out composition, so that form wiring 154.As the material that is used for conductive layer, can use the element from aluminium, chromium, copper, tantalum, titanium, molybdenum and tungsten, chosen, comprise any these elements as the alloy of composition etc.In addition, can use the material that comprises a kind of in manganese, magnesium, zirconium, beryllium, neodymium and the scandium or make up these elements.

Specifically, might adopt a kind of method, for example wherein in the zone of the opening that comprises insulation course 150, form thin (about 5 nm) titanium film by the PVD method, then form the aluminium film, in order to embed in the opening., have the function that makes oxide film (for example natural oxide film) reduction that will form titanium film on it by the formed titanium film of PVD method here, and reduce thus the contact resistance with lower electrode etc. (being source electrode 142a) here.In addition, can prevent the hillock of aluminium film.Can after the barrier film that forms titanium, titanium nitride etc., form copper film by electrochemical plating.

The opening that in insulation course 150, forms preferably with the overlapping zone of conductive layer 128b in form.By in this zone, forming opening, can suppress the increase of the element area that causes because of the contact region.

Here, the position that description impurity range 126 is connected with source electrode 142a and source electrode 142a do not use conductive layer 128b and overlapped situation with wiring 154 positions that are connected.In this case, form opening (being called again the contact in the bottom) in the insulation course 136 on being formed at impurity range 126, insulation course 138 and the insulation course 140, and form source electrode 142a in the contact in the bottom.After this, with gate insulator 146 and insulation course 150 middle and lower parts in overlapping zone, contact in form opening (being called again the contact in the top), then form wiring 154.When the contact in the top with the bottom in overlapping zone, contact in when forming, the source electrode 142a that forms in the contact in the bottom may disconnect because of etching.For fear of disconnecting, the contact in the bottom forms with contact in the top so that non-overlapping copies mutually causes the increase of element area thus.

As described in present embodiment, by using conductive layer 128b, the contact in the top can be in the situation that do not disconnect source electrode 142a and form.Therefore, the contact in the bottom and the contact in the top can form so that overlapped, in order to can suppress the increase of the element area that causes because of the contact region.In other words, the integrated level of semiconductor device can improve.

Subsequently, insulation course 156 forms so that cover wiring 154 (referring to Figure 22 C).

By above-mentioned steps, finish the transistor 162 and the capacitor 164 (referring to Figure 22 C) that comprise High Purity oxide semiconductor layer 144.

The transistorized example that can be applied to the transistor 162 shown in Figure 17 A and Figure 17 B is below described.

Oxide conducting layer as source region and drain region can be set between oxide semiconductor layer 144 and source electrode 142a and between oxide semiconductor layer 144 and drain electrode 142b.Figure 26 A and Figure 26 B illustrate the transistor 441,442 of the structure with the transistor 162 that wherein is provided with the oxide conducting layer.Note, insulation course 400 is equivalent to insulation course 136, insulation course 138, insulation course 140 etc.

The transistor 441 of Figure 26 A and Figure 26 B, 442 each in, be arranged between oxide semiconductor layer 144 and the source electrode 142a and between oxide semiconductor layer 144 and drain electrode 142b as oxide conducting layer 404a, the 404b in source region and drain region.The transistor 441 of the shape of

oxide conducting layer

404a, 404b and Figure 26 A and Figure 26 B, 442 different, this is because their manufacturing process is different.

As for the transistor 441 shown in Figure 26 A, form the lamination of oxide semiconductor film and oxide conductive film, and form island oxide semiconductor layer 144 and island oxide conductive film by the shape that same photo-mask process is processed this lamination.Form at oxide semiconductor layer and oxide conductive film at source electrode 142a and drain electrode 142b.Then, come etching island oxide conductive film with source electrode 142a and drain electrode 142b as mask, so that form

oxide conducting layer

404a, 404b as source region and drain region.

As for the transistor 442 shown in Figure 26 B, oxide conductive film forms at oxide semiconductor layer 144, and metal conductive film forms thereon.Then, process oxide conductive film and metal conductive film by same photo-mask process, so that form

oxide conducting layer

404a, 404b, source electrode 142a and drain electrode 142b as source region and drain region.

Note, in the etching of carrying out for the treatment of the shape of oxide conducting layer, suitably adjust etching condition (for example concentration of the type of etchant, etchant and etching period), in order to prevent the over etching of oxide semiconductor layer.

As the formation method of

oxide conducting layer

404a, 404b, use sputtering method, vacuum deposition method (electron beam evaporation methods etc.), arc discharge ion plating method or injection method.As the material of oxide conducting layer, can use the tin indium oxide of zinc paste, zinc oxide aluminum, oxynitriding zinc-aluminium, zinc-gallium oxide, silicon oxide-containing etc.In addition, above-mentioned material can comprise monox.

When the oxide conducting layer as the source region with the drain region is arranged between oxide semiconductor layer 144 and the source electrode 142a and between oxide semiconductor layer 144 and the drain electrode 142b time, source region and drain region can have than low resistance, and transistor 441,442 can high speed operation.

By comprising the structure of oxide semiconductor layer 144,

oxide conducting layer

404a, 404b, source electrode 142a, drain electrode 142b, transistor 441,442 withstand voltage can improve.

Below, top gate structure is adopted as the structure of the transistor 162 shown in Figure 17 A and Figure 17 B, but a mode of the present invention is not limited to this, can adopt bottom grating structure.Figure 28 A to Figure 28 C illustrates the example of bottom grating structure.

In the transistor 410 shown in Figure 28 A, gate insulator 402 arranges at gate electrode 401, and oxide semiconductor layer 403 arranges at gate insulator 402, and setting the source electrode 405a, the drain electrode 405b that are connected with oxide semiconductor layer 403.Note, gate electrode 401, oxide semiconductor layer 403, gate insulator 402, source electrode 405a, drain electrode 405b are equivalent to respectively gate electrode 148a, oxide semiconductor layer 144, gate insulator 146, source electrode 142a, the drain electrode 142b among Figure 17 A and Figure 17 B.

Transistor 420 shown in Figure 28 B is with the transistorized common ground of Figure 28 A: gate electrode 401, gate insulator 402, oxide semiconductor layer 403, source electrode 405a, drain electrode 405b are set.Transistor 420 shown in Figure 28 B is with the difference of the transistor 410 of Figure 28 A: with oxide semiconductor layer 403 insulation course 427 is set contiguously.

Transistor 430 shown in Figure 28 C is with the transistorized common ground of Figure 28 A: gate electrode 401, gate insulator 402, oxide semiconductor layer 403, source electrode 405a, drain electrode 405b are set.Transistor 430 shown in Figure 28 C is with the difference of the transistor 410 of Figure 28 A: the position that source electrode 405a and drain electrode 405b contact with oxide semiconductor layer 403.In other words, source electrode 405a and drain electrode 405b are arranged on the oxide semiconductor layer 403 and are in contact with it in the transistor 410 shown in Figure 28 A, and source electrode 405a and drain electrode 405b are arranged on oxide semiconductor layer 403 times and are in contact with it in Figure 28 C.

Because oxide semiconductor layer 144 is by High Purity, so hydrogen concentration is less than or equal to 5 * 10 in the described transistor 162 of present embodiment ¹⁹Atom/cm ³, be preferably lower than or equal 5 * 10 ¹⁸Atom/cm ³, more preferably be less than or equal to 5 * 10 ¹⁷Atom/cm ³In addition, owing to reducing oxygen defect by in oxide semiconductor layer 144, reducing hydrogen, water etc., so (be approximately 1 * 10 with the carrier concentration value of ordinary silicon wafer ¹⁴/ cm ³) compare, the value of the carrier concentration of oxide semiconductor layer 144 is fully low (for example to be lower than 1 * 10 ¹²/ cm ³, be preferably lower than 1.45 * 10 ¹⁰/ cm ³).The off state current of transistor 162 is also fully little.For example, to be less than or equal to 100 zA (1 zA (narrow general holder ampere) be 1 * 10 to the off state current under the room temperature (25 ℃) (here for per unit channel width (1 μ m)) ^-21A), be preferably lower than or equal 10 zA.

Like this, by using High Purity native oxide semiconductor layer 144, transistorized off state current can be easy to abundant reduction.In addition, by using this transistor, can access and wherein store data and can keep extremely for a long time semiconductor device.

Embodiment 3

Any mode of oxide semiconductor layer of the transistorized semiconductor layer that can be used in the above-mentioned embodiment is described with reference to Figure 27 A to Figure 27 C.

Oxide semiconductor layer in the present embodiment has the structure that comprises the first crystalline oxides semiconductor and be layered in the second thick crystalline oxides semiconductor layer of ratio the first crystalline oxides semiconductor layer on the first crystalline oxides semiconductor layer.

Insulation course 437 forms at insulation course 400.In the present embodiment, thickness more than or equal to 50 nm but the oxide insulating layer that is less than or equal to 600 nm form as insulation course 437 by PCVD method or sputtering method.For example, can use any lamination of the individual layer from silicon oxide film, gallium oxide film, pellumina, oxygen silicon nitride membrane, aluminium oxynitride film and silicon oxynitride film, chosen or these films.Note, insulation course 400 is equivalent to insulation course 136, insulation course 138, insulation course 140 etc.

Subsequently, thickness more than or equal to 1 nm but the first oxide semiconductor film that is less than or equal to 10 nm form at insulation course 437.The first oxide semiconductor film forms by sputtering method, and the underlayer temperature of the film by sputtering method in forming is set as and is greater than or equal to 200 ℃ but be less than or equal to 400 ℃.

In the present embodiment, the first oxide semiconductor film oxygen atmosphere, argon atmospher or comprise argon and the atmosphere of oxygen in, to form 5 nm under the following conditions thick: use the target that is used for oxide semiconductor (to be used for comprising In with 1:1:2 [mol ratio] ₂O ₃, Ga ₂O ₃The semi-conductive target of In-Ga-Zn-O type oxide with ZnO), the distance between substrate and the target is 170 mm, and underlayer temperature is 250 ℃, and pressure is 0.4 Pa, and direct current (DC) power is 0.5 kW.

Subsequently, the first thermal treatment is carried out under the following conditions: the atmosphere that the chamber of substrate wherein is set is the atmosphere of nitrogen or dry air.The first heat treated temperature is greater than or equal to 400 ℃ but be less than or equal to 750 ℃.By the first thermal treatment, form the first crystalline oxides semiconductor layer 450a (referring to Figure 27 A).

Depend on underlayer temperature or the first heat treated temperature when forming, the first thermal treatment causes from the crystallization on film surface, and crystal is from the film surface towards the film growth inside; Thereby obtain the c-axis oriented crystal.By the first thermal treatment, a large amount of zinc and oxygen are gathered in the film surface, and comprise zinc and oxygen and have that one or more layers Graphene type two dimensional crystal on plane forms in outermost surfaces on the hexagon; In the layer through-thickness growth of outermost surfaces, in order to form lamination.By improving heat treated temperature, the crystal growth proceeds to inside from the surface, and further proceeds to internally the bottom.

By the first thermal treatment, be diffused into interface or near interface (within interface ± 5 nm) between insulation course 437 and the first crystalline oxides semiconductor layer 450a as the oxygen in the insulation course 437 of oxide insulating layer, reduce thus the oxygen defect in the first crystalline oxides semiconductor layer.Therefore, preferably, oxygen be included in the insulation course 437 as base insulating layer (block in) with the amount that surpasses at least the stoichiometric composition ratio or between the first crystalline oxides semiconductor layer 450a and the insulation course 437 at the interface.

Subsequently, thickness forms at the first crystalline oxides semiconductor layer 450a greater than the second oxide semiconductor film of 10 nm.The second oxide semiconductor film forms by sputtering method, and the underlayer temperature of film in forming is set as and is greater than or equal to 200 ℃ but be less than or equal to 400 ℃.Be set as by the underlayer temperature during film is formed and be greater than or equal to 200 ℃ but be less than or equal to 400 ℃, precursor (precursor) can be arranged on the surface that is formed at the first crystalline oxides semiconductor layer and in the oxide semiconductor layer that is in contact with it, and can access so-called order.

In the present embodiment, the second oxide semiconductor film oxygen atmosphere, argon atmospher or comprise argon and the atmosphere of oxygen in, to form 25 nm under the following conditions thick: use the target that is used for oxide semiconductor (to be used for comprising In with 1:1:2 [mol ratio] ₂O ₃, Ga ₂O ₃The semi-conductive target of In-Ga-Zn-O type oxide with ZnO), the distance between substrate and the target is 170 mm, and underlayer temperature is 400 ℃, and pressure is 0.4 Pa, and direct current (DC) power is 0.5 kW.

Subsequently, the second thermal treatment is carried out under the following conditions: the atmosphere that the chamber of substrate wherein is set is that nitrogen divides, oxygen divides or the mixed atmosphere of nitrogen and oxygen.The second heat treated temperature is greater than or equal to 400 ℃ but be less than or equal to 750 ℃.By the second thermal treatment, form the second crystalline oxides semiconductor layer 450b (referring to Figure 27 B).The second thermal treatment is carried out in the mixed atmosphere of blanket of nitrogen, oxygen atmosphere or nitrogen and oxygen, increases thus the density of the second crystalline oxides semiconductor layer, and reduces defects count wherein.By the second thermal treatment, crystal is grown by using the first crystalline oxides semiconductor layer 450a to carry out as core, through-thickness, that is to say, the crystal growth proceeds to inside from the bottom; Therefore, form the second crystalline oxides semiconductor layer 450b.

Preferably, carry out in succession and be not exposed to air from forming insulation course 437 to second heat treated steps.Preferably during being controlled to the atmosphere that comprises few hydrogen and moisture (for example inert gas atmosphere, reduce pressure atmosphere or dry air atmosphere), carry out from forming insulation course 437 to second heat treated steps; Aspect moisture, for example can adopt dew point be-40 ℃ or lower, preferably dew point is for-50 ℃ or lower dry nitrogen atmosphere.

Subsequently, will comprise that the oxide semiconductor lamination of the first crystalline oxides semiconductor layer 450a and the second crystalline oxides semiconductor layer 450b is processed into the oxide semiconductor layer 453 (referring to Figure 27 C) of the lamination that comprises the island oxide semiconductor layer.In the accompanying drawing, interface between the first crystalline oxides semiconductor layer 450a and the second crystalline oxides semiconductor layer 450b is illustrated by the broken lines, and the first crystalline oxides semiconductor layer 450a and the second crystalline oxides semiconductor layer 450b are shown the oxide semiconductor lamination; But in fact the interface is not significantly, but illustrates for easy to understand.

Can by after the oxide semiconductor lamination forms, carrying out etching when the mask with anticipated shape, process the oxide semiconductor lamination.Mask can form by the method such as photoetching.In addition, mask can form by the method such as ink ejecting method.

For the etching of oxide semiconductor lamination, can adopt dry-etching or Wet-type etching.Much less, use capable of being combined they both.

Be characterised in that by resulting the first crystalline oxides semiconductor layer of above-mentioned formation method and the second crystalline oxides semiconductor layer, they have the c-axis orientation.Note, the first crystalline oxides semiconductor layer and the second crystalline oxides semiconductor layer comprise and wherein comprise the crystal with c-axis orientation (be called again C axle oriented crystal (CAAC): oxide C-Axis Aligned Crystal), it had not both had mono-crystalline structures not have non crystalline structure yet.The first crystalline oxides semiconductor layer and the second crystalline oxides semiconductor layer partly comprise the grain boundary.

Note, the material that is used for the first crystalline oxides semiconductor layer and the second crystalline oxides semiconductor layer comprises that quaternary metallic oxide is such as In-Sn-Ga-Zn-O class material; Ternary metal oxide is such as In-Ga-Zn-O class material (being also referred to as IGZO), In-Sn-Zn-O class material (being also referred to as ITZO), In-Al-Zn-O class material, Sn-Ga-Zn-O class material, Al-Ga-Zn-O class material, Sn-Al-Zn-O class material, In-Hf-Zn-O class material, In-La-Zn-O class material, In-Ce-Zn-O class material, In-Pr-Zn-O class material, In-Nd-Zn-O class material, In-Sm-Zn-O class material, In-Eu-Zn-O class material, In-Gd-Zn-O class material, In-Tb-Zn-O class material, In-Dy-Zn-O class material, In-Ho-Zn-O class material, In-Er-Zn-O class material, In-Tm-Zn-O class material, In-Yb-Zn-O class material, In-Lu-Zn-O class material; Binary metal oxide such as In-Zn-O class material, Sn-Zn-O class material, Al-Zn-O class material, Zn-Mg-O class material, Sn-Mg-O class material, In-Mg-O class material, In-Ga-O class material; Monobasic metal oxide such as In-O class material, Sn-O class material, Zn-O class material.In addition, above-mentioned material can comprise SiO ₂Here, for example, In-Ga-Zn-O class material refers to the oxidation film that contains indium (In), gallium (Ga), zinc (Zn), and its ratio of components is not specifically limited.In addition, In-Ga-Zn-O class material can comprise In, Ga and Zn element in addition.

Be not confined to wherein the second crystalline oxides semiconductor layer in the situation of the double-layer structure that the first crystalline oxides semiconductor layer forms, can comprise three layers or more multi-layered rhythmo structure by after forming the second crystalline oxides semiconductor layer, repeating to be used to form film formation and the heat treated process of the 3rd crystalline oxides semiconductor layer, forming.

Comprise that the oxide semiconductor layer 453 by the formed oxide semiconductor lamination of above-mentioned formation method can suitably be used for being applied to the transistor of the disclosed semiconductor device of this instructions (for example transistor 162 in embodiment 1 and the embodiment 2, the transistor 410,420,430,441 and 442 in the embodiment 2).

In the transistor 162 of embodiment 2, the oxide semiconductor lamination of present embodiment is as in the oxide semiconductor layer 403 therein, electric field is not applied to another surface from a surface of oxide semiconductor layer, and electric current not along the thickness direction of oxide semiconductor lamination (from a surface to another surface, particularly, the vertical direction in the transistor 162 of Figure 17 A and Figure 17 B) flow.Transistor has a kind of structure, and wherein electric current is mainly along the interface motion of oxide semiconductor lamination; Therefore, even even when adopting light to shine transistor or when BT stress is applied to transistor, also inhibition or reduction transistor characteristic is deteriorated.

By with the lamination of the first crystalline oxides semiconductor layer and the second crystalline oxides semiconductor layer, form transistor such as oxide semiconductor layer 453, transistor can have stable electrical specification and high reliability.

Present embodiment can suitably realize in conjunction with the structure described in any other embodiment.

Embodiment 4

In the present embodiment, the oxide that description is comprised the crystal (being called again C axle oriented crystal (C-Axis Aligned Crystal:CAAC)) of c-axis orientation, this oxide have triangle or sexangle atomic arrangement from the direction at a-b plane, surface or interface the time.In this crystal, metallic atom is arranged with layered mode along c-axis with layered mode arrangement or metallic atom and oxygen atom along c-axis, and the direction of a axle or b axle changes (crystal rotates around c-axis) in the a-b plane.

In broad terms, the oxide that comprises CAAC refers to and is included in the on-monocrystalline oxide mutually that has triangle, sexangle, equilateral triangle or regular hexagon atomic arrangement from perpendicular to the direction on a-b plane the time and wherein arrange with layered mode with layered mode arrangement or metallic atom and oxygen atom at metallic atom from perpendicular to the direction of c-axis direction the time.

The CAAC oxide is not monocrystalline oxide, but this does not represent that the CAAC oxide only is comprised of amorphous component.Although the CAAC oxide comprises crystallization part (crystalline portion), the border between a crystalline portion and another crystalline portion is unclear in some cases.

In the situation that oxygen is included among the CAAC, nitrogen can replace being included in the part of the oxygen among the CAAC.The c-axis that is included in each crystalline portion in the CAAC oxide can be direction orientation the direction of the Surface Vertical of the surface of the substrate of its formation CAAC oxide or CAAC oxide (for example with).In addition, being included in the normal on the a-b plane of each crystalline portion in the CAAC oxide can be direction orientation the direction of the Surface Vertical of the surface of the substrate of its formation CAAC oxide or CAAC oxide (for example with).

The CAAC oxide forms to wait according to it becomes conductor, semiconductor or insulator.The CAAC oxide waits and transmission or non-visible light transmissive according to its composition.

An example as this CAAC, there is a kind of crystal, this Crystallization is the film shape and has triangle or sexangle atomic arrangement when observing perpendicular to the direction on the surface of the surface of film or support substrate, and wherein when observing the cross section of film, metallic atom is arranged with layered mode with layered mode arrangement or metallic atom and oxygen atom (or nitrogen-atoms).

Describe an example of the crystal structure of CAAC oxide in detail with reference to Figure 29 A to Figure 29 E, Figure 30 A to Figure 30 C and Figure 31 A to Figure 31 C.In Figure 29 A to Figure 29 E, Figure 30 A to Figure 30 C and Figure 31 A to Figure 31 C, vertical direction is corresponding to the c-axis direction, and with the plane of c-axis perpendicular direction corresponding to the a-b plane, unless otherwise noted.When using expression " first half " and " Lower Half " simply, they refer to the first half of top, a-b plane and the Lower Half (with respect to the first half and the Lower Half on a-b plane) of below, a-b plane.Moreover in Figure 29 A to Figure 29 E, the O that is centered on by circle illustrates four-coordination O, and by two corrals around O three-fold coordination O is shown.

Figure 29 A illustrates near the structure of six four-coordination oxygen comprising a hexa-coordinate In atom and the In atom (below be called four-coordination O) atom.The structure that comprises a metallic atom and near oxygen atom thereof here, is called little family.Structure among Figure 29 A is actually octahedral structure, but is shown for the sake of brevity planar structure.Note, three four-coordination O atoms are present in each of the first half among Figure 29 A and Lower Half.In the little family shown in Figure 29 A, electric charge is 0.

Figure 29 B illustrates near the structure of two four-coordination O atoms near three three-fold coordination oxygen comprising the pentacoordinate Ga atom, Ga atom (below be called three-fold coordination O) atom and the Ga atom.All three-fold coordination O atoms are present on the a-b plane.Four-coordination O atom is present in each of the first half among Figure 29 B and Lower Half.The In atom can also have the structure shown in Figure 29 B, because the In atom can have five coordinations.In the little family shown in Figure 29 B, electric charge is 0.

Figure 29 C illustrates the structure that comprises near four four-coordination O atoms a four-coordination Zn atom and the Zn atom.In Figure 29 C, a four-coordination O atom is present in the first half, and three four-coordination O atoms are present in the Lower Half.In addition, in Figure 29 C, three four-coordination O atoms can be present in the first half, and a four-coordination O atom can be present in the Lower Half.In the little family shown in Figure 29 C, electric charge is 0.

Figure 29 D illustrates the structure that comprises near six four-coordination O atoms a hexa-coordinate Sn atom and the Sn atom.In Figure 29 D, three four-coordination O atoms are present in each of the first half and Lower Half.In the little family shown in Figure 29 D, electric charge is+1.

Figure 29 E illustrates the little family that comprises two Zn atoms.In Figure 29 E, a four-coordination O atom is present in each of the first half and Lower Half.In the little family shown in Figure 29 E, electric charge is-1.

Here, a plurality of little families form middle family, and a plurality of middle family forms big nation's (being called again structure cell (unit cell)).

Now, with the bonding rule of describing between the little family.Three O atoms in the hexa-coordinate In atom first half respectively have three approaching In atoms in downward direction among Figure 29 A relatively, and three O atoms in the Lower Half respectively have three approaching In atoms on upward direction.An O atom in the pentacoordinate Ga atom first half has an approaching Ga atom in downward direction relatively, and an O atom in the Lower Half has an approaching Ga atom in upward direction.An O atom in the four-coordination Zn atom first half has an approaching Zn atom in downward direction relatively, and three O atoms in the Lower Half respectively have three approaching Zn atoms on upward direction.Like this, near the quantity of the four-coordination O atom of the metallic atom and top equals near each of four-coordination O atom and the quantity of the metallic atom of below.Similarly, near the quantity of the four-coordination O atom of the metallic atom and below equals near each of four-coordination O atom and the quantity of the metallic atom of top.Because to help the O atom of the bonding between the group be the coordination number of four-coordination O atom, so be 4 with the quantity sum of the metallic atom of top near the O atom and near the quantity of the metallic atom of below and the O atom.Correspondingly, when the quantity sum of the four-coordination O atom below the quantity of the four-coordination O atom of metallic atom top and another metallic atom was 4, two kinds of little families that comprise metallic atom can bonding.For example, in the situation that hexa-coordinate metal (In or Sn) atom comes bonding by three four-coordination O atoms in the Lower Half, it is bonded to pentacoordinate metal (Ga or In) atom or four-coordination metal (Zn) atom.

On the c-axis direction its coordination number be 4,5 or 6 metallic atom by four-coordination O atomistic binding to another metallic atom.Except the above, can also by make up a plurality of little families form by different way in family, so the total electrical charge of hierarchy is 0.

Figure 30 A illustrates the model of the middle family in the hierarchy that is included in In-Sn-Zn-O class material.Figure 30 B illustrates the big nation that comprises three middle families.Note, Figure 30 C is illustrated in from the c-axis direction and observes atomic arrangement in the situation of the hierarchy Figure 30 B.

In Figure 30 A, omitted for the sake of brevity three-fold coordination O atom, and by using circle that four-coordination O atom is shown; Numeral in the circle illustrates the quantity of four-coordination O atom.For example, be present in three four-coordination O atoms in each of the first half and Lower Half by circle 3 expressions with respect to the Sn atom.Similarly, in Figure 30 A, be present in a four-coordination O atom in each of the first half and Lower Half with respect to the In atom by circle 1 expression.Figure 30 A also illustrates in the Lower Half in a four-coordination O atom and the first half near three four-coordination O atoms Zn atom and the first half in a four-coordination O atom and the Lower Half near the Zn atoms three four-coordination O atoms.

In the middle family that in Figure 30 A, comprises in the hierarchy of In-Sn-Zn-O class material, according to the order that begins from the top, near near the four-coordination O atom of Sn atomistic binding three four-coordination O atoms in each of the first half and Lower Half in each of the first half and Lower Half In atom, near three four-coordination O atoms of this In atomistic binding in the first half Zn atom, this Zn atom is by near the relative In atom three four-coordination O atoms of a four-coordination O atomistic binding of Zn atom in each of the first half and Lower Half in the Lower Half, and this In atomistic binding is to the little family that comprises two Zn atoms and near near the Sn atom three four-coordination O atoms of a four-coordination O atom in the first half and this a little family four-coordination O atomistic binding by relative this little family in the Lower Half in each of the first half and Lower Half.Family in a plurality of these classes of bonding is so that form big nation.

Here, the electric charge of a key of the electric charge of three-fold coordination O atom key and four-coordination O atom can be assumed to respectively-0.667 and-0.5.For example, (hexa-coordinate or pentacoordinate) In atomic charge, (four-coordination) Zn atomic charge and (pentacoordinate or hexa-coordinate) Sn atomic charge be respectively+3 ,+2 and+4.Correspondingly, comprise that the electric charge in the little family of Sn atom is+1.Therefore, need to offset+1-1 electric charge forms the hierarchy that comprises the Sn atom.As the structure with electric charge of-1, can enumerate the little family that comprises two Zn atoms shown in Figure 29 E.For example, by comprising a little family of two Zn atoms, can offset the electric charge of a little family that comprises the Sn atom, so that the total electrical charge of hierarchy can be 0.

When the big nation shown in repetition Figure 30 B, can access In-Sn-Zn-O crystalloid (In ₂SnZn ₃O ₈).Note, the crystal-like hierarchy of resulting In-Sn-Zn-O can be expressed as ingredient formula In ₂SnZn ₂O ₇(ZnO) _m(m be 0 or natural number).

Above-mentioned rule also is applicable to following oxide material: quaternary metallic oxide is such as In-Sn-Ga-Zn-O class material; Ternary metal oxide is such as In-Ga-Zn-O class material (being called again IGZO), In-Al-Zn-O class material, Sn-Ga-Zn-O class material, Al-Ga-Zn-O class material, Sn-Al-Zn-O class material, In-Hf-Zn-O class material, In-La-Zn-O class material, In-Ce-Zn-O class material, In-Pr-Zn-O class material, In-Nd-Zn-O class material, In-Sm-Zn-O class material, In-Eu-Zn-O class material, In-Gd-Zn-O class material, In-Tb-Zn-O class material, In-Dy-Zn-O class material, In-Ho-Zn-O class material, In-Er-Zn-O class material, In-Tm-Zn-O class material, In-Yb-Zn-O class material or In-Lu-Zn-O class material; Binary metal oxide such as In-Zn-O class material, Sn-Zn-O class material, Al-Zn-O class material, Zn-Mg-O class material, Sn-Mg-O class material, In-Mg-O class material or In-Ga-O class material.

As an example, Figure 31 A illustrates the model of the middle family in the hierarchy that is included in In-Ga-Zn-O class material.

In the middle family in the hierarchy of the In-Ga-Zn-O class material in being included in Figure 31 A, according to the order that begins from the top, near three four-coordination O atoms in each of the first half and Lower Half In atomistic binding is near the Zn atom four-coordination O atom in the first half, this Zn atom is by near relative three four-coordination O atomistic bindings of Zn atom Ga atom the four-coordination O atom in each in the first half and the Lower Half in the Lower Half, and this Ga atom is by near the relative In atom three four-coordination O atoms of a four-coordination O atomistic binding of Ga atom in each of the first half and Lower Half in the Lower Half.Family in a plurality of these classes of bonding is so that form big nation.

Figure 31 B illustrates the big nation that comprises three middle families.Note, Figure 31 C is illustrated in from the c-axis direction and observes atomic arrangement in the situation of the hierarchy Figure 31 B.

Here, because (hexa-coordinate or pentacoordinate) In atomic charge, (four-coordination) Zn atomic charge and (pentacoordinate) Ga atomic charge be respectively+3 ,+2 and+3, so comprise that any electric charge of little family of In atom, Zn atom and Ga atom is 0.Its result, the total electrical charge of middle family with combination of this little family of class is always 0.

In order to form the hierarchy of In-Ga-Zn-O class material, can not only use the middle family shown in Figure 31 A but also different middle family among the arrangement of using wherein In atom, Ga atom and Zn atom and Figure 31 A, form big nation.

Embodiment 5

Transistorized field-effect mobility is described in the present embodiment.

The field-effect mobility of the actual measurement of insulated gate transistor is lower than its original mobility because of a variety of causes; This phenomenon not only occurs in the situation of using oxide semiconductor.One of reason that reduces mobility is the defective of semiconductor inside or the defective at the interface between semiconductor and the dielectric film.When using the Levinson pattern, there is not the field-effect mobility under the defect situation in calculation assumption semiconductor inside in theory.

Suppose that semi-conductive original mobility and measured field-effect mobility are respectively μ ₀And μ, and potential barrier (for example grain boundary) is present in the semiconductor, and measured field-effect mobility can be expressed as following formula.

[formula 2]

Here, E represents the height of potential barrier, and k represents Boltzmann constant, and T represents absolute temperature.When supposing potential barrier owing to defective, the height of potential barrier can be expressed as following formula according to the Levinson pattern.

[formula 3]

Here, e representation element electric charge, NThe average defect concentration of per unit area in the expression raceway groove, εRepresent semi-conductive permittivity, nThe carrier number of per unit area in the expression raceway groove, C _OxThe electric capacity of expression per unit area, V _gThe expression gate voltage, and t represents channel thickness.Thickness at semiconductor layer is less than or equal in the situation of 30 nm, and it is identical that channel thickness can be counted as with semiconductor layer thickness.Leakage current in the linear zone I _dCan be expressed as following formula.

[formula 4]

Here, LThe expression channel length, WThe expression channel width, and LWith WRespectively be 10 μ m.In addition, V _dThe expression drain voltage.With the following formula both sides divided by V _gAnd when then getting the logarithm on both sides, can obtain following formula.

[formula 5]

The right of formula 5 is V _gFunction.Find from this formula, defect concentration N can from ln wherein ( I _d/ V _g) be ordinate and 1/ V _gThe degree of tilt of marking and drawing the straight line in the chart that measured value obtains for horizontal ordinate obtains.That is to say, defect concentration can be from transistorized I _d- V _gCharacteristic is assessed.Wherein the ratio of indium (In), tin (Sn) and zinc (Zn) is that the defect concentration N of the oxide semiconductor of 1:1:1 is approximately 1 * 10 ¹²/ cm ²

According to defect concentration that obtains like this etc., μ ₀Can be calculated as 120 cm by formula 2 and formula 3 ²/ Vs.The measured mobility that comprises the In-Sn-Zn oxide of defective is approximately 35 cm ²/ Vs.But, suppose not have at the interface defective, then a mobility [mu] of oxide semiconductor between semiconductor inside and semiconductor and the dielectric film ₀Be expected to be 120 cm ²/ Vs.

Note, even when there is not defective in semiconductor inside, the scattering at the interface between raceway groove and the gate insulator also affects transistorized transport property.In other words, in the mobility [mu] of the position of leaving the interface distance x between raceway groove and the gate insulator ₁Can be expressed as following formula.

[formula 6]

Here, DElectric field on the expression grid direction, and BWith GBe constant. BWith GCan obtain from actual measured results; According to above-mentioned measurement result, BBe 4.75 * 10 ⁷Cm/s, and G Be 10 nm (degree of depth that the impact of interface scattering reaches).When DDuring increase (, when gate voltage increases), second increase of formula 6, and mobility [mu] correspondingly ₁Increase.

Its raceway groove comprises desirable oxide semiconductor and does not have defective transistorized mobility [mu] in semiconductor inside ₂Result of calculation shown in figure 32.For calculating, use by Synopsys, the unit simulation software Sentaurus Device that Inc. makes, and energy gap, electron affinity, relative permittivity and the thickness of supposition oxide semiconductor are respectively 2.8 eV, 4.7 eV, 15 and 15 nm.These values obtain by measuring the film that forms via sputtering method.

In addition, the work function of supposing grid, source electrode and drain electrode is respectively 5.5 eV, 4.6 eV and 4.6 eV.The thickness of supposing gate insulator is 100 nm, and supposes that its relative permittivity is 4.1.Suppose that channel length and channel width respectively are 10 μ m, and supposition drain voltage V _dBe 0.1 V.

Shown in figure 32, mobility has more than or equal to 100 cm at the gate voltage place that slightly surpasses 1 V ²The peak value of/Vs, and uprise and reduce with gate voltage, because the impact of interface scattering increases.Note, in order to reduce interface scattering, wish that the surface of semiconductor layer is smooth (atomic layer flatness) in atom level.

The result of calculation of the characteristic of the small transistor (minute transistors) made from the oxide semiconductor with this mobility is shown in Figure 33 A to Figure 33 C, Figure 34 A to Figure 34 C and Figure 35 A to Figure 35 C.Figure 36 A and Figure 36 B illustrate the transistorized cross section structure for this calculating.Each comprises having n transistor shown in Figure 36 A and Figure 36 B in oxide semiconductor layer ⁺Semiconductor region 1103a and the semiconductor region 1103c of type conduction.The resistivity of semiconductor region 1103a and semiconductor region 1103c is 2 * 10 ^-3Ω cm.

Transistor shown in Figure 36 A is in base insulating layer 1101 and embed base insulating layer 1101 and formed by the formed inserted insulation body 1102 of aluminium oxide.Transistor comprises semiconductor region 1103a, semiconductor region 1103c, is used as intrinsic semiconductor regions 1103b and the grid 1105 of the channel formation region between them.The width of grid 1105 is 33 nm.

Gate insulator 1104 forms between grid 1105 and semiconductor region 1103b.In addition, side wall insulator 1106a and side wall insulator 1106b form in the both side surface of grid 1105, and insulator 1107 forms at grid 1105, in order to prevent grid 1105 and another short circuit between connecting up.The width of side wall insulating layer is 5 nm.Source electrode 1108a is arranged to contact with semiconductor region 1103c with semiconductor region 1103a respectively with drain electrode 1108b.Note, this transistorized channel width is 40 nm.

The transistorized something in common of transistor AND gate Figure 36 A of Figure 36 B is, it forms in base insulating layer 1101 and by the formed inserted insulation body 1102 of aluminium oxide, and it comprises semiconductor region 1103a, semiconductor region 1103c, is arranged on the intrinsic semiconductor regions 1103b between them, grid 1105, gate insulator 1104, side wall insulator 1106a, side wall insulator 1106b, insulator 1107, source electrode 1108a and the drain electrode 1108b that width is 33 nm.

Transistorized difference shown in transistor AND gate Figure 36 B shown in Figure 36 A is the conduction type of the semiconductor region under side wall insulator 1106a and the side wall insulator 1106b.In the transistor shown in Figure 36 A, the semiconductor region under side wall insulator 1106a and the side wall insulator 1106b is to have n ⁺The semiconductor region 1103a of type conduction and have n ⁺The part of the semiconductor region 1103c of type conduction, and in the transistor shown in Figure 36 B, the semiconductor region under side wall insulator 1106a and the side wall insulator 1106b is the part of intrinsic semiconductor regions 1103b.In other words, not providing not with semiconductor region 1103a (semiconductor region 1103c) in the transistor of Figure 36 B is not L with the overlapping width of grid 1105 also _OffThe zone.This zone is called deviate region, and width L _OffBe called deflected length.See from figure, deflected length equals the width of side wall insulator 1106a (side wall insulator 1106b).

Other parameter of using in the calculating as mentioned above.For calculating, use by Synopsys the unit simulation software Sentaurus Device that Inc. makes.Figure 33 A to Figure 33 C illustrates the transistorized leakage current (I with structure shown in Figure 36 A _d, solid line) and the gate voltage of mobility (μ, dotted line) ( V _g: the potential difference (PD) between grid and the source electrode) dependence.Leakage current I _dBy at supposition drain voltage (potential difference (PD) between drain electrode and the source electrode) for the calculating in the situation of+1 V obtains, and mobility [mu] by in the situation that the supposition drain voltage obtain for the calculating of+0.1 V.

The thickness that Figure 33 A is illustrated in gate insulator is transistorized gate voltage dependence in the situation of 15 nm, the thickness that Figure 33 B is illustrated in gate insulator is transistorized gate voltage dependence in the situation of 10 nm, and Figure 33 C thickness of being illustrated in gate insulator is transistorized gate voltage dependence in the situation of 5 nm.Because gate insulator is thinner, so particularly at the leakage current I of off-state _d(off state current) significantly reduces.By contrast, at mobility [mu] and the leakage current I of on-state _dThe peak value of (on state current) does not have marked change.Figure expresses leakage current and surpasses 10 μ A at the gate voltage place of about 1 V, and this is required in the memory element etc.

Figure 34 A to Figure 34 C illustrates the transistorized leakage current with structure shown in Figure 36 B I _dThe gate voltage of (solid line) and mobility [mu] (dotted line) V _gDependence, wherein deflected length L _OffBe 5 nm.Leakage current I _dBy in the situation that the supposition drain voltage obtain for the calculating of+1 V, and mobility [mu] by in the situation that the supposition drain voltage obtain for the calculating of+0.1 V.The thickness that Figure 34 A is illustrated in gate insulator is transistorized gate voltage dependence in the situation of 15 nm, the thickness that Figure 34 B is illustrated in gate insulator is transistorized gate voltage dependence in the situation of 10 nm, and Figure 34 C thickness of being illustrated in gate insulator is transistorized gate voltage dependence in the situation of 5 nm.

In addition, Figure 35 A to Figure 35 C illustrates the transistorized leakage current I with structure shown in Figure 36 B _dThe gate voltage dependence of (solid line) and mobility [mu] (dotted line), wherein deflected length L _OffBe 15 nm.Leakage current I _dBy in the situation that the supposition drain voltage obtain for the calculating of+1 V, and mobility [mu] by in the situation that the supposition drain voltage obtain for the calculating of+0.1 V.The thickness that Figure 35 A is illustrated in gate insulator is transistorized gate voltage dependence in the situation of 15 nm, the thickness that Figure 35 B is illustrated in gate insulator is transistorized gate voltage dependence in the situation of 10 nm, and Figure 35 C thickness of being illustrated in gate insulator is the transistorized gate voltage dependence in the situation of 5 nm.

In any of these structures, because gate insulator is thinner, so off state current significantly reduces, and the peak value of mobility [mu] and on state current does not occur significantly to change.

Note, the peak value of mobility [mu] is approximately 80 cm in Figure 33 A to Figure 33 C ²/ Vs is approximately 60 cm in Figure 34 A to Figure 34 C ²/ Vs, and in Figure 35 A to Figure 35 C, be approximately 40 cm ²/ Vs; Therefore, the peak value of mobility [mu] is with deflected length L _OffIncrease and reduce.In addition, this trend is applicable to off state current.On state current is also with deflected length L _OffIncrease and reduce; But the reduction of on state current is more mild more than the reduction of off state current.In addition, chart is illustrated in any of these structures, and leakage current surpasses 10 μ A at the gate voltage place of about 1 V, and this is required in the memory element etc.

Embodiment 6

In the present embodiment, comprise In, Sn and Zn as the transistor of the oxide semiconductor of principal ingredient with describing to use as oxide semiconductor.

By in heated substrate, forming oxide semiconductor or by after forming oxide semiconductor film, heat-treating, wherein will comprise In, Sn and Zn and can have advantageous feature as the transistor that the oxide semiconductor of principal ingredient is used as channel formation region.Note, principal ingredient refers to be included in the element in the composition more than or equal to 5 atom %.

By comprising In, Sn and Zn in formation as having a mind to heated substrate after the oxide semiconductor film of principal ingredient, transistorized field-effect mobility can be improved.In addition, transistorized threshold voltage can just be offset, in order to make transistor normal off (normally off).

As an example, Figure 37 A to Figure 37 C respectively illustrates wherein to use and comprises In, Sn and Zn is that 3 μ m, channel width W are the transistorized characteristic of oxide semiconductor film and the gate insulator that thickness is 100 nm of 10 μ m as principal ingredient and channel length L.Note V _dBe set as 10 V.

Figure 37 A is illustrated in not and has a mind in the situation of heated substrate forming it by sputtering method and comprise In, Sn and Zn as the transistorized characteristic of the oxide semiconductor film of principal ingredient.The peak value of transistorized field-effect mobility is 18.8 cm ²/ Vsec.On the other hand, having a mind to form in the heated substrate when comprising In, Sn and Zn as the oxide semiconductor film of principal ingredient, field-effect mobility can be improved.Figure 37 B forms it and comprises In, Sn and Zn as the transistorized characteristic of the oxide semiconductor film of principal ingredient when being illustrated in 200 ℃ of heated substrate.The peak value of transistorized field-effect mobility is 32.2 cm ²/ Vsec.

Heat-treat by comprise In, Sn and the Zn oxide semiconductor film as principal ingredient in formation after, field-effect mobility can further be improved.Figure 37 C illustrate its comprise In, Sn and Zn as the oxide semiconductor film of principal ingredient by form and then pass through the heat treated transistorized characteristic with 650 ℃ with 200 ℃ sputter.The peak value of transistorized field-effect mobility is 34.5 cm ²/ Vsec.

The heating of having a mind to of substrate estimates to have the effect that enters the moisture of oxide semiconductor film during the formation that is reduced in by sputter.In addition, the thermal treatment after film forms can discharge and remove hydrogen, hydroxyl or moisture from oxide semiconductor film.Like this, field-effect mobility can be improved.This improvement of field-effect mobility be considered to not only by dehydration or dehydrogenation remove impurity but also the interatomic disance that causes by the increase because of density reduce realize.Can be highly purified by carrying out from oxide semiconductor removal impurity, make the oxide semiconductor crystallization.In the situation that use this highly purified on-monocrystalline oxide semiconductor, ideally, estimate to realize surpassing 100 cm ²The peak value of the field-effect mobility of/Vsec.

Can make in the following manner and comprise that In, Sn and Zn are as the oxide semiconductor crystallization of principal ingredient: with the O +ion implanted oxide semiconductor, discharge hydrogen, hydroxyl or the moisture that comprises in the oxide semiconductor by thermal treatment, and make the oxide semiconductor crystallization via thermal treatment or by the another kind of thermal treatment of carrying out after a while.Process or again crystallization processing by this crystallization, can access the on-monocrystalline oxide semiconductor with favourable crystallinity.

Thermal treatment after the intentionally heating of the substrate during film forms and/or film form not only helps to improve field-effect mobility, but also helps to make the transistor normal off.Comprise therein In, Sn and Zn as principal ingredient and in the situation that do not have a mind to oxide semiconductor film that heated substrate forms as in the transistor of channel formation region, threshold voltage trends towards negative bias and moves.But, when use having a mind to heated substrate during formed oxide semiconductor film, can solve the problem that the negative bias of threshold voltage moves.That is to say, threshold voltage shift becomes so that transistor becomes normal off; This trend can be by relatively confirming between Figure 37 A and Figure 37 B.

Note, threshold voltage can also be controlled by the ratio that changes In, Sn and Zn; When the ratio of components of In, Sn and Zn is 2:1:3, estimate to form the normal off transistor.In addition, the oxide semiconductor film that has a high-crystallinity can recently obtain by the composition of setting target by following formula: In:Sn:Zn=2:1:3.

Temperature or the heat treated temperature of having a mind to heat of substrate are greater than or equal to 150 ℃, preferably are greater than or equal to 200 ℃, more preferably are greater than or equal to 400 ℃.When film forms or thermal treatment when at high temperature carrying out, transistor can normal off.

By during film forms, having a mind to heated substrate and/or by after film forms, heat-treating, can improve for the stability of gate bias stress.For example, when the intensity with 2 MV/cm applies gate bias in the time of 1 hour at 150 ℃, the drift of threshold voltage can be less than ± 1.5 V, preferably less than ± 1.0 V.

Following two transistors are carried out the BT test: sample 1, after forming oxide semiconductor film, it is not heat-treated; And sample 2, after forming oxide semiconductor film, with 650 ℃ it is heat-treated.

At first, at 25 ℃ underlayer temperature and the V of 10 V _DsMeasure transistorized V _g-I _dCharacteristic.Note V _DsRefer to drain voltage (potential difference (PD) between drain electrode and the source electrode).Then, underlayer temperature is set as 150 ℃, and V _DsBe set as 0.1 V.After this, apply the V of 20 V _g, be 2 MV/cm so that be applied to the electric field intensity of gate insulator, and this condition kept one hour.Subsequently, V _gBe set as 0 V.Then, at 25 ℃ underlayer temperature and the V of 10 V _DsMeasure transistorized V _g-I _dCharacteristic.This process is called positive BT test.

Similarly, at first, at the V of 25 ℃ underlayer temperatures and 10 V _DsMeasure transistorized V _g-I _dCharacteristic.Then, underlayer temperature is arranged on 150 ℃, and V _DsBe set as 0.1 V.After this, apply the V of-20 V _g, be-2 MV/cm so that be applied to the electric field intensity of gate insulator, and this condition kept one hour.Subsequently, V _gBe set as 0 V.Then, at 25 ℃ underlayer temperature and the V of 10 V _DsMeasure transistorized V _g-I _dCharacteristic.This process is called negative BT test.

Figure 38 A and Figure 38 B illustrate respectively the result of the negative BT test of the result of positive BT test of sample 1 and sample 1.Figure 39 A and Figure 39 B illustrate respectively the result of the negative BT test of the result of positive BT test of sample 2 and sample 2.

The side-play amount of the threshold voltage of the sample 1 that the positive BT test of cause causes and the side-play amount of testing the threshold voltage of the sample 1 that causes because of negative BT are respectively 1.80 V and-0.42 V.The side-play amount of the threshold voltage of the sample 2 that the positive BT test of cause causes and the side-play amount of testing the threshold voltage of the sample 2 that causes because of negative BT are respectively 0.79 V and 0.76 V.We find, in each of sample 1 and sample 2, threshold voltage before the BT test and the side-play amount between after the BT test little, and its reliability is high.

Thermal treatment can be carried out in oxygen atmosphere; In addition, thermal treatment can be at first carried out in the atmosphere of nitrogen or inert atmosphere or reducing under the pressure, and then carries out in the oxygen containing atmosphere of bag.By carrying out in this atmosphere, oxygen can offer oxide semiconductor film superfluously.After dehydration or dehydrogenation, oxygen is offered oxide semiconductor film, can further improve heat treated effect thus.Method as be used for providing oxygen after dehydration or dehydrogenation can adopt a kind of method, and wherein oxonium ion accelerates by electric field and injects oxide semiconductor film.Thus, can with oxygen excess offer oxide semiconductor film.

The defective that causes because of oxygen defect is easy in oxide semiconductor or at oxide semiconductor and be contacted with causing at the interface between the film of oxide semiconductor; But, when in oxide semiconductor, comprising excess oxygen by thermal treatment, can adopt excess oxygen to compensate the oxygen defect that causes later.Excess oxygen mainly is the oxygen that is present between the lattice.When being set as, superfluous oxygen concentration is greater than or equal to 1 * 10 ¹⁶/ cm ³But be less than or equal to 2 * 10 ²⁰/ cm ³The time, excess oxygen can be included in the oxide semiconductor and not cause crystal lattice distortion etc.

When heat-treating so that oxide semiconductor at least part of when comprising crystal, can access more stable oxide semiconductor film.For example, analyzing by X-ray diffraction (XRD) by being that the target of In:Sn:Zn=1:1:1 carries out sputter and when having a mind to oxide semiconductor film that heated substrate forms, observes halation pattern (halo pattern) with ratio of components.Formed oxide semiconductor film can be by coming crystallization through bakingout process.Heat treated temperature can suitably arrange; For example, when thermal treatment when carrying out for 650 ℃, in X-ray diffraction analysis, can observe clearly diffraction peak.

Carry out the XRD analysis of In-Sn-Zn-O film.XRD analysis is carried out with the X-ray diffraction meter D8 ADVANCE that Bruker AXS makes, and measures by method outside the plane (out-of-plane method).

Prepare sample A and sample B, and it is carried out XRD analysis.The below will describe a kind of method for the manufacture of sample A and sample B.

Thickness is that the In-Sn-Zn-O film of 100 nm forms in the quartz substrate of having passed through the dehydrogenation processing.

The In-Sn-Zn-O film adopts sputtering equipment to form in oxygen atmosphere with the power of 100 W (DC).Atomic ratio is that the In-Sn-Zn-O target of In:Sn:Zn=1:1:1 is used as target.Note, the substrate heating temperature during film forms is set as 200 ℃.The sample of making like this is as sample A.

Subsequently, the sample by the method manufacturing similar to the manufacture method of sample A is through 650 ℃ thermal treatment.As thermal treatment, the thermal treatment in the blanket of nitrogen was at first carried out one hour, and the thermal treatment in the oxygen atmosphere further carried out one hour, and did not reduce temperature.The sample of making like this is as sample B.

Figure 42 illustrates the XRD spectrum of sample A and sample B.In sample A, do not observe from the drawn peak value of crystal, and spend when spending to 38 and observe from the drawn peak value of crystal when 2 θ are approximately 35 degree and 37 in sample B.

As mentioned above, by having a mind to heated substrate and/or heat-treat during In, Sn and Zn form as the film of the oxide semiconductor of principal ingredient comprising after forming film, transistorized characteristic can be improved.

The heating of these substrates and thermal treatment have the effect that prevents as the hydrogen of the disadvantageous impurity of oxide semiconductor and hydroxyl being comprised in the film, the perhaps effect of removal hydrogen and hydroxyl from film.That is to say, can come highly purified oxide semiconductor by the hydrogen of from oxide semiconductor, removing as donor impurity, can access the normal off transistor thus.The highly purified of oxide semiconductor makes transistorized off state current can be less than or equal to 1 aA/ μ m.Here, the electric current of every micron channel width of unit representation of off state current.

Relation between the inverse of the underlayer temperature (absolute temperature) when Figure 43 illustrates transistorized off state current and measurement.Here, for the sake of brevity, the inverse of the underlayer temperature when transverse axis represents to measure multiply by 1000 and the numerical value (1000/T) that obtains.

Specifically, as shown in figure 43, when underlayer temperature was respectively 125 ℃, 85 ℃ and room temperature (27 ℃), off state current can be less than or equal to 1 aA/ μ m (1 * 10 ^-18A/ μ m), be less than or equal to 100 zA/ μ m (1 * 10 ^-19A/ μ m) and be less than or equal to 1 zA/ μ m (1 * 10 ^-21A/ μ m).Preferably, off state current can be less than or equal to respectively 0.1 aA/ μ m (1 * 10 125 ℃, 85 ℃ and room temperature ^-19A/ μ m), be less than or equal to 10 zA/ μ m (1 * 10 ^-20A/ μ m) and be less than or equal to 0.1 zA/ μ m (1 * 10 ^-22A/ μ m).

Note, in order to prevent that hydrogen and moisture are comprised in the oxide semiconductor film during oxide semiconductor film forms, preferably by fully suppressing to improve the purity of sputter gas from the leakage of film formation chamber outside and the degasification of passing through film formation chamber's inwall.For example, dew point is less than or equal to-70 ℃ gas preferably as sputter gas, is comprised in the film in order to prevent moisture.In addition, preferably use highly purified target, in order to do not comprise the impurity such as hydrogen and moisture.Although might from comprise In, Sn and the Zn film as the oxide semiconductor of principal ingredient, remove moisture by thermal treatment, but preferably form the film that does not comprise moisture at first, because divide used temperature than dividing used temperature higher from comprising In, Ga and Zn as releasing water the oxide semiconductor of principal ingredient from comprising In, Sn and Zn as releasing water the oxide semiconductor of principal ingredient.

The transistorized underlayer temperature of the heat treated sample B formation of it being carried out 650 ℃ and the relation between the electrical specification are used after forming oxide semiconductor film in assessment.

The transistorized channel length L that is used for measuring is 3 μ m, and channel width W is 10 μ m, and Lov is 0 μ m, and dW is 0 μ m.Note V _DsBe set as 10 V.Note, underlayer temperature is-40 ℃ ,-25 ℃, 25 ℃, 75 ℃, 125 ℃ and 150 ℃.Here, in transistor, wherein the width of an overlapping part in gate electrode and the pair of electrodes is called Lov, and pair of electrodes be not called dW with the width of the overlapping part of oxide semiconductor film.

Figure 40 illustrates I _dThe V of (solid line) and field-effect mobility (dotted line) _gDependence.Figure 41 A illustrates the relation between underlayer temperature and the threshold voltage, and Figure 41 B illustrates the relation between underlayer temperature and the field-effect mobility.

Find from Figure 41 A, threshold voltage increases and step-down with underlayer temperature.Note, threshold voltage is being reduced to-0.23 V from 1.09 V within-40 ℃ to 150 ℃ scope.

Find from Figure 41 B, field-effect mobility increases and step-down with underlayer temperature.Note, field-effect mobility within-40 ℃ to 150 ℃ scope from 36 cm ²/ Vs is reduced to 32 cm ²/ Vs.Therefore find, the variation of electrical specification is medium and small in the said temperature scope.

Comprise In, Sn and Zn as this type oxide semiconductor of principal ingredient as in the transistor of channel formation region, can remain on off state current and be less than or equal to 1 aA/ μ m and obtain being greater than or equal to 30 cm ²/ Vs, preferably be greater than or equal to 40 cm ²/ Vs, more preferably be greater than or equal to 60 cm ²The field-effect mobility of/Vs, this can realize the on state current that LSI is required.For example, L/W is among the FET of 33 nm/44nm therein, and when gate voltage is 2.7 V and drain voltage when being 1.0 V, the on state current that is greater than or equal to 12 μ A can flow.In addition, in the required temperature range of operate transistor, can guarantee sufficient electrical specification.By this class feature, even when the transistor that comprises oxide semiconductor also is arranged in the formed integrated circuit of use Si semiconductor, also can realizes having the integrated circuit of novel capabilities, and not reduce operating speed.

The below will describe In-Sn-Zn-O film wherein as the transistorized example of oxide semiconductor film.

Figure 44 A and Figure 44 B are coplanar transistorized top view and the sectional views with top grid top contact structure.Figure 44 A is transistorized top view.Figure 44 B illustrates along the section A-B of the dot-and-dash line A-B among Figure 44 A.

Transistor shown in Figure 44 B comprises: substrate 1200; Base insulating layer 1202 is arranged on the substrate 1200; The protection dielectric film 1204, be arranged on base insulating layer 1202 around; Oxide semiconductor film 1206 is arranged on base insulating layer 1202 and the protection dielectric film 1204, and comprises high resistance area 1206a and low-resistance region 1206b; Gate insulator 1208 is arranged on the oxide semiconductor film 1206; Gate electrode 1210 is arranged to overlapping with oxide semiconductor film 1206 and has been placed gate insulator 1208 therebetween; Side wall insulating film 1212 is arranged to contact with the side surface of gate electrode 1210; Pair of electrodes 1214 is arranged to contact with low-resistance region 1206b at least; Interlayer dielectric 1216 is arranged at least capping oxide semiconductor film 1206, gate electrode 1210 and pair of electrodes 1214; And connect up 1218, be arranged to be connected to by the opening that in interlayer dielectric 1216, forms at least one of pair of electrodes 1214.

Although not shown, diaphragm can be arranged to cover interlayer dielectric 1216 and wiring 1218.By diaphragm, a small amount of leakage current that the surface conductive by interlayer dielectric 1216 generates can reduce, and thereby can reduce transistorized off state current.

The below will describe In-Sn-Zn-O film wherein as transistorized another example of oxide semiconductor film.

Figure 45 A and Figure 45 B are top view and the sectional views that transistorized structure is shown.Figure 45 A is transistorized top view.Figure 45 B is the sectional view along the dot-and-dash line A-B among Figure 45 A.

Transistor shown in Figure 45 B comprises: substrate 1600; Base insulating layer 1602 is arranged on the substrate 1600; Oxide semiconductor film 1606 is arranged on the base insulating layer 1602; Pair of electrodes 1614 contacts with oxide semiconductor film 1606; Gate insulator 1608 is arranged on oxide semiconductor film 1606 and the pair of electrodes 1614; Gate electrode 1610 is arranged to oxide semiconductor film 1606 overlappingly, has placed gate insulator 1608 therebetween; Interlayer dielectric 1616 is arranged to cover gate insulation course 1608 and gate electrode 1610; Wiring 1618 is connected to pair of electrodes 1614 by the opening that forms in interlayer dielectric 1616; And diaphragm 1620, be arranged to cover interlayer dielectric 1616 and wiring 1618.

As substrate 1600, use glass substrate.As base insulating layer 1602, use silicon oxide film.As oxide semiconductor film 1606, use the In-Sn-Zn-O film.As pair of electrodes 1614, use tungsten film.As gate insulator 1608, use silicon oxide film.Gate electrode 1610 is stepped constructions of nitrogenize tantalum film and tungsten film.Interlayer dielectric 1616 is stepped constructions of oxygen silicon nitride membrane and polyimide film.Wiring 1618 respectively has wherein titanium film, aluminium film and titanium film according to this stepped construction that sequentially forms.As diaphragm 1620, use polyimide film.

Note, in the transistor with structure shown in Figure 45 A, wherein the width of an overlapping part in gate electrode 1610 and the pair of electrodes 1614 is called Lov.Similarly, pair of electrodes 1614 does not have the width of overlapping part to be called dW with oxide semiconductor film 1606.

Embodiment 7

In the present embodiment, the semiconductor device applications described in any of above-mentioned embodiment is wherein described in the situation of electronic equipment with reference to Figure 23 A to Figure 23 F.Above-mentioned semiconductor device applications is wherein described in the present embodiment in the situation of the electronic equipment such as computing machine, mobile phone (be called not only mobile phone or portable telephone device), portable information terminal (comprising portable game, audio reproducing apparatus etc.), digital camera, Digital Video, Electronic Paper, televisor (but also being called TV or television receiver).

Figure 23 A illustrates notebook-sized personal computer, and it comprises framework 701, framework 702, display part 703, keyboard 704 etc.Semiconductor device described in any of above-mentioned embodiment is arranged at least one of framework 701 and 702.Therefore, can realize having the notebook-sized personal computer of fully low power consumption, the writing and read and can carry out at a high speed of data wherein, and data can be stored for a long time.

Figure 23 B illustrates portable information terminal (PDA).Main body 711 is provided with display part 713, external interface 715, action button 714 etc.In addition, be provided for operating the pointer 712 of portable information terminal etc.The semiconductor device of describing in any of above-mentioned embodiment is arranged in the main body 711.Therefore, can realize having the portable information terminal of fully low power consumption, the writing and read and can carry out at a high speed of data wherein, and data can be stored for a long time.

Figure 23 C illustrates the E-book reader 720 in conjunction with Electronic Paper, and it comprises two frameworks, i.e. framework 721 and framework 723.Framework 721 and framework 723 comprise respectively display part 725 and display part 727.By hinge part 737 frameworks 721 with are connected connection so that E-book reader 720 can come opening and closing with hinge part 737.Framework 721 is provided with power switch 731, operation push-button 733, loudspeaker 735 etc.Framework 721 and 723 at least one be provided with the semiconductor device described in any of above-mentioned embodiment.Therefore, can realize having the E-book reader of fully low power consumption, the writing and read and can carry out at a high speed of data wherein, and data can be stored for a long time.

Figure 23 D illustrate comprise two frameworks, be the mobile phone of framework 740 and framework 741.In addition, the

framework

740 and 741 that is in the state that forms shown in Figure 23 D can be slided, so that one is overlapped on another.Therefore, the size of mobile phone can reduce, and this makes mobile phone be fit to carry.Framework 741 comprises display panel 742, loudspeaker 743, microphone 744, operation push-button 745, indicator device 746, camera lens 747, external connection terminals 748 etc.Framework 740 comprises the solar cell 749 that is used to mobile phone charging, exterior storage groove 750 etc.In addition, antenna is combined in the framework 741.Semiconductor device described in any of above-mentioned embodiment is arranged at least one of framework 740 and 741.Therefore, can realize having the mobile phone of fully low power consumption, the writing and read and can carry out at a high speed of data wherein, and data can be stored for a long time.

Figure 23 E illustrates digital camera, and it comprises main body 761, display part 767, eyepiece 763, operating switch 764, display part 765, battery 766 etc.Semiconductor device in any of above-mentioned embodiment is arranged in the main body 761.Therefore, can realize having the digital camera of fully low power consumption, the writing and read and can carry out at a high speed of data wherein, and data can be stored for a long time.

Figure 23 F is the televisor 770 that comprises framework 771, display part 773, support 775 etc.Televisor 770 can be by being included in the switch in the framework 771 or operating by telepilot 780.Semiconductor device described in any of above-mentioned embodiment is installed in framework 771 and the telepilot 780.Therefore, can realize having the televisor of fully low power consumption, the writing and read and can carry out at a high speed of data wherein, and data can be stored for a long time.

As mentioned above, the electronic equipment described in the present embodiment respectively comprises according to any the semiconductor device in the above-mentioned embodiment.Therefore can realize having the electronic equipment of low power consumption.

Description of reference numerals

120: semiconductor layer; 122: insulation course; 122a: gate insulator; 124: mask; 126: impurity range; 128a: gate electrode; 128b: conductive layer; 130: impurity range; 132: impurity range; 134: channel formation region; 136: insulation course; 138: insulation course; 140: insulation course; 142a: source electrode; 142b: drain electrode; 144: oxide semiconductor layer; 146: gate insulator; 148a: gate electrode; 148b: conductive layer; 150: insulation course; 154: wiring; 156: insulation course; 160: transistor; 162: transistor; 164: capacitor; 170: storage unit; 201: memory cell array; 202: column drive circuit; 203: horizontal drive circuit; 204: controller; The 205:I/O control circuit; 206: counter; 207: potential generation circuit; 221: bit line and source line driving circuit; 222: column decoder; 223a: analog switch; 223b: analog switch; 224: circuit; 225: circuit; 226: the latch group; 227: latch; 228: selector switch; 229: selector switch; 230: impact damper; 231: gate line and electric capacity line drive circuit; 232: line decoder; The 321:NAND circuit; 322: level translator; 323: load; 324: sensor amplifier; The 325:NAND circuit; The 331:NAND circuit; 332: level translator; The 333:NAND circuit; 334: level translator; 335: multiplexer; 336: multiplexer; 400: insulation course; 401: gate electrode; 402: gate insulator; 403: oxide semiconductor layer; 404a: oxide conducting layer; 404b: oxide conducting layer; 405a: source electrode; 405b: drain electrode; 410: transistor; 420: transistor; 427: insulation course; 430: transistor; 437: insulation course; 440: transistor; 441: transistor; 442: transistor; 450a: crystalline oxides semiconductor layer; 450b: crystalline oxides semiconductor layer; 453: oxide semiconductor layer; 500: Semiconductor substrate; 510: single crystal semiconductor substrate; 512: oxide film; 514: the embrittlement district; 516: single-crystal semiconductor layer; 518: single-crystal semiconductor layer; 701: framework; 702: framework; 703: the display part; 704: keyboard; 711: main body; 712: pointer; 713: the display part; 714: action button; 715: external interface; 720: E-book reader; 721: framework; 723: framework; 725: the display part; 727: the display part; 731: power switch; 733: operation push-button; 735: loudspeaker; 737: hinge part; 740: framework; 741: framework; 742: display panel; 743: loudspeaker; 744: microphone; 745: operation push-button; 746: indicator device; 747: camera lens; 748: external connection terminals; 749: solar cell; 750: the exterior storage groove; 761: main body; 763: eyepiece; 764: operating switch; 765: the display part; 766: battery; 767: the display part; 770: televisor; 771: framework; 773: the display part; 775: support; 780: telepilot; 1101: base insulating layer; 1102: the inserted insulation body; 1103a: semiconductor region; 1103b: semiconductor region; 1103c: semiconductor region; 1104: gate insulator; 1105: grid; 1106a: side wall insulator; 1106b: side wall insulator; 1107: insulator; 1108a: source electrode; 1108b: drain electrode; 1200: substrate; 1202: base insulating layer; 1204: the protection dielectric film; 1206: oxide semiconductor film; 1206a: high resistance area; 1206b: low-resistance region; 1208: gate insulator; 1210: gate electrode; 1212: side wall insulating film; 1214: electrode; 1216: interlayer dielectric; 1218: interlayer dielectric; 1600: substrate; 1602: base insulating layer; 1606: oxide semiconductor film; 1608: gate insulator; 1610: gate electrode; 1614: electrode; 1616: interlayer dielectric; 1618: wiring; 1620: diaphragm.

The application is incorporated in this with its complete content by reference based on the Japanese patent application No. 2010-178168 that was submitted to Japan Office on August 6th, 2010 and the Japanese patent application No. 2011-108190 that was submitted to Japan Office on May 13rd, 2011.

Claims

1. semiconductor device comprises:

The memory cell array that comprises m * n storage unit;

Driving circuit; And

Potential generation circuit,

Wherein, one of described storage unit comprises:

The first transistor that comprises first grid electrode, the first source electrode, the first drain electrode and the first channel formation region; And

The transistor seconds that comprises second gate electrode, the second source electrode, the second drain electrode and the second channel formation region,

Described the first channel formation region comprises the semiconductor material different from the material of described the second channel formation region,

Described driving circuit described storage unit each row in comprise the latch section of K position and have the write circuit of the multiplexer of K position,

And the said write circuit is connected to the latch section of described potential generation circuit and described K position.

2. semiconductor device according to claim 1, wherein said the first transistor is the p channel transistor, and described transistor seconds is the n channel transistor.

3. semiconductor device according to claim 1, described second channel formation region of wherein said transistor seconds comprises oxide semiconductor.

4. semiconductor device comprises:

The memory cell array that comprises m * n storage unit;

The first driving circuit;

The second driving circuit;

Potential generation circuit;

Bit line;

Source electrode line; And

Gate line,

Wherein, one of described storage unit comprises:

Described the first driving circuit described storage unit each row in comprise the latch section of K position and have the write circuit of the multiplexer of K position,

5. semiconductor device according to claim 4,

Wherein, described source electrode line is connected to described the first source electrode,

Described bit line is connected to described the first drain electrode and described the second drain electrode,

Described gate line is connected to described second gate electrode,

And described first grid electrode is connected to described the second source electrode.

6. semiconductor device according to claim 4, wherein said the first transistor is the p channel transistor, and described transistor seconds is the n channel transistor.

7. semiconductor device according to claim 4, described second channel formation region of wherein said transistor seconds comprises oxide semiconductor.

8. semiconductor device according to claim 4 wherein between described bit line and described source electrode line, comprises that a plurality of storage unit of one of described storage unit are connected in parallel.

9. semiconductor device according to claim 4 wherein between described bit line and described source electrode line, comprises that a plurality of storage unit series connection of one of described storage unit connect.

10. semiconductor device according to claim 4, wherein said potential generation circuit is connected to described the first driving circuit and described the second driving circuit.

11. a semiconductor device comprises:

The memory cell array that comprises m * n storage unit;

The first driving circuit;

The second driving circuit;

The counter of K position (K is natural number);

Potential generation circuit;

Bit line;

Source electrode line; And

Gate line,

Wherein, one of described storage unit comprises:

Described the first driving circuit comprises latch section and the reading circuit of K position in each row of described storage unit,

The counter of described K position is connected to described reading circuit,

And described reading circuit is connected to the latch section of described K position.

12. semiconductor device according to claim 11,

Described gate line is connected to described second gate electrode,

13. semiconductor device according to claim 11, wherein said the first transistor are the p channel transistor, and described transistor seconds is the n channel transistor.

14. semiconductor device according to claim 11, described second channel formation region of wherein said transistor seconds comprises oxide semiconductor.

15. semiconductor device according to claim 11 wherein between described bit line and described source electrode line, comprises that a plurality of storage unit of one of described storage unit are connected in parallel.

16. semiconductor device according to claim 11 wherein between described bit line and described source electrode line, comprises that a plurality of storage unit series connection of one of described storage unit connect.

17. semiconductor device according to claim 11,

Wherein, described reading circuit comprises load, sensor amplifier and NAND circuit,

Described sensor amplifier is connected to an input of described NAND circuit,

The storer read line is connected to another input of described NAND circuit,

And the latch section of described K position is connected to the output of described NAND circuit.

18. semiconductor device according to claim 11, wherein said potential generation circuit are connected to described the first driving circuit and described the second driving circuit.

19. semiconductor device according to claim 11, the counter of wherein said K position is electrically connected to the input of the latch section of described K position.

20. a semiconductor device comprises:

The memory cell array that comprises m * n storage unit;

The first driving circuit;

The second driving circuit;

The counter of K position (K is natural number);

Potential generation circuit;

Bit line;

Source electrode line; And

Gate line,

Wherein, one of described storage unit comprises:

Described the first driving circuit in each row of described storage unit, comprise the K position latch section, have write circuit and the reading circuit of the multiplexer of K position,

The counter of described K position is connected to described reading circuit,

And the latch section of described K position is connected to said write circuit and described reading circuit.

21. semiconductor device according to claim 20,

Described gate line is connected to described second gate electrode,

22. semiconductor device according to claim 20, wherein said the first transistor are the p channel transistor, and described transistor seconds is the n channel transistor.

23. semiconductor device according to claim 20, described second channel formation region of wherein said transistor seconds comprises oxide semiconductor.

24. semiconductor device according to claim 20 wherein between described bit line and described source electrode line, comprises that a plurality of storage unit of one of described storage unit are connected in parallel.

25. semiconductor device according to claim 20 wherein between described bit line and described source electrode line, comprises that a plurality of storage unit series connection of one of described storage unit connect.

26. semiconductor device according to claim 20,

Described sensor amplifier is connected to an input of described NAND circuit,

The storer read line is connected to another input of described NAND circuit,

27. semiconductor device according to claim 20, wherein said potential generation circuit are connected to described the first driving circuit and described the second driving circuit.

28. semiconductor device according to claim 20, the counter of wherein said K position is electrically connected to the input of the latch section of described K position.