JP3479375B2 - Nitrous metal oxide to form a thin film transistor and a pn junction by the metal oxide semiconductor of copper oxide such as a semiconductor device and a method for their preparation - Google Patents

Nitrous metal oxide to form a thin film transistor and a pn junction by the metal oxide semiconductor of copper oxide such as a semiconductor device and a method for their preparation

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JP3479375B2
JP3479375B2 JP06827095A JP6827095A JP3479375B2 JP 3479375 B2 JP3479375 B2 JP 3479375B2 JP 06827095 A JP06827095 A JP 06827095A JP 6827095 A JP6827095 A JP 6827095A JP 3479375 B2 JP3479375 B2 JP 3479375B2
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metal oxide
oxide semiconductor
thin film
metal
film transistor
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英樹 松村
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科学技術振興事業団
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66969Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Description

【発明の詳細な説明】 【0001】 【産業上の利用分野】本発明は,亜酸化銅等の金属酸化物半導体による薄膜トランジスタとpn接合を形成した金属酸化物半導体装置およびそれらの製造方法に関するものである。 BACKGROUND OF THE INVENTION [0001] BACKGROUND OF THE INVENTION This invention relates to methods a metal oxide semiconductor device to form a thin film transistor and a pn junction by a metal oxide semiconductor and their manufacture such as cuprous oxide it is. 【0002】薄膜トランジスタは液晶ディスプレイ,集積回路,ファクシミリ制御回路等の半導体エレクトロニクスの分野において広く使用されている。 [0002] thin film transistor liquid crystal displays, integrated circuits, widely used in the field of semiconductor electronics such as a facsimile control circuit. 本発明は,このような薄膜トランジスタおよびpn接合を有する薄膜半導体装置を金属酸化物半導体により構成したものである。 The present invention is a thin film semiconductor device having such a thin film transistor and a pn junction is obtained constituted by a metal oxide semiconductor. 【0003】 【従来の技術】液晶ディスプレイ等に使用されるトランジスタは,画素毎に付けられたスイッチング用の薄膜トランジスタと画面全体を制御する高移動度のトランジスタの2種類のトランジスタを必要とする。 [0003] The transistor used in the Prior Art Liquid crystal displays or the like requires two transistors of the transistor of the high mobility of controlling the entire thin film transistor and a screen for switching attached to each pixel. 従来は,このようなトランジスタを得るためにアモルファスシリコンに形成した画素スイッチ用薄膜トランジスタと単結晶シリコンに形成した画面制御用のトランジスタ集積回路を同一基板に貼り合わせるという方法が取られていた。 Conventionally, a method of bonding such transistors the transistor integrated circuits for screen control formed on the thin film transistor and a single crystal silicon pixel switch formed in the amorphous silicon in order to obtain the same substrate has been adopted. そのため配線が複雑になり,液晶ディスプレイのコストを押し上げる要因になっていた。 Therefore wiring is complicated, it had become a factor in pushing up the cost of the liquid crystal display. 【0004】そこで,画素スイッチ用薄膜トランジスタの製造時に,ディスプレイ用のガラス基板に画面制御用のトランジスタを形成するための様々な方法が開発されてきた。 [0004] Therefore, at the time of manufacture of the thin film transistor for pixel switching, various methods for forming a transistor for glass substrates to screen control for the display have been developed. 例えば,レーザ熱処理を用いてポリシリコンを作り,それを用いて高移動度の薄膜トランジスタを作る方法等である。 For example, to make a poly silicon using a laser heat treatment, a method, or the like, which creates a high mobility of the thin film transistor using the same. しかし,この方法は大面積化に必ずしも有効ではなく安価なガラス基板を使用して低温で作成できる薄膜トランジスタの製造方法の開発が望まれている。 However, this method has been desired to develop a method of manufacturing the thin film transistor can be created at low temperatures using an inexpensive glass substrate without necessarily effective in a large area. 【0005】 【発明が解決しようとする課題】従来のシリコン半導体薄膜を使用した薄膜トランジスタは上記のように,安価なガラス基板を使用して大面積にわたって低温で形成することは困難であった。 [0005] Using INVENTION Problems to be Solved conventional silicon semiconductor thin thin film transistor as described above, it is difficult to form at a low temperature over a large area by using an inexpensive glass substrate. また,半導体集積回路の微細化は年々進み,新しい構造のデバイスの開発が必要とされている。 Further, miniaturization of the semiconductor integrated circuit proceeds year by year, the development of devices of a new structure is required. 【0006】本発明は,このような課題を解決することのできる新しい構造の金属酸化物半導体による薄膜トランジスタと金属酸化物半導体にpn接合を形成した薄膜半導体装置およびそれら製造方法を提供する。 [0006] The present invention provides a new metal oxide structure semiconductor thin film semiconductor device to form a pn junction in the thin film transistor and the metal oxide semiconductor by and their production method that can solve such problems. そして, And,
従来はあまり省みられなかった亜酸化銅等の金属酸化物半導体に新しい観点を見出し,半導体集積回路に新しい技術をもたらすものである。 Conventionally find new perspective on a metal oxide semiconductor such as cuprous oxide was not so much reflect on those that result in the new technologies in the semiconductor integrated circuit. 【0007】 【課題を解決するための手段】亜酸化銅,酸化亜鉛,酸化アルミニム等の金属酸化物が半導体であることは周知のことである。 [0007] Means for Solving the Problems] cuprous oxide, it zinc oxide, a metal oxide such as Aruminimu is a semiconductor is well known. そして,例えば,亜酸化銅の場合,銅板をアルゴンと酸素ガスを用いてスパッタすることや,銅板を単純に熱酸化することなどによって得ることができる。 Then, for example, the case of the cuprous oxide can be obtained or be sputtered using argon and oxygen gas copper plate, such as by simply thermally oxidized copper plates. 金属酸化物半導体は,このように簡単に作れ,かつ,大面積化も容易であることから太陽電池への応用が考えられてきたが,亜酸化銅などでは金属酸化物中の過剰酸素による欠陥の作るアクセプタの密度の制御が少なくとも従来はできなかったので,pn接合ができず,そのため,亜酸化銅等の金属酸化物半導体は半導体研究の主流から忘れさられ,半導体装置として実用化をされていなかった。 Defective metal oxide semiconductor is thus easy to make, and, due to the excess oxygen in the larger area also applicable to a solar cell because it is easy but has been considered, in such cuprous oxide in the metal oxide making since control the density of the acceptor can not be at least prior the unable pn junction, therefore, a metal oxide semiconductor such as cuprous oxide being forgotten from mainstream semiconductor research, is the practical use as a semiconductor device It did not. 【0008】ところで,この金属酸化物半導体にも注目すべき長所があり,亜酸化銅の場合,低温で作成したにもかかわらずそのキャリヤ移動度は数10cm 2 /Vs By the way, there are advantages also noteworthy in this metal oxide semiconductor, when the cuprous oxide, the number despite its carrier mobility created in cold 10 cm 2 / Vs
と比較的に大きいものである。 If those relatively large. さらに,このような金属酸化物半導体は,金属膜を後から低温酸化しても得ることができる。 Furthermore, such a metal oxide semiconductor is capable of later metal film obtained even when low-temperature oxidation. つまり,金属薄膜の一部を局所的に金属酸化物半導体に変えることかできる。 In other words, either locally changing the metal oxide semiconductor part of the metal thin film. このことは,亜酸化銅等の金属酸化物を用いた薄膜トランジスタ等の電子デバイスの製作工程を簡略することができるばかりか,新しい超微細構造のデバイスの製作を容易ならしめるもので,シリコン等の金属酸化物半導体以外の半導体を用いたのでは 実現できないことである。 This is not only can be simplified fabrication process of the electronic device such as a thin film transistor using a metal oxide such as cuprous oxide, in which makes it easier to manufacture the device of a new ultrastructural, such as silicon than using a semiconductor other than the metal oxide semiconductor is that it can not achieve. 【0009】本発明は,このような金属酸化物半導体により薄膜トランジスタを作成するようにした。 [0009] The present invention was to create a thin film transistor by such a metal oxide semiconductor. また,亜酸化銅等の金属酸化物半導体の一部で知られている過剰な酸素による欠陥に対して水素等を導入することで欠陥を制御して,キャリヤ密度および導電型を制御するようにし,そのように制御された金属酸化物半導体に対して,不純物をドープし良好なpn接合が得られるようにした。 Further, by controlling the defect by introducing hydrogen or the like against defects due to excessive oxygen known in the portion of the metal oxide semiconductor, such as cuprous oxide, so as to control the carrier density and conductivity type , for such controlled metal oxide semiconductor, and as impurities doped good pn junction is obtained. さらに逆に酸素が不足することで欠陥が生じている酸化亜鉛等の金属酸化物半導体に対しては酸素,水素等を導入することにより欠陥を制御して,キャリヤ密度および導電型を制御するようにし,そのように制御された金属酸化物半導体に対して,不純物をドープし良好なpn接合が得られるようにした。 Further oxygen for metal oxide semiconductor zinc oxide or the like defect has occurred by insufficient oxygen Conversely, by controlling the defect by introducing hydrogen or the like, to control the carrier density and conductivity type to, for such controlled metal oxide semiconductor, and as impurities doped good pn junction is obtained. 【0010】図1は本発明の基本構成(1) を薄膜トランジスタをゲート電極を持つ構造の場合について例示的に示し,その製造方法の原理を説明するものである。 [0010] Figure 1 is a basic configuration of (1) for the case of the structure having a gate electrode a thin film transistor exemplarily shown in the present invention, is intended to explain the principles of the manufacturing process. 図1 Figure 1
(a), (b)において,1は基板である。 (A), in (b), 1 is a substrate. 【0011】2は電極金属である。 [0011] 2 is an electrode metal. 3は絶縁膜である。 3 is an insulating film.
4は金属膜であって,銅,亜鉛等の酸化処理をすることにより半導体となるものである。 4 is a metal film is to be the semiconductor by copper, the oxidation of the zinc. 金属膜の膜厚は,例えば,0.3μm程度であり,酸化処理後は0.6μm程度の薄膜である。 Thickness of the metal film is, for example, about 0.3 [mu] m, after oxidation treatment is a thin film of about 0.6 .mu.m. 【0012】5は金属膜4を酸化処理することにより生成した金属酸化物半導体である。 [0012] 5 is a metal oxide semiconductor produced by oxidizing the metal film 4. 図1 (a)の構造に対して,保護膜(図示せず)を形成して引き出し電極を形成することにより,例えば電極金属2をゲート電極とする薄膜トランジスタを作成することができる。 To the structure of FIG. 1 (a), by forming the lead electrode by forming a protective film (not shown), it can be prepared, for example a thin film transistor which the electrode metal 2 and the gate electrode. 【0013】図1 (b)は図1 (a)の構造の製造方法を示す。 [0013] FIG. 1 (b) shows a manufacturing method of the structure of FIG. 1 (a). 図示の番号の順に製造方法を説明する。 The manufacturing method will be described in the order of the illustrated numbers. (1) 絶縁物,シリコン半導体等の基板1に電極金属2 (1) insulator, the electrode metal 2 on the substrate 1 of silicon semiconductors,
を形成し,絶縁膜3で被覆する。 It is formed and is covered with an insulating film 3. 【0014】(2) 絶縁膜3の上に,例えば,銅,亜鉛等の金属膜4を形成する。 [0014] (2) on the insulating film 3, for example, to form a copper, a metal film 4 such as zinc. (3) 金属膜4の一部の領域をイオン注入,熱酸化,プラズマ酸化等で酸化処理する。 (3) Ion implantation a portion of a region of the metal film 4, thermal oxidation, an oxidation treatment by plasma oxidation. 【0015】さらに,必要ならば,金属酸化物半導体領域に対して,水素を導入する等で金属酸化物半導体の過剰な酸素による欠陥を制御して,キャリヤ密度および導電型を制御するようにする。 Furthermore, if necessary, the metal oxide semiconductor region, and controls the defects due to excess oxygen of the metal oxide semiconductor at such introducing hydrogen, so as to control the carrier density and conductivity type . あるいは,酸素が不足したことにより欠陥を生じている場合には,酸素もしくは水素等を導入することにより欠陥を制御して,キャリヤ密度および導電型を制御するようにする。 Alternatively, if the oxygen is caused a defect by insufficient controls the defect by introducing oxygen or hydrogen or the like, so as to control the carrier density and conductivity type. 【0016】図2は本発明の基本構成(2) であり,pn [0016] Figure 2 is a basic configuration of the present invention (2), pn
接合を持つ金属酸化物半導体についての原理的構造と製造方法を説明するものである。 Principle structure and a manufacturing method for a metal oxide semiconductor having a junction illustrates the. 図2 (a)は原理的構造であり,図2 (b)はその製造方法の原理を示す。 2 (a) it is a principle structure, FIG. 2 (b) shows the principle of the manufacturing method. 【0017】図2 (a)において,11は基板である13 [0017] In FIG. 2 (a), 11 is a substrate 13
は金属酸化物半導体であって,第1の導電型の半導体である。 It is a metal oxide semiconductor, a semiconductor of a first conductivity type. 【0018】15は接合部である。 [0018] 15 is a junction. 16は金属酸化物半導体であって,第2の導電型の半導体である。 16 is a metal oxide semiconductor, a semiconductor of a second conductivity type. 図2 (a) FIGS. 2 (a)
に対して,保護膜,電極を形成することによりダイオードとし,あるいは接合の数を増やしてトランジスタとする等で半導体装置とすることができる。 Respect, the protective film, and a diode by forming an electrode, or may be a semiconductor device in such a transistor by increasing the number of bonding. 【0019】図2 (b)は図2 (a)の原理的構造の製造方法である。 [0019] FIG. 2 (b) is a method for producing a principle structure of FIG. 2 (a). 図2(b) において,11は基板である。 In FIG. 2 (b), 11 denotes a substrate. 【0020】12は金属膜であって,銅,亜鉛等の酸化処理することにより半導体となるものである。 [0020] 12 is a metal film is to be the semiconductor by an oxidation treatment of copper, zinc and the like. 13は金属酸化物半導体(第1の導電体)である。 13 is a metal oxide semiconductor (first conductor). 【0021】14は真性半導体化領域であって,金属酸化物半導体13に水素等を照射し,金属酸化物半導体(第1の導電体)13の過剰な酸素に対して欠陥を除去し,真性半導体化した領域である。 [0021] 14 is a intrinsic semiconductor region, the hydrogen or the like by irradiating the metal oxide semiconductor 13, the defect is removed against excess oxygen of the metal oxide semiconductor (first conductor) 13, an intrinsic it is a semiconductor of the area. あるいは酸素が不足して欠陥を生じている場合には酸素もしくは水素等を導入して欠陥を除去し,真性半導体化したものである。 Or if the oxygen is generated defects insufficient defect is removed by introducing oxygen or hydrogen or the like, is obtained by intrinsic semiconducting. 【0022】15は接合部である。 [0022] 15 is a junction. 16は第2の導電型の金属酸化物半導体であって,真性半導体化領域14に第2導電型とする不純物(例えば,塩素等)をドープした金属酸化物半導体装置である。 16 is a second conductivity type metal oxide semiconductor, impurities (e.g., chlorine, etc.) to the second conductivity type in the intrinsic semiconductor region 14 is a metal oxide semiconductor device doped with. 【0023】図2 (b)により,図2 (a)の薄膜半導体装置の製造方法について説明する。 [0023] The FIG. 2 (b), a method for manufacturing the thin film semiconductor device of FIG. 2 (a). (1) 基板11に金属膜12を形成する(例えば,厚さ0.3μm)。 (1) forming a metal film 12 on the substrate 11 (e.g., a thickness of 0.3 [mu] m). (2) 金属膜12を酸化処理し,第1の導電体型の金属酸化物半導体13とする。 (2) the metal film 12 is oxidized, and the first conductive type metal oxide semiconductor 13. 【0024】(3) 金属酸化物半導体13の酸素の過不足による欠陥を除去する等で真性半導体化する。 [0024] (3) to the intrinsic semiconductor of the like to remove the defects due to excess and deficiency of oxygen of the metal oxide semiconductor 13. (4) 真性半導体化領域14に第2の導電型の不純物をドープし,第1の導電型の金属酸化物半導体13とpn (4) a second conductivity type impurity doped intrinsic semiconductor region 14, a first conductivity type metal oxide semiconductor 13 and the pn
接合を形成する。 To form a bond. 【0025】 【作用】本発明によれば,低温処理により高移動度の薄膜トランジスタおよびpn接合を持つ金属酸化物薄膜半導体を低コストで製造することができる。 [0025] According to the present invention, it is possible to produce a metal oxide thin film semiconductor having a thin film transistor and a pn junction of high mobility by low temperature treatment at a low cost. また,後述するが,金属化酸化物半導体は高温の熱処理にも耐えるとともに高温アニールにより移動度も高くなるので,高温熱処理する集積回路技術に対しても新しい適用を可能とするものである。 As will be described later, metallized oxide semiconductor also becomes higher mobility by high-temperature annealing with withstand high-temperature heat treatment, and makes it possible to new applicable to integrated circuit technology for high-temperature heat treatment. 【0026】なお,図1の本発明の基本構成(1) では, [0026] In the basic configuration of the present invention in FIG. 1 (1),
ゲート電極を持つ構造の薄膜トランジスタについて説明したが,メタルベーストランジスタ等の他の構造の薄膜トランジスタに対しても適用できるものである。 It has been described a thin film transistor structure having a gate electrode, but is applicable also to other thin-film transistor structures, such as a metal base transistor. また, Also,
図1の本発明の基本構成によれば金属酸化物半導体の幅をトンネル電流が流れる程度にすることができるので, Since the width of the metal oxide semiconductor may be to the extent that a tunnel current flows according to the basic configuration of the present invention in FIG. 1,
この点からも本発明によれば,微小電流で高速動作する新しい集積回路技術を切り開くことができるものである。 According to even present invention from this point, but that can open up new integrated circuit technology that high-speed operation with a small current. 【0027】 【実施例】本発明の金属酸化物半導体として亜酸化銅を使用する場合について実施例を説明する。 [0027] The embodiment will be described for the case of using cuprous oxide as the metal oxide semiconductor of the embodiment of the present invention. 【0028】図3は本発明で使用する酸化物半導体の特性の例を示す図である。 [0028] FIG. 3 is a diagram showing an example of an oxide semiconductor characteristics for use in the present invention. 図3は,アルゴン中で,銅薄膜を室温でスパッタ法により堆積した後,その銅薄膜を2 3, in an argon, it was deposited by sputtering at room temperature a copper thin film, the copper thin film 2
50°C前後の温度で熱酸化して得られた亜酸化銅半導体のキャリヤ密度をホール効果により求まる移動度の関係を実測した結果を示したものである。 The carrier density of the cuprous oxide semiconductor obtained by thermal oxidation at 50 ° C before and after the temperature shows the results of actual measurement of the relationship between the mobility determined by the Hall effect. 【0029】この時,亜酸化銅の極性は,p型である。 [0029] At this time, the polarity of the cuprous oxide is a p-type.
キャリヤ密度は10 16 cm -3以下と小さく,移動度は数10cm 2 /V・sである。 Carrier density is as small as 10 16 cm -3 or less, the mobility is several 10cm 2 / V · s. このキャリヤは過剰酸素による欠陥が作るアクセプタから供給されているものであるが,この方法で作られた亜酸化銅のキャリヤ密度は低いので,酸素に作用して過剰酸素の欠陥を除去できる水素,ナトリウム,カリウム,銅,亜鉛などを10 11から10 12 cm -2ほどイオン注入することで容易にキャリヤ密度の制御が可能である。 This carrier is one that has been supplied from the acceptor to produce defects caused by excess oxygen, since the carrier concentration of the cuprous oxide made by this method is low, hydrogen can be removed defects excess oxygen acts on oxygen, sodium, potassium, possible copper, control of readily carrier density by such an ion implantation 10 11 about 10 12 cm -2 zinc. イオン注入のドープ量がこのように低いので,イオン注入によって発生する欠陥も少なく抑えることができ,400°C程度の以下の低温の熱処理でも,十分にイオン注入による欠陥を除去することができる。 Since the doping amount of ion implantation is such low, can be suppressed small defects generated by ion implantation, in the following low temperature heat treatment at about 400 ° C, it is possible to remove the defects due to sufficient ion implantation. 【0030】本発明は,このような亜酸化銅等の酸化物半導体の持つ性質に着目し,これを用いて低温で薄膜トランジスタを製造するようにしたものである。 [0030] The present invention focuses on the nature of the oxide semiconductor such as such cuprous oxide, is obtained so as to produce a thin film transistor at a low temperature by using this. なお,本発明は,亜酸化銅のみならず,酸化亜鉛,酸化アルミニウム,酸化タンタル等の他の金属酸化物半導体に対しても適用できるものである。 The present invention is applicable not cuprous oxide only, zinc oxide, aluminum oxide, but can also be applied to other metal oxide semiconductor such as tantalum oxide. 【0031】図4は本発明の実施例1であって,薄膜トランジスタである。 [0031] Figure 4 is a first embodiment of the present invention, a thin film transistor. 図4において,21はガラス基板である(図1 (a)の基板1に相当する)。 4, 21 (corresponding to the substrate 1 in FIG. 1 (a)) is a glass substrate. 【0032】22はゲート電極である(図1 (a)の電極金属2に相当する)。 [0032] 22 is a gate electrode (corresponding to the electrode metal 2 of Figure 1 (a)). 23はゲート絶縁膜である(図1 23 denotes a gate insulating film (FIG. 1
(a)の絶縁膜3に相当する)。 Corresponding to the insulating film 3 (a)). 24,24'は金属膜であって,ソース,ドレイン電極である。 24, 24 'is a metal film, a source, a drain electrode. 【0033】25は金属酸化物半導体であって,金属膜24,24'を酸化処理して得られた金属半導体である。 [0033] 25 is a metal oxide semiconductor, a metal semiconductor obtained by oxidizing the metal film 24, 24 '. 26は絶縁膜である。 26 is an insulating film. 【0034】図4において,絶縁膜26,金属酸化物半導体25の表面にさらに絶縁保護膜(図5工程(6) 参照)を形成し,ソース,ドレイン電極24,24'に接続する電極を引き出すことによりゲート電極22を持つ薄膜トランジスタとする。 [0034] In FIG. 4, the insulating film 26, an insulating protective film on the surface of the metal oxide semiconductor 25 (FIG. 5 step (6) refer) is formed, pull out the electrodes connected to the source, the drain electrodes 24, 24 ' a thin film transistor having a gate electrode 22 by. 【0035】図5は図4の薄膜トランジスタの製造方法を示す。 [0035] Figure 5 illustrates a manufacturing method of a thin film transistor of FIG. 工程(1) ガラス基板21にクロムあるいはアルミニューム等の金属を堆積し,それをフォトレジスト加工により,ゲート電極となるように成型する。 Step (1) depositing a metal such as chromium or aluminum on the glass substrate 21, a photoresist process it is molded so that the gate electrode. この工程で,まず,第1のパターンマスクを用いる。 In this step, first, using the first pattern mask. また,本発明では,全て低温度で処理するのでここに使用するガラスは高価格の高融点ガラスである必要はない。 In the present invention, any glass used herein because treatment with low temperature need not be a high-melting-point glass of high price. 【0036】工程(2) 全体にシリコン酸化膜あるいはシリコン窒化膜等のゲート絶縁膜を堆積する。 [0036] Step (2) depositing a gate insulating film such as a silicon oxide film or a silicon nitride film on the entire. 工程(3) 銅等の金属酸化物半導体となる薄膜の金属膜24,24'を堆積し,フォトレジスト加工により,ソース,ドレイン部を含めたトランジスタのパターン,およびソース,ドレインからの接続配線部のパターン(図示せず)も含めて成型する。 Step (3) depositing a thin metal film 24, 24 made of a metal oxide semiconductor such as copper ', a photoresist process, the source, the pattern of the transistor including the drain portion and the source, the connection wiring portion from the drain pattern (not shown) also molded including. この時,第2のパターンマスクを用いる。 At this time, using a second pattern mask. 【0037】工程(4) 次の酸化工程のマスクとなる膜,例えばシリコン窒化膜などを全体に堆積する。 [0037] Step (4) film serving as a mask for the next oxidation step, is deposited such throughout for example, a silicon nitride film. この時,フォトレジスト膜を用いることもできる。 At this time, it is also possible to use a photoresist film. そして, And,
これらの膜を堆積した後に,ガラス基板21の裏面より露光し,工程(1) で作成したゲート電極のパターンをマスクとしてフォトレジスト膜を露光し,その膜にフォトレジスト加工により孔を開ける。 After depositing these films were exposed from the rear surface of the glass substrate 21, exposing the photoresist film pattern of the gate electrode created in step (1) as a mask, a hole with a photoresist processed into the membrane. この工程で,薄膜トランジスタのチャネル部とゲート電極22を自己整合させる。 In this step, the channel portion and the gate electrode 22 of the thin film transistor is self-aligned. 【0038】工程(5) では,200°Cから400°C [0038] In step (5), 400 ° from the 200 ° C C
程度の間の低温で全体を熱酸化,もしくはプラズマ酸化などをすることにより,開口から露出した金属膜24を酸化し,金属酸化物半導体に変化させる(工程(4) で絶縁膜26には孔を開けられている)。 Thermally oxidizing the entire low temperature between the degree, or by a plasma oxidation, by oxidizing the metal film 24 exposed from the opening, the holes in the insulating film 26 by changing the metal oxide semiconductor (Step (4) It is open). 【0039】工程(6) 形成されたトランジスタの全体をシリコン窒化膜等の絶縁膜で被覆し,かつフォトレジスト加工により電極取り出し部に孔を開ける。 [0039] The overall process (6) formed transistors covered with an insulating film such as a silicon nitride film, and a hole in the electrode extraction portion by a photoresist process. この時, At this time,
第3のマスクパターンを用いる。 The third mask pattern is used. 【0040】上記のように,本実施例によればマスクパターンを3枚で薄膜トランジスタを製造することができる。 [0040] As described above, it is possible to manufacture a thin film transistor with three mask patterns according to this embodiment. なお,上記の工程において,工程(5) の金属膜の酸化は,酸素イオン注入の他,熱酸化,プラズマ酸化,酸素イオン照射,レーザ 酸素ドーピング等の手段により行うことができる。 In the above step, oxidation of the metal film of step (5), in addition to the oxygen ion implantation, thermal oxidation, plasma oxidation, the oxygen ion irradiation can be performed by means such as a laser oxygen doping. 【0041】また,酸素欠陥を除去することによりキャリヤ密度,導電型を制御したり,あるいは不純物ドーピングによりp,n型の導電型の制御,抵抗率等の制御をする必要がある場合には,工程(5)と工程(6)の間で,イオン注入法,イオンドーピング法,熱拡散法,プラズマ熱酸化法,あるいはレーザドーピング法等の手段で行うことができる。 Further, the carrier density by removing the oxygen defects, to control the conductivity type or p by an impurity doping, if n-type conductivity control, it is necessary to control the resistivity and the like, between steps (5) and the step (6), an ion implantation method, an ion doping method, a thermal diffusion method can be carried out by a means of plasma thermal oxidation method, or a laser doping method, or the like. 【0042】このとき,酸素過剰による欠陥(亜酸化銅の場合)を補償する目的で水素,リチウム,ナトリウム,カリウム,銅,インジウム,亜鉛等の1種もしくは複数種の不純物を金属酸化物半導体に導入し,その導体のキャリヤ密度および導電型を制御することができる。 [0042] At this time, the hydrogen in order to compensate for the excess oxygen due to defects (for cuprous oxide), lithium, sodium, potassium, copper, indium, one or more impurities such as zinc to the metal oxide semiconductor introduced, it is possible to control the carrier density and the conductivity type of the conductor.
酸素を照射した場合には欠陥が増え抵抗を増加させる。 When exposed to oxygen increases the increased defect resistance. 【0043】さらに,上記のようにキャリヤ密度および導電型が制御された金属酸化物半導体に弗素,塩素,リン,砒素,アンチモン等の元素を導入することで導電型を制御することもできる。 [0043] It is also possible to control the conductivity type by introducing fluorine, chlorine, phosphorus, arsenic, an element of antimony to the metal oxide semiconductor carrier density and conductivity type is controlled as described above. 【0044】図6は本実施例1の方法で作成された薄膜トランジスタの特性の例である。 [0044] FIG. 6 shows an example of characteristics of the thin film transistor that is created by the method of the first embodiment. 図6の特性の薄膜トランジスタは次のようなものである。 Thin film transistor characteristics shown in FIG. 6 is as follows. 金属酸化物半導体は亜酸化銅である。 Metal oxide semiconductor is cuprous oxide. ゲート絶縁膜はシリコン酸化膜であり,ゲート電極は低抵抗の結晶シリコンである。 The gate insulating film is a silicon oxide film, the gate electrode is a crystalline silicon having a low resistance. 【0045】亜酸化銅は,銅薄膜を室温でアルゴンガスを用いたスパッタ法により約80秒ほどの時間で堆積した銅薄膜を350°Cで約18分間,熱酸化することにより作られている。 The cuprous oxide, copper thin film deposited at the time of approximately 80 seconds by a sputtering method using argon gas at room temperature copper thin film 350 ° C for about 18 minutes, are made by thermally oxidizing . この薄膜トランジスタにおいては, In this thin film transistor,
チャネル長L=50μm,チャネル幅175μmである。 Channel length L = 50 [mu] m, a channel width 175 .mu.m. 図6は薄膜トランジスタのソース・ドレイン間電流I DSの平方根をゲート・ソース間電圧V GSの関数としてその特性を示している。 Figure 6 shows the characteristics of the square root of the source-drain current I DS of the TFT as a function of gate-source voltage V GS. この傾きから移動度を求めることができる。 It can be determined mobility from the slope. 図6の例は移動度が約100cm 2 /Vs Examples of 6 mobility of about 100 cm 2 / Vs
である。 It is. 【0046】本発明によれば,移動度が数10cm 2 According to the [0046] The present invention, mobility is the number 10cm 2 /
Vsから100cm 2 /Vs近くまでの大きなものが得られる。 Big things from Vs to 100cm 2 / Vs nearby is obtained. 図7は本発明の実施例2であり,メタルベーストランジスタに本発明を適用したものである。 Figure 7 is a second embodiment of the present invention, it is obtained by applying the present invention to the metal base transistor. 【0047】図7 (a)はメタルベーストランジスタの構造であり,図7 (b),図7 (c)はその製造方法を説明するものである。 [0047] FIG. 7 (a) is a structure of the metal base transistor, FIG. 7 (b), the FIG. 7 (c) illustrate the manufacturing method. 図7 (a)において,30は基板である。 In FIG. 7 (a), 30 denotes a substrate. 【0048】30'は金属膜(亜酸化銅)である。 [0048] 30 'is a metal film (nitrous oxide copper). 31 31
は金属酸化物半導体であって,亜酸化銅(p型)でありエミッタである。 Is a metal oxide semiconductor, a is the emitter and cuprous oxide (p-type). 32は金属ベースであって,銅である(厚さ約10Å〜50Å)。 32 is a metal base, a copper (thickness of about 10Å~50Å). 【0049】33は金属酸化物半導体であって,亜酸化銅(p型)でありコレクタである。 [0049] 33 is a metal oxide semiconductor, a is the collector and cuprous oxide (p-type). 図7 (a)において, In FIG. 7 (a),
電極配線は図示を省略されている。 Electrode wires are not shown. 図7 (b)により,図7 (a)のメタルベーストランジスタの製造方法を説明する。 The FIG. 7 (b), illustrating a manufacturing method for a metal base transistor of FIG. 7 (a). 金属膜として銅を使用するものとする。 It shall use the copper as the metal film. (1) 基板(ガラス,石英,シリコン等)30に銅を厚さ約0.3μm程度にスパッタ法により形成する。 (1) forming the substrate (glass, quartz, silicon, etc.) with copper 30 to a thickness of about 0.3μm by sputtering. 【0050】(2) 電気炉中で銅30”の表面を熱酸化し,厚さ0.1μmだけ銅30”を消費して約0.2μ [0050] (2) "thermally oxidizing the surface of the copper 30 by a thickness 0.1 [mu] m" copper 30 in an electric furnace at about consuming 0.2μ
mの厚さの亜酸化銅の膜31'を形成する。 To form a film 31 'of the cuprous oxide having a thickness of m. このとき, At this time,
250°Cで約15分ぐらい乾燥酸素中で熱酸化する。 About 15 minutes at 250 ° C for thermal oxidation in a dry oxygen. 【0051】(3) これに再度,銅を室温で堆積する。 [0051] (3) which again, deposit copper at room temperature.
膜厚は約0.1μmである。 The film thickness is about 0.1μm. (4) 再び,電気炉中で,新たに堆積した銅の表面のうちのほとんど全ての部分を熱酸化して亜酸化銅に変える。 (4) Again, in an electric furnace, it converted to cuprous oxide by thermally oxidizing substantially all portions of the newly deposited copper surface. このとき,酸化時間を微妙に制御して極く薄い銅の膜32'(厚さ0.001〜0.005μm)を残してメタルベーストランジスタのベースとする。 At this time, the base of the metal base transistor, leaving very thin copper film 32 '(thickness 0.001~0.005Myuemu) by delicately controlling the oxidation time. この時の熱酸化条件は,200°C,160分前後である。 Thermal oxidation conditions in this case is 200 ° C, 160 minutes before and after. 【0052】図7 (b)における酸化の過程において,図7 (c)(2) に示すように,亜酸化銅33'の表面を窒化シリコン膜で被覆すると,図7 (c)(3) のようにベース電極の取り出し口を容易にすることができる。 [0052] In the process of oxidation in FIG. 7 (b), the as shown in FIG. 7 (c) (2), when coating the surface of the cuprous oxide 33 'with the silicon nitride film, Fig. 7 (c) (3) the outlet of the base electrode can be easily as. 【0053】図8は本発明の実施例3である。 [0053] FIG 8 is a third embodiment of the present invention. 図8は, Figure 8,
ゲート電極を備える薄膜トランジスタにおいてソース・ Source in a thin film transistor comprising a gate electrode
ドレイン電極間の金属絶縁体半導体の幅をトンネル電流が流れる程度に狭くし,ゲート電圧によってトンネル電流を制御するようにしたものである。 The width of the metal insulator semiconductor between the drain electrode is narrowed to the extent that tunnel current flows is obtained by so controlling the tunneling current by the gate voltage. 【0054】図8 (a)は構造であり,図8 (b)はその特性の例である。 [0054] 8 (a) is a structure, FIG. 8 (b) are examples of characteristics. 図8 (a) 121は基板であって,ガラス,シリコン等である。 Figure 8 (a) 121 is a substrate, glass, silicon or the like. 【0055】122はゲート電極である。 [0055] 122 is a gate electrode. 123はゲート絶縁膜である。 123 is a gate insulating film. 124,124'は金属膜であって, 124, 124 'is a metal film,
ソース電極,ドレイン電極となるものである。 Source electrode, and serves as a drain electrode. 【0056】125は金属酸化物半導体である。 [0056] 125 is a metal oxide semiconductor. 126 126
はギャップであって,金属酸化物半導体の125の最小幅(金属膜124と金属膜124'の間の最小幅)であって,金属膜(ドレイン電極)124と金属膜(ソース電極)124'間の金属酸化物半導体125にトンネル電流が流れる程度のものである。 Is a gap, the minimum width of the metal oxide semiconductor 125 (the metal layer 124 and the metal film 124 'a minimum width between), a metal film (drain electrode) 124 and the metal film (source electrode) 124' a metal oxide semiconductor 125 between those of a degree that a tunnel current flows. 例えば,約0.005 For example, about 0.005
〜0.01μm程度である。 It is about ~0.01μm. 【0057】このようにすることにより,ゲート電極1 [0057] By doing so, the gate electrode 1
22の電圧によるソース・ドレイン間電流I DSの急峻な立ち上がり特性を得ることができる。 Steep rise characteristic of the source-drain current I DS by voltage 22 can be obtained. そのため,動作が高速化し,微小電流で動作することができる。 Therefore, it is possible to operate is faster, operating at a small current. 【0058】図8 (b)は図8 (a)の薄膜トランジスタの特性の例である。 [0058] FIG. 8 (b) shows an example of characteristics of the thin film transistor of FIG. 8 (a). 横軸はソース電極124'とドレイン電極124間の電圧V DSであり,縦軸はソース電極12 Horizontal axis is the voltage V DS between the drain electrode 124 and the source electrode 124 ', and the ordinate the source electrode 12
4'とドレイン電極124間の電流I DSである。 4 'and a current I DS between the drain electrode 124. パラメータはゲート電圧V GS (ソース電極124'とゲート電極124間電圧)である。 Parameter is a gate voltage V GS (voltage between the source electrode 124 'and the gate electrode 124). 【0059】例えば,ゲート電圧をV GS 'としておいてV DSをしだいに大きくするとV DS 'の電圧でソース電極124'とドレイン電極124の間にトンネル電流が流れ,図8 (b)のように立ち上がり特性の急峻な特性が得られる(V GSで制御することもできる)。 [0059] For example, a tunnel current flows between the drain electrode 124 and the source electrode 124 'in' gradually increased to the V DS the V DS keep in a 'voltage of the gate voltage V GS, as shown in FIG. 8 (b) steep characteristic of rising characteristics can be obtained (can be controlled by V GS). 【0060】図9 (a)は図9の本発明の実施例3の製造方法を示す図である。 [0060] FIG. 9 (a) is a diagram showing a manufacturing method of Example 3 of the present invention in FIG. 図9 (a),図9 (b),図9 (c)において,121は基板である。 FIG. 9 (a), in FIG. 9 (b), the FIG. 9 (c), 121 denotes a substrate. 【0061】122はゲート電極である。 [0061] 122 is a gate electrode. 123はゲート絶縁膜である。 123 is a gate insulating film. 124,124'は金属膜であって, 124, 124 'is a metal film,
ソース電極,ドレイン電極となるものである。 Source electrode, and serves as a drain electrode. 【0062】125は金属酸化物半導体である。 [0062] 125 is a metal oxide semiconductor. 128 128
はマスク用絶縁膜であって,窒化シリコン等の膜である。 Is an insulating film for a mask, a film of silicon nitride or the like. 図9 (a)の(2) は,エッチングによりマスク用絶縁膜128に開口を設けた後の状態を示す。 (2) in FIG. 9 (a) shows a state after an opening in the mask insulating film 128 by etching. 【0063】130はフォトレジストマスクである。 [0063] 130 is a photoresist mask. 図9 (a)において, (1) 基板121にゲート電極を形成し,さらにその全面をゲート絶縁膜123で被覆する(厚さ約0.02μ In FIG. 9 (a), (1) a gate electrode formed on the substrate 121, further coating the entire surface of the gate insulating film 123 (thickness of about 0.02μ
m)。 m). その上に,銅,亜鉛,アルミニュウム等の金属膜124をスパッタ法等で形成する(厚さ約0.05μ Thereon, copper, zinc, a metal film 124 such as aluminum is formed by sputtering or the like (having a thickness of about 0.05μ
m)。 m). (2) 金属膜124の全面にマスク用絶縁膜128形成する。 (2) the entire surface insulating mask film 128 formed of the metal film 124. その上にフォトレジストを塗布しマスクを使用して露光し,フォトレジストマスク130を作る。 As a photoresist is applied over the exposed using a mask, making the photoresist mask 130. そして,フォトレジストマスク130によりマスク用絶縁膜をエッチングし,図9 (a)の(2) のような開口部を持つマスク用絶縁膜128を作成する。 Then, a mask insulating film is etched by a photoresist mask 130, to create a mask insulating film 128 having an opening, such as (2) in FIG. 9 (a). このとき,エッチング特性により図8 (b)のように上部で広く,下部で狭い開口が得られるので,エッチング時間を調整することにより,マスク用絶縁膜128の開口の下部をリソグラフィの限界より狭くすることができる。 At this time, the etching characteristic wide at the top as in FIG. 8 (b), because the narrow opening at the bottom is obtained, by adjusting the etching time, the lower opening of the mask insulating film 128 smaller than the limit of lithography can do. 【0064】(3) (2) の状態において,マスク用絶縁膜128をマスクとして金属膜124を酸化し,マスク用絶縁膜を除去する。 [0064] (3) In the state of (2), the metal film 124 by oxidizing the mask insulating film 128 as a mask, removing the mask insulating film. このとき,酸化の形状は,図9 At this time, the shape of the oxide is 9
(c)に示すように開口部の上部で広く,下部で狭い形状となる。 Wide at the top of the opening as shown in (c), the narrow shape at the bottom. この性質を利用して,金属酸化物半導体125 By utilizing this property, a metal oxide semiconductor 125
の最小幅をトンネル電流が流れる程度の狭いものとすることができる。 The minimum width of the can be made narrow enough to flow a tunnel current. 【0065】図10は本発明の実施例4であって,金属酸化物半導体によりバイポーラトランジスタを構成した別の実施例である。 [0065] Figure 10 is a fourth embodiment of the present invention, which is another embodiment example in which the bipolar transistor by a metal oxide semiconductor. 本発明は,金属絶縁物半導体の酸素の過不足による欠陥を補償する目的で金属絶縁物半導体に不純物を導入することにより,キャリヤ密度および導電型を制御し,半導体装置へ適用できるようにしたものである。 The present invention, which by introducing the impurities in the metal insulator semiconductor for the purpose of compensating for the defects caused by excess or deficiency of metal insulator semiconductor oxygen to control the carrier density and conductivity types were to be applied to the semiconductor device it is. 例えば,不純物として水素,リチウム,ナトリウム,カリウム,銅,インジウム等を金属酸化物半導体に導入することにより亜酸化銅等の金属酸化物半導体の過剰な酸素による結果を除去し,キャリヤ密度,導電型を制御することができる。 For example, hydrogen as an impurity, lithium, sodium, potassium, copper, to remove the results of indium by excess oxygen of the metal oxide semiconductor, such as cuprous oxide by introducing the metal oxide semiconductor, the carrier density, conductivity type it is possible to control the. そのようにキャリヤ密度および導電型を制御した金属半導体に対して,さらに,弗素,塩素,リン,砒素,アンチモン等の元素を導入することで導電型を制御することにより良好なpn接合を作成することができる。 So against the carrier density and conductivity type controlled metal semiconductor, further creates fluorine, chlorine, phosphorus, arsenic, good pn junction by controlling the conductivity type by introducing an element of antimony be able to. 【0066】図10において,60は基板であって,ガラス,石英,シリコン等である。 [0066] In FIG. 10, 60 is a substrate, glass, quartz, silicon, or the like. 60'は金属膜(銅) 60 'metal film (copper)
である。 It is. 【0067】61は金属酸化物半導体(p型)であって,亜酸化銅でありコレクタである。 [0067] 61 is a metal oxide semiconductor (p-type), a is the collector and cuprous oxide. 62は金属酸化物半導体(n型)であって,亜酸化銅でありベースである。 62 is a metal oxide semiconductor (n-type), a is the base and cuprous oxide. 63は金属酸化物半導体(p型)であって,亜酸化銅でありエミッタである。 63 is a metal oxide semiconductor (p-type), a is the emitter and cuprous oxide. 【0068】図10において,電極の引き出し線は省略されている。 [0068] In FIG. 10, the lead wire of the electrode is omitted. 図10のバイポーラトランジスタの製造方法について説明する。 A method for manufacturing the bipolar transistor of FIG. 10. (1) 基板(ガラス,シリコン等)60に室温で銅をスパッタ法により堆積する。 (1) it is deposited by sputtering a copper at room temperature to the substrate (glass, silicon, etc.) 60. 膜厚は下部に電極として0. 0 as the electrode on the lower film thickness.
2μmの銅を残したまま,全て厚さ0.8μmの亜酸化銅とするため,0.6μm程度である。 Leaving the 2μm copper, for nitrous oxide copper of all thickness 0.8μm, it is about 0.6μm. 【0069】(2) 250°C,6時間程度乾燥酸素中で熱酸化し,0.8μmの亜酸化銅の膜を作る。 [0069] (2) is thermally oxidized at 250 ° C, about 6 hours Drying oxygen, making a film of 0.8μm in cuprous oxide. 250 250
°Cでは絶縁体である酸化銅(本発明者等の研究によりCuO)が亜酸化銅(Cu 2 O)の代わりに作られてしまうことはないことが明きらかにされている。 ° It is apparent not be C, copper oxide is an insulator (CuO studies of the present inventors) it will be made in place of the cuprous oxide (Cu 2 O). 350° 350 °
C以上の熱酸化では絶縁性の酸化銅が表面に生じる)。 Generated on the surface copper oxide insulative in C or more thermal oxidation). 【0070】(3) この亜酸化銅をアルゴンの雰囲気中で800°C,30分の熱処理をすることにより特性を向上させる(本発明者等の研究により,250°Cの熱酸化で作られた亜酸化銅は800°Cの熱処理にも耐えられ,さらにモビリティ等の特性も向上することが明らかにされている(図11参照))。 [0070] (3) The cuprous oxide to improve the properties by heat treatment at 800 ° C, 30 minutes in an atmosphere of argon (the present inventors study, made by thermal oxidation of 250 ° C cuprous oxide can withstand even a heat treatment of 800 ° C, it has been shown to further improve the characteristics such as mobility (see FIG. 11)). 【0071】(4) Li,Na,Kなどの金属,Inなどの銅サイトに入って不足銅成分を補う元素をイオン注入し,その後のアルゴン雰囲気中800°C,30分の熱処理により,n型亜酸化銅を形成する。 [0071] (4) Li, Na, metals such as K, the element to compensate for the lack copper component contained in the copper sites such as In ions are implanted by the subsequent argon atmosphere 800 ° C, 30 minutes of heat treatment, n forming a mold nitrous oxide copper. この時,n型を形成する不純物としては他に,Se,S,F,Cl, At this time, the other as an impurity to form an n-type, Se, S, F, Cl,
Br,I等が考えられる。 Br, I and the like can be considered. また,P,Si,As等も考えられる。 Moreover, P, Si, As, etc. are also contemplated. 【0072】(5) さらに(4) で作られたn型層の表面部を再度p型に反転する目的でイオン注入を行う。 [0072] (5) further performing ion implantation surface of the produced n-type layer in the purpose of re-inverted to p-type (4). その後,800°C,30分の熱処理を行う。 Thereafter, a heat treatment of 800 ° C, 30 min. ・なお,上記において,(3) ,(4) ,(5) は,図10 · In the above, (3), (4), (5), 10
(b)のようにイオン注入しておき1回の熱処理で行うことができる。 (B) it can be carried out in a heat treatment once in advance by ion implantation as. 【0073】また,工程(4) までとしてダイオードとしても良い。 [0073] Also, step (4) may be a diode with up. 図11は本発明で使用する亜酸化銅のアニール温度による亜酸化銅の特性変化を示す図である。 Figure 11 is a graph showing changes in characteristics of the cuprous oxide by the annealing temperature of the cuprous oxide used in the present invention. 【0074】図11は,アニール時間30分として,アニール温度により亜酸化銅のホール移動度,キャリヤ密度,抵抗の変化をアニール前とアニール後により比較したものである。 [0074] Figure 11 is a annealing time 30 minutes, the hole mobility of the cuprous oxide by annealing temperature, carrier density, a change in resistance is obtained by comparing the post-annealing before and annealing. 横軸はアニール温度である。 The horizontal axis is annealing temperature. 【0075】図11に示すように,亜酸化銅はアニール温度によりアニール前に比較して良好な特性に変化することが示されている。 [0075] As shown in FIG. 11, cuprous oxide as compared to before annealing has been shown to vary in good properties by the annealing temperature. 特に,800°C程度の高温でもアニールに耐え,移動度も高くなることから,高温処理の半導集積回路としても利用できることが示されている。 In particular, withstand the annealing at a high temperature of about 800 ° C, since even higher mobility, it has been shown that can be used as a semiconducting integrated circuit of the high-temperature process. 【0076】図12は本発明の実施例5であって,そのようにして,金属酸化物半導体により,バイポーラトランジスタを構成したものである。 [0076] Figure 12 is a fifth embodiment of the present invention, in that way, the metal oxide semiconductor, which is constituted of bipolar transistors. 図12において,41 12, 41
は基板である。 It denotes a substrate. 【0077】42は金属酸化物半導体(p型)であって,コレクタである。 [0077] 42 is a metal oxide semiconductor (p-type), a collector. 43は絶縁膜1である。 43 is an insulating film 1. 44は金属酸化物半導体であって,n型のベースである。 44 is a metal oxide semiconductor, an n-type base. 【0078】45は電極線1であって,金属酸化物半導体(n型)(ベース)44の引き出し線である。 [0078] 45 is an electrode wire 1, a lead wire of a metal oxide semiconductor (n-type) (base) 44. 46は絶縁膜2である。 46 is an insulating film 2. 【0079】47は金属酸化物半導体(p型)であって,エミッタである。 [0079] 47 is a metal oxide semiconductor (p-type), an emitter. 48は電極配線2であって,エミッタ47の引き出し線である。 48 is an electrode wiring 2, a lead wire of the emitter 47. 図12の実施例5のバイポーラトランジスタの製造方法について説明する。 A method for manufacturing the bipolar transistor of the fifth embodiment of FIG 12. 【0080】(1) 基板41上に金属酸化物半導体(p [0080] (1) a metal oxide semiconductor on a substrate 41 (p
型)42を形成する。 Type) 42 to forming. さらに,金属酸化物半導体42上に絶縁膜1(43)を形成する。 Further, an insulating film 1 (43) on the metal oxide semiconductor 42. (2) 絶縁膜1(43)をエッチングしてベース領域形成用の開口50を設け,前述した方法により金属酸化物半導体層42の表面に不純物をドープし,導電型をn型としてpn接合を形成する。 (2) an opening 50 for the base region form provided insulating film 1 (43) is etched, the pn junction of impurities doped into the surface of the metal oxide semiconductor layer 42, the conductive type of the n-type by the method described above Form. さらに,ベース引き出し電極線45を配線する。 Furthermore, wiring the base electrode line 45. 【0081】(3) (2) の状態で全面に絶縁膜1(4 [0081] (3) (2) states insulation over the entire surface at a film 1 (4
3)を設け,エッチングによりエミッタ領域形成用の開口51を設け,前述の導電型の制御方法によりベース領域の一部の導電型をp型にすることによりpn接合を形成する。 3) is provided, an opening 51 for the emitter region formed provided by etching to form the pn junction by a p-type part of the conductivity type of the base region under the control method of the conductive type of the above. その後,エミッタ引き出し電極47を設ける。 Then, providing the emitter electrode 47. 【0082】以後,表面保護膜(図示せず)等を形成してバイポーラトランジスタとする。 [0082] Hereinafter, a bipolar transistor by forming a surface protective film (not shown) or the like. なお,上記において,亜酸化銅等の金属酸化物半導体が,もともと内部に含む元素またはある種の物質を,中性子照射による核反応,もしくは水素原子照射による核反応など,結果的に元素またはある種の物質が酸素に変化する反応により, In the above, a metal oxide semiconductor such as cuprous oxide, originally an element or certain substances including therein the nuclear reaction by neutron irradiation, or nuclear reaction by hydrogen irradiation, resulting in elemental or certain by reaction of the substance changes in oxygen,
金属の一部または全部が反応して形成されるようにしても良い。 Part of the metal or the whole may be formed by the reaction. 【0083】 【発明の効果】本発明によれば,低温処理により高移動度の薄膜トランジスタを大面積に作成することができる。 [0083] According to the present invention, it is possible to create a thin film transistor of the high mobility by low-temperature treatment to a large area. また製造コストも低くすることができる。 Also it is possible to lower manufacturing cost. 【0084】さらに,本発明によれば金属酸化物半導体にpn接合を良好に作成することができ,pn接合を持つ金属酸化物薄膜半導体を低コストで製造することができる。 [0084] Further, according to the present invention can be satisfactorily create a pn junction to the metal oxide semiconductor, a metal oxide thin film semiconductor having a pn junction can be manufactured at a low cost. 【0085】また,本発明によれば,金属薄膜の一部をトンネル電流が流せるほどの微小な幅の金属酸化物半導体を得ることが可能なので,全く新しい原理で動作する超微細トランジスタを製作し,超LSIの集積度を飛躍的に高めかつ信号処理時間も飛躍的に速めた超LSIを製作することができる。 Further, according to the present invention, since it is possible to obtain a metal oxide semiconductor fine width of a portion of the metal thin film as flown tunnel current, produced ultrafine transistor operating in completely new principle , it is possible to manufacture a dramatically enhanced and ultra LSI for signal processing time quickened dramatically the integration degree of the super LSI.

【図面の簡単な説明】 【図1】本発明の基本構成(1) を示す図である。 It is a diagram showing the basic configuration of (1) BRIEF DESCRIPTION OF THE DRAWINGS [Figure 1] present invention. 【図2】本発明の基本構成(2) を示す図である。 2 is a diagram showing the basic configuration (2) of the present invention. 【図3】本発明で使用する金属酸化物半導体の特性の例を示す図である。 3 is a diagram showing an example of a metal oxide semiconductor characteristics for use in the present invention. 【図4】本発明の実施例1を示す図である。 4 is a diagram showing a first embodiment of the present invention. 【図5】本発明の実施例1の製造方法を示す図である。 5 is a diagram showing a manufacturing method of Example 1 of the present invention. 【図6】本発明の実施例1の特性の例を示す図である。 6 is a diagram showing an example of characteristics of Example 1 of the present invention. 【図7】本発明の実施例2を示す図である。 7 is a diagram showing a second embodiment of the present invention. 【図8】本発明の実施例3を示す図である。 8 is a diagram showing a third embodiment of the present invention. 【図9】本発明の実施例3の製造方法を示す図である。 9 is a diagram showing a manufacturing method of Example 3 of the present invention. 【図10】本発明の実施例4を示す図である。 10 is a diagram showing a fourth embodiment of the present invention. 【図11】本発明実施例のアニール温度による亜酸化銅の変化を示す図である。 11 is a graph showing changes in cuprous oxide by annealing temperature of the present invention embodiment. 【図12】本発明の実施例5を示す図である。 12 is a diagram showing a fifth embodiment of the present invention. 【符号の説明】 1:基板2:電極金属3:絶縁膜4:金属膜5:金属酸化物半導体11:基板12:金属膜13:金属酸化物半導体(第1の導電型) 14:真性半導体化領域15:接合部(pn接合) 16:金属酸化物半導体(第2の導電型) [Description of Reference Numerals] 1: substrate 2: electrode metal 3: insulating film 4: metal film 5: Metal oxide semiconductor 11: substrate 12: metal film 13: metal-oxide semiconductor (first conductivity type) 14: intrinsic semiconductor region 15: junction (pn junction) 16: metal oxide semiconductor (second conductivity type)

Claims (1)

  1. (57)【特許請求の範囲】 【請求項1】 基板上に,形成した金属薄膜を酸化処理することにより半導体化した金属酸化物半導体とを備えることを特徴とする金属酸化物半導体による薄膜トランジスタ。 (57) to the Claims 1] substrate, a thin film transistor with a metal oxide semiconductor, characterized in that it comprises a metal oxide semiconductor to which semiconductive by the formed metal thin film oxidation. 【請求項2】 基板上に備えられたゲート電極と,該ゲート電極上に絶縁膜を介して設けられた金属酸化物半導体の薄膜と,該金属酸化物半導体薄膜に接続された電極とを備えることを特徴とする請求項1に記載の金属酸化物半導体による薄膜トランジスタ。 Comprising 2. A gate electrode provided on the substrate, a thin film of a metal oxide semiconductor which is provided via an insulating film on the gate electrode, and an electrode connected to the metal oxide semiconductor thin film thin film transistor according to the metal oxide semiconductor of claim 1, wherein the. 【請求項3】 該絶縁膜上に設けた金属膜の一部を酸化して得た金属酸化物半導体の最小幅をトンネル電流が流れる程度の幅とすることを特徴とする請求項2に記載の金属酸化物半導体による薄膜トランジスタ。 Wherein wherein the minimum width of the metal oxide semiconductor obtained by oxidizing a part of the metal film provided on the insulating film in claim 2, characterized in that the width of the extent that a tunnel current flows thin film transistor due to the metal oxide semiconductor. 【請求項4】 金属酸化物半導体−金属−金属酸化物半導体構造であることを特徴とする請求項1に記載の金属酸化物半導体による薄膜トランジスタ。 4. A metal oxide semiconductor - metal - TFT with a metal oxide semiconductor of claim 1, characterized in that the metal oxide semiconductor structure. 【請求項5】 基板上に金属薄膜を設け,該金属薄膜を酸化処理することにより第1の導電型を持つ金属酸化物半導体とし,該金属酸化物半導体に第2の導電型不純物を導入して第1の導電型と第2の導電型の接合を形成し,半導体装置とすることを特徴とするpn接合を形成した金属酸化物半導体装置。 5. The metal thin film formed on a substrate, a metal oxide semiconductor having a first conductivity type by oxidation the metal thin film, a second conductive type impurity is introduced into the metal oxide semiconductor Te first conductivity type and forms a junction of the second conductivity type, metal oxide semiconductor device in which a pn junction, characterized in that the semiconductor device. 【請求項6】 酸素過剰による欠陥を補償する目的で, In 6. The purpose of compensating for defects due to oxygen excess,
    水素,リチウム,ナトリウム,カリウム,銅,亜鉛,インジウムの1種もしくは複数種の不純物を金属酸化物半導体に導入し,その金属酸化物半導体のキャリヤ密度および導電型を制御することを特徴とする請求項1,2, According to hydrogen, lithium, sodium, potassium, copper, zinc, characterized in that one or more impurities of the indium into the metal oxide semiconductor, for controlling the carrier density and the conductivity type of the metal oxide semiconductor claim 1,
    3,4に記載の金属酸化物半導体による薄膜トランジスタもしくは請求項5に記載のpn接合を形成した金属酸化物半導体装置の製造方法。 Method for producing a metal oxide semiconductor device in which a pn junction according to the thin film transistor or claim 5 with a metal oxide semiconductor according 3,4. 【請求項7】 酸素不足による欠陥を補償する目的で, In 7. purpose of compensating for defects due to oxygen deficiency,
    酸素,水素もしくは周期律表における酸素と同じ族の元素の1種もしくは複数種の不純物を金属酸化物半導体に導入し,その金属酸化物半導体のキャリヤ密度および導電型を制御することを特徴とする請求項1,2,3,4 Oxygen, one or more impurities of the same family of elements as oxygen in hydrogen or the periodic table is introduced into the metal oxide semiconductor, and controlling the carrier density and the conductivity type of the metal oxide semiconductor according to claim 1, 2, 3, 4
    に記載の金属酸化物半導体による薄膜トランジスタもしくは請求項5に記載のpn接合を形成した金属酸化物半導体装置の製造方法。 Method for producing a metal oxide semiconductor device in which a pn junction according to the thin film transistor or claim 5 with a metal oxide semiconductor described. 【請求項8】 キャリヤ密度および導電型が制御された金属酸化物半導体にイオウ、セレン,弗素,塩素,リン,砒素,アンチモンの元素を導入することで導電型を制御することを特徴とする請求項6もしくは7に記載の金属酸化物半導体による薄膜トランジスタもしくはpn 8. carrier density and conductivity types sulfur controlled metal oxide semiconductor, selenium, according to fluorine, chlorine, phosphorus, arsenic, and controlling the conductivity type by introducing an element of antimony TFT or pn by metal oxide semiconductor according to claim 6 or 7
    接合を形成した金属酸化物半導体装置の製造方法。 Method for producing a metal oxide semiconductor device forming a junction.
JP06827095A 1995-03-27 1995-03-27 Nitrous metal oxide to form a thin film transistor and a pn junction by the metal oxide semiconductor of copper oxide such as a semiconductor device and a method for their preparation Expired - Lifetime JP3479375B2 (en)

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