KR101500866B1 - Fabrication methods of low-temperature CMOS polycrystalline thin film transistor - Google Patents

Fabrication methods of low-temperature CMOS polycrystalline thin film transistor Download PDF

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KR101500866B1
KR101500866B1 KR20130127136A KR20130127136A KR101500866B1 KR 101500866 B1 KR101500866 B1 KR 101500866B1 KR 20130127136 A KR20130127136 A KR 20130127136A KR 20130127136 A KR20130127136 A KR 20130127136A KR 101500866 B1 KR101500866 B1 KR 101500866B1
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South Korea
Prior art keywords
source
drain
polycrystalline silicon
thin film
film transistor
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KR20130127136A
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Korean (ko)
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장성근
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청운대학교 인천캠퍼스 산학협력단
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

Abstract

The present invention relates to a low temperature process CMOS thin film transistor (TFT) structure and fabrication method, which improves the source and drain series resistance, source and drain contact resistance arising in the fabrication process and structure of the transistor in forming the source and drain of the CMOS TFT Forming n +, p + polycrystalline silicon simultaneously with channel silicon formation; forming n +, p + polycrystalline silicon and metal source and drain structures of the CMOS TFTs for the source and drain; Temperature process CMOS polysilicon thin film transistor fabrication process characterized by forming source and drain metals prior to formation of the source and drain regions, thereby improving the source and drain series resistance and contact resistance arising from the conventional manufacturing process and structural problems of the source and drain .

Description

[0001] Fabrication methods of low-temperature CMOS polycrystalline thin film transistors [0002]

The present invention relates to a method of manufacturing NMOS and PMOS thin film transistors essential for integrating a driving circuit into a panel in the manufacture of a CMOS process polycrystalline silicon thin film transistor liquid crystal display (TFT-LCD) panel of a low temperature process, and more particularly, TFT) structure and a manufacturing method thereof.

Thin film transistors are used as active elements in image sensors, various display devices and high speed static random access memory (SRAM) as key elements of large area displays. Currently, most thin-film transistor liquid crystal display (TFT-LCD) panels are manufactured directly on the panel, while the driver circuits are manufactured on silicon semiconductor wafers and attached to the panel. In the manufacture of thin film transistor liquid crystal display (TFT-LCD) panels, NMOS TFT and PMOS TFT devices are required in order to integrate a driving circuit to a panel. Therefore, the source and the drain of the CMOS thin film transistor are selectively formed by ion implantation of n + and p + impurities at a high concentration mostly by a long time heat treatment process. There arises a problem that the drivability is lowered due to the source and drain series resistance generated in the manufacturing process and structure of the transistor and the drain current due to the increase of the source and drain contact resistance when forming the source and drain of the top gate NMOS TFT and the PMOS TFT.

Currently, TFT thin film transistors are manufactured directly on panels in the manufacture of most display (TFT-LCD) panels, but drive circuits are manufactured on silicon semiconductor wafers and attached to panels. In order to integrate the driving circuits into the panel, it is necessary to fabricate a CMOS polycrystalline silicon thin film transistor. To this end, high concentration n + and p + impurities are implanted into the source and drain regions of the thin film transistor and formed by a long heat treatment process. Source and drain series resistances generated in the manufacturing process and structure of the transistor when forming the source and drain of the top gate NMOS TFT and the PMOS TFT and the ion implantation problem in the large area display when the source and drain regions are formed by the conventional low- And the contact resistance of the source and the drain increase, the characteristics of the polycrystalline silicon thin film transistor are deteriorated.
The manufacturing method and problems of the conventional low-temperature process CMOS polycrystalline silicon thin film transistor device will be described.

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1A to 1D are cross-sectional views illustrating a conventional method of manufacturing a CMOS polycrystalline silicon thin film transistor device. In order to manufacture a CMOS polycrystalline silicon thin film transistor, first, an amorphous silicon layer (2) and a stopper film (3) layer are formed on a substrate (1) as shown in Fig. Then, the amorphous silicon layer (2) and the etching stopper layer (3) are patterned using a predetermined photoresist pattern as a mask, thereby exposing the exposed substrate region to the etching stopper layer (3) and the amorphous silicon (2) The layers are successively etched to a predetermined depth to form the source and drain regions. Next, referring to FIG. 1B, n-type impurities are ion-implanted using an n + ion implantation mask, and p-type impurities are ion-implanted using a p + ion implantation mask to perform a solid phase crystallization The n + source and drain polycrystalline silicon 2A and the p + source and drain polycrystalline silicon 2B layers are formed, respectively.
Next, referring to FIG. 1C, a channel amorphous silicon layer 4, a gate insulating film 5, and a gate thin film 6 are sequentially formed on the entire surface of the substrate. Then, the gate thin film 6 is patterned by using a predetermined photoresist pattern as a mask, and the portion of the substrate to be exposed is exposed to the gate thin film 6, the gate insulating film 5 and the channel amorphous silicon 4 layer And etched to a predetermined depth to form an active region.
Next, referring to FIG. 1D, a device protection film 7 is formed. Then, a contact window is formed by etching the protective oxide film using a predetermined photoresist pattern as a mask, and a wiring metal is formed by depositing an aluminum wiring metal layer 8 on the entire surface of the substrate. Then, the wiring metal layer is patterned by using a predetermined photoresist pattern as a mask, and the metal of the exposed portion of the substrate is etched to form a wiring metal pattern 8. As described above, when the sources and drains of the conventional CMOS top gate NMOS TFT and the PMOS TFT are formed, the n + and p + source and drain polycrystalline silicon in the channel of the polycrystalline silicon thin film transistor generated in the manufacturing process and structure of the transistor, The series resistance and the contact resistance between the n + and p + source and drain and the metal interconnection increase, which is a factor for lowering the characteristics of the polycrystalline silicon thin film transistor.

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Forming a channel amorphous silicon (13), an n + source and drain polycrystalline silicon (17A), source and drain metal (12) structures of an NMOS TFT in a low temperature process CMOS polycrystalline silicon thin film transistor fabrication; Forming the n + source and drain polycrystalline silicon (17A) simultaneously with the formation of the channel amorphous silicon (13); The source and drain metal layers 12 are inserted between the channel amorphous silicon 13 and the wiring metal 20 to form a series resistance from the channel through the n + source and drain polycrystalline silicon to the wiring metal 20, ) And the wiring metal (20) is reduced.

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According to the present invention, the n + and p + polycrystalline silicon source and drain regions necessary for manufacturing a low-temperature process CMOS polycrystalline silicon thin film transistor can be simultaneously formed with the channel polycrystalline silicon, and the electrical characteristics A low-temperature process CMOS polycrystalline silicon thin film transistor composed of an improved NMOS TFT and a PMOS TFT can be manufactured.

1A to 1D are cross-sectional views of a device for explaining a method of manufacturing a conventional CMOS polycrystalline silicon thin film transistor device.
FIGS. 2A to 2G are sectional views of a device for explaining a method of manufacturing a low-temperature CMOS polycrystalline silicon thin film transistor according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings 2a to 2g.
The method of manufacturing a CMOS polycrystalline silicon thin film transistor according to the present invention is applicable to various modules for manufacturing a thin film transistor in a low temperature process. Although the glass substrate is described as an example in the present embodiment, the present invention is not limited thereto, and can be applied to various types of substrates such as wafers and other substrates.
2A through 2G show a method of manufacturing a semiconductor device according to an embodiment of the present invention in accordance with a process order. First, the source and drain metal layers 12 are formed on the substrate 1 as shown in FIG. 2A. Then, the metal layer is patterned using a predetermined photoresist pattern as a mask, and the exposed portions of the substrate are etched to form source and drain regions. Next, referring to FIG. 2B, amorphous silicon and a channel amorphous silicon layer 13 to be used as n + and p + polycrystalline silicon sources and drains are simultaneously formed, and then a gate insulating film 14 layer is formed. In order to form the source and the drain of the NMOS TFT, an n-type impurity is ion-implanted through the open portion of the n + ion implantation photoresist layer 15A as in 2c, The p-type impurity is ion-implanted through the open portion of the ion-implanting photoresist 15B layer. After the ion implantation of the n-type impurity and the p-type impurity ions, a solid phase crystallization process is performed in an electric furnace in a nitrogen atmosphere to convert the channel amorphous silicon layer 13 into polycrystalline silicon. Next, referring to Figs. 2E and 2F, a gate thin film 16 layer is formed on the entire surface of the substrate. Then, the gate thin film 16 is patterned by using a predetermined photoresist pattern as a mask, and the exposed portion of the substrate is etched to a predetermined depth by the gate thin film 16 and the gate insulating film 14, And the drain polycrystalline silicon 17A and the p + source and drain polycrystalline silicon 17B are simultaneously etched to a predetermined depth to form an active region. At this time, the n + source and drain polycrystalline silicon 17A regions are formed by the n-type impurity ion-implanted in the open region of the n + ion implantation photoresist layer 15A and the opening of the p + ion implantation photoresist 15B layer The p + source and drain polycrystalline silicon 17B regions are formed by the p-type impurity ion-implanted into the channel region, and the channel polycrystalline silicon 18 region is formed.
Next, referring to FIG. 2G, a device protection film 19 is formed. Then, the device protection film 19 is etched using a predetermined photoresist pattern as a mask to form a contact window, and a wiring metal layer is deposited on the entire surface of the substrate to form the interconnection 20. Then, the wiring metal layer 20 is patterned using a predetermined photoresist pattern as a mask, and the metal of the exposed substrate portion is etched to form a wiring metal pattern 20.

1, 11: substrate
2: amorphous silicon
2A, 17A: n + source and drain polycrystalline silicon
2B, 17B: p + source and drain polycrystalline silicon
3: etch stop film
4, 13: channel amorphous silicon
5, 14: gate insulating film
6, 16: gate thin film
12: Source and drain metal
15A: n + photoresist for ion implantation 15B: p + ion implantation photoresist
18: channel polycrystalline silicon
7, 19: element protection film 8, 20: wiring metal

Claims (2)

In the fabrication of low temperature CMOS polycrystalline silicon thin film transistors,
Forming a channel amorphous silicon 13, n + source and drain polycrystalline silicon 17A, source and drain metal 12 structures of the NMOS TFT;
Forming the n + source and drain polycrystalline silicon (17A) simultaneously with the formation of the channel amorphous silicon (13); A source and drain metal layer 12 is inserted between the channel polycrystalline silicon 18 and the wiring metal 20 to form a series resistance from the channel through the n + source and drain polycrystalline silicon to the wiring metal 20, ) And the wiring metal (20) is reduced. The method for manufacturing a CMOS polycrystalline silicon thin film transistor according to claim 1,
The method according to claim 1,
Forming a channel amorphous silicon 13, p + source and drain polycrystalline silicon 17B, source and drain metal 12 structures of the PMOS TFT;
Forming the p + source and drain polycrystalline silicon 17B at the same time as forming the channel amorphous silicon 13; The source and drain metal layers 12 are inserted between the channel polycrystalline silicon 18 and the wiring metal 20 to form a series resistance between the channel and the p + source and drain polycrystalline silicon and the wiring metal 20, ) And the wiring metal (20) is reduced. The method for manufacturing a CMOS polycrystalline silicon thin film transistor according to claim 1,



KR20130127136A 2013-10-24 2013-10-24 Fabrication methods of low-temperature CMOS polycrystalline thin film transistor KR101500866B1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0951103A (en) * 1995-08-09 1997-02-18 Citizen Watch Co Ltd Thin-film transistor and its manufacturing method
KR100292047B1 (en) * 1997-12-26 2001-07-12 구본준, 론 위라하디락사 Tft and method for fabricating the same
KR20080050965A (en) * 2006-12-04 2008-06-10 한국전자통신연구원 Complementary metal oxide semiconductor device using thin film transistor and method of fabricating the same
KR20120138254A (en) * 2010-04-15 2012-12-26 한국전자통신연구원 Semiconductor device and method for manufacturing the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0951103A (en) * 1995-08-09 1997-02-18 Citizen Watch Co Ltd Thin-film transistor and its manufacturing method
KR100292047B1 (en) * 1997-12-26 2001-07-12 구본준, 론 위라하디락사 Tft and method for fabricating the same
KR20080050965A (en) * 2006-12-04 2008-06-10 한국전자통신연구원 Complementary metal oxide semiconductor device using thin film transistor and method of fabricating the same
KR20120138254A (en) * 2010-04-15 2012-12-26 한국전자통신연구원 Semiconductor device and method for manufacturing the same

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