KR100521275B1 - Cmos thin film transistor and display device using the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS thin film transistor and a display device using the same, wherein a thickness of polysilicon formed on a substrate included in an active channel region is thicker than an N-type thin film transistor than a P-type thin film transistor. By providing a CMOS thin film transistor and a flat panel display device using the same, the size of the crystal grains included in the P-type thin film transistor is smaller than the size of the crystal grains included in the P-type thin film transistor can control the absolute value of the threshold voltage and current mobility. Thus, CMOS thin film transistors and flat panel display devices with improved electrical characteristics can be provided.

Description

CMOS Thin Film Transistor and Display Device Using the Same {CMOS THIN FILM TRANSISTOR AND DISPLAY DEVICE USING THE SAME}

[Industrial use]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS thin film transistor and a display device using the same, and more particularly, a CMOS thin film transistor having a high current mobility and little difference in absolute values of threshold voltages of a P-type thin film transistor and an N-type thin film transistor. A display device is used.

[Prior art]

In general, circuits using a CMOS metal thin film transistor (CMOS TFT) are used to drive an active matrix LCD, an organic EL device, an image sensor, and the like. However, in general, the absolute value of the threshold voltage of the TFT is larger than the absolute value of the threshold voltage of the MOS transistor using a single crystal semiconductor. Moreover, the absolute value of the threshold voltage of the N-type thin film transistor is very different from the absolute value of the P-type thin film transistor. For example, when the threshold voltage of the N-type thin film transistor is 2V, it is -4V in the P-type thin film transistor.

Therefore, it is not desirable to operate the circuit that the absolute value of the threshold voltage of the P-type thin film transistor and the N-type thin film transistor is very different, and in particular, it serves as a large barrier to reducing the driving voltage. For example, a P-type thin film transistor having a large absolute value of a threshold voltage generally does not operate properly at a low driving voltage.

That is, the P-type thin film transistor merely functions as a passive element such as a resistor and does not operate fast enough. To operate the P-type thin film transistor like a passive device, the driving voltage needs to be high enough.

In particular, when the gate electrode is made of a material having a work function of 5 eV or less, such as aluminum, the difference in work function between the gate electrode and the intrinsic silicon semiconductor is reduced by -0.6 eV. As a result, the threshold voltage of the P-type thin film transistor is shifted to a negative value, and the threshold voltage of the N-type thin film transistor is close to 0V. Therefore, the N-type thin film transistor is generally made to be on-state.

In the above state, it is preferable that the absolute values of the threshold voltages of the N-type thin film transistor and the P-type thin film transistor are almost the same. In conventional single crystal semiconductor integrated circuit technology, the threshold voltage has been controlled using N or P type impurity doping at very small concentrations of up to 10 ¹⁸ atoms / cm 3. That is, the threshold voltage has been controlled with an accuracy of 0.1 V or less by impurity doping at a concentration of 10 ¹⁵ to 10 ¹⁸ atoms / cm 3.

However, when using a semiconductor other than a single crystal semiconductor, no shift in threshold voltage is observed even when impurities are added at a concentration of 10 ¹⁸ atoms / cm 3 or less. Moreover, when the concentration of the impurity is 10 ¹⁸ atoms / cm 3 or more, the threshold voltage changes rapidly, and the conductivity becomes p-type or n-type. This is because polycrystalline silicon has many defects. Since the defect concentration is 10 ¹⁸ atoms / cm 3, the added impurities cannot be trapped and activated by this defect. Moreover, the concentration of impurities is greater than the concentration of defects and excess impurities are activated and the conductivity type is changed to n or p type.

In order to solve this problem, in US Patent Nos. 6,492,268, 6,124,603 and 5,615,935, the channel length of the P-type thin film transistor is made smaller than the channel length of the N-type thin film transistor by varying the channel length. However, this patent also has a problem in that the manufacturing process is complicated because the channel length must be manufactured differently.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems described above, and an object of the present invention is to control the size of crystal grains when crystallizing a channel region so that the difference between the absolute values of the threshold voltages of the P-type thin film transistor and the N-type thin film transistor. The present invention provides a CMOS thin film transistor having little current and high current mobility and a display device using the same.

The present invention to achieve the above object,

The thickness of the polysilicon formed on the substrate included in the active channel region is thicker than the N-type thin film transistor than the P-type thin film transistor, and the grain size of the N-type thin film transistor is included in the P-type thin film transistor. Provided is a CMOS thin film transistor characterized in that the size is also small.

In addition, the present invention

Board,

A buffer layer formed on the substrate, and

In a CMOS thin film transistor comprising a P-type thin film transistor and an N-type thin film transistor including a polysilicon film formed on the buffer layer,

The P-type thin film transistor provides a CMOS thin film transistor comprising an insulating layer between the substrate and the buffer layer.

In addition, the present invention

A liquid crystal display device or an organic EL device using the CMOS thin film transistor is provided.

Hereinafter, with reference to the accompanying drawings of the present invention will be described in more detail.

In the present invention, the P-type thin film transistor and the N-type thin film formed in the CMOS thin film transistor in consideration of the size of the crystal grains of the polysilicon included in the active channel region affect the electrical characteristics of the thin film transistor, that is, the current mobility and the threshold voltage. In order to improve the electrical characteristics of a CMOS thin film transistor by controlling the size of crystal grains of polysilicon formed in the transistor.

1A to 1I are process diagrams sequentially showing a process for manufacturing a CMOS thin film transistor according to an embodiment of the present invention.

As shown in FIG. 1A, a buffer layer 11 is first deposited on a substrate 10 having an N-type thin film transistor region 10a and a P-type thin film transistor region 10b. SiO ₂ or the like is used as the buffer layer 11. After depositing the buffer layer 11, amorphous silicon 12 is deposited on the buffer layer 11. At this time, the amorphous silicon 12 is deposited to a thickness of 500 to 1,500 kPa.

Then, as illustrated in FIG. 1B, the photoresist pattern 13 is formed on the amorphous silicon 12 in the N-type thin film transistor region 10a, and the amorphous silicon is dry-etched. Then, the amorphous silicon 12b of the P-type thin film transistor region 10b is etched by a predetermined depth so that the thickness of the amorphous silicon 12a layer of the N-type thin film transistor region and the amorphous silicon 12b layer of the P-type thin film transistor region differ in thickness. Will occur.

At this time, the thickness of the amorphous silicon 12b remaining in the P-type thin film transistor is about 300 to 800 GPa.

After removing the photoresist 13, as shown in FIG. 1C, the laser is irradiated to crystallize the amorphous silicon into polysilicon. At this time, since the thickness of the amorphous silicon (12b) layer of the P-type thin film transistor region is smaller than the thickness of the amorphous silicon (12a) layer of the N-type thin film transistor region, the amorphous silicon of the P-type thin film transistor region is almost completely melted and then crystallized. The amorphous silicon in the N-type thin film transistor region is crystallized after only the upper portion thereof is melted. As a result, the size of the crystal grains of the polysilicon formed in the P-type thin film transistor region is increased, and the size of the crystal grains of the polysilicon formed in the N-type thin film transistor region is relatively large. It is formed smaller than the size of.

In this case, since the polysilicon of the P-type thin film transistor region has a larger grain size than the N-type thin film transistor region, the number including the grain boundary becomes smaller than that of the N-type thin film transistor region.

On the other hand, when the amorphous silicon is crystallized using a laser, a grain boundary, which is a boundary between grains, is formed, and when the device is manufactured, the grain boundary affects the current mobility and threshold voltage of the P-type thin film transistor and the N-type thin film transistor. Go crazy. In other words, it is known that the grain boundary acts as a trap for an electric charge carrier.

3 is a graph showing a change in current mobility according to grain size of polysilicon. Referring to FIG. 3, it can be seen that as the grain size increases, the current mobility also increases.

Therefore, in the case of the P-type thin film transistor region, as the number of grain boundaries is less, the current mobility in the N-type thin film transistor region is relatively increased and the threshold voltage is lowered, so the P-type thin film transistor region and the N-type thin film are The difference in the current characteristics between the transistor regions is reduced and almost eliminated.

At this time, the channel region of the N-type thin film transistor and the channel region of the P-type thin film transistor are formed to have the same width.

On the other hand, in the present invention, it is preferable to use the ELA (Laer Eximer Annealing) method as a laser crystallization method, it is preferable to use a laser using energy of 320 mJ / ㎠.

After forming the polysilicon pattern, as shown in FIG. 1D, the polysilicon pattern 12a of the channel region 10a of the N-type thin film transistor is exposed to provide conductivity to the N-type thin film transistor, and then the patterned photoresist is exposed. Channel doping is performed with an N-type dopant using (14) as a mask.

In the present invention, it may have a structure of a conventional N-type thin film transistor, may have a lightly doped drain (LDD) structure or an off-set structure, but is not limited to a specific structure. However, in the present embodiment, for convenience of description, the following steps will be described with respect to the CMOS thin film transistor having the LDD structure.

Subsequently, as shown in FIG. 1E, the photoresist 14 is removed, a gate insulating film 15 is formed on the substrate 10, and a gate electrode material is deposited thereon. Subsequently, a gate electrode material is etched using a mask on the substrate 10 to form gate electrodes 16a and 16b of the N-type thin film transistor and the P-type thin film transistor in the corresponding region. Next, in order to form an LDD structure, ion-implanted N-type low concentration impurities into the polysilicon pattern 12a of the N-type thin film transistor region 10a to form low-dense source / drain regions on both sides of the gate electrode 16a. 17).

Subsequently, as shown in FIG. 1F, after the photoresist is applied to the entire surface of the substrate 10 on which the low concentration source / drain regions 17 are formed, impurities to the N-type thin film transistor region 10a are performed by performing a photolithography process. While preventing ion implantation, a mask for forming a source / drain region of a P-type thin film transistor is formed, and the mask is used to form a high concentration of P-type impurities into the polysilicon pattern 12b of the P-type thin film transistor region 10b. Ion implantation forms a high concentration source / drain region 19 of the P-type thin film transistor.

Subsequently, as shown in FIG. 1G, after removing the mask and applying photoresist on the substrate 10 again, a photolithography process is performed to perform a gate electrode and the P-type thin film transistor region of the N-type thin film transistor ( A mask 20 is formed to prevent impurity ion implantation into 10a). Next, the high concentration source / drain regions 21 are formed by ion implanting N-type high concentration impurities into the polysilicon pattern 12a of the N-type thin film transistor region 10a using the mask 20.

Next, as shown in FIG. 1H, after removing the mask 20, an interlayer insulating layer 22 is formed on the entire surface of the substrate 10. Subsequently, by placing a mask on the substrate 10, the interlayer insulating layer 22 is etched so that the source / drain regions 19 and 21 of the N-type thin film transistor and the P-type thin film transistor are exposed, thereby etching the N-type thin film transistor region 10a. ) And the contact holes 23a and 23b are formed in the P-type thin film transistor region 10b, respectively.

Finally, as shown in FIG. 1I, after depositing a conductive metal material for forming a source / drain electrode on the entire surface of the substrate 10, the conductive metal material is etched using a mask to form an N-type thin film transistor and a P-type. Source / drain electrodes 24a and 24b of the thin film transistor are formed, respectively.

Thus, a CMOS thin film transistor including an N-type thin film transistor having an LDD structure and a P-type thin film transistor having a conventional structure was produced.

Meanwhile, according to another exemplary embodiment of the present invention, a method of differently forming grain sizes of polysilicon formed in the polysilicon patterns 12a and 12b of the P-type thin film transistor region and the N-type thin film transistor region is illustrated in FIGS. 2A to 2C. Shown in

First, referring to FIGS. 2A to 2C, an insulating layer 25 such as SiNx is first formed in a P-type thin film transistor region 10b in a region where a P-type thin film transistor is formed on a substrate. Then, as shown in FIG. 2B, the buffer layer 11 is formed over the entire surface of the substrate 10. As the buffer layer 11, SiO ₂ or the like as mentioned above is used. Thereafter, amorphous silicon is deposited to the same thickness over the entire surface of the substrate 10, and then the silicon is crystallized with a laser to form polysilicon patterns 12a and 12b.

At this time, since an insulating layer such as SiNx is applied to the lower part of the P-type thin film transistor, the amount of energy of the irradiated laser is conducted to the outside through the substrate is smaller than that of the N-type thin film transistor area where the insulating layer is not applied to the lower part. do. That is, since the thermal conductivity becomes smaller in the P-type thin film transistor, the amount of energy affecting the amorphous silicon is greater in the amorphous silicon in the P-type thin film transistor region than in the N-type thin film transistor region. This becomes more melted, and thus the size of crystal grains formed becomes larger in the P-type thin film transistor region. Therefore, the electrical characteristics between the P-type thin film transistor and the N-type thin film transistor are almost eliminated for the reasons described above.

The laser crystallization method used herein uses ELA (Eximer Laser Annealing) method, and the laser used uses a laser having an energy of 320 mJ / cm 2.

Subsequent processes produce a CMOS thin film transistor using the same process as described above with reference to FIGS. 1D to 1I.

As in the present invention, a CMOS thin film transistor having a crystal grain size of polysilicon included in an active channel region of an N-type thin film transistor is smaller than that of a polysilicon grain contained in an active channel region of a P-type thin film transistor is used for a display device. It is preferably used in an active element type LCD or an organic electroluminescent element.

As described above, the absolute value and the current mobility of the threshold voltage can be controlled by varying the size of the crystal grains in the active channel region of the N-type thin film transistor and the P-type thin film transistor included in the COMS thin film transistor. A CMOS thin film transistor having improved characteristics can be provided.

1A to 1I are process diagrams sequentially showing a process for manufacturing a CMOS thin film transistor according to an embodiment of the present invention.

2A through 2C are flowcharts sequentially illustrating a process for manufacturing a CMOS thin film transistor according to another exemplary embodiment of the present invention.

3 is a graph showing a change in current mobility according to grain size of polysilicon.

Claims (11)

The thickness of the polysilicon of the N-type thin film transistor is thicker than the thickness of the polysilicon of the P-type thin film transistor formed on the substrate included in the active channel region, and the size of crystal grains included in the N-type thin film transistor is greater than that of the P-type thin film. A CMOS thin film transistor, wherein the size of crystal grains contained in the transistor is smaller than that. The method of claim 1, The thickness of the polysilicon of the P-type thin film transistor is a CMOS thin film transistor of 300 to 800 kHz. The method of claim 1, The thickness of the polysilicon of the N-type thin film transistor is a CMOS thin film transistor of 500 to 1,500 kPa. The method of claim 1, The polysilicon is a CMOS thin film transistor that is manufactured by ELA (Eximer Laser Anealing) crystallization method. The method of claim 1, Wherein said CMOS thin film transistor comprises an LDD structure or an off-set structure. Board; A buffer layer formed on the substrate; And In a CMOS thin film transistor comprising a P-type thin film transistor and an N-type thin film transistor including a polysilicon film formed on the buffer layer, And the p-type thin film transistor comprises an insulating layer between the substrate and the buffer layer. The method of claim 6, Wherein the buffer layer is SiO ₂ and the insulating layer is formed of SiNx. The method of claim 6, The polysilicon is a CMOS thin film transistor that is manufactured by ELA (Eximer Laser Anealing) crystallization method. The method of claim 6, Wherein said CMOS thin film transistor comprises an LDD structure or an off-set structure. A display device comprising the CMOS thin film transistor according to claim 1 or 6. The method of claim 10, And the display device is a liquid crystal display element or an organic electroluminescent display device.