JP3325996B2 - Semiconductor device manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and a structure for manufacturing a thin film transistor used for an image sensor, a liquid crystal display and other integrated circuits.

[0002]

2. Description of the Related Art In recent years, products which mount a thin film transistor (generally referred to as a TFT) on a large-sized device to improve the performance and reduce the size by simplifying peripheral circuits have been marketed. Have been. Especially in 1990
Large liquid crystal displays mounted on small personal computers called notebooks or laptops, which began to spread from around the year, employ an active matrix system in which thin film transistors are arranged in each of the liquid crystal pixels. It has excellent characteristics. However, there is a problem that the manufacturing process is complicated and expensive, and there is a strong demand for cost reduction.

At present, almost all thin film transistors used in this large-sized liquid crystal display use amorphous silicon at the product level, but amorphous silicon thin film transistors have low performance as a transistor (for example, single crystal in terms of electron mobility). In the case of a silicon transistor, which is 10 ⁻² to 10 ⁻³ times, a circuit for driving a thin film transistor disposed in a pixel needs to externally dispose an IC made of single crystal silicon.

When a thin film transistor using amorphous silicon is arranged in a pixel, it is necessary to supply a large current and obtain a sufficient driving speed, so that a wide channel width is required. However, when the channel width of a thin film transistor arranged in a pixel is widened, there is a dilemma that the aperture ratio of the pixel, which is one of the factors for improving the display quality, is reduced. Also, in terms of reliability, the electrical instability of the amorphous silicon film or amorphous silicon nitride film itself is inherently present.

As a means for solving all of these disadvantages, a method of forming a thin film transistor using polycrystalline silicon has been expected. In this case, the on-state current is several tens to 100 times or more that of the amorphous silicon TFT, and the amorphous silicon TF is not only reliable.
There is no instability like T. In addition, since both N-type and P-type transistors can be formed, a CMOS circuit can be formed, which is advantageous for the demand for low power consumption.

Although the polycrystalline silicon thin film transistor has excellent properties as described above, it has a high off-state current,
When the gate voltage is applied to the reverse bias side (negative side for N-type TFT, positive side for P-type TFT), the current increases, or the drain current increases rapidly when the drain voltage increases. There are still many points that need to be improved.

It is known that this increase in current on the reverse bias side can be avoided by forming an offset structure or an LDD structure on the drain electrode side. Conventionally, to form an offset structure, after patterning the gate electrode, a silicon oxide film is formed by a film forming method with good step coverage, and etched back by a highly anisotropic etching method. The main method has been to form a mask at the time of doping called a so-called side wall or spacer. This side wall is formed on both sides of the gate electrode in the conventional method. As a result, an offset or a high resistance portion is also formed on the source electrode side, and this portion becomes a resistance in series with the TFT. There is a disadvantage that the on-current is reduced. In addition, to eliminate the offset and the high resistance portion on the source side, it is possible to increase the number of times of photolithography twice and the number of times of ion implantation twice, but this increase in the number of steps obviously increases the cost and lowers the yield.

Further, even in a MOS transistor having an SOI (Silicon On Insulator) structure using single crystal silicon in which an increase in off current is not observed, such as a polycrystalline silicon thin film transistor, when there is no offset structure or LDD structure, In such a case, a phenomenon in which the drain current sharply increases is likely to occur, and if the operation is performed in a bias state in which such a phenomenon occurs, defects such as a shift in the threshold value and a decrease in the on-current are likely to occur.

[0009]

[Problems to be solved by the present invention] As described above,
A TFT that has a small current flowing between the drain and source electrodes when an off current or a reverse bias gate voltage is applied, has a sufficiently large on current, and has a high reliability that does not cause a rapid increase in the drain current is required. Had been.

In order to obtain such a TFT, it is desirable to form an offset structure or an LDD structure only on the drain side. However, the conventional method cannot manufacture without a large increase in the number of steps. , Was very disadvantageous in terms of yield and cost. Therefore, an object of the present invention is to manufacture a TFT having high yield and high reliability without sacrificing electrical characteristics by minimizing the increase in the number of steps to solve such inconveniences. I do.

[0011]

In order to solve the above-mentioned problems, an offset structure or an LD is provided in a self-aligned manner only on the drain electrode side while minimizing the number of steps.
A method for forming the D structure will be described below.

First, a film (shielding material) having etching resistance to the etching material for the gate electrode is formed following the formation of a low-resistance film serving as a gate electrode. This shielding material may be a material which is hard to be etched in a predetermined etching process as compared with a material forming the gate electrode (gate electrode material), that is, a material which can have a selective ratio with the material forming the gate electrode at the time of etching. is necessary. For example,
It is possible to use a material that is etched for a specific etchant as a gate electrode, and use a material that is not etched for that etchant as a shielding material. When aluminum is used as the gate electrode material,
Chromium can be used as a shielding material. This is based on the fact that chromium is hardly etched by an etchant for etching aluminum. When one-conductivity-type silicon is used as a gate electrode material, silicon oxide can be used as a shielding material. This is because the etching rate for dry etching of silicon oxide is extremely low for silicon of one conductivity type.

Next, this shielding material is formed into a gate electrode pattern by photolithography. After the shielding film is removed by etching, the gate electrode material is etched.

At this time, by performing isotropic etching,
The gate electrode material can be selectively side-etched. As a result of this etching, a structure in which the shielding material overhangs on the gate electrode material is obtained.

Next, the shielding material in the overhang portion on the source region side is removed by a photolithography process. As a result, a state is obtained in which the source region is exposed and the overhanging shielding material remains only on the drain region. By doping an impurity imparting one conductivity type by ion implantation in this state, an offset structure can be obtained. That is, doping is not performed under the gate electrode and the overhanged portion (immediately below the overhanging shielding material), and the overhanged portion can be used as an offset region.

Further, by selecting an appropriate thickness of the shielding material and a suitable doping condition, one conductivity type is imparted to the overhanged portion (immediately below the overhanging shielding material) at a lower concentration than the source / drain region. Can be doped, and a lightly doped region can be formed. That is, an LDD (lightly doped drain) structure can be realized.

For example, by implanting impurities through the shielding film remaining in the drain region, the area immediately below the shielding film is 1 × 1.
Doping can be performed at a concentration of 0 ¹⁵ to 1 × 10 ¹⁸ atoms / cm ³ , and other portions such as a contact portion are 1 × 10 ¹⁹
Doping can be performed at a concentration of about 1 × 10 ²¹ atoms / cm ³ .

The impurity implantation process is divided into two steps.
Forming a source / drain region in the second implantation,
A lightly doped region (LDD region) can also be formed between the drain region and the channel formation region in the implantation of the turning plane.

In this case, the first impurity implantation is performed under the condition that the ion implantation is not performed in the region masked by the shielding material (for example, realized by controlling the acceleration voltage).
After that, the shielding material is removed, and then a second impurity implantation is performed, and light doping is performed on a region masked by the shielding material (a region where the overhang is formed).

As another method, the first impurity implantation is performed under conditions (for example, realized by controlling an acceleration voltage) in which ions are not implanted into a region masked by the shielding material, and the second impurity implantation is performed. Implantation is performed by applying greater energy to the ions than the first time (the accelerating voltage may be increased), and the impurities can be lightly doped immediately below the shielding material.

In any case, the region masked by the overhanging shielding material is doped with impurity ions (for example, phosphorus or boron) at a lower concentration than the other exposed regions, so that the masking is performed by the overhanging shielding material. The region thus set can be a lightly doped region.

[0022]

By providing an overhanging shielding film only on the drain region side on the gate electrode, it is possible to easily form an offset or LDD structure only on the drain electrode side in a self-aligned manner. Further, since this configuration can be realized by a simple process, it is possible to improve the yield and reduce the cost.

[0023]

【Example】

[Embodiment 1] FIGS. 1 to 3 are sectional views showing the steps of manufacturing a thin film transistor manufactured according to the present invention. This embodiment relates to a configuration in which an offset region is formed between a drain region and a channel formation region.

First, amorphous silicon 102 is formed on a glass substrate 101 covered with a protective film (not shown) by, for example, the LPCVD method. Next, 500-850 ° C
Amorphous silicon is solid-phase grown and crystallized at about the same temperature. (Fig. 1 (A))

The temperature of the solid phase growth depends on the heat resistance of the glass substrate. The limit temperature is around 600 ° C. for non-alkali glass, but it can be used at a temperature of 850 ° C. or higher for crystalline glass. Further, instead of solid phase growth, crystallization means by irradiation with laser light or strong light may be used. Alternatively, a method of obtaining a crystalline silicon film having crystallinity simultaneously with film formation may be employed.

Next, the crystalline silicon film subjected to the solid phase growth is patterned to form an active layer 1 as shown in FIG.
03 and 104 are formed. Further, a silicon oxide film 105
Is formed to a thickness of 1000 ° by a plasma CVD method.
(Fig. 1 (C))

Then, n ⁺ poly-Si to be a gate electrode later
The film 106 is formed to a thickness of 2500 ° by a plasma CVD method. (Fig. 1 (D))

In this state, a silicon oxide film (SiO ₂ film) 107 is formed to a thickness of 2000 ° as a shielding material.
(FIG. 1 (E))

Next, as shown in FIG. 1F, a gate electrode is patterned by photolithography using a resist mask. FIG. 1F shows the shielding member 107.
FIG. 3 is a diagram obtained by etching with a hydrofluoric acid-based etchant. Further, the n ⁺ poly-Si film 106 is dry-etched.
Is etched. At this time, by performing etching for an appropriate period of time in an equal manner, the shielding member 107 is overhanged as shown in FIG. In this step, gate electrodes 109 and 110 are formed.

The offset or the length of the LDD can be controlled by the length of the overhang. Further, the length of the overhang can be controlled by the etching conditions of the n ⁺ poly-Si film 106. In this example, the length of the overhang was set to 500 nm. Therefore, the length of the offset is about 500 nm.
This length can be set to the required length.

Next, as shown in FIG. 2A, the overhang on the source electrode side is removed by photolithography. In FIG. 2, the drain region is on the left side of the gate electrodes 109 and 110. In this state, a region is formed between the drain region and the channel formation region (formed as a gate electrode) by being masked by the shielding material 107.

Next, as shown in FIG.
Ions are implanted at a dose of 10 ¹⁵ atoms / cm ² . In this step, the shielding member 107 and the gate electrodes 109, 110
Is not ion-implanted into a portion that becomes a mask, and phosphorus ions are implanted into other regions.

Further, as shown in FIG. 2C, the portion other than the portion to be made P-type is covered with a resist 111, and boron is added to 5 × 1.
Ions are implanted at a dose of 0 ¹⁵ atoms / cm ² .

The state shown in FIG. 2D is obtained by removing the resist 111 by ashing. Further, activation was performed at 500 ° C. for 12 hours, and each TF was activated.
The impurity doped in the T source / drain region is activated.

Thus, the drain region 112, the offset region 113, the channel forming region 114, and the source region 11
5, a P-channel TFT portion having a gate electrode 109, a drain region 116, an offset region 117, a channel forming region 118, a source region 119, and a gate electrode 1
10 and an N-channel TFT portion having the same. The silicon oxide film 105 becomes a gate insulating film.

Next, as shown in FIG. 2E, a phosphorus glass 120 is formed as an interlayer insulating film by a normal pressure CVD method.
A contact hole is formed as shown in FIG. Further, as shown in FIG. 3B, an aluminum film 121 is used as an electrode.
Is formed by a sputtering method, and patterning is performed as shown in FIG. 3C to complete a left P-channel TFT and a right N-channel TFT.

In the TFT manufacturing process described above, P
The offset region 113 of the channel TFT and the offset region 117 of the P-channel TFT can be formed in a self-aligned manner (self-aligned). Moreover, by appropriately setting the conditions in the step of performing side etching of the gate electrode (the step shown in FIG. 1G), the length of the offset region can be controlled, and the characteristics of the TFT can be easily controlled. it can. Further, since it has excellent reproducibility, it is extremely useful in maintaining quality and yield. Since it can be realized by a simpler process, a TFT can be obtained at low cost, which is extremely useful in industry.

The TFT shown in the present embodiment (N on the right
FIG. 4B shows the electrical characteristics of the channel TFT. FIG. 4B shows the electrical characteristics of a TFT having a conventional structure.
Shown in The TFT whose electric characteristics are shown in FIG. 4B is manufactured without providing the shielding member 107 in the step shown in FIG. The only difference between the two is whether there is an offset area 117 or not.

As is clear from FIG. 4A, the conventional T
In the FT, breakdown occurs in a high voltage region of VD. On the other hand, in the TFT of this embodiment, such a phenomenon is not observed as shown in FIG. The TFT having the characteristics as shown in FIG. 4B is a transistor characteristic that allows easy circuit design even when used in an analog circuit, and is extremely preferable.

Second Embodiment In the first embodiment, an offset region is formed by utilizing the fact that impurity ions implanted by the shielding member 107 are shielded. In this embodiment,
An example in which light doping is performed on a region masked with a shielding material by using the shielding material 107 in the manufacturing process described in Embodiment 1 will be described.

In order to realize this embodiment, FIG.
In the step shown in FIG. 2B, by increasing the acceleration voltage, 1 × 1 phosphorus ions are added to the area masked by the shielding material 107 (the areas indicated by 113 and 117 in FIG. 2D).
At a dose of 0 ¹² atom / cm ² , boron ions are
It may be implanted at a dose of × 10 ¹² atom / cm ² . That is, the injected ions penetrate the shielding material 107 to some extent,
What is necessary is just to light-dope the area | region shown by 13 or 117.

In the present embodiment, a part of the ions implanted by the shielding material 107 during doping is shielded, and a part of the ions is allowed to pass therethrough, thereby making it possible to compare with an exposed region (which becomes a source / drain region). To form a lightly doped region.

The doping conditions are not limited to the above conditions, and the impurity ions implanted into the lightly doped drain region may be 1 × 10 ¹⁵ to 1 × 10 ¹⁸ atoms / cm ^3.
It can be determined in a timely manner within the range. This may be set according to the required characteristics of the TFT and the device to be used.

In this embodiment, an LDD structure is realized by controlling the conditions of ion implantation.
Under the conditions described in the first embodiment, the same effect can be obtained even if the thickness of the shielding member 107 is reduced. That is, by reducing the thickness of the shielding material 107, a part of the implanted ions can be transmitted, and the lightly doped region 113 or 117 can be transmitted.
Can be formed.

[Embodiment 3] In this embodiment, after the step shown in FIG. 2B, the shielding material 107 is removed, and phosphorus ions are further implanted, so that the regions 113 and 117 become lightly doped regions. Is what you do. In this embodiment, the two left and right TFTs are N-channel TFTs.
Therefore, the step of FIG. 2C is omitted. By employing the structure of this embodiment, a TFT having an LDD structure can be manufactured.

[Embodiment 4] In this embodiment, after the step shown in FIG. 2B, a second implantation of phosphorus ions is carried out with a stronger accelerating voltage, and regions 113 and 117 are defined as lightly doped regions. Is what you do. In order to increase the acceleration voltage, it is necessary to transmit 11
This is for implanting into the regions indicated by reference numerals 3 and 117. By adopting the configuration of this embodiment, the TF having the LDD structure
T can be made.

[0047]

According to the present invention, an offset structure or an LD
It is possible to easily manufacture a MOS transistor having a D structure without a major process change.

[Brief description of the drawings]

FIG. 1 shows a manufacturing process of an example.

FIG. 2 shows a manufacturing process of an example.

FIG. 3 shows a manufacturing process of an example.

FIG. 4 shows electrical characteristics of a conventional TFT and a TFT manufactured in an example.

[Explanation of symbols]

101 glass substrate 102 amorphous silicon 103 active layer 104 active layer 105 silicon oxide film 106 n ⁺ poly-Si film 107 ..Shielding material (silicon oxide film) 108 ........ Resist mask 109 ........ Gate electrode 110 ........ Gate electrode 111 ........ Resist mask 112 ........ Drain region 113 ........ Offset Region 114 Channel forming region 115 Source region 116 Drain region 117 Offset region 118 Channel forming region 119 Source region 120 Interlayer insulating film (phosphorus glass) 121 ... Aluminum film

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-5-182983 (JP, A) JP-A-5-21454 (JP, A) JP-A-2-20060 (JP, A) JP-A-63-1988 240069 (JP, A) JP-A-57-64973 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/78 H01L 29/786 H01L 21/336

Claims (5)

(57) [Claims] A source region, a drain region, and the drain region;
And an offset area provided only on the in-area side.
A crystalline silicon film and a gate on the crystalline silicon film
Having an insulating film and a gate electrode on the gate insulating film
A method for manufacturing a thin film transistor, comprising: forming a conductive film on the gate insulating film;
Forming a mask and etching the conductive film using the mask;
After that, the conductive film under the mask is side-etched.
To form the gate electrode, and the mask on the crystalline silicon film to be the source region
Is partially removed, and impurities are removed using the partially removed mask.
Doping the crystalline silicon film with the source region
Region, the drain region and the offset region are formed.
A method for manufacturing a thin film transistor. A source region, a drain region, and the drain region;
Crystal having LDD region provided only on in-region side
Silicon film and gate insulation on the crystalline silicon film
Thin film having a film and a gate electrode on the gate insulating film
A method for manufacturing a transistor, comprising: forming a conductive film over the gate insulating film;
Forming a mask and etching the conductive film using the mask;
After that, the conductive film under the mask is side-etched.
Forming the gate electrode, and forming the gate electrode on the crystalline silicon film serving as the source region.
The mask is partially removed and the mask is removed using the partially removed mask.
Doping the crystalline silicon film with the source
Forming a region, the drain region and the LDD region.
A method for manufacturing a thin film transistor. 3. A source region, a drain region and the drain region.
Crystal having LDD region provided only on in-region side
Silicon film and gate insulation on the crystalline silicon film
Thin film having a film and a gate electrode on the gate insulating film
What manufacturing method der transistor, said forming a conductive film on the gate insulating film, on said conductive film
Forming a mask and etching the conductive film using the mask;
After that, the conductive film under the mask is side-etched.
To form the gate electrode, and the mask on the crystalline silicon film to be the source region
Is partially removed, and the first mask is removed using the partially removed mask.
Doping impurities, doping a second impurity
The source region and the drain are formed in the crystalline silicon film.
Forming a region and said LDD region
Method for manufacturing thin film transistor. 4. A source region, a drain region and said drain region.
Crystal having LDD region provided only on in-region side
Silicon film and gate insulation on the crystalline silicon film
Thin film having a film and a gate electrode on the gate insulating film
A method for manufacturing a transistor, comprising: forming a conductive film over the gate insulating film;
Forming a mask and etching the conductive film using the mask;
After that, the conductive film under the mask is side-etched.
To form the gate electrode, and the mask on the crystalline silicon film to be the source region
Is partially removed, and the first mask is removed using the partially removed mask.
Doping impurities, removing the mask entirely,
Doping impurities into the crystalline silicon film
A source region, the drain region, and the LDD region;
Method of manufacturing thin film transistor characterized by forming
Law. 5. The method according to any one of claims 1 to 4, wherein
And the impurity is boron or phosphorus.
A method for manufacturing a thin film transistor.