JP2002050764A - Thin-film transistor, array substrate, liquid crystal display, organic el display, and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To resolve the problem that conventionally polycrystalline silicon transistor which requires heat treatment process at a high temperature for the formation of source and drain regions, and that it is difficult to form a minute transistor due to diffusion of impurities from the source and drain regions. SOLUTION: A silicon/germanium region is formed by implanting germanium ions into the source and drain regions of a polycrystalline silicon transistor. As a result, it becomes possible to activate the impurities in the source and drain regions, even at low temperatures. Moreover, since the activation at low temperature becomes possible, the diffusion of the impurities from the source and drain regions is suppressed, and the formation of a minute transistor of a long gate becomes possible.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film transistor, an array substrate using the thin film transistor, a liquid crystal display device, an organic EL display device, and a method for manufacturing the same.

[0002]

2. Description of the Related Art In a liquid crystal display or an organic EL display, there is a technique of forming a switching element and a driving peripheral circuit on a glass substrate by forming a thin film transistor from polycrystalline silicon. Liquid crystal displays are required to have higher definition, higher responsiveness, and lower power consumption.To realize these technologies, transistors with short channel lengths and channel widths made of polycrystalline silicon must be reduced in voltage. Need to be driven.

[0003]

However, since a polycrystalline silicon thin film transistor has an active region formed of polycrystalline silicon, a heat treatment step required for forming the thin film transistor requires the formation of source and drain regions. In polycrystalline silicon, the dopant introduced into the substrate rapidly diffuses in the crystal grain boundaries, causing a problem that the dopant diffuses in the channel direction. In a polycrystalline silicon thin film transistor, Lightly Dop, which is a source and a drain region having a low dopant concentration, is provided in the transistor to reduce off current.
It is necessary to form an ed Drain (LDD) region.

However, in order to obtain desired transistor characteristics, it is necessary to precisely control the LDD length and the dopant concentration in the LDD region. LDD is diffused due to the
It becomes difficult to precisely control the length and the dopant concentration contained in the LDD portion. Further, since polycrystalline silicon has a feature that the resistivity of polycrystalline silicon greatly changes in a region where the dopant concentration is low, L
There is a problem that the resistance value in the DD region changes greatly. As a result, the parasitic resistance of the transistor fluctuates, which causes a problem that a large variation occurs in the drive current.

In addition, as the transistor element becomes finer, the contact diameter and the diffusion region of the source and drain regions become smaller, and the ratio of the contact resistance in the parasitic resistance and the diffusion resistance in the source and drain regions increases. As a result, there is a problem that the driving force of the transistor is reduced.

In order to activate the dopant introduced into the source, drain and LDD regions, the temperature is usually set at 600 ° C.
It requires an annealing step of a certain degree. However, in a thin film transistor formed on a glass substrate, 60
In a process step at a high temperature of about 0 ° C., there is a problem that the glass is distorted.

Due to these problems, it has been difficult to manufacture a thin-film transistor having a short channel length and capable of operating at a low voltage on a glass substrate from polycrystalline silicon.

[0008]

In order to solve the above-mentioned problems, a transistor in which the source and drain regions are formed of polysilicon by using polysilicon germanium for the source and drain regions of the transistor. In comparison, the activation of the dopant is possible even at a low temperature. Therefore, the activation temperature of the dopant implanted into the source and drain regions can be reduced. As a result, diffusion of the dopant from the source and drain regions to the channel portion is suppressed, so that a short-channel transistor can be manufactured with good controllability. Further, since the source and drain regions are formed of silicon germanium, the sheet resistance of the source and drain regions and the contact resistance between the source and drain regions and the source / drain metal can be reduced, and the driving force of the transistor can be increased. Can be.

In addition, since the process temperature can be lowered, the activation heat treatment step of the source and drain regions conventionally performed in the heat treatment furnace may be performed by using a rapid heat treatment apparatus such as lamp annealing. Since the resistance of the source and drain regions can be sufficiently reduced, the throughput can be greatly improved by performing an activation process using a lamp annealing device or the like.

When polycrystalline silicon is used for the channel region, polycrystalline silicon germanium having a close lattice constant is desirable as a material used for the source and drain regions, but the melting point is lower than that of the semiconductor material used for forming the channel region of the transistor. It is also possible to apply a low semiconductor material or silicide to the source and drain regions.

In a transistor whose source and drain regions are made of polycrystalline silicon germanium, desired source and drain regions can be formed by injecting germanium after forming a gate electrode.

As a prior art, it has been reported that the process temperature can be lowered by using a transistor using polycrystalline silicon germanium for all of the channel, source, and drain regions which are active regions of the transistor. When silicon germanium is used for the portion, a phenomenon occurs in which the off-current increases. Further, when polycrystalline silicon germanium is used for the channel region, the defect density is increased as compared with the case where polycrystalline silicon is used for the channel, so that there is a problem that the sub-threshold characteristics of the transistor are deteriorated.

In the thin film transistor of the present invention, by using polycrystalline silicon germanium only in the source and drain regions, the off-state current is not increased and the sub-threshold characteristic is not deteriorated. It is possible to improve the described transistor characteristics and suppress the variation in characteristics.

In a transistor formed of polycrystalline silicon, an LDD region is often formed to reduce off-current. In the present invention, polycrystalline silicon germanium is used for both the LDD region and the source and drain regions. It is also possible to use polycrystalline silicon germanium only for the source and drain regions. When polycrystalline silicon germanium is used only for the source and drain regions, the resistance of the LDD region becomes relatively high, so that the off-state current can be reduced.

Further, by using the thin film transistor described above as a switching element on an array substrate, the thin film transistor can be used not only as a liquid crystal display but also as a switching element and a driving circuit element in a display using an organic electroluminescent device. It is possible.

[0016]

FIG. 1 shows a thin film transistor according to an embodiment of the present invention.

In the thin film transistor of the present invention, the channel region 104 is formed of polycrystalline silicon, and the LDD region 107 and the source and drain regions 108 are formed of polycrystalline silicon germanium.

By using this structure, the process temperature for manufacturing a thin film transistor using polycrystalline silicon as a channel can be reduced. Further, since the sheet resistance of the source and drain regions and the contact resistance between the source and drain and the source / drain metal 111 can be reduced, a transistor with a large drive current can be obtained.

As a result, since the channel width of the thin film transistor can be reduced, a high definition display having a high aperture ratio in a liquid crystal display can be manufactured.

Further, since a sufficient driving current can be obtained even at a low voltage, the threshold voltage of the thin film transistor can be lowered, and a liquid crystal display with low power consumption can be formed.

Further, by lowering the process temperature, diffusion of impurities from the source and drain regions can be reduced, and a transistor having a short channel length can be formed. Thus, power consumption can be reduced.

In order to reduce the off-state current of the pixel transistor, polycrystalline silicon germanium can be used only for the source and drain regions, and polycrystalline silicon can be used for the LDD region.

The manufacturing method of the present invention will be described with reference to FIG.

As shown in FIG. 2A, a silicon oxide film 202 is formed on a glass substrate 201 by a plasma CVD method.
An undercoat film is formed by forming a film having a thickness of about 0 nm. Thereafter, as shown in FIG. 2-2, an amorphous silicon film 203 having a thickness of about 50 nm is subsequently formed by a plasma CVD method. The dehydrogenation treatment is performed at a temperature of about 450 ° C. in a nitrogen atmosphere. Then, polycrystalline silicon is formed by irradiating the amorphous silicon with excimer laser light. Thereafter, the polysilicon film is patterned into a desired pattern by performing photolithography and etching.

In this step, the island-shaped polycrystalline silicon 204 shown in FIG. 2-3 is formed. As shown in FIG. 2-4, plasma CVD is subsequently performed using TEOS gas as a source gas.
A gate insulating film 205 is formed by forming a silicon oxide film of about 100 nm by a method.

After a MoW alloy serving as a gate electrode is formed to a thickness of about 400 to 500 nm by sputtering, patterning is performed by photolithography and etching to form a gate electrode 206 shown in FIG. 2-5.

Although the MoW alloy is used for the gate electrode in the present embodiment, polycrystalline silicon germanium may be used. In this case, a gate electrode made of polycrystalline silicon germanium can be formed by forming an amorphous silicon film and subsequently performing a germanium ion implantation step and an annealing step. When polycrystalline silicon germanium is used for the gate electrode, a P-type transistor has a P-type gate electrode and an N-channel
Since an N-type gate electrode can be used for a transistor, a threshold voltage of the transistor can be reduced.

Next, a dose amount of 1 × 10 ¹⁴ to 1 × 10 ¹⁷ c
By implanting ions containing germanium under the condition of m ⁻² , germanium can be added to a region other than the channel portion. At this time, the implantation amount of ions containing germanium is desirably about 1 × 10 ¹⁶ cm ⁻² .

Thereafter, a photolithography process is performed, and a low-concentration boron implantation of a dose of about 5 × 10 ¹² cm ⁻² is performed only in a desired region using a resist mask by ion doping, thereby forming a p-region. To form
The n − region 207 can be formed by implanting phosphorus at a low concentration of about 5 × 10 ¹² cm ⁻² .

Thereafter, a silicon oxide film having a thickness of about 500 nm is formed by a plasma CVD method. Thereafter, the silicon oxide film is anisotropically etched by a dry etching method under conditions that a sufficient etching selectivity with respect to polycrystalline silicon can be ensured, and the side wall 208 of the silicon oxide film is self-aligned with the side of the gate electrode. To form

In the present embodiment, the sidewall is formed of a silicon oxide film, but may be formed of a stacked film of a silicon oxide film and a silicon nitride film. When the insulating film side wall is a stacked film of a silicon oxide film and a silicon nitride film, processing variations in the width of the side wall can be reduced, and thus the LDD length can be controlled with high precision.

Thereafter, a photolithography step is performed when forming the p + region, and a dose of 1 × 1 is applied only to a desired region by ion doping using a resist mask.
A p + region is formed by implanting boron at a high concentration of about 0 ¹⁴ cm ⁻² , and similarly, a photolithography process is performed when forming an n + region, and only a desired region is formed using a resist mask. An n + region can be formed by performing high-concentration phosphorus implantation at a dose of about 1 × 10 ¹⁴ cm ⁻² using an ion doping method.

As shown in FIG. 2-6, in this step, after the side wall of the silicon oxide film formed in a self-aligned manner on the side of the gate electrode, the source and drain regions are implanted by implanting a high concentration of dopant. 209 can be formed in a self-aligned manner.

In this embodiment, the LDD region is formed by implanting ions containing germanium after forming the gate electrode and then implanting a low-concentration dopant.
It is also possible to implant ions containing germanium after first implanting a low-concentration dopant. Alternatively, the LDD region can be formed of polycrystalline silicon by implanting ions containing germanium after forming the sidewalls of the insulating film, and only the source and drain regions can be formed of polycrystalline silicon germanium.

Next, as shown in FIG.
The silicon oxide film 210 as an interlayer insulating film is
It is formed to a thickness of about 00 nm. Subsequently, a contact hole is formed by photolithography and an etching process.

Thereafter, Ti serving as a source / drain metal is formed.
/ Al film is formed with a film thickness of 80/4000 nm, and photolithography and an etching process are used to form the film shown in FIG.
As shown in FIG. 7, a desired source / drain metal 211 is formed.

Thereafter, a silicon nitride film having a thickness of about 500 nm is formed as a passivation film by a plasma CVD method. Finally, hydrogenation treatment is performed by annealing in a hydrogen atmosphere or a nitrogen atmosphere at a temperature of about 350 ° C. for about 1 hour to introduce hydrogen into the polysilicon serving as an active layer and the interface between the polysilicon and the gate insulating film. In the hydrogenation treatment step, after the silicon oxide film 210 serving as an interlayer insulating film is formed, hydrogenation by hydrogen radicals can be performed by plasma discharge of hydrogen gas by a plasma CVD method. By performing hydrogenation treatment with hydrogen radicals using plasma, hydrogen is efficiently and sufficiently introduced.

FIG. 3 shows the dependence of the ON current of the NMOS transistor on the activation annealing temperature of the transistor. Here, the activation annealing time is constant at one hour at all annealing temperatures.

Here, when silicon germanium is not used for the source and the drain, the activation annealing temperature is 6
If the temperature is not higher than 00 ° C., the mobility and threshold voltage of the transistor are not saturated. On the other hand, when germanium is implanted, the characteristics are saturated at an annealing temperature of 500 ° C. This shows that the activation annealing temperature can be lowered by using silicon germanium for the source and drain regions and the LDD region.

As a result of measuring the sheet resistance of the source and drain regions and the contact resistance between the source and drain metal, using polycrystalline silicon germanium for the source and drain regions as compared with polycrystalline silicon,
It was found that the sheet resistance and the contact resistance of both the N-type and the P-type were reduced.

From these results, in the thin film transistor using polycrystalline silicon germanium for the source and drain regions, the sheet resistance of the source and drain regions and the contact resistance between the source and drain regions and the source / drain metal are reduced. , N-type transistors also have the feature that the drive current increases.

At an activation annealing temperature of 600 ° C.,
Although the threshold voltage of the NMOS transistor varies greatly, when the source and drain regions are formed of silicon germanium, the variation in the threshold voltage can be significantly reduced at an activation annealing temperature of 500 ° C.

From this, it is possible to lower the activation heat treatment temperature by forming the source and drain regions of the transistor with silicon germanium and to reduce the variation of the threshold voltage in the short channel transistor. Thus, the channel TFT can be actually used.

In a normal polysilicon TFT, the accumulation of holes below the channel during the operation of the transistor causes the potential of the polysilicon substrate to fluctuate, causing instability in the characteristics. With the use of silicon germanium, since silicon germanium has a band offset in the valence band with respect to silicon, holes easily flow to the drain, so that holes hardly accumulate below the channel. Accordingly, there is also a feature that instability of transistor characteristics is eliminated because the channel potential does not fluctuate due to accumulation of holes.

[0045]

As described above, in the thin film transistor of the present invention, it is possible to lower the process temperature for producing the transistor and to realize a short channel transistor which can operate at a low voltage. In addition, even in a short channel transistor, it is possible to obtain uniform and excellent characteristics with little characteristic variation. Further, since the contact resistance and the diffusion resistance in the source / drain portion can be reduced, the driving current of the transistor can be increased. Instability of characteristics is eliminated without accumulation of charge in the channel region, so that a transistor having stable characteristics can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a thin film transistor according to an embodiment of the present invention.

FIG. 2 is a diagram showing a manufacturing process of the thin film transistor according to the embodiment of the present invention.

FIG. 3 is a diagram showing ON current dependency of an NMOS transistor with respect to activation annealing temperature.

DESCRIPTION OF SYMBOLS 104 Channel region 107 LDD region 108 Source / drain region 111 Source / drain metal 201 Glass substrate 202 Silicon oxide film 203 Amorphous silicon film 204 Island-like polycrystalline silicon 205 Gate insulating film 206 Gate electrode 207 n-region 208 Side wall 209 Source and drain region 210 Interlayer insulating film 211 Source / drain metal

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) BA03 BA27 BA43 CA19 DA13 DB04 EB02 FA01 FB02 FB14 GB10 JA01 JA20 5F110 AA04 AA06 AA07 AA09 AA17 AA30 BB01 CC02 DD02 DD13 EE04 EE08 EE32 EE44 FF02 FF30 GG02 GG13 GG45 HJ01 HJ02 HJ04 NN30 QQ24 QQ25

Claims (15)

[Claims] In a thin film transistor formed on an insulating substrate, a source and a drain portion are formed of a material different from a channel region, and a melting point of a material used for the channel region is the source and the drain. A thin film transistor formed of a semiconductor having a higher melting point than a material of the region. 2. A thin film transistor formed on an insulating substrate, wherein a channel region in the transistor is formed of a polycrystalline semiconductor.
The thin film transistor as described in the above. 3. A thin film transistor formed on an insulating substrate, wherein the channel region of the transistor is made of polycrystalline silicon, and the source and drain regions are made of polycrystalline silicon germanium. The thin film transistor as described in the above. 4. A thin film transistor formed on an insulating substrate, wherein a channel region is formed of polycrystalline silicon, source and drain regions are formed of polycrystalline silicon germanium, and germanium atoms in the polycrystalline silicon germanium of the source and drain regions are provided. The concentration is 1% or more and 80% or less.
4. The thin film transistor according to any one of claims 1 to 3. 5. A thin film transistor formed on an insulating substrate, wherein a source and drain region having a lower dopant concentration than the source and drain regions is provided between the channel region and the source and drain regions. 5. The thin film transistor according to any one of items 1 to 4. 6. A thin film transistor formed on an insulating substrate, wherein the dopant concentration in the source and drain regions having a low dopant concentration is one tenth or less of the dopant concentration in the source and drain. The thin film transistor according to claim 1. 7. An array substrate having a thin film transistor, wherein the thin film transistor has a channel portion formed of polycrystalline silicon and a source and a drain portion formed of polycrystalline silicon germanium. 8. A liquid crystal display device of an active matrix drive type having a thin film transistor, wherein the thin film transistor has a channel portion made of polycrystalline silicon, and a source and a drain portion made of polycrystalline silicon germanium. Liquid crystal display device. 9. An active matrix drive type organic EL display device having an organic EL element and a thin film transistor connected to the organic EL element, wherein the thin film transistor has a channel portion made of polycrystalline silicon, and has a source and a rain portion. Is formed from polycrystalline silicon germanium. 10. An implanting step of adding germanium to source and drain regions by implanting ions containing germanium after processing of a gate electrode when forming source and drain regions in a thin film transistor. A crystallization step of crystallizing source and drain regions by performing heat treatment. 11. The implantation amount of germanium-containing ions in the step of implanting germanium-containing ions is one.
The method for producing a thin film transistor according to claim 10, wherein the thickness is not less than × 10 ¹⁴ cm ^{−2 and not} more than 1 × 10 ¹⁷ cm ⁻² . 12. The method according to claim 10, wherein the heat treatment performed after the implantation step according to claim 10 is performed at a temperature of 600 ° C. or less. 13. The method for manufacturing a thin film transistor according to claim 10, wherein the heat treatment performed after the injection step according to claim 10 is performed by an apparatus using light as a heat source. 14. A method for manufacturing a thin film transistor, comprising:
A step of adding germanium to the source and drain regions by implanting ions containing germanium after processing the gate electrode, and a step of forming source and drain regions containing low-concentration dopants by implanting low-concentration dopants A step of continuously forming an insulating film, a step of forming an insulating film side wall formed of the insulating film on the side of the gate electrode in a self-aligned manner by anisotropic etching, and a step of implanting a high concentration dopant to Forming a drain region. 15. The method according to claim 14, wherein the insulating film formed on the side of the gate electrode is a silicon oxide film or a laminated film of a silicon oxide film and a silicon nitride film.