KR20000046960A - Fabrication method of transistor of semiconductor device - Google Patents
Fabrication method of transistor of semiconductor device Download PDFInfo
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- KR20000046960A KR20000046960A KR1019980063699A KR19980063699A KR20000046960A KR 20000046960 A KR20000046960 A KR 20000046960A KR 1019980063699 A KR1019980063699 A KR 1019980063699A KR 19980063699 A KR19980063699 A KR 19980063699A KR 20000046960 A KR20000046960 A KR 20000046960A
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- forming
- gate electrode
- transistor
- source
- semiconductor device
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 title claims abstract description 19
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 239000010410 layer Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 125000006850 spacer group Chemical group 0.000 claims abstract description 8
- 239000012535 impurity Substances 0.000 claims abstract description 7
- 239000011229 interlayer Substances 0.000 claims abstract description 6
- 238000005468 ion implantation Methods 0.000 claims description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 5
- 229910052796 boron Inorganic materials 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 4
- 229910019001 CoSi Inorganic materials 0.000 claims description 2
- 229910005883 NiSi Inorganic materials 0.000 claims description 2
- 229910008484 TiSi Inorganic materials 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 9
- 229910021332 silicide Inorganic materials 0.000 abstract 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract 1
- 230000005669 field effect Effects 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000005465 channeling Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Abstract
Description
본 발명은 반도체장치의 트랜지스터 제조방법에 관한 것으로서, 보다 상세하게는 특수한 공정의 추가 없이 얕은 접합의 소오스와 드레인을 형성하여 쇼트 채널 효과를 억제할 뿐만 아니라 제조공정의 단축으로 제조수율을 향상시킬 수 있도록 한 반도체장치의 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor manufacturing method of a semiconductor device, and more particularly, to form a source and a drain of a shallow junction without adding a special process to suppress short channel effects and to improve manufacturing yield by shortening the manufacturing process. The present invention relates to a transistor manufacturing method of a semiconductor device.
전계효과 트랜지스터(Field-Effect Transistor; FET)라 함은 다수 캐리어가 반도체 표면을 따라서 드리프트 하는 것을 게이트 전계에 의해 제어하는 방식의 트랜지스터를 말하는 것으로서 소수캐리어의 주입이 없으므로 축적효과에 의한 응답 속도의 저하가 없고, 잡음이 적은 장점이 있다. 전계효과 트랜지스터에는 게이트의 구조에 의해 접합형 전계효과 트랜지스터(Junction Field-Effect Transistor ; JFET)와 쇼트키 장벽 게이트형 및 절연 게이트형 전계효과 트랜지스터(Insulator Gate Field Effect Transistor ; IGFET)가 있다.Field-Effect Transistors (FETs) refer to transistors in which a majority of carriers drift along the semiconductor surface by means of a gate electric field, and there is no injection of a small number of carriers, thereby reducing the response speed due to the accumulation effect. There is no noise and low noise. Field effect transistors include junction field-effect transistors (JFETs) and Schottky barrier gate type and insulator gate field effect transistors (IGFETs) by gate structures.
MOS트랜지스터의 경우에는 쇼트 채널화와 함께 핫캐리어에 의한 소자의 특성 저하가 심화되어 소자의 동작 전압을 그만큼 낮게 설정하게 되었으며 소자의 드레인 구조도 n+ 농도의 드레인 구조의 주위를 저농도로 감싸준 DDD(Double Diffused Drain)구조와 드레인과 채널과의 연결 부위의 농도를 낮추어 준 LDD(Lightly Doped Drain)구조로 개량되었다.In the case of MOS transistors, short channelization and deterioration of device characteristics due to hot carriers have increased, and the operating voltage of the device has been set as low as possible. Diffused Drain (LDD) structure and LDD (Lightly Doped Drain) structure that reduced the concentration of the connection between the drain and the channel.
도 1 내지 도 4는 종래의 LDD구조의 트랜지스터 제조 방법을 설명하기 위한 LDD 구조를 갖는 트랜지터의 게이트 형성공정을 단계적으로 나타낸 단면도들이다.1 to 4 are cross-sectional views sequentially illustrating a gate forming process of a transistor having an LDD structure for explaining a conventional LDD structure transistor manufacturing method.
먼저, 도 1과 같이 반도체기판(10) 위에 소자간 격리를 위한 필드산화막(20)을 형성하고 게이트산화막(30)과 게이트폴리막(40)을 차례대로 증착한다.First, as shown in FIG. 1, a field oxide film 20 for isolation between devices is formed on the semiconductor substrate 10, and the gate oxide film 30 and the gate poly film 40 are sequentially deposited.
그런다음, 도 2와 같이 도 1에서 증착된 게이트폴리막(40)과 게이트산화막(30)을 마스크를 통해 이방성식각하여 게이트전극(42)을 형성한다.Then, as shown in FIG. 2, the gate poly film 40 and the gate oxide film 30 deposited in FIG. 1 are anisotropically etched through a mask to form the gate electrode 42.
그 다음은, 도 3과 같이 소오스/드레인영역(50)이 형성될 부분에 p형 불순물을 얇게 도핑시켜 p- 접합층(52)을 형성시킨다.Next, as shown in FIG. 3, a p-type impurity is lightly doped in a portion where the source / drain region 50 is to be formed to form the p− junction layer 52.
그런다음, 도 4와 같이 결과물 전면에 100Å 정도 질화막을 증착하고 블랭킷 식각을 하여 게이트 전극(42) 양측면에 스페이서(60)를 형성한 후 p형 불순물을 강하게 주입시키고 열공정을 실시하여 소오스/드레인영역(50)의 p+ 접합층(54)을 형성한다.Next, as shown in FIG. 4, a nitride film is deposited on the entire surface of the resultant and blanket is etched to form spacers 60 on both sides of the gate electrode 42. Then, p-type impurities are strongly injected and thermal processes are performed. P + junction layer 54 of region 50 is formed.
위와 같이 반도체기판(10)에 게이트산화막(30), 게이트전극(42)을 형성하고 소오스/드레인영역(50)인 소오스/드레인이 형성될 채널영역 형성부분에 감광막 패턴을 형성하고 p- 이온주입을 실시하고, 그 후 스페이서(60)를 형성한 후 다시 p+이온주입을 실시한 후 열공정을 실시하여 LDD구조의 트랜지스터를 형성하게 된다.As described above, the gate oxide film 30 and the gate electrode 42 are formed on the semiconductor substrate 10, and the photoresist pattern is formed on the channel region forming portion where the source / drain region, which is the source / drain region 50, is formed. After that, the spacer 60 is formed, and then p + ion implantation is performed again, followed by a thermal process to form a transistor having an LDD structure.
위와 같은 LDD구조로도 점차적으로 고집적화 되어감에 따라 채널길이가 작아지게 되어 핫캐리어 효과 및 쇼트 채널 효과에 의한 트랜지스터의 특성저하가 발생된다는 문제점이 있다.In the LDD structure as described above, as the channel density is gradually increased, there is a problem that the characteristics of the transistor are reduced due to the hot carrier effect and the short channel effect.
이러한 쇼트 채널 효과를 억제하기 위해 소오스/드레인의 얕은 접합화가 진행되고 있으나 얕은 접합 형성방법은 프로세스가 복잡하고, 특수공정이 추가되기 때문에 이러한 복잡한 프로세스에 의해 결함이 많이 발생하여 제조수율이 저하된다는 문제점이 있다.In order to suppress such short channel effects, shallow junctions of the source / drain are being progressed, but the shallow junction formation method is complicated by a process, and a special process is added. There is this.
또한, 위와 같이 p+ 접합층의 도판트로 사용되는 보론은 원자량이 11로써 가장 작은 불순물로 확산율이 매우빨라 이온주입되어 얕은 접합 형성자체가 매우어렵기 때문에 쇼트 채널 효과가 현저하게 나타나게 된다는 문제점이 있다.In addition, as described above, boron used as a dopant of the p + junction layer has a problem that the short channel effect is remarkable because the diffusion rate is very fast with the smallest impurities having an atomic weight of 11, and the shallow junction formation itself is very difficult.
본 발명은 상기와 같은 문제점을 해결하기 위해 창작된 것으로서, 본 발명의 목적은 특수한 공정의 추가 없이 얕은 접합의 소오스와 드레인을 형성하여 쇼트 채널 효과를 억제할 뿐만 아니라 제조공정의 단축으로 제조수율을 향상시킬 수 있도록 한 반도체장치의 트랜지스터 제조방법을 제공함에 있다.The present invention has been made to solve the above problems, an object of the present invention is to form a shallow junction source and drain without the addition of a special process to suppress the short channel effect as well as to reduce the production yield The present invention provides a method for manufacturing a transistor of a semiconductor device that can be improved.
도 1 내지 도 4는 종래의 LDD구조의 트랜지스터 제조방법을 설명하기 위한 LDD 구조를 갖는 트랜지터 제조공정을 단계적으로 나타낸 단면도들이다.1 to 4 are cross-sectional views sequentially illustrating a transistor manufacturing process having an LDD structure for explaining a conventional transistor manufacturing method of an LDD structure.
도 5 내지 도 8은 본 발명에 의한 얕은 접합 구조의 트랜지스터 제조방법을 설명하기 위한 트랜지스터 제조공정을 순차적으로 도시한 단면도들이다.5 to 8 are cross-sectional views sequentially illustrating a transistor manufacturing process for explaining a transistor manufacturing method of a shallow junction structure according to the present invention.
- 도면의 주요부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings
10 : 기판 42 : 게이트전극10: substrate 42: gate electrode
50 : 소오스/드레인영역 52 : p- 접합층50 source / drain region 52 p-junction layer
54 : p+ 접합층 60 : 스페이서54: p + junction layer 60: spacer
70 : 살리사이드층 80 : 층간절연막70 salicide layer 80 interlayer insulating film
90 : 금속 패턴90: metal pattern
상기와 같은 목적을 실현하기 위한 본 발명은 기판위로 게이트전극을 형성한 후 p- LDD 이온주입하는 단계와, 게이트전극 측벽에 스페이서를 형성하는 단계와, 게이트전극 상부와 p- LDD 이온주입된 상부에 살리사이드층을 형성하는 단계와, 결과물 전면에 층간절연막을 형성한 후 소오스/드레인 영역에 콘택을 형성하는 단계와, 콘택을 통해 p+ 이온주입하여 p+ 접합층을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.The present invention for achieving the above object is the step of forming a gate electrode on the substrate and then implanting p-LDD ions, forming a spacer on the sidewall of the gate electrode, the gate electrode and the p-LDD ion implanted top Forming a salicide layer on the substrate; forming an interlayer insulating film on the entire surface of the resultant; forming a contact in the source / drain region; and forming a p + junction layer by implanting p + ion through the contact. It features.
위에서 p- LDD 이온주입시 얕은 접합을 형성하기 위해 BF2와, BF2를 끌어당기고 기판의 결정구조를 파괴시켜 이온주입의 채널링을 방지하는 Ge을 순차적으로 주입한다.When on the p- LDD ion implantation for forming a shallow junction pulling and BF 2, BF 2 is injected into the Ge that by destroying the crystal structure of the substrate preventing channeling of ion-implantation in order.
또한, 살리사이드층은 균일한 면저항을 갖는 물질로 형성한다.In addition, the salicide layer is formed of a material having a uniform sheet resistance.
위와 같은 방법에 의한 본 발명의 작용을 설명하면 다음과 같다.Referring to the operation of the present invention by the above method as follows.
p- LDD 이온주입시 얕은 접합을 형성하기 위한 BF2, Ge을 순차적으로 주입하여 얕은 접합을 형성한 후, 스페이서를 형성하고 면저항 균일도가 우수한 살리사이드층을 형성한 후, 층간절연막을 형성하고 p+ 접합층이 형성될 영역에 콘택을 형성한 후 p+ 불순물을 강하게 주입하여 p+ 접합층을 형성하여 낮은 접촉저항을 갖는 얕은 접합의 소오스/드레인을 형성하게 된다.When implanting p- LDD ion, BF 2 and Ge are sequentially injected to form a shallow junction, and then a shallow junction is formed, a spacer is formed, a salicide layer having excellent sheet resistance uniformity is formed, and an interlayer insulating film is formed. After forming a contact in a region where a junction layer is to be formed, a p + junction layer is formed by strongly injecting p + impurities to form a source / drain of a shallow junction having a low contact resistance.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. 또한 본 실시예는 본 발명의 권리범위를 한정하는 것은 아니고, 단지 예시로 제시된 것이며 종래 구성과 동일한 부분은 동일한 부호 및 명칭을 사용한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.
도 5 내지 도 8은 본 발명에 의한 얕은 접합 구조의 트랜지스터 제조방법을 설명하기 위한 트랜지스터 제조공정을 순차적으로 도시한 단면도들이다.5 to 8 are cross-sectional views sequentially illustrating a transistor manufacturing process for explaining a transistor manufacturing method of a shallow junction structure according to the present invention.
도 5와 같이 기판(10)위로 게이트전극(42)을 형성한 후 p- LDD 이온주입으로 BF2를 10 KeV의 에너지로 주입하고 소오스/드레인 영역(50)의 실리콘의 결정구조를 파괴하여 이온주입의 채널링을 방지하고 BF2를 끌어당기는 Ge를 60 KeV의 에너지와 1×1015∼10×1015ions/㎤ 로 주입하여 p- 접합층(52)의 얕은 접합을 형성한다.After forming the gate electrode 42 on the substrate 10 as shown in FIG. 5, BF 2 is implanted with 10 KeV of energy through p-LDD ion implantation, and the crystal structure of silicon in the source / drain region 50 is destroyed. Ge, which prevents channeling of the implant and attracts BF 2 , is implanted with energy of 60 KeV at 1 × 10 15 to 10 × 10 15 ions / cm 3 to form a shallow junction of the p-junction layer 52.
그런다음, 도 6과 같이 게이트전극(42)의 측벽에 스페이서(60)를 형성한다.Then, spacers 60 are formed on the sidewalls of the gate electrode 42 as shown in FIG. 6.
그리고, 도 7과 같이 좁은 폭의 소오스/드레인영역(50) 상부와 게이트전극(42) 상부에 매우 균일한 면저항을 갖는 TiSi2, NiSi, CoSi2중 어느 하나로 살리사이드층(70)을 형성한다.As shown in FIG. 7, the salicide layer 70 is formed of any one of TiSi 2 , NiSi, and CoSi 2 having a very uniform sheet resistance on the narrow source / drain region 50 and the gate electrode 42. .
그런다음, 도 8과 같이 결과물 전면에 층간절연막(80)을 형성한 후 소오스/드레인 영역(50)에 콘택을 형성하고 강하게 보론을 도핑하여 p+ 접합층(54)을 형성한다. 이후 금속 패턴을 형성하여 소오스/드레인 영역(50)과 금속 패턴(90)과의 접촉저항을 낮출수 있도록 한다.Then, as shown in FIG. 8, after forming the interlayer insulating film 80 on the entire surface of the resultant, a contact is formed in the source / drain region 50 and strongly doped with boron to form a p + junction layer 54. Thereafter, a metal pattern is formed to lower the contact resistance between the source / drain region 50 and the metal pattern 90.
상기한 바와 같이 본 발명은 p+ 접합층을 형성하기 위한 이온주입 마스크 패턴없이 소오스/드레인 영역에 콘택을 형성한 후 보론을 도핑하여 형성함으로써 소오스/드레인 영역과 폴리실리콘 패드와의 접촉저항을 줄일 수 있도록 하여 간단한 제조공정으로 접촉저항을 줄일 수 있을 뿐만 아니라 제조수율의 향상 및 제조단가를 줄일 수 있다는 이점이 있다.As described above, the present invention can reduce the contact resistance between the source / drain region and the polysilicon pad by forming a contact in the source / drain region without the ion implantation mask pattern for forming the p + junction layer and then doping with boron. In order to reduce the contact resistance by a simple manufacturing process, there is an advantage that the manufacturing yield can be improved and the manufacturing cost can be reduced.
또한, 확산속도가 매우빠른 보론 도판트에 대해 쇼트 채널효과를 억제할 수 있어 p형 얕은 접합을 형성할 수 있어 고집적에 매우 용이하다는 이점이 있다.In addition, the short channel effect can be suppressed for the boron dopant having a very high diffusion rate, so that a p-type shallow junction can be formed, which is very easy for high integration.
Claims (4)
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| KR1019980063699A KR20000046960A (en) | 1998-12-31 | 1998-12-31 | Fabrication method of transistor of semiconductor device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100476887B1 (en) * | 2002-03-28 | 2005-03-17 | 삼성전자주식회사 | Mos transistor with extended silicide layer of source/drain region and method of fabricating thereof |
| KR100477473B1 (en) * | 2000-08-02 | 2005-03-17 | 마쯔시다덴기산교 가부시키가이샤 | Thin film transistor and fabrication method thereof and thin film transistor array board, liquid crystal display device and electro-luminescence display device |
| KR100491141B1 (en) * | 2001-03-02 | 2005-05-24 | 삼성에스디아이 주식회사 | TFT and Method for Fabricating the Same and Active Matrix display device and Method for fabricating the Same using the TFT |
-
1998
- 1998-12-31 KR KR1019980063699A patent/KR20000046960A/en not_active Application Discontinuation
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100477473B1 (en) * | 2000-08-02 | 2005-03-17 | 마쯔시다덴기산교 가부시키가이샤 | Thin film transistor and fabrication method thereof and thin film transistor array board, liquid crystal display device and electro-luminescence display device |
| KR100491141B1 (en) * | 2001-03-02 | 2005-05-24 | 삼성에스디아이 주식회사 | TFT and Method for Fabricating the Same and Active Matrix display device and Method for fabricating the Same using the TFT |
| US7488982B2 (en) | 2001-03-02 | 2009-02-10 | Samsung Mobile Display Co., Ltd. | Thin film transistor and manufacturing method thereof, and active matrix display device and manufacturing method thereof |
| KR100476887B1 (en) * | 2002-03-28 | 2005-03-17 | 삼성전자주식회사 | Mos transistor with extended silicide layer of source/drain region and method of fabricating thereof |
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