JP2933121B2 - Method for manufacturing thin film transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor formed by a thin film process, and more particularly, to polysilicon (ie, polycrystalline silicon) used as a switching element of an active matrix liquid crystal display and its peripheral driving circuit. The present invention relates to a method for manufacturing a thin film transistor using as an active layer.

[0002]

2. Description of the Related Art In a liquid crystal display panel, a hydrogenated amorphous silicon thin film transistor (hereinafter referred to as a thin film transistor) is formed on an insulating substrate by a thin film process because it can form a large area at a low temperature as an element for driving a liquid crystal display. , A-Si: H TFT). Further, for realization of a high-definition and small-sized panel, a thin film transistor (hereinafter, referred to as a polysilicon TFT) using polysilicon as an active layer, which can be used as a switching element of a liquid crystal driving element and a peripheral driving circuit thereof, is expected. ing.

[0003] Polysilicon TFTs have higher carrier mobility than a-Si: H TFTs, so they can perform high switching operations and can be applied to peripheral driving circuits, but they have crystal grains. Since the off-leak current generated by the application of an electric field to the field is high, and the image quality of the liquid crystal display panel is reduced, there is a problem that it is not suitable as a switching element for driving a liquid crystal. Therefore, as measures to reduce off-leakage current, the LightlyDoped Dra
In structures (LDD structures), offset structures, multi-gate structures, and the like have been proposed. However, according to these structures, new problems such as an increase in resistance of the source region and the drain region, a decrease in on-current due to a decrease in leak current, and an increase in element size occur.

[0004]

Therefore, a field-induction-drain structure (FID structure) has been proposed as a means for further reducing the leak current (K. Tanaka et.al, Ex.
tended Abstracts of 22th Int. Conf. on Solid State
Devices and Materials, 1990, pp1011). FIG.
It is sectional drawing which shows the conventional thin film transistor (TFT) which has an ID structure. This proposal, as shown in FIG.
By applying a positive bias to the second gate 502 when the channel type TFT is off (first gate Vg <0), the FID
The region 508 is inverted to reduce the electric field applied to the end of the drain 505. This structure has a feature that the off-state current can be reduced without lowering the on-state current, and is advantageous as compared with the proposed structure and the like. However, this structure has a first gate electrode (main-gate electrode) 50 as shown in FIG.
1 requires a second gate electrode (sub-gate electrode) 502 with an interlayer insulating film 503 interposed therebetween.
Since it is necessary to apply a reverse bias to the second gate electrode 502, there is a problem that the manufacturing process is many and complicated, and the cost of the device is high.

An object of the present invention is to provide a thin film transistor which has both good transistor characteristics and low leakage current (for example, 1 pA or less).

It is another object of the present invention to provide a thin film transistor having a simple structure, a small number of manufacturing steps, and the above characteristics.

Still another object of the present invention is to provide a method of manufacturing a thin film transistor which can relatively easily obtain the above thin film transistor.

[0008]

According to the present invention, there are provided a source / drain electrode, polysilicon serving as a channel, a gate insulating film, and a gate electrode formed on an insulating substrate. The polysilicon includes at least two types of polysilicon portions, a first polysilicon portion located near the drain end and a second polysilicon portion located in all channel regions except the first polysilicon portion. The gate inversion voltage of the first polysilicon portion is lower than the gate voltage of the second polysilicon portion, and n
In a method of manufacturing a thin film transistor for manufacturing a channel type thin film transistor, the method further includes a step of forming the polysilicon serving as the channel by pulsed laser irradiation. A method for manufacturing a thin film transistor characterized by being covered with a silicon layer is obtained.

According to the present invention, there is provided a semiconductor device having a source / drain electrode, polysilicon serving as a channel, a gate insulating film, and a gate electrode formed on an insulating substrate. And at least two types of polysilicon portions, a first polysilicon portion located near the end and a second polysilicon portion located in all channel regions excluding the first polysilicon portion.
The gate inversion voltage of the polysilicon portion is higher than the gate voltage of the second polysilicon portion, and in the method for manufacturing a thin film transistor for manufacturing a p-channel type thin film transistor, in the method of manufacturing a p-channel type thin film transistor, A method for manufacturing a thin film transistor is provided, comprising a step of forming by laser irradiation, wherein only the second polysilicon portion is covered with a silicon dioxide layer during pulsed laser irradiation.

[0010]

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a thin film transistor according to the present invention and a method for manufacturing the same will be described with reference to the drawings.

[First Embodiment] FIG. 1 is a sectional view showing a thin film transistor according to a first embodiment of the present invention.
FIG. 4 is a view for explaining a manufacturing process of the first polysilicon portion and the second polysilicon portion. Hereinafter, with reference to FIG. 1 and FIG.
Will be described.

Referring to FIG. 1, an a-Si thin film is deposited on a quartz or alkali-free glass substrate 109 by LPCVD (Low Pressure Chemical Vapor Deposition) and then polycrystallized by solid phase growth. . The deposition temperature is 450 ° C., the film thickness is 100 nm, and the solid phase growth temperature × time is 600 ° C. × 24 hours. A photoresist pattern is formed on the polysilicon thin film thus formed, and phosphorus ions are implanted using the photoresist as a mask to form a source electrode 105 and a drain electrode 104. Next, the polysilicon layer is processed into an island shape using photolithography and dry etching (source electrode 105, channel region 1).
06 and the drain electrode 104).

Next, the steps of manufacturing the first polysilicon portion and the second polysilicon portion will be described. Referring to FIG. 2, a photoresist pattern is formed on polysilicon layer 204 on glass substrate 109, and low-concentration ion implantation of phosphorus is performed using photoresist as implantation mask 202 to form phosphorus doping layer 206. The dose is 3 × 10 ¹²
cm ^-2 . As a result, the gate inversion voltage of the phosphorus doping layer portion shifts by about 10 V in the negative direction.

Next, referring to FIG. 1 again, after washing with heated sulfuric acid and nitric acid, washing with water is sufficiently performed, and after drying, L
SiO ₂ is used as the gate insulating film 103 by PCVD.
Deposit 20 nm. The deposition temperature is 400 ° C. After the deposition, referring to FIG. 1 and FIG. 2 together, an ion implantation region (highly doped layer 203, phosphorus doped layer 206,
Alternatively, activation of the drain electrode 104, the source electrode 105, and the first polysilicon portion 107 in FIG. 1) is performed at 600 ° C. for 12 hours. Thereafter, referring to FIG. 1, Al is deposited as a gate electrode 101 by a 300 nm sputtering method, and is patterned by photolithography and dry etching. Further, for the purpose of hydrogen passivation of polysilicon, hydrogen plasma processing is performed to improve characteristics. The treatment was performed at 350 ° C. for 30 minutes using RF plasma having parallel plate electrodes. After this,
An interlayer insulating film 102 is formed as a passivation film.

The thin film transistor (channel width 4 μm, channel length 4 μm (second
+2 μm (first polysilicon part)
The drain current (ID) -gate voltage (VG) characteristic (drain voltage VD = 10 V) of the sample was measured, and the off current was 4 × 10 ⁻¹³ A (VG = −6 V) and the on current was 2 × 10
^-5 A (VG = 10 V) and sufficient characteristics for driving a liquid crystal element.

In the n-channel type thin film transistor according to the first embodiment, when a negative bias is applied to the gate electrode 101, the region of the second polysilicon portion 108 is in an accumulation state, so that the transistor is off. At this time, the first polysilicon portion 107 is in a reversed state at a lower voltage than the second polysilicon portion 108, that is, in a negative bias state. Therefore, like the above-described conventional FID structure thin film transistor, the drain electrode The electric field applied to the 104 end can be reduced. On the other hand, when a positive bias is applied to the gate electrode 101, the first polysilicon portion 107 and the second polysilicon portion 10 are turned on.
The regions 8 are both turned on, and there is no decrease in the on-current.

Second Embodiment A thin film transistor according to a second embodiment of the present invention has a first polysilicon portion in which polysilicon serving as a channel is located near the drain end and an entire channel region excluding the first polysilicon portion. And at least two types of polysilicon portions located in the first polysilicon portion, the gate inversion voltage of the first polysilicon portion is higher than the gate inversion voltage of the second polysilicon portion,
This is a p-channel thin film transistor, and has the same operation and effect as the n-channel thin film transistor in Embodiment 1. The p-channel thin film transistor according to the second embodiment is manufactured by replacing phosphorus in the manufacturing method of the n-channel thin film transistor of the first embodiment with boron.

[Embodiment 3] Embodiment 3 of the present invention
Is a method for manufacturing a thin film transistor according to the present invention, and the manufacturing process of the first polysilicon portion and the second polysilicon portion is different from the manufacturing process of the first embodiment (FIG. 2). However, the thin film transistor finally obtained by this manufacturing method has the structure shown in FIG. 1 as in the first embodiment.

First, as in the first embodiment (FIG. 1), the L
An a-Si thin film is deposited by a PCVD method. The deposition temperature is 450 ° C. and the film thickness is 100 nm. A photoresist pattern is formed on the polysilicon thin film thus formed, and phosphorus ions are implanted using the photoresist as a mask to form a source electrode 105 and a drain electrode 104. Next, the polysilicon layer is processed into an island shape using photolithography and dry etching (see the source electrode 105, the channel region 106, and the drain electrode 104).

FIG. 3 is a view for explaining a manufacturing process of the first polysilicon portion and the second polysilicon portion according to the third embodiment. Referring to FIG. 3, glass substrate 10
After forming SiO ₂ as an annealing cap film on the polysilicon layer on 9 (see the drain electrode 104, the source electrode 105, and the channel region 106), a resist pattern is formed by photolithography, and the photoresist is used as a mask. The SiO ₂ layer on the non-cap annealed polysilicon portion 307 is removed with hydrofluoric acid to form an annealed cap film 301. The thickness of the annealing cap film 301 is 100 nm.

In this state, excimer laser annealing (EL
A) Perform 302. The laser is a XeCl laser having a wavelength of 308 nm and a pulse width of 50 nsec.
mJ and the number of irradiations were 15 shots. In this embodiment, X
Although the eCl laser is used, similar effects can be obtained by other excimer lasers such as ArF, KrF, and XeF, and pulsed lasers such as a YAG laser. As a result, the non-cap-annealed polysilicon portion 307 (the first polysilicon portion 107 in FIG. 1) and the cap-annealed polysilicon portion 308 (the second polysilicon portion 10 in FIG. 1)
8) are simultaneously formed.

As a sample for comparison of characteristics described later, a thin film transistor having only a non-cap annealing polysilicon portion as polysilicon and a thin film transistor having only a cap annealing polysilicon portion 308 as polysilicon were also manufactured.

After the annealing cap film 301 is peeled off with hydrofluoric acid, referring to FIG. 1, as in the first embodiment, cleaning with heated sulfuric acid and nitric acid is performed, and then water washing is sufficiently performed.
After drying, Si is used as the gate insulating film 103 by LPCVD.
O ₂ is deposited at a deposition temperature of 400 ° C. to a thickness of 120 nm. After the deposition, the ion implantation region (the drain electrode 104, the source electrode 105, the first
Is activated at 600 ° C. for 12 hours. Thereafter, Al is deposited as the gate electrode 101 by a 300 nm sputtering method, and is patterned by photolithography and dry etching. further,
For hydrogen passivation of polysilicon, R
Using F plasma, the hydrogen plasma processing is performed at a processing temperature of 350.
Perform at 30 ° C. for 30 minutes to improve the characteristics. After that, an interlayer insulating film 102 is formed as a passivation film. According to the manufacturing method of the third embodiment described above, a thin film transistor having the same structure as that of the first embodiment and shown in FIG. 1 was obtained. That is, according to the third embodiment, the cap-annealed polysilicon film 308 and the non-cap-annealed polysilicon film 307 as shown in FIG. 3 can be simultaneously formed in the channel region 106, and the thin film transistor according to the present invention can be easily manufactured. Needless to say, a p-channel thin film transistor can be manufactured by replacing phosphorus with boron in the third embodiment.

A thin film transistor (channel width 4 μm, channel length 4 μm) manufactured through the process according to the third embodiment
The drain current (ID) -gate voltage (VG) characteristic (drain voltage VD = 10 V) of (second polysilicon portion) +2 μm (first polysilicon portion) was measured. FIG.
Shows the drain current (ID) -gate voltage (VG) characteristics of the thin film transistor of the present invention according to Embodiment 3 in Sample A.
FIG. In FIG. 4, the thin film transistor according to the present invention has good on / off characteristics, and the thin film transistor (sample B) having only the non-cap-annealed polysilicon portion 307 as polysilicon, and the thin film transistor having only the cap-annealed polysilicon portion 308 as polysilicon. Compared with the thin film transistor having silicon (sample C),
It can be seen that the effect of reducing the leak current is remarkable. In particular, the sample B has a low flat band voltage and a low threshold value, that is, a low gate inversion voltage.

[0026]

According to the thin film transistor of the present invention, the first polysilicon portion in which the polysilicon serving as the channel is located near the drain end and the second polysilicon portion located in the entire channel region except for the first polysilicon portion are provided. Wherein the gate inversion voltage of the first polysilicon portion is lower or higher than the gate inversion voltage of the second polysilicon portion;
Even without te, almost -10 volts <gate voltage Vg <0
In the range of volts, the vicinity of the drain becomes an n-state,
A reverse bias junction is formed. As a result, the sub-ga
Te can be omitted, and the structure can be simplified. Further, since an FID structure capable of obtaining the FID effect is realized by adding only a few steps, low cost and low leakage without sacrificing on-current (for example, 1 pA or less is possible). Can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a thin film transistor according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining a method of manufacturing the thin film transistor shown in FIG.

FIG. 3 is a view illustrating a method for manufacturing a thin film transistor according to a third embodiment of the present invention.

FIG. 4 is a diagram showing drain current-gate voltage characteristics of a thin film transistor manufactured according to a third embodiment, together with characteristics of a sample for comparison.

FIG. 5 is a sectional view showing a thin film transistor according to a conventional example.

[Explanation of symbols]

 Reference Signs List 101 gate electrode 102, 503 interlayer insulating film 103 gate insulating film 104 drain electrode 105 source electrode 106 channel region 107 first polysilicon portion 108 second polysilicon portion 109, 509 glass substrate 201 phosphorus doping 202 implantation mask 203 high concentration Doping layer 204 polysilicon layer 206 phosphorus doping layer 301 anneal cap film 302 excimer laser anneal (ELA) 307 non-cap anneal polysilicon portion 308 cap anneal polysilicon portion 501 first gate electrode 502 second gate electrode 504 gate insulating film 508 FID region

Claims (2)

(57) [Claims] 1. A semiconductor device having a source / drain electrode, polysilicon serving as a channel, a gate insulating film, and a gate electrode formed on an insulating substrate, wherein the polysilicon serving as a channel is located near a drain end. A first polysilicon portion and at least two types of polysilicon portions located in all channel regions excluding the first polysilicon portion, wherein a gate inversion of the first polysilicon portion is included; The voltage is lower than the gate voltage of the second polysilicon portion. In the method of manufacturing a thin film transistor for manufacturing an n-channel thin film transistor, the step of forming the polysilicon to be the channel by pulsed laser irradiation is included. Wherein only the second polysilicon portion is covered with a silicon dioxide layer at the time of pulse laser irradiation. A method for manufacturing a thin film transistor. 2. A semiconductor device comprising a source / drain electrode, polysilicon serving as a channel, a gate insulating film, and a gate electrode formed on an insulating substrate, wherein the polysilicon serving as a channel is located near a drain end. A first polysilicon portion and at least two types of polysilicon portions located in all channel regions excluding the first polysilicon portion, wherein a gate inversion of the first polysilicon portion is included; The voltage is higher than the gate voltage of the second polysilicon portion. In the method of manufacturing a thin film transistor for manufacturing a p-channel thin film transistor, the step of forming the polysilicon to be the channel by pulse laser irradiation is included. Wherein only the second polysilicon portion is covered with a silicon dioxide layer at the time of pulse laser irradiation. A method for manufacturing a thin film transistor.