CN100368911C - Liquid crystal display device - Google Patents
Liquid crystal display device Download PDFInfo
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- CN100368911C CN100368911C CNB2005100064894A CN200510006489A CN100368911C CN 100368911 C CN100368911 C CN 100368911C CN B2005100064894 A CNB2005100064894 A CN B2005100064894A CN 200510006489 A CN200510006489 A CN 200510006489A CN 100368911 C CN100368911 C CN 100368911C
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- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 28
- 239000010410 layer Substances 0.000 claims description 50
- 239000004065 semiconductor Substances 0.000 claims description 38
- 239000000758 substrate Substances 0.000 claims description 36
- 229910045601 alloy Inorganic materials 0.000 claims description 31
- 239000000956 alloy Substances 0.000 claims description 31
- 238000000034 method Methods 0.000 claims description 18
- 239000012212 insulator Substances 0.000 claims description 16
- 230000015572 biosynthetic process Effects 0.000 claims description 13
- 239000011229 interlayer Substances 0.000 claims description 12
- 238000002347 injection Methods 0.000 abstract 2
- 239000007924 injection Substances 0.000 abstract 2
- 238000005468 ion implantation Methods 0.000 description 14
- 230000000694 effects Effects 0.000 description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 230000002860 competitive effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
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- Thin Film Transistor (AREA)
Abstract
The present invention relates to a liquid crystal display device which comprises a first N-shaped LLD (light doped drain) and a second N-shaped LDD, wherein a gate electrode is used as a mask, the N-shaped LDD is formed by an inclined injection mode, and the first N-shaped LDD and the second N-shaped LDD are respectively connected with a source electrode / drain region. The liquid crystal display device comprises a third P-shaped LDD and a fourth P-shaped LDD, a gate electrode is used as a mask in the same way, and the P-shaped LDD is formed by an inclined injection mode, wherein the third P-shaped LDD and the fourth P-shaped LDD respectively surround the source electrode / drain region, the first N-shaped LDD and the second N-shaped LDD.
Description
Technical field
The present invention is about a kind of liquid crystal indicator, and has a low-doped drain (Lightly Doped Drain especially in regard to a kind of; LDD) liquid crystal indicator.
Prior art
In order to increase the aperture opening ratio of LCD, the raceway groove of low temperature polycrystalline silicon liquid crystal indicator must be dwindled, raceway groove is relatively along with dwindling, the result causes short-channel effect (Shortchannel effect), makes voltage can produce thermoelectronic effect (Hotelectron effect) when executive component.
Again because channel shortening, make depletion region (Depletion region) between being adjacent to source electrode and draining along with voltage-operated and more and more approaching, even link together.Relatively, it is serious and obvious that leakage current of source electrode and drain electrode (Leakage current) and punch through (Punch-through effect) also become thereupon, makes low temperature polycrystalline silicon liquid crystal indicator electrology characteristic degenerate and instability.
Because the P type low-doped drain of routine techniques (P-type lightly doped drain) enclosing region has only N type low-doped drain (N-type lightly doped drain), it is smaller that this element can reduce the effect of leakage current and punchthrough effect, when operating voltage was bigger, source electrode still can produce leakage current and punchthrough effect with the drain electrode lower end area.
Therefore, industry is needed a kind of liquid crystal indicator with low-doped drain badly, and except can reducing thermoelectron, leakage current and penetration effect, product is also more competitive.
Summary of the invention
One of fundamental purpose of the present invention is to provide the liquid crystal indicator of a kind of N of having type LDD, with the electric field between reduction source electrode and the drain electrode, and eliminates thermoelectronic effect.
Another object of the present invention is to provide the liquid crystal indicator of a kind of P of having type LDD, source electrode and drain electrode are surrounded, and then suppress the expansion of depletion region between source electrode and the drain electrode comprehensively, reduce leakage current and punchthrough effect between source electrode and the drain electrode.
According to above-mentioned purpose, the present invention also provides a kind of manufacture method of liquid crystal indicator, and the mask that directly uses grid (Gate electrode) to inject as ion is to form source/drain (source/drain); In addition, form N type LDD and P type LDD, and reach the position that changes LDD, as buried type LDD (Buried lightly doped drain) by changing different incident angles and energy with the method that tilts to inject (tilted implantation).
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, cited below particularlyly go out preferred embodiment, and cooperate appended graphicly, be described in detail below:
The accompanying drawing summary
Figure 1A is the process section of the liquid crystal indicator with P type LDD in accordance with a preferred embodiment of the present invention to 1G;
Fig. 2 A is the process section of the liquid crystal indicator with P type LDD in accordance with a preferred embodiment of the present invention to 2G;
Fig. 3 A is the process section of the liquid crystal indicator with P type LDD in accordance with a preferred embodiment of the present invention to 3G;
Fig. 4 A is the process section of the liquid crystal indicator with P type LDD in accordance with a preferred embodiment of the present invention to 4G.
Embodiment
In order to suppress the expansion of source electrode and drain electrode depletion region comprehensively, reduce leakage current (Leakage current) and punchthrough effect (Punch-through effect) between source electrode and the drain electrode, the invention provides a kind of P type LDD with source electrode and drain electrode and N type LDD encirclement, its formation method as shown in Figures 1 to 4.
According to a preferred embodiment of the invention, shown in Figure 1A to Fig. 1 G, the formation method of above-mentioned liquid crystal indicator comprises following key step: at first, a substrate 102 is provided, then, forms a cushion 104 on aforesaid substrate 102 surfaces, on aforesaid substrate 102, form a semiconductor layer 110, on above-mentioned semiconductor layer 110, form a gate insulator 120 again, on above-mentioned gate insulator 120, form a gate electrode 130 then, shown in Figure 1A.
Then, utilizing ion implantation, is mask with above-mentioned gate electrode 130, injects N type alloy such as As, P, AsH
x, or PH
xIn above-mentioned semiconductor layer 110, to form source/drain regions 140/150, shown in Figure 1B.Above-mentioned N type alloy is to reach between 1 * 10 with the energy between 10 to 20KeV in about direction perpendicular to aforesaid substrate 102 surfaces
15To 5 * 10
15Ions/cm
2Dosage inject in the above-mentioned semiconductor layer 110.
Then, utilizing ion implantation, is mask with above-mentioned gate electrode 130, reaches between 5 * 10 with the energy between 10 to 50KeV in II, I direction respectively
12To 1 * 10
14Ions/cm
2Dosage inject N type alloy such as As, P, AsH
x, or PH
xIn above-mentioned semiconductor layer 110, with the part overlapping N type doped regions of formation, and form N type LDD160 and 161 with above-mentioned source/drain regions 140/150, it is positioned at above-mentioned gate insulator 120 belows, shown in Fig. 1 C and 1D.Above-mentioned II, about 40 to 80 degree of I deviation in driction substrate 102 normals to a surface.
Afterwards, utilizing ion implantation, is mask with above-mentioned gate electrode 130, reaches between 5 * 10 with the energy between 40 to 80KeV in III, IV direction respectively
11To 2 * 10
12Ions/cm
2Dosage inject P type alloy such as B, BH
x, or BF
xIn above-mentioned semiconductor layer 110, contain this source/drain regions 140/150 and this N type LDD160 and 161 respectively to form P type doped regions, and then produce P type LDD165/166, shown in Fig. 1 E and 1F.Above-mentioned III, about 40 to 60 degree of IV deviation in driction substrate 102 normals to a surface.
Then, form an interlayer dielectric layer 170, cover the surface of above-mentioned gate electrode 130 and aforesaid substrate 102.Then form lead 180, to connect above-mentioned source/drain regions 140/150, shown in Fig. 1 G at above-mentioned interlayer dielectric layer 170.
According to another preferred embodiment of the present invention, shown in Fig. 2 A to Fig. 2 G, the formation method of above-mentioned liquid crystal indicator comprises following key step: at first, a substrate 202 is provided, then, forms a cushion 204 on aforesaid substrate 202 surfaces, on aforesaid substrate 202, form a semiconductor layer 210, on above-mentioned semiconductor layer 210, form a gate insulator 220 again, on above-mentioned gate insulator 220, form a gate electrode 230 then, shown in Fig. 2 A.
Then, utilizing ion implantation, is mask with above-mentioned gate electrode 230, reaches between 5 * 10 with the energy between 10 to 50KeV in II, I direction respectively
12To 1 * 10
14Ions/cm
2Dosage inject N type alloy such as As, P, AsH
x, or PH
xIn above-mentioned semiconductor layer 210, to form N type doped regions 232 and 234, shown in Fig. 2 B and 2C.Above-mentioned II, about 40 to 80 degree of I deviation in driction substrate 202 normals to a surface.
Then, utilizing ion implantation, is mask with above-mentioned gate electrode 230, injects N type alloy such as As, P, AsH
x, or PH
xIn the above-mentioned semiconductor layer 210, forming source/drain regions 240/250, and overlapping and form N type LDD260 and 261 with the part of above-mentioned N type doped regions 232 and 234, it is positioned at above-mentioned gate insulator 220 belows, shown in Fig. 2 D.Above-mentioned N type alloy is to reach between 1 * 10 with the energy between 10 to 20KeV in about direction perpendicular to aforesaid substrate 202 surfaces
15To 5 * 10
15Ions/cm
2Dosage inject in the above-mentioned semiconductor layer 210.
Afterwards, utilizing ion implantation, is mask with above-mentioned gate electrode 230, reaches between 5 * 10 with the energy between 40 to 80KeV in III, IV direction respectively
11To 2 * 10
12Ions/cm
2Dosage inject P type alloy such as B, BH
x, or BF
xIn above-mentioned semiconductor layer 210, contain above-mentioned source/drain regions 240/250 and above-mentioned N type LDD260 and 261 respectively to form P type doped regions, and then produce P type LDD265/266, shown in Fig. 2 E and 2F.Above-mentioned III, about 40 to 60 degree of IV deviation in driction substrate 202 normals to a surface.
Then, form an interlayer dielectric layer 270, cover the surface of above-mentioned gate electrode 230 and aforesaid substrate 202.Then form lead 280, to connect above-mentioned source/drain regions 240/250, shown in Fig. 2 G at this interlayer dielectric layer 270.
According to another preferred embodiment of the present invention, shown in Fig. 3 A to Fig. 3 G, the formation method of this liquid crystal indicator comprises following key step: at first, a substrate 302 is provided, then, forms a cushion 304 on aforesaid substrate 302 surfaces, on aforesaid substrate 302, form a semiconductor layer 310, on above-mentioned semiconductor layer 310, form a gate insulator 320 again, on above-mentioned gate insulator 320, form a gate electrode 330 then, as shown in Figure 3A.
Afterwards, utilizing ion implantation, is mask with above-mentioned gate electrode 330, reaches between 5 * 10 with the energy between 40 to 80KeV in III, IV direction respectively
11To 2 * 10
12Ions/cm
2Dosage inject P type alloy such as B, BH
x, or BF
xIn above-mentioned semiconductor layer 310, to form P type doped regions 340/350, shown in Fig. 3 B and 3C.Above-mentioned III, about 40 to 60 degree of IV deviation in driction substrate 302 normals to a surface.
Then, utilizing ion implantation, is mask with above-mentioned gate electrode 330, injects N type alloy such as As, P, AsH
x, or PH
xIn the above-mentioned semiconductor layer 310, forming source/drain regions 360/370, and above-mentioned source/drain regions 360/370 respectively with the overlapping of above-mentioned P type doped regions 340/350, and form P type LDD3401/3501, shown in Fig. 3 D figure.Above-mentioned N type alloy is to reach between 1 * 10 with the energy between 10 to 20KeV in about direction perpendicular to aforesaid substrate 302 surfaces
15To 5 * 10
15Ions/cm
2Dosage inject in the above-mentioned semiconductor layer 310.
Then, utilizing ion implantation, is mask with above-mentioned gate electrode 330, reaches between 5 * 10 with the energy between 10 to 50KeV in I, II direction respectively
12To 1 * 10
14Ions/cm
2Dosage inject N type alloy such as As, P, AsH
x, or PH
xIn above-mentioned semiconductor layer 310, to form overlapping with the part of above-mentioned P type doped regions 340/350 and above-mentioned source/drain regions 360/370 respectively N type doped regions, and producing N type LDD380 and 390, it is positioned at above-mentioned gate insulator 320 belows, shown in Fig. 3 E and 3F.Above-mentioned I, about 40 to 80 degree of II deviation in driction substrate 302 normals to a surface.
Then, form an interlayer dielectric layer 392, cover the surface of above-mentioned gate electrode 330 and aforesaid substrate 302.Then form lead 394, to connect above-mentioned source/drain regions 360/370, shown in Fig. 3 G at above-mentioned interlayer dielectric layer 392.
According to another preferred embodiment of the present invention, shown in Fig. 4 A to Fig. 4 G, the formation method of above-mentioned liquid crystal indicator comprises following key step: at first, a substrate 402 is provided, then, forms a cushion 404 on aforesaid substrate 402 surfaces, on aforesaid substrate 402, form a semiconductor layer 410, on above-mentioned semiconductor layer 410, form a gate insulator 420 again, on above-mentioned gate insulator 420, form a gate electrode 430 then, shown in Fig. 4 A.
Afterwards, utilizing ion implantation, is mask with above-mentioned gate electrode 430, reaches between 5 * 10 with the energy between 40 to 80KeV in III, IV direction respectively
11To 2 * 10
12Ions/cm
2Dosage inject P type alloy such as B, BH
x, or BF
xIn above-mentioned semiconductor layer 410, to form P type doped regions 440/450, shown in Fig. 4 B and 4C.Above-mentioned III, about 40 to 60 degree of IV deviation in driction substrate 402 normals to a surface.
Then, utilizing ion implantation, is mask with above-mentioned gate electrode 430, reaches between 5 * 10 with the energy between 10 to 50KeV in I, II direction respectively
12To 1 * 10
14Ions/cm
2Dosage inject N type alloy such as As, P, AsH
x, or PH
xIn above-mentioned semiconductor layer 410, with overlapping with the part of the above-mentioned P type doped regions 440/450 respectively N type doped regions 460/470 of formation, and form P type LDD4401/4501, shown in Fig. 4 D and 4E.Above-mentioned I, about 40 to 80 degree of II deviation in driction substrate 402 normals to a surface.
Then, utilizing ion implantation, is mask with above-mentioned gate electrode 430, injects N type alloy such as As, P, AsH
x, or PH
xIn above-mentioned semiconductor layer 410, to form source/drain regions 472/474, and above-mentioned source/drain regions 472/474 respectively with the overlapping of above-mentioned P type doped regions 440/450 and above-mentioned N type doped regions 460/470, and generation N type LDD480 and 490, it is positioned at above-mentioned gate insulator 420 belows, shown in Fig. 4 F.Above-mentioned N type alloy is to reach between 1 * 10 with the energy between 10 to 20KeV in about direction perpendicular to aforesaid substrate 402 surfaces
15To 5 * 10
15Ions/cm
2Dosage inject in the above-mentioned semiconductor layer 410.
Then, form an interlayer dielectric layer 492, cover the surface of above-mentioned gate electrode 430 and aforesaid substrate 402.Then form lead 494, to connect above-mentioned source/drain regions 472/474, shown in Fig. 4 G at above-mentioned interlayer dielectric layer 492.
According to another preferred embodiment of the present invention, shown in Fig. 1 G, above-mentioned liquid crystal indicator mainly comprises: a substrate 102 and a cushion 104; Semiconductor layer 110 places on the aforesaid substrate 102; Gate insulator 120 places on the above-mentioned semiconductor layer 110; Gate electrode 130 places on the above-mentioned gate insulator 120; Source/drain regions 140/150, its formation method are to be mask with above-mentioned gate electrode 130, inject N type alloy such as As, P, AsH
x, and PH
xIn above-mentioned semiconductor layer 110; N type LDD160/161 is to be mask with above-mentioned gate electrode, reaches a pitch angle respectively from different directions and injects N type alloy such as As, P, AsH with ion implantation
x, or PH
xIn the above-mentioned semiconductor layer 110, the part that produces N type doped regions and above-mentioned source/drain regions 140/150 is overlapping and form; P type LDD165/166, it is to be mask with above-mentioned gate electrode, reaches a pitch angle respectively from different directions and injects P type alloy such as B, BH with ion implantation
x, or BF
xIn the above-mentioned semiconductor layer 110, produce P type doped regions and contain above-mentioned source/drain regions 140/150 and above-mentioned N type doped regions and form; Interlayer dielectric layer 170 places on the surface of above-mentioned gate electrode 130 and aforesaid substrate; And lead 180, place in the above-mentioned interlayer dielectric layer and the above-mentioned source/drain regions 140/150 of above-mentioned lead 180 connections.
Wherein, above-mentioned source/drain regions is by with above-mentioned N type alloy such as As, P, AsH
x, or PH
xForm approximately injecting in the above-mentioned semiconductor layer 110 perpendicular to the direction on aforesaid substrate surface.
Though it is open that the present invention has come as mentioned above with several preferred embodiments; but it is not to be used for limiting the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; should make and change arbitrarily and revise, so protection scope of the present invention should be with being as the criterion that accompanying claims were limited.
Claims (7)
1. liquid crystal indicator comprises:
A substrate;
A cushion places on this substrate;
A semiconductor layer places on this cushion;
A gate insulator is placed on this semiconductor layer;
A gate electrode places on this gate insulator;
A source/drain regions, its formation method are to be mask with this gate electrode, inject first alloy in this semiconductor layer;
First doped regions, its formation method are to be mask with this gate electrode, inject second alloy in this semiconductor layer in the direction of first angle, and wherein the part of this first doped regions and this source/drain regions is overlapping; And
Second doped regions, its formation method are to be mask with this gate electrode, inject the 3rd alloy in this semiconductor layer in the direction of second angle, and wherein the part of this second doped regions and this source/drain regions is overlapping.
2. liquid crystal indicator as claimed in claim 1 more comprises:
The 3rd doped regions, its formation method are to be mask with this gate electrode, inject the 4th alloy in this semiconductor layer in the direction of third angle degree, and wherein one of this source/drain regions and this first doped regions are contained in the 3rd low-doped drain district; And
The 4th doped regions, its formation method are to be mask with this gate electrode, inject the 5th alloy in this semiconductor layer in the direction of the 4th angle, and wherein one of this source/drain regions and this second doped regions are contained in the 4th low-doped drain district.
3. liquid crystal indicator as claimed in claim 2, this source/drain regions form with this first doped regions and second doped regions respectively and overlap.
4. liquid crystal indicator as claimed in claim 3, this source/drain regions are by this first alloy is formed injecting in this semiconductor layer perpendicular to the direction of this substrate surface.
5. liquid crystal indicator as claimed in claim 1, this first alloy, this second alloy, and the 3rd alloy be to be selected from by As, P, AsH
x, and PH
xIn the group of being formed one.
6. liquid crystal indicator as claimed in claim 1, the 4th alloy, the 5th alloy are to be selected from by B, BH
x, and BF
xIn the group of being formed one.
7. liquid crystal indicator as claimed in claim 1 more comprises an interlayer dielectric layer, places on the surface of this gate electrode and this substrate; And placing the interior lead of this interlayer dielectric layer, this lead connects this source/drain regions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100064894A CN100368911C (en) | 2005-02-03 | 2005-02-03 | Liquid crystal display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100064894A CN100368911C (en) | 2005-02-03 | 2005-02-03 | Liquid crystal display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1632680A CN1632680A (en) | 2005-06-29 |
| CN100368911C true CN100368911C (en) | 2008-02-13 |
Family
ID=34853066
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100064894A Expired - Fee Related CN100368911C (en) | 2005-02-03 | 2005-02-03 | Liquid crystal display device |
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| Country | Link |
|---|---|
| CN (1) | CN100368911C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107039498A (en) * | 2016-02-04 | 2017-08-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1196832A (en) * | 1996-06-28 | 1998-10-21 | 精工爱普生株式会社 | Thin film transistor, method of its manufacture and circuit and liquid crystal display using thin film transistor |
| CN1335533A (en) * | 2000-07-25 | 2002-02-13 | 达碁科技股份有限公司 | Thin-film transistor LCD and its manufacture |
| CN1336692A (en) * | 2000-08-02 | 2002-02-20 | 松下电器产业株式会社 | Film transistor and its mfg. method, film transistor array substrate, liquid crystal display device and electroluminhescent display |
| US6479867B2 (en) * | 2000-12-19 | 2002-11-12 | Hitachi, Ltd. | Thin film transistor |
| US20030209709A1 (en) * | 2001-02-06 | 2003-11-13 | Hideo Tanabe | Display device with an improved contact hole arrangement for contacting a semiconductor layer through an insulation film |
| JP2004170999A (en) * | 1994-12-27 | 2004-06-17 | Seiko Epson Corp | Thin-film semiconductor unit, liquid crystal display device and method for manufacturing the same, and electronic equipment |
-
2005
- 2005-02-03 CN CNB2005100064894A patent/CN100368911C/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004170999A (en) * | 1994-12-27 | 2004-06-17 | Seiko Epson Corp | Thin-film semiconductor unit, liquid crystal display device and method for manufacturing the same, and electronic equipment |
| CN1196832A (en) * | 1996-06-28 | 1998-10-21 | 精工爱普生株式会社 | Thin film transistor, method of its manufacture and circuit and liquid crystal display using thin film transistor |
| CN1335533A (en) * | 2000-07-25 | 2002-02-13 | 达碁科技股份有限公司 | Thin-film transistor LCD and its manufacture |
| CN1336692A (en) * | 2000-08-02 | 2002-02-20 | 松下电器产业株式会社 | Film transistor and its mfg. method, film transistor array substrate, liquid crystal display device and electroluminhescent display |
| US6479867B2 (en) * | 2000-12-19 | 2002-11-12 | Hitachi, Ltd. | Thin film transistor |
| US20030209709A1 (en) * | 2001-02-06 | 2003-11-13 | Hideo Tanabe | Display device with an improved contact hole arrangement for contacting a semiconductor layer through an insulation film |
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| Publication number | Publication date |
|---|---|
| CN1632680A (en) | 2005-06-29 |
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