CN110838445B - Semiconductor device and method of forming the same - Google Patents
Semiconductor device and method of forming the same Download PDFInfo
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- CN110838445B CN110838445B CN201810929594.2A CN201810929594A CN110838445B CN 110838445 B CN110838445 B CN 110838445B CN 201810929594 A CN201810929594 A CN 201810929594A CN 110838445 B CN110838445 B CN 110838445B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 82
- 238000000034 method Methods 0.000 title claims abstract description 65
- 238000009792 diffusion process Methods 0.000 claims abstract description 139
- 230000004888 barrier function Effects 0.000 claims abstract description 129
- 150000002500 ions Chemical class 0.000 claims abstract description 120
- 239000000758 substrate Substances 0.000 claims abstract description 44
- 238000005530 etching Methods 0.000 claims abstract description 15
- 239000010410 layer Substances 0.000 claims description 42
- 230000008569 process Effects 0.000 claims description 32
- 238000000137 annealing Methods 0.000 claims description 26
- 238000005468 ion implantation Methods 0.000 claims description 23
- 239000000463 material Substances 0.000 claims description 15
- 239000011229 interlayer Substances 0.000 claims description 14
- -1 boron ions Chemical class 0.000 claims description 12
- 229910052698 phosphorus Inorganic materials 0.000 claims description 12
- 239000011574 phosphorus Substances 0.000 claims description 12
- 125000006850 spacer group Chemical group 0.000 claims description 10
- 229910052785 arsenic Inorganic materials 0.000 claims description 8
- 229910052796 boron Inorganic materials 0.000 claims description 8
- 229910052731 fluorine Inorganic materials 0.000 claims description 8
- 239000012535 impurity Substances 0.000 description 13
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- 230000005012 migration Effects 0.000 description 3
- 238000013508 migration Methods 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
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- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 208000032750 Device leakage Diseases 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910001423 beryllium ion Inorganic materials 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
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- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
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Abstract
The invention discloses a method for forming a semiconductor device, which comprises the following steps: providing a semiconductor substrate and a grid structure, wherein the grid structure is formed above the semiconductor substrate; etching the semiconductor substrate positioned at two sides of the grid structure to form a first groove; forming a source/drain in the first groove, wherein a region below the grid structure and between the source/drain is a channel; etching part of the source/drain or part of the semiconductor substrate to form a second groove, wherein the second groove is adjacent to one side of the rest of the source/drain, which is close to the grid structure; forming a diffusion barrier structure at the bottom of the second groove, wherein the type of ions in the diffusion barrier structure is opposite to that of ions in the source/drain, the top of the diffusion barrier structure is higher than the bottom of the source/drain, and the bottom of the diffusion barrier structure is not higher than the bottom of the source/drain; and forming a dielectric layer in the second groove. The diffusion barrier structure can effectively prevent current from leaking at the lower part of the channel and the lower part of the source/drain, avoid electric leakage and improve the performance of the semiconductor device.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor device and a method for forming the same.
Background
As the integration level of semiconductor devices increases, the size of the devices gradually decreases, and the size of the critical structures also decreases. If the width of the channel is narrowed, short Channel Effect (SCE) occurs, and the normal function of the device cannot be satisfied.
At present, ions are doped in the source/drain at two sides of the channel, but due to the technical characteristics of doping, the ion concentration in the source/drain is not uniform, the ion concentration at the lower part of the source/drain is lower than that at the upper part, and the ion concentration is lower at the position, close to the channel, at the lower part of the source/drain. When a voltage is applied, leakage is liable to occur, and the performance of the semiconductor device is degraded.
Therefore, a method for forming a semiconductor device and a semiconductor device capable of solving the device leakage are needed.
Disclosure of Invention
The embodiment of the invention discloses a semiconductor device and a forming method thereof, wherein a diffusion barrier structure is formed between the lower part of a source/drain and the lower part of a channel, so that the semiconductor device is prevented from generating electric leakage.
The invention discloses a method for forming a semiconductor device, which comprises the following steps: providing a semiconductor substrate and a grid structure, wherein the grid structure is formed above the semiconductor substrate; etching the semiconductor substrate positioned at two sides of the grid structure to form a first groove; forming a source/drain in the first groove, wherein a region below the grid structure and between the source/drain is a channel; etching part of the source/drain or part of the semiconductor substrate to form a second groove, wherein the second groove is adjacent to one side of the rest of the source/drain, which is close to the grid structure; forming a diffusion barrier structure at the bottom of the second groove, wherein the ion type in the diffusion barrier structure is opposite to that in the source/drain, the top of the diffusion barrier structure is higher than the lower part of the source/drain, and the bottom of the diffusion barrier structure is not higher than the lower part of the source/drain; and forming a dielectric layer in the second groove.
According to an aspect of the invention, the concentration of ions in the diffusion barrier structure is lower than the concentration of ions in the source/drain adjacent to the diffusion barrier structure, and the concentration of ions in the diffusion barrier structure is higher than the concentration of ions in the channel.
According to one aspect of the invention, the distance between the top of the source/drain and the bottom of the source/drain is/ 1 The distance between the top of the diffusion barrier structure and the bottom of the source/drain is l 2 ，2≤l 1 :l 2 ≤5。
According to one aspect of the invention, the diffusion barrier structure has a width dimension in the range of 15nm to 25nm.
According to one aspect of the invention, the process steps for forming the diffusion barrier structure include: after forming the second groove, carrying out ion implantation on the source/drain or the semiconductor substrate which is positioned at the bottom of the second groove to form a diffusion barrier region; and annealing the diffusion barrier region to form a diffusion barrier structure.
According to one aspect of the present invention, the process of performing ion implantation includes a penetration-resistant ion implantation process.
According to one aspect of the invention, the direction of the ion implantation is perpendicular to the top surface of the gate structure.
According to one aspect of the invention, ions in the diffusion barrier structureThe categories include: boron ions, phosphorus ions or arsenic ions, and the concentration range of the ions in the diffusion barrier structure is as follows: 5X 10 12 /cm 3 ～3×10 13 /cm 3 。
According to an aspect of the invention, the ions in the diffusion barrier structure further comprise: C. one or more combinations of Ge, N and F ions.
According to one aspect of the invention, the annealing treatment process is a laser pulse thermal annealing process, and the conditions of the annealing process comprise: the annealing temperature range is 900-1100 ℃, and the annealing time range is 10-100 s.
According to an aspect of the present invention, after forming the source/drain and before forming the second recess, further comprising: forming an interlayer dielectric layer between the adjacent grid structures; and etching to remove part of the interlayer dielectric layer and expose the source/drain or the semiconductor substrate to form a second groove.
According to one aspect of the invention, after the source/drain is formed and before the interlayer dielectric layer is formed, side walls are formed on two side walls of the gate structure.
According to one aspect of the invention, the process of forming the source/drain includes an epitaxial growth process.
According to one aspect of the invention, the dielectric layer material formed in the second recess comprises Si, siGe, or SiC.
Correspondingly, the invention also provides a semiconductor device, comprising: the semiconductor device comprises a semiconductor substrate, a source/drain, a channel and a grid structure, wherein the grid structure is arranged above the semiconductor substrate, the source/drain is formed in the semiconductor substrate at two sides of the grid structure, and the channel is formed below the grid structure and positioned between the source/drain; the diffusion barrier structure is adjacent to one side, close to the grid structure, of the source/drain, the type of ions in the diffusion barrier structure is opposite to that of the ions in the source/drain, the top of the diffusion barrier structure is higher than the bottom of the source/drain, and the bottom of the diffusion barrier structure is not higher than the bottom of the source/drain; and the dielectric layer is arranged above the diffusion barrier structure.
According to an aspect of the invention, the concentration of ions in the diffusion barrier is lower than the concentration of ions in the source/drain adjacent to the diffusion barrier, the concentration of ions in the diffusion barrier is higher than the concentration of ions in the channel.
According to one aspect of the invention, the distance between the top of the source/drain and the bottom of the source/drain is/ 1 The distance between the top of the diffusion barrier structure and the bottom of the source/drain is l 2 ，2≤l 1 :l 2 ≤5。
According to one aspect of the invention, the width dimension of the diffusion barrier structure is in the range of 15nm to 25nm.
According to one aspect of the invention, the ion species in the diffusion barrier structure comprises: boron ions, phosphorus ions or arsenic ions, and the concentration range of the ions in the diffusion barrier structure is as follows: 5X 10 12 /cm 3 ～3×10 13 /cm 3 。
According to an aspect of the invention, the ions in the diffusion barrier structure further comprise: C. one or more combinations of Ge, N and F ions.
Compared with the prior art, the technical scheme of the invention has the following advantages:
when the semiconductor device is formed, the diffusion barrier structure is formed at the bottom of the second groove, the type of ions in the diffusion barrier structure is opposite to that of ions in the source/drain, and impurity ions positioned at the lower part of the source/drain can be inhibited from diffusing into a channel, so that an ion diffusion region is prevented from being formed between the lower part of the channel and the lower part of the source/drain, and current is prevented from leaking from the lower parts of the source/drain and the channel after voltage is applied. Meanwhile, the top of the diffusion barrier structure is higher than the bottom of the source/drain, the bottom of the diffusion barrier structure is not higher than the bottom of the source/drain, and as leakage current mostly occurs at the lower parts of the source/drain and the channel, the formation of the diffusion barrier structure at the position can not affect the normal migration of electrons and can also ensure the leakage of the blocking current.
Further, the concentration of ions in the diffusion barrier structure is lower than the concentration of ions in the source/drain adjacent to the diffusion barrier structure, and the concentration of ions in the diffusion barrier structure is higher than the concentration of ions in the channel. The ion concentration in the diffusion barrier structure is lower than that in the source/drain adjacent to the diffusion barrier structure, so that the function of the source/drain is not inhibited, and the purpose of blocking current leakage is achieved.
Accordingly, in the semiconductor device manufactured by the embodiment of the present invention, the type of ions in the diffusion barrier structure is opposite to the type of ions in the source/drain, and the diffusion barrier structure is opposite to the type of ions in the source/drain, so that impurity ions located at the lower portion of the source/drain can be suppressed from diffusing into the channel, and current does not leak from the source/drain and the lower portion of the channel after voltage is applied.
Drawings
Fig. 1-7 are schematic cross-sectional structure views of a method of forming a semiconductor device according to an embodiment of the present invention.
Detailed Description
As described above, in the conventional semiconductor device, there is a problem that current easily leaks in the source/drain and the lower portion of the channel.
The research finds that the reasons for the problems are as follows: the ion concentration of the lower part of the source/drain is lower than that of the upper part thereof, and impurity ions at the lower part of the source/drain are easy to diffuse into the channel to form an impurity diffusion region. When a voltage is applied, current flows between the impurity diffusion regions, which causes current leakage and reduces the performance of the semiconductor device.
In order to solve the problem, the invention provides a method for forming a semiconductor device, wherein a diffusion barrier structure is formed between the lower part of a source/drain and the lower part of a channel, so that electric leakage can be effectively avoided, and the performance of the device is improved.
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be understood that the relative arrangement of parts and steps, numerical expressions, and numerical values set forth in these embodiments should not be construed as limiting the scope of the present invention unless it is specifically stated otherwise.
Further, it should be understood that the dimensions of the various elements shown in the figures are not necessarily drawn to scale relative to actual scale, for example, the thickness or width of some layers may be exaggerated relative to other layers for ease of illustration.
The following description of the exemplary embodiment(s) is merely illustrative and is not intended to limit the invention or its application or uses in any way.
Techniques, methods, and apparatus that are known to one of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the present description where applicable.
It should be noted that like reference numerals and letters refer to like items in the following figures, and thus, once an item is defined or illustrated in one figure, further discussion thereof will not be required in the subsequent description of the figures.
Referring to fig. 1, a gate structure 110 is formed on a semiconductor substrate 100.
The semiconductor substrate 100 serves as a process foundation for forming a semiconductor device. The material of the semiconductor substrate 100 is at least one of the following materials: polysilicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and the like. In the embodiment of the present invention, the material of the semiconductor substrate 100 is polysilicon, and the semiconductor substrate 100 further includes other structures, such as: the structures of metal plugs, metal connection layers, dielectric layers, etc., or other semiconductor devices including these structures are not limited in this respect.
It should be noted that, in other embodiments of the present invention, the semiconductor substrate 100 may also be a fin portion formed by a semiconductor substrate, and a dielectric layer or a sacrificial layer may also be formed between the semiconductor substrate 100 and the gate structure 110, which is not limited herein. Specifically, in the embodiment of the present invention, 100 is a fin portion formed of a semiconductor substrate.
The gate structure 110 serves a control function. The gate structure 110 may include a gate, a high-k dielectric layer, and/or a work function layer, etc., and is not particularly limited herein.
Referring to fig. 2, source/drain 120 is formed.
Source/drain 120 completes the circuit conduction after subsequent application of voltage. The process steps for forming the source/drain 120 include: the semiconductor substrate 100 on both sides of the gate structure 110 is etched to form a first recess (not shown), and then a source/drain 120 is formed in the first recess.
The source/drain 120 is formed inside the semiconductor substrate 100 on both sides of the gate structure 110, the cross-sectional shape of the source/drain 120 is related to the type of the finally formed MOS device, and the cross-sectional shape of the source/drain 120 includes a sigma shape or a U shape, which is not particularly limited herein. Likewise, the material of the source/drain 120 is also related to the specific type of MOS device and is not specifically limited herein.
In an embodiment of the present invention, the process of forming the source/drain 120 includes an epitaxial growth process. The source/drain 120 can be made more dense using an epitaxial growth process.
Typically, after forming the source/drain 120, an annealing process is performed on the source/drain 120.
The region under the gate structure 110 and between the source/drain 120 is a channel region (not shown) for electron mobility.
Referring to fig. 3, spacers 130 are formed on two sides of the gate structures 110, and an interlayer dielectric layer 140 is formed between adjacent gate structures 110.
The formation of the sidewall spacers 130 occupies space for the subsequent formation of the second recess. The material of the sidewall spacer 130 includes one or a combination of SiN and SiON, specifically, in the embodiment of the present invention, the material of the sidewall spacer 130 is SiN.
Meanwhile, the lower portion of the sidewall spacer 130 may be in contact with all of the source/drain 120, or may be in contact with part of the source/drain 120 and part of the semiconductor substrate 100 at the same time, which is not limited herein. Specifically, in the embodiment of the present invention, the lower portions of the sidewalls 130 are all in contact with the source/drain 120.
It should be noted that, in other embodiments of the present invention, the sidewall spacers 130 may also be formed before the first recess is formed, and then the first recess and the source/drain 120 are formed.
An interlevel dielectric layer 140 is formed to isolate adjacent gate structures 110. In the embodiment of the present invention, the material of the interlayer dielectric layer 140 is SiO 2 。
It should be noted that, in another embodiment of the present invention, after the source/drain 120 is formed, the interlayer dielectric layer 140 may be directly formed between the adjacent gate structures 110 without forming the sidewall spacers 130.
Referring to fig. 4, the sidewalls are etched away.
The removal of the side walls is prepared for the formation of the second recesses 10. In the embodiment of the present invention, after removing the spacers, a portion of the source/drain 120 or a portion of the semiconductor substrate 100 is exposed. In the embodiment of the present invention, since the lower portion of the sidewall is all in contact with the source/drain 120, the source/drain 120 is all exposed after the sidewall is removed. In another embodiment of the present invention, after removing the spacers, a portion of the source/drain 120 and a portion of the semiconductor substrate 100 are exposed.
The process of etching to remove the side wall is a conventional process in semiconductor production. In the embodiment of the invention, the process for etching the side wall comprises a plasma dry etching process. During etching, the process has good directionality and is easy to control, and the sidewall of the gate structure 110 is not damaged. Obviously, the dry etching process has a certain etching selection ratio for the side wall and the interlayer dielectric layer 140, so that the interlayer dielectric layer 140 is not removed by etching when the side wall is etched.
In another embodiment of the present invention, since no sidewall is formed, after the interlayer dielectric layer 140 is formed, a portion of the interlayer dielectric layer 140 close to two sidewalls of the gate structure 110 is directly etched to form the second recess 10, exposing the source/drain 120 or the semiconductor substrate 100.
Referring to fig. 5, a portion of the source/drain 120 or a portion of the semiconductor substrate 100 is etched to form a second recess 10.
The second recess 10 is formed for the subsequent formation of a diffusion isolation structure. The second recess 10 is formed adjacent to a side of the remaining source/drain 120 adjacent to the gate structure 110.
The process of forming the second groove 10 by etching is the same as the process of etching the side wall.
Referring to fig. 6, a diffusion barrier structure 150 is formed at the bottom of the second groove 10.
The diffusion barrier structure 150 is formed to prevent current leakage from the source/drain lower portion and the channel lower portion after voltage application, preventing leakage.
Generally, after the source/drain 120 is formed, the source/drain 120 needs to be ion implanted. However, the distribution of ions in the source/drain 120 is not uniform, and the upper portion of the source/drain 120 has a higher ion concentration and the lower portion has a lower ion concentration. In a method of forming a semiconductor device, ions in a lower portion of a source/drain 120 are easily diffused toward a channel region, and an impurity diffusion region is formed between the lower portion of the source/drain 120 and a lower portion of the channel. When a voltage is applied, a current flows between the impurity diffusion regions, causing current leakage. Thus, after the diffusion barrier structure 150 is formed, leakage of electrons is blocked, and the performance of the semiconductor device is improved.
Thus, embodiments of the present invention have certain requirements on the location of the diffusion barrier 150. Specifically, in the embodiment of the present invention, the top of the diffusion barrier 150 is higher than the bottom of the source/drain 120, and the bottom of the diffusion barrier 150 is not higher than the bottom of the source/drain 120. If the top of the diffusion barrier 150 is too high, normal circuit conduction is prevented. And in the embodiment of the present invention, the distance between the top of the source/drain 120 and the bottom thereof is l 1 The distance between the top of the diffusion barrier 150 and the bottom of the source/drain 120 is l 2 ，2≤l 1 :l 2 Less than or equal to 5. Specifically, in the present example,/ 1 :l 2 And (5) =2. In another embodiment of the invention,/ 1 :l 2 And (5). The positional relationship between the top and bottom of the diffusion barrier 150 ensures normal migration of electrons in the channel when a voltage is applied, and prevents leakage.
It should be noted that, since the shape of the source/drain 120 is not fixed, the bottom of the source/drain 120 refers to the lowest position of the source/drain 120, as shown in fig. 6.
Meanwhile, the embodiment of the present invention also has certain requirements on the width of the diffusion barrier structure 150. The width dimension of the diffusion barrier structure 150 is w, w is not less than 15nm and not more than 25nm. Specifically, in the present embodiment, w =15nm. In another embodiment of the invention, w =25nm. In yet another embodiment of the present invention, w =20nm.
In embodiments of the present invention, there are a variety of methods of forming the diffusion barrier structure 150. Specifically, in the embodiment of the present invention, after the second groove 10 is formed, ion implantation is performed on the remaining source/drain 120 or the semiconductor substrate 100 located at the bottom of the second groove 10 to form a diffusion barrier region (not shown), and then annealing treatment is performed on the diffusion barrier region to form the diffusion barrier structure 150. In another embodiment of the present invention, after forming the second groove 10, a portion of the material layer (not labeled) is formed at the bottom of the second groove 10, then ion implantation is performed on the material layer to form a diffusion barrier region (not labeled), and then annealing treatment is performed on the diffusion barrier region to form the diffusion barrier structure 150.
Specifically, in the embodiment of the present invention, the process of performing ion Implantation on the remaining source/drain 120 or the semiconductor substrate 100 located at the bottom of the second recess 10 is an Anti-penetration ion Implantation (APT) process, and a vertical Implantation manner is adopted during the ion Implantation, that is, an included angle between the direction of the ion Implantation and the top of the gate structure 110 is 90 °. This vertical implantation avoids internal diffusion of ions into the source/drain 120, channel, or gate structure 110. The direction and location of the ion implantation is shown in fig. 6.
The ion species implanted and the implant power are related to the type of MOS device being formed. In an embodiment of the present invention, the ion type in the source/drain 120 is opposite to the ion type in the diffusion barrier structure 150. The opposite ion type of the source/drain 120 exists in the diffusion barrier structure 150, so that the diffusion barrier structure 150 can inhibit the diffusion of the impurity ions in the source/drain 120 to the channel, and avoid the formation of an impurity ion diffusion region between the lower part of the source/drain 120 and the lower part of the channel, so as to prevent the current from leaking from the lower part of the source/drain 120 after the voltage is applied, and prevent the current leakage.
In the embodiment of the present invention, if the device is an NMOS device or an N-type FinFET structure, the implanted ions are boron (B) ions, and the conditions of the ion implantation include: a power of 12Kv to 20Kv (here, the power is 12Kv or more and 20Kv or less, i.e., the range includes the end points, and the subsequent ranges are as defined herein), and the concentration of the B ion is in the range of 5X 10 12 /cm 3 ～3×10 13 /cm 3 . If it is a PMOS device or P-type FinFET structure, noteThe ions are phosphorus (P) ions or arsenic (As) ions, and the conditions of ion implantation include: the power is 35 Kv-75 Kv, and the concentration range of phosphorus (P) ions or arsenic (As) ions is 5 multiplied by 10 12 /cm 3 ～3×10 13 /cm 3 . Specifically, in the embodiment of the present invention, the structure is an N-type FinFET structure, the implanted ions are boron (B) ions, and the ion implantation conditions include: power 12Kv, concentration of B ion 5X 10 12 /cm 3 . In another embodiment of the present invention, the structure is a P-type FinFET structure, the implanted ions are phosphorus (P) ions, and the conditions of the ion implantation include: power 35Kv, concentration of phosphorus (P) ion 3X 10 13 /cm 3 。
In the embodiment of the present invention, the diffusion barrier structure 150 further includes other impurity ions, such as: C. one or more combinations of Ge, N and F ions. These ions can fill in the gaps between the atoms, improve the bonding force between the atoms, increase the strength of the diffusion barrier structure 150, and prevent the chemical bonds from breaking during annealing. Specifically, in the embodiment of the present invention, C and F are further included in the diffusion barrier structure 150. In another embodiment of the present invention, N and Ge are also included in the diffusion barrier structure 150. In yet another embodiment of the present invention, the diffusion barrier structure 150 contains F.
In an embodiment of the present invention, the ion concentration of the diffusion barrier structure 150 is lower than the ion concentration in the source/drain 120 adjacent to the diffusion barrier structure 150. This does not inhibit the implementation of the source/drain 120 function. Meanwhile, the ion concentration of the diffusion barrier structure 150 is higher than that in the channel.
The process of annealing the diffusion barrier region is a laser pulse thermal annealing process. The laser pulse thermal annealing process can achieve the goals of rapid temperature rise and ion activation in a short time, and can reduce the extent of diffusion of other impurities. In the embodiment of the invention, the annealing temperature ranges from 900 ℃ to 1100 ℃, and the annealing time ranges from 10s to 100s. Specifically, in the embodiment of the present invention, the annealing temperature is 900 ℃, and the annealing time is 10s. In another embodiment of the present invention, the annealing temperature is 1100 ℃ and the annealing time is 100s.
Referring to fig. 7, a dielectric layer 160 is formed in the second recess 10.
The dielectric layer 160 is formed to fill the second recess 10, so that the structure of the device is complete. Since the formation of the second recess 10 requires the removal of a portion of the source/drain 120, in embodiments of the present invention, the dielectric layer 160 needs to be formed in relation to the type of device or structure and matched to the type of source/drain 120. If the device is an NMOS device or an N-type FinFET structure, the dielectric layer 160 is made of SiC containing P ions with a concentration range of 5 × 10 18 /cm 3 ～6×10 19 /cm 3 . If the device is a PMOS device or a P-type FinFET structure, the dielectric layer 160 is made of Si and/or SiGe and contains B ions in a concentration range of 2 × 10 18 /cm 3 ～3×10 19 /cm 3 . Specifically, in the embodiment of the invention, in the N-type FinFET structure of the device, the material of the dielectric layer 160 is SiC, and the concentration of P ions contained in the SiC is 5 × 10 18 /cm 3 . In another embodiment of the present invention, in a P-type FinFET structure of a device, the dielectric layer 160 is Si and/or SiGe containing B ions at a concentration of 2X 10 18 /cm 3 。
It should be noted that, in the embodiment of the present invention, after the dielectric layer 160 is formed, an interlayer dielectric layer is further formed to fill the second groove 10.
In summary, embodiments of the present invention disclose a method for forming a semiconductor device, in which a diffusion barrier structure is formed between the lower portion of a source/drain and a channel, so as to prevent current leakage after voltage is applied, avoid current leakage, and improve the performance of the semiconductor device.
Accordingly, with continued reference to fig. 7, the present invention further provides a semiconductor device, comprising: semiconductor substrate 100, source/drain 120, channel (not labeled), and gate structure 110.
The gate structure 110 is disposed over the semiconductor substrate 100, and the source/drain 120 is formed in the semiconductor substrate 100 at both sides of the gate structure 110.
The function and material of the semiconductor substrate 100, the function and material of the source/drain 120, the position of the channel and the function of the gate structure 110 are as described above.
In an embodiment of the present invention, a diffusion barrier structure 150 is further included. The diffusion barrier structure 150 can prevent impurity ions in the source/drain 120 from diffusing into the channel, prevent current leakage from the channel and the lower portion of the source/drain after voltage is applied, and prevent leakage.
Embodiments of the present invention have certain requirements on the location of the diffusion barrier structure 150. The diffusion barrier structure 150 is adjacent to a side of the source/drain 120 that is adjacent to the gate structure 110. And particularly, in the embodiment of the present invention, the top of the diffusion barrier structure 150 is higher than the bottom of the source/drain 120, and the bottom of the diffusion barrier structure 150 is not higher than the bottom of the source/drain 120.
And in the embodiment of the present invention, the distance between the top of the source/drain 120 and the bottom thereof is l 1 The distance between the top of the diffusion barrier structure 150 and the bottom of the source/drain 120 is l 2 ，2≤l 1 :l 2 Less than or equal to 5. Specifically, in the present example,/ 1 :l 2 And (5) =2. In another embodiment of the invention,/ 1 :l 2 And (5). The positional relationship between the top and bottom of the diffusion barrier 150 not only ensures the normal migration of electrons in the channel when a voltage is applied, but also prevents electrical leakage.
Embodiments of the present invention also have certain requirements on the width of the diffusion barrier structure 150. The width dimension of the diffusion barrier structure 150 is w, w is not less than 15nm and not more than 25nm. Specifically, in the present embodiment, w =15nm. In another embodiment of the invention, w =25nm. In yet another embodiment of the present invention, w =20nm.
In an embodiment of the present invention, the ion concentration of the diffusion barrier structure 150 is lower than the ion concentration in the source/drain 120 adjacent to the diffusion barrier structure 150 and higher than the ion concentration in the channel.
In the embodiment of the present invention, if the device is an NMOS device or an N-type FinFET structure, the implanted ions are boron (B) ions, and the conditions of the ion implantation include: the power is 12 Kv-20Kv, the concentration range of B ions is 5 x 10 12 /cm 3 ～3×10 13 /cm 3 . If it is a PMOS device or P-type FinFET structure, the implanted ions are phosphorus (P:p) ions or arsenic (As) ions, the conditions of the ion implantation including: the power is 35 Kv-75 Kv, and the concentration range of phosphorus (P) ions or arsenic (As) ions is 5 multiplied by 10 12 /cm 3 ～3×10 13 /cm 3 . Specifically, in the embodiment of the present invention, the structure is an N-type FinFET structure, the implanted ions are boron (B) ions, and the ion implantation conditions include: power 12Kv, concentration of B ion 5X 10 12 /cm 3 . In another embodiment of the present invention, the structure is a P-type FinFET structure, the implanted ions are phosphorus (P) ions, and the conditions of the ion implantation include: power 35Kv, concentration of phosphorus (P) ion 3X 10 13 /cm 3 。
In an embodiment of the present invention, the diffusion barrier structure 150 further includes other impurity ions, such as: C. one or more combinations of Ge, N and F ions. These ions can fill in the gaps between atoms, improve the bonding force between atoms, increase the strength of the diffusion barrier structure 150, and avoid the breakage of chemical bonds during annealing. Specifically, in the embodiment of the present invention, C and F are further included in the diffusion barrier structure 150. In another embodiment of the present invention, the diffusion barrier structure 150 further includes N and Ge therein. In yet another embodiment of the present invention, the diffusion barrier structure 150 contains F.
Likewise, the ion type in the diffusion barrier 150 is opposite to the ion type in the source/drain 120. The diffusion barrier structure 150 has an opposite ion type to that of the source/drain 120, so that the diffusion barrier structure 150 can inhibit the ions in the source/drain 120 from diffusing to the channel, and current does not leak from the lower part of the source/drain 120 after voltage is applied, thereby avoiding leakage.
The embodiment of the present invention further includes a dielectric layer 160. The dielectric layer 160 completes the structure of the device in order to fill the second groove 10. The material of the dielectric layer 160 and the type of ions contained therein are as described above.
In summary, embodiments of the present invention disclose a semiconductor device, in which a diffusion barrier structure is formed between the lower portion of the source/drain and the channel, so as to prevent current leakage after voltage is applied, avoid current leakage, and improve the performance of the semiconductor device.
Thus far, the present invention has been described in detail. Some details well known in the art have not been described in order to avoid obscuring the concepts of the present invention. Those skilled in the art can now fully appreciate how to implement the teachings disclosed herein, in view of the foregoing description.
Although some specific embodiments of the present invention have been described in detail by way of illustration, it should be understood by those skilled in the art that the above illustration is only for the purpose of illustration and is not intended to limit the scope of the invention. It will be appreciated by those skilled in the art that modifications can be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (20)
1. A method of forming a semiconductor device, comprising:
providing a semiconductor substrate and a gate structure, wherein the gate structure is formed above the semiconductor substrate;
etching the semiconductor substrate positioned at two sides of the grid structure to form a first groove;
forming a source/drain in the first groove, wherein a region below the grid structure and between the source/drain is a channel;
etching part of the source/drain or part of the semiconductor substrate to form a second groove, wherein the second groove is adjacent to one side, close to the grid structure, of the rest of the source/drain;
forming a diffusion barrier structure at the bottom of the second groove, wherein the ion type in the diffusion barrier structure is opposite to that in the source/drain, the top of the diffusion barrier structure is higher than the bottom of the source/drain, and the bottom of the diffusion barrier structure is not higher than the bottom of the source/drain; and
and forming a dielectric layer in the second groove.
2. The method according to claim 1, wherein a concentration of ions in the diffusion barrier structure is lower than a concentration of ions in the source/drain adjacent to the diffusion barrier structure, and wherein a concentration of ions in the diffusion barrier structure is higher than a concentration of ions in the channel.
3. The method of claim 1, wherein a distance between the top of the source/drain and the bottom of the source/drain is/ 1 The distance between the top of the diffusion barrier structure and the bottom of the source/drain is l 2 ，2≤l 1 :l 2 ≤5。
4. The method of claim 3, wherein a width dimension of the diffusion barrier structure is in a range of 15nm to 25nm.
5. The method of claim 1, wherein the process step of forming the diffusion barrier structure comprises:
after the second groove is formed, carrying out ion implantation on the source/drain or the semiconductor substrate which is positioned at the bottom of the second groove and is remained so as to form a diffusion barrier region; and
and carrying out annealing treatment on the diffusion barrier region to form the diffusion barrier structure.
6. The method according to claim 5, wherein the ion implantation process comprises a penetration-preventing ion implantation process.
7. The method of claim 6, wherein the direction of the ion implantation is perpendicular to the top surface of the gate structure.
8. The method of claim 5, wherein the ion species in the diffusion barrier structure comprises: boron ions, phosphorus ions or arsenic ions, the concentration range of the ions in the diffusion barrier structure is 5 x 10 12 /cm 3 ～3×10 13 /cm 3 。
9. The method of claim 8, wherein the ions in the diffusion barrier structure further comprise: C. one or more combinations of Ge, N and F ions.
10. The method as claimed in claim 5, wherein the annealing process is a laser pulse thermal annealing process, and conditions of the annealing process include: the annealing temperature range is 900-1100 ℃, and the annealing time range is 10-100 s.
11. The method of claim 1, wherein after forming the source/drain and before forming the second recess, further comprising:
forming an interlayer dielectric layer between the adjacent grid structures; and
and etching to remove part of the interlayer dielectric layer, and exposing the source/drain or the semiconductor substrate to form the second groove.
12. The method of claim 11, further comprising forming spacers on two sidewalls of the gate structure after forming the source/drain and before forming the interlayer dielectric layer.
13. The method of claim 1, wherein the process of forming the source/drain comprises an epitaxial growth process.
14. The method of claim 1, wherein a material forming the dielectric layer in the second recess comprises Si, siGe, or SiC.
15. A semiconductor device, comprising:
the semiconductor device comprises a semiconductor substrate, a source/drain, a channel and a grid structure, wherein the grid structure is arranged above the semiconductor substrate, the source/drain is formed in the semiconductor substrate at two sides of the grid structure, and the channel is formed below the grid structure and positioned between the source/drain;
the diffusion barrier structure is adjacent to one side, close to the grid structure, of the source/drain, the ion type in the diffusion barrier structure is opposite to that in the source/drain, the top of the diffusion barrier structure is higher than the bottom of the source/drain, and the bottom of the diffusion barrier structure is not higher than the bottom of the source/drain; and
and the dielectric layer is arranged above the diffusion barrier structure.
16. The semiconductor device according to claim 15, wherein a concentration of ions in the diffusion barrier structure is lower than a concentration of ions in the source/drain adjacent to the diffusion barrier structure, and wherein a concentration of ions in the diffusion barrier structure is higher than a concentration of ions in the channel.
17. The semiconductor device of claim 15, wherein a distance between the top of the source/drain and the bottom of the source/drain is/ 1 The distance between the top of the diffusion barrier structure and the bottom of the source/drain is l 2 ，2≤l 1 :l 2 ≤5。
18. The semiconductor device of claim 17, wherein the diffusion barrier structure has a width dimension in a range of 15nm to 25nm.
19. The method of claim 15, wherein the ion species in the diffusion barrier structure comprises: boron ions, phosphorus ions or arsenic ions, wherein the concentration range of the ions in the diffusion barrier structure is as follows: 5X 10 12 /cm 3 ～3×10 13 /cm 3 。
20. The method of forming a semiconductor device according to claim 19, wherein the ions in the diffusion barrier structure further comprise: C. one or more combinations of Ge, N and F ions.
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