CN107039498A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN107039498A CN107039498A CN201610081030.9A CN201610081030A CN107039498A CN 107039498 A CN107039498 A CN 107039498A CN 201610081030 A CN201610081030 A CN 201610081030A CN 107039498 A CN107039498 A CN 107039498A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 65
- 238000000034 method Methods 0.000 title claims abstract description 57
- 150000002500 ions Chemical class 0.000 claims abstract description 161
- 239000000758 substrate Substances 0.000 claims abstract description 137
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 11
- 239000000463 material Substances 0.000 claims description 39
- -1 boron ion Chemical class 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 18
- 239000010703 silicon Substances 0.000 claims description 18
- 229910052796 boron Inorganic materials 0.000 claims description 16
- 238000002347 injection Methods 0.000 claims description 15
- 239000007924 injection Substances 0.000 claims description 15
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 8
- 229910052732 germanium Inorganic materials 0.000 claims description 8
- 238000002513 implantation Methods 0.000 claims description 8
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 7
- 229910000681 Silicon-tin Inorganic materials 0.000 claims description 6
- LQJIDIOGYJAQMF-UHFFFAOYSA-N lambda2-silanylidenetin Chemical compound [Si].[Sn] LQJIDIOGYJAQMF-UHFFFAOYSA-N 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 238000011065 in-situ storage Methods 0.000 claims description 4
- 229910001449 indium ion Inorganic materials 0.000 claims description 4
- 230000008569 process Effects 0.000 claims description 3
- 229910001432 tin ion Inorganic materials 0.000 claims description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 36
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 16
- 125000006850 spacer group Chemical group 0.000 description 14
- 230000005012 migration Effects 0.000 description 9
- 238000013508 migration Methods 0.000 description 9
- 230000009467 reduction Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 3
- 230000006835 compression Effects 0.000 description 3
- 238000007906 compression Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 229910007245 Si2Cl6 Inorganic materials 0.000 description 1
- 229910003818 SiH2Cl2 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- ZOCHARZZJNPSEU-UHFFFAOYSA-N diboron Chemical compound B#B ZOCHARZZJNPSEU-UHFFFAOYSA-N 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- QUZPNFFHZPRKJD-UHFFFAOYSA-N germane Chemical compound [GeH4] QUZPNFFHZPRKJD-UHFFFAOYSA-N 0.000 description 1
- 229910052986 germanium hydride Inorganic materials 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 241000894007 species Species 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- LXEXBJXDGVGRAR-UHFFFAOYSA-N trichloro(trichlorosilyl)silane Chemical compound Cl[Si](Cl)(Cl)[Si](Cl)(Cl)Cl LXEXBJXDGVGRAR-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
Abstract
The present invention provides a kind of semiconductor structure and forming method thereof, wherein, the forming method includes：Substrate is provided；Grid structure is formed over the substrate, and the grid structure both sides include the first side and second side relative with the first side；The substrate of the side of grid structure first is performed etching, groove is formed；There are the first Doped ions in bottom portion of groove formation high-doped zone, the high-doped zone in the first side of grid structure；The epitaxial layer of the filling groove is formed on the high-doped zone of the first side；The epitaxial layer of first side is doped to form drain region, there are the second Doped ions in the drain region, second Doped ions are different from the ionic type of first Doped ions.Wherein, the high-doped zone forms PN junction with drain region, and the PN junction has stronger built in field, the breakdown voltage of the PN junction can be reduced, so as to reduce the junction breakdown voltage of semiconductor structure.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of semiconductor structure and its formation side
Method.
Background technology
Electrostatic is a kind of natural phenomena of objective reality, and the mode of generation has a variety of, such as contact, rub,
Appliance chamber sensing etc..Electrostatic has accumulation for a long time, high voltage, low battery, low current and action time
Short the characteristics of.
For electronic product, static discharge (Electrostatic discharge, ESD) is that influence is integrated
One principal element of circuit reliability.ESD is a kind of quick N-process of electric charge.Due to electrostatic electricity
Pressure is very high, and destructive consequence can be brought to integrated circuit, the failure of integrated circuit is caused.Therefore, it is
Protection integrated circuit exempts from ESD infringement, and esd protection circuit is also designed in integrated circuit, to prevent
Only integrated circuit is damaged by ESD.
Fig. 1 is a kind of structural representation of esd protection circuit of prior art.
Fig. 1 is refer to, the structural representation of esd protection circuit is shown, the esd protection circuit is grid
The transistor that pole 1 and source electrode 2 are grounded；The drain electrode 3 of the transistor and the electrostatic end 4 by protection circuit
It is connected.
When by protection circuit 4 build up of electrostatic charge of electrostatic end when, the drain electrode 3 of the esd protection circuit with
Source electrode 2 forms certain electrical potential difference, makes transistor reverse breakdown, makes circuit turn-on, by electrostatic end 4
Electrostatic charge is exported, so as to reduce the electrostatic charge at the electrostatic end 4, and then is prevented by protection circuit by ESD
Infringement.
However, the esd protection circuit of prior art formation has higher breakdown voltage.
The content of the invention
The problem of present invention is solved is to provide a kind of semiconductor structure and forming method thereof, can reduce ESD
The breakdown voltage of protection circuit.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, including：There is provided
Substrate；Grid structure is formed over the substrate, and the grid structure both sides include the first side, Yi Jiyu
The second relative side of first side；The substrate of the side of grid structure first is performed etching, groove is formed；
The bottom portion of groove formation high-doped zone in the first side of grid structure, in the high-doped zone with first adulterate from
Son；The epitaxial layer of the filling groove is formed on the high-doped zone of the first side；To the institute of the first side
State epitaxial layer to be doped to form drain region, there are the second Doped ions, second doping in the drain region
Ion is different from the ionic type of first Doped ions.
Optionally, in addition to：The substrate of the side of grid structure second is performed etching, groove is formed；
The bottom portion of groove formation high-doped zone in the second side of grid structure；Formed on the high-doped zone of the second side
Fill the epitaxial layer of the groove；The epitaxial layer of second side is doped to form source region, in the source region
With second Doped ions.
Optionally, the step of forming high-doped zone includes：First side of grid structure bottom portion of groove is served as a contrast
Bottom carries out ion implanting, forms the high-doped zone in the substrate of bottom portion of groove, and injection ion includes the
One Doped ions.
Optionally, the material of the substrate is silicon；Ion is carried out to the substrate of the side of grid structure first
In the step of injection, injection ion also includes the second ion, and second ion is germanium or tin.
Optionally, the technique ginseng of ion implanting is carried out to the substrate of first side of grid structure bottom portion of groove
Number includes：First Doped ions are boron ion；The Implantation Energy of boron ion is 2KeV~10KeV,
Implantation dosage is 1E14atoms/cm2~1E15atoms/cm2。
Optionally, in addition to：Stressor layers, the surface of the stressor layers are formed on the high-doped zone surface
Less than substrate surface；The stressor layers are doped, Doped ions are the first Doped ions；Described
The epitaxial layer of stress layer surface formation filling groove.
Optionally, the step of forming high-doped zone includes：In the lower surface formation stressor layers of the groove,
The surface of the stressor layers is less than substrate surface；The stressor layers are doped, formed described highly doped
Area, Doped ions are the first Doped ions.
Optionally, the method for forming the stressor layers is epitaxial growth technology；The epitaxial layer is mixed
Miscellaneous step includes：Answered during stressor layers described in epitaxial growth using doping process in situ described
The first Doped ions of doping in power layer.
Optionally, the material of the substrate is silicon；The material of the stressor layers is SiGe or silicon tin.
Optionally, first Doped ions are boron ion or indium ion.
Optionally, the doping concentration of the first Doped ions is 1E20atoms in the high-doped zone
/cm3~1E21atoms/cm3。
Optionally, the thickness of the high-doped zone is 10nm~40nm.
Optionally, the thickness of the epitaxial layer is 40nm~80nm.
Optionally, formed before the high-doped zone, in addition to：Form the covering gate structure sidewall
The first side wall；Formed before the epitaxial layer, in addition to：Remove first side wall.
Accordingly, the present invention also provides a kind of semiconductor structure, including：Substrate；Positioned at the substrate table
The grid structure in face, the grid structure both sides include the first side and second side relative with the first side,
There is groove in the substrate of first side of grid structure；Bottom portion of groove positioned at the side of grid structure first
The high-doped zone of substrate surface, the high-doped zone has the first Doped ions, first high-doped zone
Surface is less than the substrate surface；Drain region on the high-doped zone of first side of grid structure, it is described
Drain region has the second Doped ions, the ionic type of second Doped ions and first Doped ions
It is different.
Optionally, in addition to：Groove in the substrate of second side of grid structure；Positioned at the grid
The high-doped zone of the second side of pole structure bottom portion of groove substrate surface；It is highly doped positioned at the side of grid structure second
Source region in miscellaneous area.
Optionally, the thickness of the high-doped zone is 10nm~40nm.
Optionally, the material of the high-doped zone is the SiGe containing the first Doped ions or silicon tin.
Optionally, first Doped ions are boron ion or tin ion.
Optionally, the concentration of first Doped ions is 1E20atoms/cm3~1E21atoms/cm3。
Compared with prior art, technical scheme has advantages below：
The forming method of the semiconductor structure of the present invention in the first side of grid structure bottom portion of groove by forming height
Doped region, and the first Doped ions of high-doped zone are different from the ionic type of second Doped ions in drain region,
Then the high-doped zone forms PN junction with drain region, and the PN junction has stronger built in field, can dropped
The breakdown voltage of the low PN junction, so as to reduce the junction breakdown voltage of transistor.The knot of reduction transistor is hit
The cut-in voltage of esd protection circuit can be reduced by wearing voltage, be enable by the electrostatic in protection circuit fully
Release, so as to improve the protective value of ESD circuit.
Further, the material of the substrate is silicon, and injection ion includes the second ion, second ion
For germanium or tin, the lattice constant of second ion is more than the lattice constant of substrate, therefore second note
The migration rate of carrier in longitudinal tension stress, increase substrate can be provided for substrate by entering ion.
Further, stressor layers can also be formed in the groove, the stressor layers can increase in substrate
The migration rate of carrier.
Further, the first side wall is formed on the gate structure sidewall before the high-doped zone is formed,
First side wall can prevent high-doped zone too close to grid structure lower substrate, so as to avoid
The side of grid structure first and the second side high-doped zone break-through.
In the semiconductor structure of the present invention, the drain region bottom is in contact with high-doped zone, described highly doped
The first Doped ions in area are different from the ionic type of the Doped ions of drain region second.The drain region and second
Side high-doped zone forms PN junction, and the PN junction has stronger built in field, can reduce the PN
The breakdown voltage of knot, so as to reduce the junction breakdown voltage of semiconductor structure.The junction breakdown electricity of semiconductor structure
The reduction of pressure can reduce the cut-in voltage of esd protection circuit, enable to be filled by the electrostatic in protection circuit
Divide release, so as to improve the protective value of ESD circuit.
Brief description of the drawings
Fig. 1 is a kind of structural representation of esd protection circuit；
Fig. 2 to Fig. 8 is the structural representation of each step of the embodiment of forming method one of semiconductor structure of the present invention
Figure；
Fig. 9 is the structural representation of another embodiment of forming method of semiconductor structure of the present invention.
Embodiment
There are problems in semiconductor structure, for example：The breakdown voltage of esd protection circuit is higher.
With reference to a kind of forming method of semiconductor structure, the breakdown voltage for analyzing esd protection circuit is relatively low
Reason：
In the forming method of esd protection circuit, before drain region is formed, substrate is doped, shape
Into well region, the well region forms PN junction with drain region.The breakdown voltage of the PN junction determines that ESD is protected
The cut-in voltage of protection circuit.Doping concentration yet with well region is relatively low, causes what well region was formed with drain region
PN junction built in field intensity is small, and the breakdown voltage of PN junction is higher, so that the knot of esd protection circuit is hit
Wear voltage higher.The cut-in voltage that higher junction breakdown voltage is easily caused esd protection circuit is higher, from
And be difficult enable fully to be discharged by the electrostatic in protection circuit, and then make esd protection circuit be difficult to by
Protection circuit provides effective protection.
To solve the technical problem, the invention provides a kind of forming method of semiconductor structure, including：
Substrate is provided；Form grid structure over the substrate, the grid structure both sides include the first side, with
And second side relative with the first side；The substrate of the side of grid structure first is performed etching, formed recessed
Groove；Have first to mix in bottom portion of groove formation high-doped zone, the high-doped zone in the first side of grid structure
Heteroion；The epitaxial layer of the filling groove is formed on the high-doped zone of the first side；To the first side
The epitaxial layer be doped to form drain region, in the drain region have the second Doped ions, described second
Doped ions are different from the ionic type of first Doped ions.
Wherein, forming method of the invention in the side of grid structure first by forming high-doped zone, and makes height
First Doped ions of doped region are different from the ionic type of second Doped ions in drain region, then described highly doped
Miscellaneous area forms PN junction with drain region, and the PN junction has stronger built in field, can reduce the PN
The breakdown voltage of knot, so as to reduce the junction breakdown voltage of semiconductor structure.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings
The specific embodiment of the present invention is described in detail.
Fig. 2 to Fig. 8 is the structural representation of each step of the embodiment of forming method one of semiconductor structure of the present invention
Figure.
Refer to Fig. 2, there is provided substrate 100.
In the present embodiment, the substrate 100 provides technique platform to form semiconductor structure.Specifically,
The semiconductor structure is the n-type transistor of grid and source ground.
In the present embodiment, the substrate 100 is silicon substrate, in other embodiments, the substrate 100
Can also be the Semiconductor substrates such as germanium substrate, silicon-Germanium substrate or silicon-on-insulator substrate.
With continued reference to Fig. 2, grid structure 110, the grid structure 110 are formed on the substrate 100
Both sides include the first side I and second side II relative with the first side I.The lower section of grid structure 110
Substrate 100 constitutes transistor channel.
In the present embodiment, the gate dielectric layer that the grid structure 110 includes being located on substrate 100 (is not marked
Show), the gate dielectric layer is used to realize the electric insulation between grid and substrate 100；Positioned at the gate medium
Grid (not indicating) on layer；Mask layer (not indicating) on grid；Cover grid structure 110
The side wall (not indicating) of side wall.For the composition and forming method of the grid structure 110, herein seldom
Repeat.
It should be noted that in the present embodiment, it is described before the step of forming grid structure 110
The forming method of semiconductor structure also includes carrying out the substrate 100 ion implanting formation well region.
In the present embodiment, the transistor is n-type transistor, in the step of forming the well region, note
Enter ion for p-type ion, specifically, the injection ion is boron ion.
In addition, after the step of forming grid structure 110, the forming method also includes to the grid
The substrate 100 of the both sides of structure 110 carries out being lightly doped to form lightly doped district 111.
Described be lightly doped can form shallow-layer amorphous area, so as to reduce the drain source area Doped ions being subsequently formed
Spread to the lower channels of grid structure 110, reduce the possibility of drain source area break-through.
In the present embodiment, the semiconductor structure is n-type transistor, then the injection ion being lightly doped
For arsenic ion.
Fig. 3 is refer to, the side I substrates 100 of grid structure 110 first are performed etching, groove is formed
120, the groove 120 is used to make the surface of the first side I substrates 100 be less than the lower channels of grid structure 110
Surface, so that the high-doped zone surface being subsequently formed is less than the channel surface.
It should be noted that for simplification of flowsheet, in the present embodiment, to the first side I substrates 100
While performing etching, the forming method also includes：Second side II substrates 100 are performed etching, shape
Into groove 120.
Specifically, in the present embodiment, being entered by dry etching to the substrate 100 of the both sides of grid structure 110
Row etching, forms groove 120.Dry etching is anisotropy, with good profile control, so as to
Enough reduce the infringement to the lower channels of grid structure 110.In other embodiments, wet method can also be passed through
Etching or the coefficient lithographic method of dry method, wet method.
If it should be noted that the depth of the groove 120 is too small, easily make to be subsequently formed is highly doped
The depth in miscellaneous area is too small, it is difficult to reduce the junction breakdown voltage of transistor；If the depth of the groove 120
Excessive, the depth of the high-doped zone of formation is excessive, easily increases technology difficulty.Therefore, in the present embodiment,
The depth of the groove 120 is 20nm~40nm.
It is follow-up to need to form high-doped zone, the height in the side I of grid structure 110 first bottom of groove 120
There are the first Doped ions in doped region.It is described to be formed before high-doped zone is formed in the present embodiment
Method also includes：Form the first side wall of the covering side wall of grid structure 110.Below with reference to Fig. 4
Illustrated with Fig. 5.
Fig. 4 is refer to, the first side wall 130 of the covering side wall of grid structure 110 is formed.
First side wall 130 be used to increase between the first side I and the second side II high-doped zones 140 away from
From preventing the first side I and the break-through of the second side II high-doped zones 140.
In the present embodiment, the material of first side wall 130 is silicon nitride, in other embodiments, institute
The material for stating the first side wall 130 can also be silicon oxynitride.
Specifically, the step of forming the first side wall 130 includes：Form the covering grid structure 110
And the spacer material layer of substrate 100；Remove the first spacer material on grid structure 110 and substrate 100
Layer, retains the first spacer material layer being formed on the side wall of grid structure 110 and forms the first side wall 130.
In this implementation, the grid structure 110 and substrate 100 are covered by chemical vapor deposition method formation
The first spacer material layer.In other embodiments, it can also be covered by atom layer deposition process formation
The first spacer material layer of the grid structure 110 and substrate 100.
In this implementation, the on grid structure 110 and substrate 100 is removed by anisotropic dry etch
The side walling bed of material.Anisotropic dry etch is different in the etch rate of different directions, can remove grid
The first spacer material layer in pole structure 110 and substrate 100, and retain and be formed at the side of grid structure 110
The first spacer material layer on wall forms the first side wall 130.
Fig. 5 is refer to, in the side I of grid structure 110 first groove 120 (as shown in Figure 4) bottom shape
Into high-doped zone 140, there are the first Doped ions in the high-doped zone 140.
The concentration of first Doped ions is larger in the high-doped zone 140, and first Doped ions with
The ionic types of the Doped ions of drain region second being subsequently formed is different, therefore, the high-doped zone 140 with
The drain region forms PN junction.The high-doped zone 140 of highly doped ion concentration can be formed compared with intensity with drain region
Built in field, so as to reduce the breakdown voltage of formed PN junction, and then reduce the knot for forming transistor
Breakdown voltage.
It should be noted that in the present embodiment, there is groove 120 in the second side II substrates 100,
While forming high-doped zone 140, the forming method also includes：At the second side II bottom of groove 120
Portion forms high-doped zone 140.
In the present embodiment, the step of forming high-doped zone 140 includes：In the both sides of grid structure 110
The surface of substrate 100 of the bottom of groove 120 forms stressor layers；The stressor layers are doped to form described
High-doped zone 140, Doped ions are the first Doped ions.
In the present embodiment, first Doped ions be p-type ion, specifically, described first adulterate from
Son is boron ion or indium ion.
In the present embodiment, the stressor layers are formed by epitaxial growth technology, and pass through doping process in situ
The stressor layers are doped.During doping in situ is carried out to the stressor layers, using containing
The reacting gas of first Doped ions is doped to the stressor layers, forms high-doped zone 140.
In the present embodiment, the lattice constant of the stressor layers is more than the lattice constant of substrate 100, Neng Gou
Compression is provided for substrate 100 on longitudinal direction, so that tension is provided for substrate 100 in the horizontal, and then
Increase the migration rate of channel carrier.
Specifically, the substrate 100 is silicon substrate, and first Doped ions are p-type ion, then
The material of the stressor layers is SiGe.Therefore the material of the high-doped zone 140 is the silicon containing boron ion
Germanium.In other embodiments, the material of the high-doped zone can also be the silicon tin containing boron ion.
In the present embodiment, if the thickness of the high-doped zone 140 is too small, it is difficult to the leakage that is subsequently formed
Area forms PN junction, so as to it is difficult to reduce the junction breakdown voltage of transistor；If the high-doped zone 140
Thickness is excessive, easily increases technology difficulty.Therefore, in the present embodiment, the thickness of the high-doped zone 140
Spend for 10nm~40nm；
In the present embodiment, the technological parameter of the epitaxial growth includes：Reaction temperature is 700 DEG C~850 DEG C；
Gas pressure intensity is 5mTorr~50mTorr；Reacting gas includes silicon source gas, ge source gas and impurity gas.
The silicon source gas is SiH4、SiH2Cl2Or Si2Cl6, the flow of the silicon source gas is
1sccm~1000sccm；The ge source gas is GeH4, the flow of the ge source gas is
1sccm~1000sccm, the impurity gas is diborane (B2H6), the flow of the impurity gas is
0.1slm~50slm.
If it should be noted that the concentration of first Doped ions is too small, it is difficult to play reduction crystal
The effect of pipe junction breakdown voltage；If the concentration of first Doped ions is excessive, the scattering to carrier
Effect is larger, is easily reduced the migration rate of carrier.Specifically, the concentration of first Doped ions
For 1E20atoms/cm3~1E21atoms/cm3, in the present embodiment, the concentration of first Doped ions is
1E20atoms/cm3~4E20atoms/cm3。
It should be noted that as shown in fig. 6, being formed after the high-doped zone 140, the formation side
Method also includes removing first side wall 130.
In the present embodiment, first side wall 130 is removed by dry etching.In other embodiments, also
First side wall can be removed by wet etching.
Fig. 7 is refer to, the filling groove 120 is formed on the first side I high-doped zone 140 (such as
Shown in Fig. 4) epitaxial layer 150, the epitaxial layer 150 be used for form transistor drain.
It should be noted that in the present embodiment, the second side II has groove 120, filling institute is formed
While stating epitaxial layer 150 of groove 120, the forming method also includes：Described in the second side II
The epitaxial layer 150 of the filling groove 120 is formed on high-doped zone 140.
In the present embodiment, the material of the epitaxial layer 150 is monocrystalline silicon.
If it should be noted that the thickness of the epitaxial layer 150 were too small, the drain region and source being subsequently formed
The thickness in area is small, it is difficult to form PN junction with high-doped zone 140；If the thickness mistake of the epitaxial layer 150
Greatly, it is difficult to make the drain region that is subsequently formed and source region be contacted with the high-doped zone 140, so as to be hardly formed
PN junction.Therefore, the thickness of the epitaxial layer is in the range of 40nm~80nm.It is described in the present embodiment
The thickness of epitaxial layer 150 is 50nm~60nm.
In the present embodiment, by epitaxial growth technology on the high-doped zone 140 of the both sides of grid structure 110
Form the epitaxial layer 150.
Fig. 8 is refer to, the first side I epitaxial layer 150 (as shown in Figure 7) is doped to be formed
There are the second Doped ions in drain region 160, the drain region 160.Second Doped ions with it is described highly doped
The ionic type of first Doped ions is different in miscellaneous area 140.
It should be noted that in the present embodiment, while being doped to the first side I epitaxial layer 150,
The forming method also includes：Second side II epitaxial layer 150 is doped, in the second side II formation source regions
161.There are the second Doped ions in shown source region 161.
In the present embodiment, first Doped ions are p-type ion, then second Doped ions are n-type
Ion, specifically, second Doped ions are phosphonium ion.In other embodiments, described second mixes
Heteroion is arsenic ion.
If it should be noted that the concentration of second Doped ions were too low, the side I of drain region 160 and first
The PN junction built in field that high-doped zone 140 is formed is weaker, it is difficult to reduce the junction breakdown voltage of transistor；If
The excessive concentration of second Doped ions, junction breakdown voltage is no longer reduced with the rise of doping concentration,
In addition it is also easy to increase technology difficulty.Therefore, in the present embodiment, the concentration of second Doped ions is
5E18atoms/cm3~1E21atoms/cm3
In the present embodiment, ion implanting formation institute is carried out by the epitaxial layer 150 to the both sides of grid structure 110
Drain region 160 and source region 161 are stated, injection ion is second Doped ions.
Specifically, the technological parameter of the ion implanting includes：Implantation dosage is 5E13atoms
/cm2~5E15atoms/cm2；Implantation Energy is 5KeV~30KeV.
It should be noted that in the present embodiment, the first side I epitaxial layer 150 is doped to be formed Lou
Before the step of area 160, the forming method of the semiconductor structure also includes, and forms the covering grid knot
Second side wall 131 of the side wall of structure 110.
Second side wall 131 is used to prevent drain region and source region too close to described 110 times box drains of grid structure
Road, it is to avoid drain-source break-through occur.
In the present embodiment, the material of second side wall 131 is silicon nitride.In other embodiments, it is described
The material of second side wall can also be silicon oxynitride.
In the present embodiment, the step of forming the second side wall 131 includes：Form the covering grid structure
110 and substrate 100 the second spacer material layer；Remove the second side wall on grid structure 110 and substrate 100
Material layer, retains the second spacer material layer for being formed at the sidewall surfaces of grid structure 110, forms the second side wall
131。
In the present embodiment, the top table of grid structure 110 is covered by chemical vapor deposition method formation
The second spacer material layer of face and side wall and drain region 160 and source region 161.In other embodiments, may be used also
To cover the second spacer material layer of the grid structure and substrate by atom layer deposition process formation.
In this implementation, the on grid structure 110 and substrate 100 is removed by anisotropic dry etch
Two spacer materials layer.Anisotropic dry etch is different in the etch rate of different directions, can remove grid
The second spacer material layer of the top surface of pole structure 110, drain region 160 and the surface of source region 161, and retain
The the second spacer material layer for being formed at the sidewall surfaces of grid structure 110 forms the second side wall 131.
Fig. 9 is the structural representation of another embodiment of forming method of semiconductor structure of the present invention.
It refer to Fig. 9, the something in common of the present embodiment and previous embodiment will not be described here, difference
Including：After the step of forming groove 220, to the groove of the side A of grid structure 210 first
220 base substrates 200 carry out ion implanting, and high-doped zone is formed in the substrate 200 of the bottom of groove 220
240, injection ion includes the first Doped ions.
In the present embodiment, the base substrate 200 of groove 220 to the side A of grid structure 210 first is entered
While row ion implanting, the forming method also includes：It is recessed to the side B of grid structure 210 second
The substrate 200 of the bottom of groove 220 carries out ion implanting, forms high in the substrate 200 of the bottom of groove 220
Doped region 240.
In the present embodiment, the substrate 200 of the bottom of 210 grooves on two sides of grid structure 200 is carried out from
In the step of son injection, injection ion also includes the second ion.The lattice constant of second ion is more than
The lattice constant of substrate 200, can provide longitudinal compression for substrate 200, so as to be carried for substrate 200
For horizontal tensile stress, increase the migration rate of carrier.
In the present embodiment, the material of the substrate 200 is silicon, and second ion is germanium ion.At it
In his embodiment, second ion can also be tin ion.
In the present embodiment, ion implanting is carried out to the substrate 200 of the side A of grid structure 210 first
Technological parameter includes：Implantation Energy is 20KeV~30KeV；Implantation dosage is 1E15atoms
/cm2~4E15atoms/cm2。
It should be noted that above example be with by the substrate to the both sides of grid structure 210 carry out from
Son injection forms high-doped zone 240；Illustrated exemplified by forming epitaxial layer on the surface of high-doped zone 240
's.In another embodiment, formed after high-doped zone, formed before epitaxial layer, the forming method
It can also include：Stressor layers are formed on the high-doped zone surface, the surface of the stressor layers is less than substrate
Surface；The stressor layers are doped, Doped ions are the first Doped ions；In the stressor layers table
Face forms the epitaxial layer of filling groove.
It should also be noted that, being respectively formed the implementation of high-doped zone 240 in the both sides of grid structure 210 above
Example is only one.In other embodiments of the invention, only it can also be formed in the grid structure side
High-doped zone.
To sum up, the forming method of semiconductor structure of the invention passes through in the first side of grid structure bottom portion of groove
Formed high-doped zone, and high-doped zone the first Doped ions and drain region the second Doped ions ionic species
Type is different, then the high-doped zone forms PN junction with drain region, and the PN junction has stronger built in field,
The breakdown voltage of the PN junction can be reduced, so as to reduce the junction breakdown voltage of transistor.Reduce transistor
Junction breakdown voltage can reduce the cut-in voltage of esd protection circuit, make to be obtained by the electrostatic in protection circuit
Fully to discharge, so as to improve the protective value of ESD circuit.
In alternative, the material of the substrate is silicon, and injection ion includes the second ion, described second
Ion is germanium or tin, and the lattice constant of second ion is more than the lattice constant of substrate, therefore described the
Two injection ions can provide the migration rate of carrier in longitudinal tension stress, increase substrate for substrate.
Further, stressor layers can also be formed in the groove, the stressor layers can increase in substrate
The migration rate of carrier.
Further, the first side wall is formed on the gate structure sidewall before the high-doped zone is formed,
First side wall can prevent high-doped zone too close to grid structure lower substrate, so as to avoid
The side of grid structure first and the second side high-doped zone break-through.
Accordingly, the present invention also provides a kind of semiconductor structure, including：Substrate；On the substrate
Grid structure, the grid structure both sides include the first side and second side relative with the first side；It is located at
High-doped zone on the substrate of first side of grid structure, the high-doped zone has the first Doped ions；
Drain region on the high-doped zone of first side of grid structure, the drain region has the second Doped ions；
Second Doped ions are different from the ionic type of first Doped ions.
Fig. 8 is refer to, the structural representation of the embodiment of semiconductor structure one of the present invention is shown.The semiconductor
Structure includes：
Substrate 100；
Grid structure 110 positioned at the surface of substrate 100, the both sides of grid structure 110 include first
The side I and second side II relative with the first side I, the side I substrates 100 of grid structure 110 first
In have groove；
High-doped zone 140 positioned at the surface of bottom portion of groove substrate 100 of the side I of grid structure 110 first,
There are the first Doped ions, the surface of the first high-doped zone 140 is less than institute in the high-doped zone 140
State the surface of substrate 100；
Drain region 160 on the side high-doped zone 140 of grid structure 110 first, the drain region 160
With the second Doped ions, described and Doped ions are different from the ionic type of first Doped ions.
Semiconductor structure of the present invention is described in detail below in conjunction with accompanying drawing.
Substrate 100, the substrate 100 is used to provide operating platform to form semiconductor structure.The present embodiment
In, the semiconductor structure is the n-type transistor of grid and source ground.
In the present embodiment, the substrate 100 is silicon substrate, but the substrate 100 of the present invention does not limit to
In this, the substrate 100 can also be the semiconductors such as germanium substrate, silicon-Germanium substrate or silicon-on-insulator substrate
Substrate.
Grid structure 110 on the substrate 100, the both sides of grid structure 110 include the first side
The I and second side II relative with the first side I, the lower substrate 100 of grid structure 110 constitutes transistor
Raceway groove.
In the present embodiment, the gate dielectric layer that the grid structure 110 includes being located on substrate 100 (is not marked
Show), the gate dielectric layer is used to realize the electric insulation between grid and substrate 100；Positioned at the gate medium
Grid (not indicating) on layer；Hard mask layer (not indicating) on grid；Cover the grid knot
The side wall (not indicating) of the side wall of structure 110.
It should be noted that the semiconductor structure also includes the lightly doped district positioned at the raceway groove both sides
111.The lightly doped district 111 is amorphous area, can reduce the drain source area Doped ions that are subsequently formed to grid
The lower channels of pole structure 110 spread, and reduce the possibility of drain source area break-through.
In the present embodiment, the semiconductor structure is n-type transistor, then the lightly doped drain has and mixed
Heteroion arsenic.
In addition, the semiconductor structure also includes the well region being located in substrate 100.
In the present embodiment, the transistor is n-type transistor, and the well region is p traps.In the well region
With p-type ion, specifically, in the present embodiment, the well region has boron ion.
High-doped zone 140 positioned at the surface of substrate 100 of the side I bottom portion of groove of grid structure 110 first,
The high-doped zone 140 has the first Doped ions.
Drain region 160 on the side I high-doped zones 140 of grid structure 110 first, the drain region 160
With the second Doped ions.Second Doped ions are different from the ionic type of first Doped ions.
The concentration of first Doped ions is larger in the high-doped zone 140, and first Doped ions with
The ionic type of the second Doped ions is different in drain region, therefore, the high-doped zone 140 and the drain region
Form PN junction.The high-doped zone 140 of highly doped ion concentration can form the built-in of higher-strength with drain region
Electric field, so as to reduce the breakdown voltage of the PN junction, and then reduces the junction breakdown voltage for forming transistor.
It should be noted that the semiconductor structure also includes being located at the second side II bottom portion of groove substrates
The high-doped zone 140 on 100 surfaces.
In the present embodiment, first Doped ions be p-type ion, specifically, described first adulterate from
Son is boron ion or indium ion.
In the present embodiment, the lattice constant of high-doped zone 140 is more than the lattice constant of substrate 100, can
Compression is provided for substrate 100 in the vertical, so as to provide tension in the horizontal for substrate 100, is entered
And increase the migration rate of channel carrier.
In the present embodiment, the substrate 100 is silicon substrate, the material of the high-doped zone 140 be containing
The SiGe of boron ion.In other embodiments, the material of the high-doped zone can also be containing boron ion
Silicon tin.
In the present embodiment, if the thickness of the high-doped zone 140 is too small, it is difficult to be formed with drain region 160
PN junction, so as to it is difficult to reduce the junction breakdown voltage of transistor；If the thickness mistake of the high-doped zone 140
Greatly, technology difficulty is easily increased.Therefore, specifically, the thickness of the high-doped zone 140 is
In 10nm~40nm, the present embodiment, the thickness of the high-doped zone 140 is 15nm~20nm.
If it should be noted that the concentration of first Doped ions is too small, it is difficult to play reduction crystal
The effect of pipe junction breakdown voltage；If the concentration of first Doped ions is excessive, the scattering to carrier
Effect is larger, is easily reduced the migration rate of carrier.Specifically, the doping of first Doped ions
Concentration is 1E20atoms/cm3~1E21atoms/cm3.In the present embodiment, first Doped ions it is dense
Spend for 1E20atoms/cm3~3E20atoms/cm3。
It should be noted that the semiconductor structure also includes：Positioned at the side II of grid structure 110 second
Source region 161 on high-doped zone 140.
In the present embodiment, first Doped ions are p-type ion, then second Doped ions are n-type
Ion, specifically, second Doped ions are phosphonium ion.In other embodiments, described second mixes
Heteroion is arsenic ion.
If it should be noted that the concentration of second Doped ions were too low, the side I of drain region 160 and first
The PN junction built in field that high-doped zone 140 is formed is weaker, it is difficult to reduce the junction breakdown voltage of transistor；If
The excessive concentration of second Doped ions, junction breakdown voltage is no longer reduced with the rise of doping concentration,
In addition it is also easy to increase technology difficulty.Therefore, in the present embodiment, the concentration of second Doped ions is
5E18atoms/cm3~1E20atoms/cm3。
If it should be noted that the thickness of the drain region 160 and source region 161 is too small, it is difficult to it is highly doped
Miscellaneous area 140 forms PN junction；If the thickness of the drain region 160 and source region 161 is excessive, easily increase work
Skill difficulty.Therefore, in the present embodiment, the thickness of the drain region 160 and source region 161 is 50nm~60nm.
It should be noted that the semiconductor structure also includes：Cover the of the side wall of grid structure 110
Two side walls 131.
Second side wall 131 is used to make drain region 160 and source region 161 away from described 110 times box drains of grid structure
Road, it is to avoid drain source area break-through occur.
In the present embodiment, the material of second side wall 131 is silicon nitride.In other embodiments, it is described
The material of second side wall can also be silicon oxynitride.
It should be noted that the embodiment that the both sides of grid structure 110 are respectively provided with high-doped zone 140 is only one,
In other embodiments, the semiconductor structure only can also have groove in grid structure side, and only
Bottom portion of groove substrate surface in grid structure side has high-doped zone.
To sum up, in semiconductor structure of the invention, there is high-doped zone below the drain region, it is described highly doped
The first Doped ions in miscellaneous area are different from the ionic type of the Doped ions of drain region second.The drain region and the
Two sides high-doped zone form PN junction, and the PN junction has stronger built in field, can reduce the PN
The junction breakdown voltage of knot, so as to reduce the junction breakdown voltage of semiconductor structure.Semiconductor structure junction breakdown electricity
The reduction of pressure can reduce the cut-in voltage of esd protection circuit, enable to be filled by the electrostatic in protection circuit
Divide release, so as to improve the protective value of ESD circuit.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, it can make various changes or modifications, therefore the guarantor of the present invention
Shield scope should be defined by claim limited range.
Claims (20)
1. a kind of forming method of semiconductor structure, it is characterised in that including：
Substrate is provided；
Form grid structure over the substrate, the grid structure both sides include the first side and with the
The second relative side of side；
The substrate of the side of grid structure first is performed etching, groove is formed；
Have first to mix in bottom portion of groove formation high-doped zone, the high-doped zone in the first side of grid structure
Heteroion；
The epitaxial layer of the filling groove is formed on the high-doped zone of the first side；
The epitaxial layer of first side is doped to form drain region, in the drain region have second adulterate from
Son, second Doped ions are different from the ionic type of first Doped ions.
2. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that also include：To institute
The substrate for stating the side of grid structure second is performed etching, and forms groove；
The bottom portion of groove formation high-doped zone in the second side of grid structure；
The epitaxial layer of the filling groove is formed on the high-doped zone of the second side；
The epitaxial layer of second side is doped to form source region, in the source region have described second adulterate from
Son.
3. the forming method of semiconductor structure as claimed in claim 1 or 2, it is characterised in that formed highly doped
The step of miscellaneous area, includes：Ion implanting is carried out to first side of grid structure bottom portion of groove substrate,
The high-doped zone is formed in the substrate of bottom portion of groove, injection ion includes the first Doped ions.
4. the forming method of semiconductor structure as claimed in claim 3, it is characterised in that the material of the substrate
Expect for silicon；
In the step of carrying out ion implanting to the substrate of the side of grid structure first, injection ion also includes
Second ion, second ion is germanium or tin.
5. the forming method of semiconductor structure as claimed in claim 3, it is characterised in that to the grid knot
The technological parameter that the substrate of the first side of structure bottom portion of groove carries out ion implanting includes：Described first adulterate from
Son is boron ion；The Implantation Energy of boron ion is 2KeV~10KeV, and implantation dosage is 1E14atoms
/cm2~1E15atoms/cm2。
6. the forming method of semiconductor structure as claimed in claim 3, it is characterised in that also include：Institute
State high-doped zone surface and form stressor layers, the surface of the stressor layers is less than substrate surface；Answer described
Power layer is doped, and Doped ions are the first Doped ions；It is recessed in stress layer surface formation filling
The epitaxial layer of groove.
7. the forming method of semiconductor structure as claimed in claim 1 or 2, it is characterised in that formed highly doped
The step of miscellaneous area, includes：
In the lower surface formation stressor layers of the groove, the surface of the stressor layers is less than substrate surface；
The stressor layers are doped, the high-doped zone is formed, Doped ions are the first Doped ions.
8. the forming method of semiconductor structure as claimed in claim 7, it is characterised in that form the stress
The method of layer is epitaxial growth technology；
The step of being doped to the epitaxial layer includes：Adopted during stressor layers described in epitaxial growth
Adulterated the first Doped ions with doping process in situ in the stressor layers.
9. the forming method of semiconductor structure as claimed in claim 7, it is characterised in that the material of the substrate
Expect for silicon；The material of the stressor layers is SiGe or silicon tin.
10. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that first doping
Ion is boron ion or indium ion.
11. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the high-doped zone
In the first Doped ions doping concentration be 1E20atoms/cm3~1E21atoms/cm3。
12. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the high-doped zone
Thickness be 10nm~40nm.
13. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the epitaxial layer
Thickness is 40nm~80nm.
14. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that formed described highly doped
Before miscellaneous area, in addition to：Form the first side wall of the covering gate structure sidewall；
Formed before the epitaxial layer, in addition to：Remove first side wall.
15. a kind of semiconductor structure, it is characterised in that including：
Substrate；
Positioned at the grid structure of the substrate surface, the grid structure both sides include the first side, Yi Jiyu
There is groove in the second relative side of first side, first side of grid structure substrate；
It is described highly doped positioned at the high-doped zone of the bottom portion of groove substrate surface of the side of grid structure first
Area has the first Doped ions, and first high-doped zone surface is less than the substrate surface；
Drain region on the high-doped zone of first side of grid structure, the drain region have second adulterate from
Son, second Doped ions are different from the ionic type of first Doped ions.
16. semiconductor structure as claimed in claim 15, it is characterised in that also include：
Groove in the substrate of second side of grid structure；
Positioned at the high-doped zone of second side of grid structure bottom portion of groove substrate surface；
Source region on the high-doped zone of second side of grid structure.
17. semiconductor structure as claimed in claim 15, it is characterised in that the thickness of the high-doped zone is
10nm~40nm.
18. semiconductor structure as claimed in claim 15, it is characterised in that the material of the high-doped zone be containing
There are the SiGe or silicon tin of the first Doped ions.
19. semiconductor structure as claimed in claim 15, it is characterised in that first Doped ions be boron from
Son or tin ion.
20. semiconductor structure as claimed in claim 15, it is characterised in that the concentration of first Doped ions
For 1E20atoms/cm3~1E21atoms/cm3。
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Application publication date: 20170811 |