JPH0828514B2 - Thin film transistor and manufacturing method thereof - Google Patents
Thin film transistor and manufacturing method thereofInfo
- Publication number
- JPH0828514B2 JPH0828514B2 JP23704388A JP23704388A JPH0828514B2 JP H0828514 B2 JPH0828514 B2 JP H0828514B2 JP 23704388 A JP23704388 A JP 23704388A JP 23704388 A JP23704388 A JP 23704388A JP H0828514 B2 JPH0828514 B2 JP H0828514B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- source
- drain
- semiconductor layer
- film transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010409 thin film Substances 0.000 title claims description 34
- 238000004519 manufacturing process Methods 0.000 title description 7
- 239000010408 film Substances 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 12
- 239000002019 doping agent Substances 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 11
- 230000001133 acceleration Effects 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 4
- 238000000034 method Methods 0.000 description 18
- 239000010410 layer Substances 0.000 description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 239000011521 glass Substances 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 7
- 230000005684 electric field Effects 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 5
- 238000009826 distribution Methods 0.000 description 4
- 230000004913 activation Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、絶縁物基板上に低温プロセスで製造でき、
高移動度、高耐圧でリーク電流の少ない薄膜トランジス
タに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application] The present invention can be manufactured on an insulating substrate by a low temperature process,
The present invention relates to a thin film transistor having high mobility, high breakdown voltage, and small leak current.
近年ガラス基板上に薄膜能動デバイスをつくりこむ技
術は、大面積透過型液晶ディスプレイや密着型イメージ
センサ等を初めとする各所に応用がめざされ、研究が活
発化している。そのなかでも大面積に均一に成膜できる
a-Si:Hは既に製品レベルの応用が進んでいる。しかしa-
Si:Hでは移動度が非常に遅いためその応用分野が制限さ
れている。すなわち光センサやスイッチングデバイスと
しては応用可能であるが、これらを駆動する周辺回路を
同時につくりこもうとした場合移動度が単結晶シリコン
の約1000分の１と低いため必要とする速さの駆動回路を
製作することができない。現在この様な駆動回路はシリ
コンウエハー上で製作されワイヤボンディングで薄膜デ
バイスと接続しているのが現状である。しかし製造コス
トや配線の歩どまりなどの点から、将来的には全薄膜化
が必用とされている。このためにはガラス基板上に高移
動度薄膜を製作する手段が必用となる。最近では、ガラ
ス基板上で単結晶シリコンを得ることも可能となってき
た。しかしこのためにはかなりの高温プロセスを必用と
し、ガラス基板も含め他の部分が高温にさらされること
になる。この結果使用するガラス基板などを耐熱性の高
い物にしなければならないこと、他部への損傷の問題等
が生じでくる。そこで低温プロセスで均一に高移動度の
薄膜能動デバイスを作成する研究が各所でおこなわてて
いる。その一つとして多結晶シリコンのTFTの研究開発
がおこなわれている。In recent years, the technology for forming thin film active devices on a glass substrate has been applied to various places such as large area transmissive liquid crystal displays and contact image sensors, and research has been activated. Among them, it is possible to form a uniform film on a large area.
a-Si: H is already being applied at the product level. But a-
The mobility of Si: H is very slow, limiting its field of application. In other words, it can be applied as an optical sensor or switching device, but when trying to build the peripheral circuits that drive them at the same time, the mobility is as low as about 1/1000 that of single-crystal silicon, so driving at the required speed is possible. I can't make a circuit. At present, such a drive circuit is manufactured on a silicon wafer and is connected to a thin film device by wire bonding. However, due to factors such as manufacturing cost and wiring yield, it is necessary to reduce the total thickness in the future. For this purpose, means for producing a high mobility thin film on a glass substrate is necessary. Recently, it has become possible to obtain single crystal silicon on a glass substrate. However, this requires a fairly high temperature process and exposes other parts including the glass substrate to high temperatures. As a result, the glass substrate to be used must have a high heat resistance, and problems such as damage to other parts occur. Therefore, research is being carried out in various places to uniformly produce high mobility thin film active devices by low temperature processes. As one of them, research and development of a polycrystalline silicon TFT has been conducted.
しかし、多結晶シリコンTFTでは通常のMOSFETやまた
アモルファスシリコンのFETに比べても、リーク電流が
多いことが問題となっている。However, the problem with polycrystalline silicon TFTs is that they have more leakage current than ordinary MOSFETs and amorphous silicon FETs.
第５図は従来のプレーナ型薄膜トランジスタの構造及
びその製造方法を示したものである。まずガラス基板１
上に活性層となる多結晶シリコン３をアイランド化しゲ
ート絶縁膜４、ゲート電極５形成後、ゲート電極をパタ
ーン化する（第５図（ａ））。この後、ゲート電極をマ
スクとしてイオン注入によりソース・ドレイン領域７を
形成する（第５図（ｂ））。この後層間絶縁膜８の形
成、コンタクトホール形成を行い、メタル配線によりソ
ース・ドレイン電極２を形成して薄膜トランジスタがで
き上る（第５図（ｃ））。ソース・ドレインの形成は第
２図（ｂ）に示すように表面濃度を高くするようなプロ
ファイルを持つような加速エネルギでイオン注入を行な
う。これはソース・ドレイン電極とのオーミック性をよ
くするためである。このような構造ではドレイン端の濃
度プロファイルは急峻なジャンクションとなり空乏層に
高電界が集中する。これがオフ電流が大きい原因となっ
ている。リーク電流が多いことは液晶のスイッチングデ
バイスとしても、駆動回路を製作する上でも問題とな
る。特に液晶やエレクトロルミネッセンス素子（EL）等
高電圧を必要とするデバイスを駆動する応用が多いた
め、高耐圧で低リーク電流のデバイスが必要である。し
かし通常のプレーナ型多結晶薄膜トランジスタでは特に
高電界印加時にリーク電流が急激に増大するという問題
点を持っている。従来MOSFETの高耐圧化の方法としてLD
D構造があるが、この方法をそのまま薄膜トランジスタ
に適用するとレジスト工程を含め工程数が増える。また
移動度、しきい値の劣化などを引き起こすという問題点
があった。本発明の目的は工程数の増加や、移動度、閾
値の劣化を引き起こすことなく耐圧、リーク電流につい
て改善されたデバイス構造及びその構造方法を得ること
にある。FIG. 5 shows the structure of a conventional planar type thin film transistor and its manufacturing method. First glass substrate 1
After forming the gate insulating film 4 and the gate electrode 5 by forming the polycrystalline silicon 3 which becomes an active layer on the top, the gate electrode is patterned (FIG. 5A). After that, the source / drain regions 7 are formed by ion implantation using the gate electrode as a mask (FIG. 5B). After that, the interlayer insulating film 8 is formed and contact holes are formed, and the source / drain electrodes 2 are formed by the metal wiring to complete the thin film transistor (FIG. 5 (c)). The formation of the source / drain is performed by ion implantation with acceleration energy having a profile such that the surface concentration is increased as shown in FIG. 2 (b). This is to improve ohmic contact with the source / drain electrodes. In such a structure, the concentration profile at the drain end becomes a steep junction, and a high electric field is concentrated in the depletion layer. This is the cause of the large off current. A large amount of leak current is a problem not only as a liquid crystal switching device but also as a driver circuit. In particular, since there are many applications for driving devices that require high voltage such as liquid crystal and electroluminescence element (EL), devices with high breakdown voltage and low leakage current are required. However, the conventional planar type polycrystalline thin film transistor has a problem that the leak current rapidly increases especially when a high electric field is applied. LD is used as a method to increase the breakdown voltage of conventional MOSFETs.
Although there is a D structure, if this method is directly applied to a thin film transistor, the number of steps including the resist step increases. Further, there is a problem that mobility and threshold values are deteriorated. An object of the present invention is to obtain a device structure and a structure method thereof, which have improved breakdown voltage and leak current without increasing the number of steps, deterioration of mobility and threshold value.
この発明は、絶縁性基板上に設けられたソース・ドレ
イン電極とその上部に設けられた多結晶薄膜半導体層、
ゲート絶縁膜層、ゲート電極よりなる順スタガ型薄膜ト
ランジスタに於て、多結晶薄膜半導体層中のソース・ド
レイン領域のドーパント濃度を膜厚の方向にチャネル側
（ゲート電極側）を低くソース・ドレイン電極側を高く
した縦型LDD構造（ライトリィ・ドープド・ドレイン）
を有することを特徴とする構成になっている。またこの
薄膜トランジスタは、ソース・ドレイン領域形成時に多
結晶薄膜半導体層最下部にピークを持つ濃度プロファイ
ルとなる加速エネルギでゲート電極側から多結晶薄膜半
導体層中にイオン注入を行うことによってドーパント濃
度を膜厚の方向にチャネル側を低くソース・ドレイン電
極側を高くしたソース・ドレイン領域を形成する方法で
製造することができる。This invention relates to a source / drain electrode provided on an insulating substrate and a polycrystalline thin film semiconductor layer provided on the source / drain electrode,
In a forward staggered thin film transistor including a gate insulating film layer and a gate electrode, the dopant concentration of the source / drain region in the polycrystalline thin film semiconductor layer is set to be low on the channel side (gate electrode side) in the film thickness direction. Vertical LDD structure with raised side (lightly doped drain)
It is characterized by having. In addition, this thin film transistor has a dopant concentration which is formed by performing ion implantation from the gate electrode side into the polycrystalline thin film semiconductor layer with acceleration energy that has a concentration profile having a peak at the bottom of the polycrystalline thin film semiconductor layer when forming the source / drain regions. It can be manufactured by a method of forming source / drain regions in which the channel side is low and the source / drain electrode side is high in the thickness direction.
薄膜を使用して製作される薄膜トランジスタの構造と
しては通常のプレーナタイプとよばれる構造とソース・
ドレイン電極とゲート電極とで薄膜半導体層をはさんだ
スタガード構造と呼ばれる構造がある。通常のプレーナ
構造の薄膜トランジスタではソース・ドレイン間に電圧
を加えて行ったときにドレイン端に高電界が印加され、
この点でのバンドギャップ間の電界エミッション電流が
リーク電流の原因となる。ここで結晶シリコンではこの
ようなバンド間のリーク電流は少ないため通常では問題
とならない。しかし多結晶シリコンではバンドギャップ
中に多くの粒界トラップが存在しこれを介してのバンド
間のリーク電流が流れやすい。このため高電圧印加時に
急激なリーク電流の増加が観測される。このようなリー
ク電流は多結晶シリコンでは本質的に避けられないもの
である。しかしこの電流はドレイン端の空乏層間にかか
る電界に依存しているのでドレインのドーピング濃度を
小さくすれば、この領域にかかる電界を軽減しリーク電
流を低減することができる。しかし一方でソース・ドレ
インの寄生抵抗を高くすることになる。あるいは電極メ
タルとのオーミック性の問題からあまりドーピング濃度
を下げることはできない。そこで本発明ではドレイン端
の近傍のみドーピング濃度が低いLDD構造を再現性良く
製作し移動度、しきい値の低下をひき起こすことなくソ
ース・ドレイン間の耐圧を向上させリーク電流の改善を
行なっている。順スタガードタイプのトランジスタでは
チャネルとドレイン電極とが活性層の膜厚だけはなれて
いる。そこで表面のドーパント濃度を低くし深くなるに
つれて高いドーパント濃度分布を形成すれば縦型の微小
なLDD構造となり移動度などの低下を引き起こす事なく
リーク電流、耐圧に優れた特性が実現できる。ソース・
ドレイン電極とのオーミック性も良好である。The structure of a thin film transistor manufactured using a thin film is called a normal planar type structure and source
There is a structure called a staggered structure in which a thin film semiconductor layer is sandwiched between a drain electrode and a gate electrode. In a normal planar thin film transistor, when a voltage is applied between the source and drain, a high electric field is applied to the drain end,
The electric field emission current between the band gaps at this point causes a leak current. Here, in crystalline silicon, such a leak current between bands is small, so that it does not usually cause a problem. However, in polycrystalline silicon, many grain boundary traps exist in the band gap, and leak current between bands easily flows through the traps. Therefore, a sudden increase in leak current is observed when a high voltage is applied. Such leak current is essentially unavoidable in polycrystalline silicon. However, since this current depends on the electric field applied to the depletion layer at the drain end, the electric field applied to this region can be reduced and the leak current can be reduced by reducing the doping concentration of the drain. However, on the other hand, the parasitic resistance of the source / drain is increased. Alternatively, the doping concentration cannot be lowered so much due to the problem of ohmic contact with the electrode metal. Therefore, in the present invention, an LDD structure in which the doping concentration is low only near the drain edge is manufactured with good reproducibility, and the withstand voltage between the source and the drain is improved and the leak current is improved without causing the lowering of the mobility and the threshold value. There is. In the forward staggered type transistor, the channel and drain electrodes are deviated from each other by the thickness of the active layer. Therefore, if the dopant concentration on the surface is lowered and a higher dopant concentration distribution is formed as the depth becomes deeper, a vertical minute LDD structure is formed, and characteristics excellent in leak current and breakdown voltage can be realized without lowering mobility and the like. Source·
The ohmic contact with the drain electrode is also good.
イオン注入法を用いてソース・ドレイン領域を形成す
る時、通常は表面濃度が高くなるように加速電圧の設定
をするが、この加速電圧をより高くすることにより、表
面のドーパント濃度を低くし深くなるにつれて高いドー
パント濃度分布をつくることができる。さらにこのドー
パントの活性化を通常用いられる熱処理による活性化で
なくラピッドサーマルアニーリングで行えばこのドーピ
ングプロファイルを変えることなく活性化が行える。通
常の熱処理ではプロファイルが鈍化し効果が半減する恐
れがあるからである。以上の方法により簡単に自己整合
的に縦型LDD構造が作成できる。順スタガ型トランジス
タのソース・ドレイン領域の形成にこの方法を用いるこ
とにより、前述した縦型LDD構造のトランジスタが作製
でき、移動度などの低下を引き起こす事なくリーク電
流、耐圧に優れた特性が実現できる。またこの方法によ
るとゲート絶縁膜をそのまま層間絶縁膜として使うこと
もできるので、配線工程が短縮されマスク工程が少なく
てすむという利点もあわせ持っている。When the source / drain regions are formed by using the ion implantation method, the acceleration voltage is usually set so that the surface concentration is high.By increasing the acceleration voltage, the surface dopant concentration is lowered and the A higher dopant concentration distribution can be created. Furthermore, if activation of this dopant is performed by rapid thermal annealing instead of activation by heat treatment that is usually used, activation can be performed without changing the doping profile. This is because the profile may be blunted by ordinary heat treatment and the effect may be halved. By the above method, the vertical LDD structure can be easily created in a self-aligned manner. By using this method to form the source / drain regions of the forward staggered transistor, the transistor of the vertical LDD structure described above can be manufactured, and excellent characteristics of leakage current and withstand voltage are realized without lowering mobility. it can. Further, according to this method, since the gate insulating film can be used as it is as an interlayer insulating film, it also has an advantage that the wiring process can be shortened and the mask process can be reduced.
以下添付の図面に示す実施例により発明の詳細を説明
する。第１図（ａ），（ｂ），（ｃ）は本発明の一実施
例を示す工程図である。第１図（ａ）に示すように高融
点金属を用いてガラス基板１の表面にソース・ドレイン
電極２のパターンを形成する。活性層となる多結晶シリ
コン３をアイランド化した後、ゲート絶縁膜４、ゲート
電極５を順次成膜し、ゲート電極パターンを形成すると
ころまでは通常のデバイス作製プロセスと同様に行う
（第１図（ｂ））。この後ゲート電極５をマスクとして
イオン注入法により自己整合的にソース・ドレイン高濃
度領域７を形成した（第１図（ｃ））。ここではＰイオ
ン６を200keVの加速エネルギで打ち込んだ。この結果第
２図（ａ）に示すように多結晶シリコン表面のドーパン
ト密度を低く、深くなるに連れてドーピング濃度が高く
なるようにすることができた。この時の加速エネルギは
イオン種、ゲート絶縁膜の厚さによって変化するが適当
な加速エネルギーを選ぶことによって同様のプロファイ
ルを得ることが可能である。この結果、チャネル近傍の
ドーピング濃度が低く、電極に近づくに連れドーピング
濃度が高い縦型のLDD構造を有するトランジスタが簡単
に得られた。ドーピング濃度分布の制御性、再現性も高
い。第１図に示す本発明の構造ではソース・ドレイン電
極が多結晶シリコンの下部にあるため、表面濃度を低減
することが可能であり、この結果LDD構造が得られたの
である。Hereinafter, the details of the invention will be described with reference to the accompanying drawings. 1 (a), (b) and (c) are process drawings showing an embodiment of the present invention. As shown in FIG. 1A, a pattern of the source / drain electrodes 2 is formed on the surface of the glass substrate 1 using a refractory metal. After the polycrystalline silicon 3 which becomes the active layer is formed into an island, the gate insulating film 4 and the gate electrode 5 are sequentially formed, and the process up to the point where the gate electrode pattern is formed is performed in the same manner as a normal device manufacturing process (see FIG. 1). (B)). After that, the source / drain high-concentration regions 7 were formed in a self-aligned manner by ion implantation using the gate electrode 5 as a mask (FIG. 1 (c)). Here, P ions 6 are implanted with an acceleration energy of 200 keV. As a result, as shown in FIG. 2 (a), the dopant density on the surface of the polycrystalline silicon was low, and the doping concentration could be increased as the depth increased. The acceleration energy at this time varies depending on the ion species and the thickness of the gate insulating film, but a similar profile can be obtained by selecting an appropriate acceleration energy. As a result, a transistor having a vertical LDD structure, in which the doping concentration near the channel is low and the doping concentration becomes higher as it gets closer to the electrode, was easily obtained. The controllability and reproducibility of the doping concentration distribution are also high. In the structure of the present invention shown in FIG. 1, since the source / drain electrodes are located under the polycrystalline silicon, it is possible to reduce the surface concentration, and as a result, the LDD structure is obtained.
実際に製作した薄膜トランジスタの特性を第３図に示
す。ドレイン電流のゲート電圧による変化を示してい
る。実線が本発明による製作されたトランジスタで破線
で示すのが従来の方法で作製したトランジスタの特性で
ある。この様に電界効果移動度、しきい値は殆ど変わら
ず、オフ電流は減少しておりリーク電流については大き
く改善されていることがわかった。また第４図にゲート
電圧を0Vにした時のドレイン電圧に対するリーク電流の
特性を示す。従来のプレーナ構造の薄膜トランジスタで
は、ドレイン電圧の増加に従い、急激なリーク電流の増
加がみられているが、本発明によるトランジスタではこ
のような急激なリーク電流の増加はみられていない。特
に高電圧駆動下においてリーク電流の著しい改善が得ら
れた。耐圧は30V以上あり、30Vの電圧印加時でもリーク
電流は10-10Ａ以下である。この結果従来のプレーナ型
トランジスタに比べ高耐圧、低リーク電流のトランジス
タがえられた。The characteristics of the actually manufactured thin film transistor are shown in FIG. The change of the drain current with the gate voltage is shown. The solid line indicates the transistor manufactured according to the present invention, and the broken line indicates the characteristics of the transistor manufactured by the conventional method. As described above, it was found that the field effect mobility and the threshold value hardly changed, the off current decreased, and the leak current was greatly improved. Further, FIG. 4 shows the characteristics of the leak current with respect to the drain voltage when the gate voltage is 0V. In the conventional thin film transistor having the planar structure, the leak current rapidly increases as the drain voltage increases, but the transistor according to the present invention does not show such a rapid leak current increase. Especially, the leakage current was remarkably improved under high voltage driving. The withstand voltage is 30 V or more, and the leak current is 10 -10 A or less even when a voltage of 30 V is applied. As a result, a transistor having a high breakdown voltage and a low leakage current was obtained as compared with the conventional planar type transistor.
プレーナ型トランジスタにおいても同様な方法で縦型
LDD構造を作成することができるが、ドレイン電極のオ
ーミック性や製造の制御性などの点から順スタガの法が
優れていた。The vertical type is also applied to the planar type transistor by the same method.
Although the LDD structure can be formed, the forward stagger method was excellent in terms of ohmic characteristics of the drain electrode and controllability of manufacturing.
以上詳述したように、本発明による薄膜トランジスタ
の製造方法により微少な縦型LDD構造が簡単な工程で再
現性よく制作できた。またこの製造方法を用いた本発明
による構造の薄膜トランジスタにより高耐圧でリーク電
流が少なく高速動作が可能な薄膜トランジスタを得るこ
とができた。この結果回路構成においても高電圧で駆動
でき、回路設計のマージンが高くとれるようになった。As described in detail above, a minute vertical LDD structure can be produced with good reproducibility by a simple process by the method of manufacturing a thin film transistor according to the present invention. Further, a thin film transistor having a high breakdown voltage, a small leak current and a high speed operation can be obtained by the thin film transistor having the structure according to the present invention using this manufacturing method. As a result, the circuit configuration can be driven at a high voltage, and the circuit design margin can be increased.
第１図は本発明の一実施例を示す図。第２図（ａ），
（ｂ）は本発明のトランジスタと従来のトランジスタの
活性層におけるドーパント濃度分布を示す図、第３図及
び第４図は本発明と従来のトランジスタの特性を比較し
た図、第５図は従来例を示す図である。 1.……ガラス基板、２……ソース・ドレイン電極、３…
…多結晶シリコン、４……ゲート絶縁膜（SiO2膜）、５
……ゲート電極、６……イオン、７……ソース・ドレイ
ン高濃度領域、８……層間絶縁膜。FIG. 1 is a diagram showing an embodiment of the present invention. Figure 2 (a),
(B) is a diagram showing the dopant concentration distribution in the active layer of the transistor of the present invention and the conventional transistor, FIGS. 3 and 4 are diagrams comparing the characteristics of the present invention and the conventional transistor, and FIG. 5 is a conventional example. FIG. 1 .... Glass substrate, 2 ... Source / drain electrodes, 3 ...
… Polycrystalline silicon, 4 …… Gate insulating film (SiO 2 film), 5
...... Gate electrode, 6 ... Ion, 7 ... Source / drain high concentration region, 8 ... Interlayer insulating film.
Claims (2)
ン電極とその上部に設けられた多結晶薄膜半導体層、ゲ
ート絶縁膜層、ゲート電極よりなる順スタガ型薄膜トラ
ンジスタに於て、前記多結晶薄膜半導体層のソース・ド
レイン領域（ソース・ドレイン電極に接する領域）のド
ーパント濃度を膜厚の方向にチャネル側を低くソース・
ドレイン電極側を高くした縦型LDD構造（ライトリィ・
ドープド・ドレイン）を有することを特徴とする薄膜ト
ランジスタ。1. A forward stagger type thin film transistor comprising a source / drain electrode provided on an insulating substrate and a polycrystalline thin film semiconductor layer provided on the source / drain electrode, a gate insulating film layer, and a gate electrode, wherein the polycrystalline The dopant concentration of the source / drain regions (regions in contact with the source / drain electrodes) of the thin film semiconductor layer is lowered in the channel direction in the direction of the film thickness.
Vertical LDD structure with a high drain electrode side (lightly
A thin film transistor having a doped drain.
結晶薄膜半導体層、ゲート絶縁膜、ゲート電極を積層形
成した後、多結晶薄膜半導体層最下部にピークを持つ濃
度プロファイルとなる加速エネルギでゲート電極側より
多結晶薄膜半導体層中にイオン注入を行うことによって
多結晶薄膜半導体層中のドーパント濃度を膜厚の方向に
チャネル側を低く、ソース・ドレイン電極側を高くした
ソース・ドレイン領域を形成することを特徴とする薄膜
トランジスタの製造方法。2. Acceleration energy having a concentration profile having a peak at the bottom of the polycrystalline thin film semiconductor layer after a source / drain electrode, a polycrystalline thin film semiconductor layer, a gate insulating film, and a gate electrode are laminated and formed on an insulating substrate. By implanting ions from the gate electrode side into the polycrystalline thin film semiconductor layer, the source / drain regions are formed so that the dopant concentration in the polycrystalline thin film semiconductor layer is lower in the direction of film thickness on the channel side and higher on the source / drain electrode side. Forming a thin film transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23704388A JPH0828514B2 (en) | 1988-09-20 | 1988-09-20 | Thin film transistor and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23704388A JPH0828514B2 (en) | 1988-09-20 | 1988-09-20 | Thin film transistor and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0283939A JPH0283939A (en) | 1990-03-26 |
| JPH0828514B2 true JPH0828514B2 (en) | 1996-03-21 |
Family
ID=17009559
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23704388A Expired - Lifetime JPH0828514B2 (en) | 1988-09-20 | 1988-09-20 | Thin film transistor and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0828514B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5480818A (en) * | 1992-02-10 | 1996-01-02 | Fujitsu Limited | Method for forming a film and method for manufacturing a thin film transistor |
| JP2009182167A (en) * | 2008-01-31 | 2009-08-13 | Dainippon Printing Co Ltd | Production process of thin-film transistor, and thin-film transistor |
-
1988
- 1988-09-20 JP JP23704388A patent/JPH0828514B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0283939A (en) | 1990-03-26 |
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