JPH02206173A - Polycrystalline thin-film transistor - Google Patents

Polycrystalline thin-film transistor

Info

Publication number
JPH02206173A
JPH02206173A JP2797789A JP2797789A JPH02206173A JP H02206173 A JPH02206173 A JP H02206173A JP 2797789 A JP2797789 A JP 2797789A JP 2797789 A JP2797789 A JP 2797789A JP H02206173 A JPH02206173 A JP H02206173A
Authority
JP
Japan
Prior art keywords
current
holes
gate electrode
insulating film
active layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2797789A
Other languages
Japanese (ja)
Inventor
Kenji Sera
賢二 世良
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2797789A priority Critical patent/JPH02206173A/en
Publication of JPH02206173A publication Critical patent/JPH02206173A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To make breakdown strength of the title transistor high and to decrease leakage of current by providing a plurality of through holes in a semiconductor active layer and providing a gate insulating film and a gate electrode also on the sidewalls of the through-holes. CONSTITUTION:A multiplicity of through-holes 6 are provided in a semiconductor active layer 2a consisting of a polycrystalline silicon film, and a gate insulating film 3 and a gate electrode 4 are provided also on the side walls of the through-holes 6. A plurality of through-holes are provided particularly under the gate electrode 4 so that the semiconductor layer has a mesh-like shape. Thus, the semiconductor layer itself has high resistance and OFF current is lowered. Accordingly, the interface with the insulating film constituting a channel 9 has an increased area whereby an effective W/L ratio is increased and large ON current can be obtained. Consequently, a high ON/OFF current ratio can be obtained, breakdown strength between the source and drain can be improved and leakage of current can be decreased.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、多結晶薄膜トランジスタの製造方法に関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a polycrystalline thin film transistor.

〔従来の技術〕[Conventional technology]

近年ガラス基板上に薄膜能動デバイスをつくりこむ技術
は、大面積透過型液晶デイスプレィや密着型イメージセ
ンサ等を初めとする各種の応用がめざされ、研究が活発
化している。そのなかでも大面積に均一に成膜できるａ
−８ｉ：Ｈ薄膜（無定形゛シリコン薄膜）は既に製品レ
ベルの応用が進んでいる。しかしａ−８ｔ：Ｈ薄膜では
移動度が非常に遅いためその応用分野が制限されている
。In recent years, research into technology for fabricating thin-film active devices on glass substrates has been intensified, with the aim of creating various applications such as large-area transmissive liquid crystal displays and contact image sensors. Among them, a can form a film uniformly over a large area.
-8i:H thin film (amorphous silicon thin film) is already being applied at the product level. However, the mobility of the a-8t:H thin film is very slow, which limits its field of application.

すなわち光センサやスイッチングデバイスとしては応用
可能であるが、これらを駆動する周辺回路を同時につく
りこもうとした場合移動度が単結晶シリコンの約１００
０分の１と低いため必要とする速さの駆動回路を作成す
ることができない。現在この様な駆動回路はシリコンウ
ェーハ上で作成されワイヤボンディングで薄膜デバイス
と接続しているのが現状である。しかし製造コストや配
線の歩どまりなどの点から、将来的には全薄膜化が必用
とされている。このためにはガラス基板上に高移動度薄
膜を作成する手段が必要となる。最近では、ガラス基板
上で単結晶シリコンを得ることも可能となってきた。し
かしこのためにはがなりの高温プロセスを必用とし、ガ
ラス基板も含め他の部分が高温にさらされることになる
。この結果使用するガラス基板などを耐熱性の高い物に
しなければならないこと、他部への損傷の問題等が生じ
てくる。そこで低温プロセスで均一に高移動度の薄膜能
動デバイスを作成する研究が各所でおこなわれている。In other words, it can be applied as optical sensors and switching devices, but if you try to simultaneously create peripheral circuits to drive these devices, the mobility will be about 100 times that of single crystal silicon.
Since the speed is as low as 1/0, it is not possible to create a drive circuit with the required speed. Currently, such drive circuits are fabricated on silicon wafers and connected to thin film devices by wire bonding. However, from the viewpoint of manufacturing costs and wiring yields, it will be necessary to make all the films thinner in the future. This requires a means to create a high-mobility thin film on a glass substrate. Recently, it has become possible to obtain single crystal silicon on a glass substrate. However, this requires a very high-temperature process, and other parts, including the glass substrate, are exposed to high temperatures. As a result, the glass substrate used has to be made of a material with high heat resistance, and problems such as damage to other parts arise. Therefore, research is being conducted in various places to create thin film active devices with uniformly high mobility using low-temperature processes.

第６図は従来のプレーナ型薄膜トランジスタの構造を示
したものである。アイランド化された多結晶シリコン膜
２上にゲート絶縁膜３、ゲート電極４形成後、ゲート電
極をマスクとしてイオン注入によりソース領域２ｓ、　
ドレイン領域２ｄを形成し、眉間絶縁膜７の形成、コン
タクトホール形成を行い、メタル配線を行う。このよう
な作成法により低温で電界効果移動度１００ｃｎｆ／Ｖ
、ｓ以上の性能が得られるようになった。FIG. 6 shows the structure of a conventional planar thin film transistor. After forming a gate insulating film 3 and a gate electrode 4 on the islanded polycrystalline silicon film 2, source regions 2s,
A drain region 2d is formed, a glabellar insulating film 7 is formed, a contact hole is formed, and metal wiring is formed. With this manufacturing method, the field effect mobility is 100cnf/V at low temperature.
, s or higher performance can now be obtained.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし多結晶シリコンＴＰＴでは通常のＭＯＳＦＥＴや
またアモルファスシリコンのＦＥＴに比べても、漏れ電
流が多いことが問題となっている。漏れ電流が多いこと
は液晶のスイッチングデバイスとしても、駆動回路を作
成する上でも問題問題となる。特に液晶やＥＬ等高電圧
を必要とするデバイスを駆動する応用が多いため、高耐
圧で低漏れ電流のデバイスが必要である。しかし通常の
プレーナ型多結晶薄膜トランジスタでは特に高電界印加
時に漏れ電流が急激に増大するという問題点を持ってい
る。However, a problem with polycrystalline silicon TPTs is that they have a higher leakage current than normal MOSFETs or even amorphous silicon FETs. A large amount of leakage current is a problem both in liquid crystal switching devices and in creating drive circuits. In particular, since there are many applications for driving devices that require high voltage such as liquid crystals and EL, devices with high breakdown voltage and low leakage current are required. However, ordinary planar polycrystalline thin film transistors have the problem that leakage current increases rapidly, especially when a high electric field is applied.

本発明の目的は工程数の増加や、移動度、しきい値の劣
化を引き起こすことなく耐圧、漏れ電流について改善さ
れたデバイス構造を得ることにある。An object of the present invention is to obtain a device structure with improved breakdown voltage and leakage current without increasing the number of steps or causing deterioration of mobility or threshold value.

〔課題を解決するための手段〕[Means to solve the problem]

この発明の要旨とするところは、絶縁性基板上に設けら
れた半導体活性層とそれをおおうゲート絶縁膜及びゲー
ト電極を含む多結晶薄膜トランジスタに於て、前記半導
体活性層に複数の貫通孔を有し、前記貫通孔の側壁部に
もゲート絶縁膜及びゲート電極が設けられているという
ものである。The gist of the present invention is to provide a polycrystalline thin film transistor including a semiconductor active layer provided on an insulating substrate, a gate insulating film covering the same, and a gate electrode, in which the semiconductor active layer has a plurality of through holes. However, a gate insulating film and a gate electrode are also provided on the side walls of the through hole.

〔作用〕[Effect]

通常のプレーナ構造の薄膜トランジスタではソース・ド
レイン間に電圧を加えて行ったときにドレイン端に高電
界が印加され、この点でのバンドギャップ間の電界エミ
ッション電流が漏れ電流の原因となる。ここで単結晶シ
リコンではこのようなバンド間の漏れ電流は少ないため
通常では問題とならない。しかし多結晶シリコンではバ
ンドギャップ中に多くの粒界トラップが存在しこれを介
してのバンド間の漏れ電流が流れやすい。このため高電
圧印加時に急激な漏ね電流の増加が観測される。このよ
うな漏れ電流は多結晶シリコンでは本質的に避けられな
いものである。しかしこの電流はドレイン端の空乏層に
かかる電界に依存しているのでトレインのドーピング濃
度を小さくすれば、この領域にかかる電界を軽減し漏れ
電流を低減することができる。しかし一方でソース・ド
レインの寄生抵抗を高くすることになる、あるいは電極
金属とのオーミック性の問題からあまりドーピング濃度
を下げることはできない。一方でこのような漏れ電流も
チャネルを形成する半導体層の抵抗で制限される。ａ−
８ｉのトランジスタではこの半導体の抵抗が大きいため
ドレイン端での漏れ電流が大きいにもかかわらず漏れ電
流は低く押えられている。そこで本発明ではチャネルを
形成する活性層、特にゲート電極下部に複数の貫通孔を
設け、網目上の形状をもたせることにより、半導体層自
体の抵抗を高くし、オフ電流を低くしている。さらに活
性層に多数の貫通孔を有するため、チャネルを形成する
絶縁膜との界面を形成する面積が大きくなる。すなわち
第２図はトランジスタのチャネル部を拡大したものであ
るが、この図に示すように、半導体層に縦方向だけでな
く、横方向からも電界がかかるためチャネルを形成する
面積が大きくなる。このため実効的なＷ／Ｌ比が大きく
なり、大きなオン電流を得られる。この結果、高いオン
・オフ電流比を得、ソース・ドレイン間の耐圧を向上さ
せ漏れ電流の改善を行なっている。さらに電界が縦方向
だけでなく横方向からも印加されるため端部で電界強度
が強まり急峻なサブスレッショルド特性を有するという
利点も合わせ持っている。ただし、この電界強度の強ま
りはトレイン端にあっては漏れ電流の増加を引き起こす
。このため活性層上に形成される貫通孔はゲート電極下
のみにあって、ドレイン端には存在しないことが重要で
ある。In a normal thin film transistor with a planar structure, when a voltage is applied between the source and drain, a high electric field is applied to the drain end, and the electric field emission current between the band gaps at this point causes leakage current. Here, in single-crystal silicon, such leakage current between bands is small, so it usually does not pose a problem. However, in polycrystalline silicon, there are many grain boundary traps in the band gap, and leakage current between bands easily flows through these traps. For this reason, a rapid increase in leakage current is observed when high voltage is applied. Such leakage current is essentially unavoidable in polycrystalline silicon. However, since this current depends on the electric field applied to the depletion layer at the drain end, by reducing the doping concentration of the train, the electric field applied to this region can be reduced and leakage current can be reduced. However, on the other hand, the doping concentration cannot be lowered much because it increases the parasitic resistance of the source and drain, or because of the problem of ohmic relationship with the electrode metal. On the other hand, such leakage current is also limited by the resistance of the semiconductor layer forming the channel. a-
In the 8i transistor, the resistance of this semiconductor is large, so even though the leakage current at the drain end is large, the leakage current is kept low. Therefore, in the present invention, a plurality of through holes are provided in the active layer forming the channel, particularly in the lower part of the gate electrode, to give the active layer a mesh shape, thereby increasing the resistance of the semiconductor layer itself and lowering the off-state current. Furthermore, since the active layer has a large number of through holes, the area for forming an interface with an insulating film forming a channel becomes large. That is, FIG. 2 is an enlarged view of the channel portion of a transistor, and as shown in this figure, an electric field is applied to the semiconductor layer not only in the vertical direction but also in the lateral direction, so that the area in which the channel is formed becomes large. Therefore, the effective W/L ratio becomes large, and a large on-current can be obtained. As a result, a high on/off current ratio is obtained, the withstand voltage between the source and drain is improved, and leakage current is improved. Furthermore, since the electric field is applied not only in the vertical direction but also in the lateral direction, the electric field strength becomes stronger at the edges and has the advantage of having steep subthreshold characteristics. However, this increase in electric field strength causes an increase in leakage current at the ends of the train. For this reason, it is important that the through hole formed on the active layer exists only under the gate electrode and not at the drain end.

〔実施例〕〔Example〕

次に本発明の実施例について説明する。 Next, examples of the present invention will be described.

第１図（ａ）は本発明の一実施例を示す平面模式図、第
１図（ｂ）は第１図（ａ＞のｘ−ｘ’線断面図、第２図
は部分拡大断面図である。FIG. 1(a) is a schematic plan view showing one embodiment of the present invention, FIG. 1(b) is a sectional view taken along line xx' of FIG. 1(a), and FIG. 2 is a partially enlarged sectional view. be.

多結晶シリコン膜からなる半導体活性層２ａには多数の
貫通孔６が設けられている。A large number of through holes 6 are provided in the semiconductor active layer 2a made of a polycrystalline silicon film.

次に、この実施例の製法について説明する。Next, the manufacturing method of this example will be explained.

第３図（ａ）、（ｂ）は本発明の一実施例の製法を説明
するための工程順に配置したトランジスタチップの断面
図である。FIGS. 3(a) and 3(b) are cross-sectional views of transistor chips arranged in the order of steps for explaining a manufacturing method according to an embodiment of the present invention.

第３図（ａ）に示すように、多結晶シリコン膜２を厚さ
０．２μｍに成膜し、幅２００　）ｔ　ｍの短冊型にパ
ターニングする。このとき中央部（長さ２０μｍ）に４
μｍＸ４μｍの四角の貫通孔６を１００個形成する。次
に、第３図（１〕）に示すようにゲート絶縁膜３、ゲー
ト電極４を成膜しケート電極パターンを形成する。この
後ゲート電極をマスクとしてイオン注入法により自己整
合的に高濃度のソース領域２Ｓ、ドレイン領域２ｄを形
成しデバイスを完成させる。アイランドの形状以外は通
常のデバイス作成プロセスと同じで、網状チャネル構造
を有するトランジスタが簡単に得られた。この様な構造
は、第５図に示すスタガー構造においても有効である。As shown in FIG. 3(a), a polycrystalline silicon film 2 is formed to a thickness of 0.2 μm and patterned into a rectangular shape with a width of 200 mm. At this time, 4
100 square through holes 6 of μm×4 μm are formed. Next, as shown in FIG. 3(1), a gate insulating film 3 and a gate electrode 4 are formed to form a gate electrode pattern. Thereafter, a highly doped source region 2S and drain region 2d are formed in a self-aligned manner by ion implantation using the gate electrode as a mask to complete the device. Except for the shape of the island, the process was the same as a normal device fabrication process, and a transistor with a mesh channel structure was easily obtained. Such a structure is also effective in the staggered structure shown in FIG.

Ｗ／Ｌ＝２００／２０の従来例（第６図）のチャネル表
面積は ２００Ｘ２０＝４０００゜ この実施例の貫通孔側壁の面積は４Ｘ４Ｘ１００Ｘ０．
２＝３２０なので、チャネル面積は２４００＋３２０＝
２７４０となる。従って従来例と本実施例では、体積は
４０００　：　２４００、表面積は４０００：２７４０
となる。The channel surface area of the conventional example (FIG. 6) with W/L=200/20 is 200×20=4000°, and the area of the through hole side wall of this embodiment is 4×4×100×0.
2=320, so the channel area is 2400+320=
It becomes 2740. Therefore, in the conventional example and this example, the volume is 4000:2400 and the surface area is 4000:2740.
becomes.

この結果オン電流がチャネル表面積に依存し漏れ電流が
体積に依存すると仮定するとオンオフ比は１．１６倍と
なる。しかし実際には漏れ電流は体積に大きく依存して
いるのでこれ以上のオンオフ比の改善となる。さらに、
貫通孔の上端面部の活性層にかかる電界強度は他に比べ
強いためオン電流はこのような計算値以上に大きくなり
、しかも側壁面は垂直でないため実際の側壁面積も計算
よりは大きくなる。As a result, assuming that the on-current depends on the channel surface area and the leakage current depends on the volume, the on-off ratio becomes 1.16 times. However, in reality, the leakage current largely depends on the volume, so the on-off ratio cannot be further improved. moreover,
Since the electric field strength applied to the active layer at the upper end surface of the through hole is stronger than elsewhere, the on-current is larger than this calculated value, and since the side wall surface is not vertical, the actual side wall area is also larger than the calculated value.

このような結果から上述の計算により導いたような貫通
孔の側壁面積の総計が上面側の面積の少なくとも２０％
を越えるとき、オンオフ比は３倍以上となる。From these results, the total side wall area of the through hole as derived from the above calculation is at least 20% of the top surface area.
When it exceeds , the on-off ratio becomes three times or more.

実際に製作した多結晶薄膜トランジスタのゲート電圧−
ドレイン電流の特性を第３図に示す。実線が本発明によ
る構造のトランジスタで破線で示すのが従来の構造をも
つＩ・ランジスタの特性である。この様に電界効果移動
度、しきい値とも改善されており、オフ電流は減少して
おり漏れ電流については大きく改善されていることがわ
かった。Gate voltage of actually manufactured polycrystalline thin film transistor -
Figure 3 shows the drain current characteristics. The solid line shows the characteristics of the transistor having the structure according to the present invention, and the broken line shows the characteristics of the I transistor having the conventional structure. In this way, it was found that both the field effect mobility and the threshold value were improved, the off-state current was reduced, and the leakage current was greatly improved.

耐圧は３０Ｖ以上あり、３０Ｖの電圧印加時でも漏れ電
流は１Ｏ−１０Ａ以下である。この結果従来のプレーナ
型トランジスタに比べ高耐圧、低漏れ電流のトランジス
タが得られた。The breakdown voltage is 30V or more, and even when a voltage of 30V is applied, the leakage current is 1O-10A or less. As a result, a transistor with higher breakdown voltage and lower leakage current than conventional planar transistors was obtained.

〔発明の効果〕〔Effect of the invention〕

以上詳述したように、本発明により高耐圧で漏れ電流が
少なく高速動作が可能な多結晶薄膜トランジスタを得る
ことができた。この結果回路構成においても高電圧で駆
動でき、回路設計のマージンが高くとれるようになった
。As described in detail above, the present invention makes it possible to obtain a polycrystalline thin film transistor with high breakdown voltage, low leakage current, and high-speed operation. As a result, the circuit configuration can be driven at a high voltage, allowing a higher margin in circuit design.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）は本発明の一実施例を示す平面模式図、第
１図（ｂ）は第１図（ａ’）のｘ−ｘ’線断面図、第２
図は一実施例を示す拡大断面図、第３図（ａ）、（ｂ）
は一実施例の製法を示す工程順に配置した断面図、第４
図は本発明と従来例を比較して示す特性図、第５図（ａ
＞は一実施例の変形を示す平面模式図、第５図（ｂ）は
第５図（ａ）のｘ−ｘ′線断面図、第６図（ａ）は従来
例を示す平面模式図、第６図（ｂ）は第６図（ａ）のｘ
−ｘ’線断面図である。 １・・・ガラス基板（絶縁性基板）、２・・・多結晶シ
リコン膜、２ａ・・・半導体活性層、２ｂ・・・ドレイ
ン−つ 領域、２ｓ・・・ソース領域、３・・・ゲート絶縁膜、
４・・・ゲート電極、５・・・イオン、６・・・貫通孔
、７・・・層間絶縁膜、８ｓ・・・ソース電極、８ｄ・
・・ドレイン電極。FIG. 1(a) is a schematic plan view showing one embodiment of the present invention, FIG. 1(b) is a sectional view taken along line xx' of FIG. 1(a'), and FIG.
The figure is an enlarged sectional view showing one embodiment, FIGS. 3(a) and (b)
4 is a cross-sectional view arranged in the order of steps showing the manufacturing method of one example.
The figure is a characteristic diagram comparing the present invention and the conventional example, and Fig. 5 (a
> is a schematic plan view showing a modification of one embodiment, FIG. 5(b) is a sectional view taken along the line xx′ of FIG. 5(a), and FIG. 6(a) is a schematic plan view showing a conventional example. Figure 6(b) is the x in Figure 6(a)
-x' line sectional view. DESCRIPTION OF SYMBOLS 1...Glass substrate (insulating substrate), 2...Polycrystalline silicon film, 2a...Semiconductor active layer, 2b...Drain region, 2s...Source region, 3...Gate insulating film,
4... Gate electrode, 5... Ion, 6... Through hole, 7... Interlayer insulating film, 8s... Source electrode, 8d...
...Drain electrode.

Claims (1)

【特許請求の範囲】[Claims] 絶縁性基板上に設けられた半導体活性層とそれをおおう
ゲート絶縁膜及びゲート電極を含む多結晶薄膜トランジ
スタに於て、前記半導体活性層に複数の貫通孔を有し、
前記貫通孔の側壁部にもゲート絶縁膜及びゲート電極が
設けられていることを特徴とする多結晶薄膜トランジス
タ。In a polycrystalline thin film transistor including a semiconductor active layer provided on an insulating substrate, a gate insulating film covering the same, and a gate electrode, the semiconductor active layer has a plurality of through holes,
A polycrystalline thin film transistor characterized in that a gate insulating film and a gate electrode are also provided on the side wall of the through hole.
JP2797789A 1989-02-06 1989-02-06 Polycrystalline thin-film transistor Pending JPH02206173A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2797789A JPH02206173A (en) 1989-02-06 1989-02-06 Polycrystalline thin-film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2797789A JPH02206173A (en) 1989-02-06 1989-02-06 Polycrystalline thin-film transistor

Publications (1)

Publication Number Publication Date
JPH02206173A true JPH02206173A (en) 1990-08-15

Family

ID=12235922

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2797789A Pending JPH02206173A (en) 1989-02-06 1989-02-06 Polycrystalline thin-film transistor

Country Status (1)

Country Link
JP (1) JPH02206173A (en)

Cited By (11)

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Publication number Priority date Publication date Assignee Title
EP0735589A2 (en) * 1995-03-30 1996-10-02 Kabushiki Kaisha Toshiba Semiconductor device with a trench gate and method of manufacturing the same
WO1999031719A1 (en) * 1997-12-17 1999-06-24 Matsushita Electric Industrial Co., Ltd. Semiconductor thin film, method of producing the same, apparatus for producing the same, semiconductor device and method of producing the same
WO2008059633A1 (en) * 2006-11-15 2008-05-22 Sharp Kabushiki Kaisha Semiconductor element, method for fabricating the same and display
WO2013155332A1 (en) * 2012-04-13 2013-10-17 SanDisk Technologies, Inc. Thin film transistor
CN103943684A (en) * 2014-03-26 2014-07-23 京东方科技集团股份有限公司 TFT, a manufacturing method of thin film transistor, array substrate and display device
US9165933B2 (en) 2013-03-07 2015-10-20 Sandisk 3D Llc Vertical bit line TFT decoder for high voltage operation
US9240420B2 (en) 2013-09-06 2016-01-19 Sandisk Technologies Inc. 3D non-volatile storage with wide band gap transistor decoder
US20160260840A1 (en) * 2014-10-22 2016-09-08 Boe Technology Group Co., Ltd. Array substrate, manufacturing method thereof and display device
CN106898653A (en) * 2015-12-21 2017-06-27 昆山国显光电有限公司 Drive thin film transistor (TFT), image element circuit and display device
EP3261128A1 (en) * 2016-06-23 2017-12-27 Karlsruher Institut für Technologie Vertical field-effect transistor, a method for its manufacture, its use, and electronics comprising said field-effect transistor
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Cited By (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0735589A2 (en) * 1995-03-30 1996-10-02 Kabushiki Kaisha Toshiba Semiconductor device with a trench gate and method of manufacturing the same
EP0735589A3 (en) * 1995-03-30 1997-10-08 Toshiba Kk Semiconductor device with a trench gate and method of manufacturing the same
WO1999031719A1 (en) * 1997-12-17 1999-06-24 Matsushita Electric Industrial Co., Ltd. Semiconductor thin film, method of producing the same, apparatus for producing the same, semiconductor device and method of producing the same
US6528397B1 (en) 1997-12-17 2003-03-04 Matsushita Electric Industrial Co., Ltd. Semiconductor thin film, method of producing the same, apparatus for producing the same, semiconductor device and method of producing the same
US6806498B2 (en) 1997-12-17 2004-10-19 Matsushita Electric Industrial Co., Ltd. Semiconductor thin film, method and apparatus for producing the same, and semiconductor device and method of producing the same
WO2008059633A1 (en) * 2006-11-15 2008-05-22 Sharp Kabushiki Kaisha Semiconductor element, method for fabricating the same and display
WO2013155332A1 (en) * 2012-04-13 2013-10-17 SanDisk Technologies, Inc. Thin film transistor
US9406781B2 (en) 2012-04-13 2016-08-02 Sandisk Technologies Llc Thin film transistor
US8865535B2 (en) 2012-04-13 2014-10-21 Sandisk Technologies Inc. Fabricating 3D non-volatile storage with transistor decoding structure
US8923048B2 (en) 2012-04-13 2014-12-30 Sandisk Technologies Inc. 3D non-volatile storage with transistor decoding structure
US9123420B2 (en) 2012-04-13 2015-09-01 Sandisk Technologies Inc. 3D non-volatile storage with transistor decoding structure
US9129681B2 (en) 2012-04-13 2015-09-08 Sandisk Technologies Inc. Thin film transistor
US9165933B2 (en) 2013-03-07 2015-10-20 Sandisk 3D Llc Vertical bit line TFT decoder for high voltage operation
US9240420B2 (en) 2013-09-06 2016-01-19 Sandisk Technologies Inc. 3D non-volatile storage with wide band gap transistor decoder
CN103943684A (en) * 2014-03-26 2014-07-23 京东方科技集团股份有限公司 TFT, a manufacturing method of thin film transistor, array substrate and display device
US9620652B2 (en) 2014-03-26 2017-04-11 Boe Technology Group Co., Ltd. TFT and manufacturing method thereof, array substrate
US20160260840A1 (en) * 2014-10-22 2016-09-08 Boe Technology Group Co., Ltd. Array substrate, manufacturing method thereof and display device
US9917198B2 (en) * 2014-10-22 2018-03-13 Boe Technology Group Co., Ltd. Array substrate, manufacturing method thereof and display device
CN106898653A (en) * 2015-12-21 2017-06-27 昆山国显光电有限公司 Drive thin film transistor (TFT), image element circuit and display device
EP3261128A1 (en) * 2016-06-23 2017-12-27 Karlsruher Institut für Technologie Vertical field-effect transistor, a method for its manufacture, its use, and electronics comprising said field-effect transistor
CN110556428A (en) * 2018-06-01 2019-12-10 三星电子株式会社 Thin film transistor, method of manufacturing the same, thin film transistor panel, and electronic device
EP3588596A1 (en) * 2018-06-01 2020-01-01 Samsung Electronics Co., Ltd. Thin film transistor and method of manufacturing the same and thin film transistor panel and electronic device
US11296289B2 (en) 2018-06-01 2022-04-05 Samsung Electronics Co., Ltd. Thin film transistor and method of manufacturing the same and thin film transistor panel and electronic device
CN110556428B (en) * 2018-06-01 2024-05-14 三星电子株式会社 Thin film transistor, method of manufacturing the same, thin film transistor panel, and electronic device

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