JPH05218429A - Polycrystal silicon thin film transistor - Google Patents

Abstract

PURPOSE:To actually show the higher ON-OFF current ratio by a method wherein a source.drain electrode is formed to be overlapped with a gate electrode while offsetting against a contact hole thereby enabling a thin film to be formed. CONSTITUTION:Firstly, a doped polycrystal silicon thin film 201 to be a gate electrode is formed on a glass substrate 101. Next, after patterning into an electrode shape, a gate insulating film 301 is formed on the glass substrate 101 and the gate electrode 201 and then a polycrystal silicon 401 to be an active layer is formed on the gate insulating film 301. Later, another insulating film 501 is formed to make a contact hole 901. Furthermore, a source.drain electrode 601 is formed of double layer film comprising doped polycrystal silicon 601a and aluminum 601b for source.drain region. At this time, the source.drain electrode 601 is to be formed to be overlapped with the gate electrode 201 while offsetting against the contact hole 901.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a polycrystalline silicon thin film transistor having a small leak current on an insulating substrate.

[0002]

2. Description of the Related Art In recent years, a technique for forming a thin film active device on a glass substrate has been aimed at application to various places such as a large area transmissive liquid crystal display and a contact image sensor, and research has been activated. Among them, the polycrystalline silicon thin film transistor has been attracting attention as the most promising device that can be manufactured into an all-thinned device in which peripheral driving circuits are integrated. However, there is a problem in that a thin film transistor using polycrystalline silicon has a larger leak current than a normal MOSFET or an amorphous silicon thin film transistor. A large amount of leak current is a problem not only as a liquid crystal switching device but also as a driver circuit. In particular, since there are many applications for driving devices that require high voltage such as liquid crystal and EL, devices with high breakdown voltage and low leak current are required. However, an ordinary planar type polycrystalline thin film transistor has a problem that a leak current sharply increases especially when a high electric field is applied. In a normal planar structure thin film transistor, when a voltage is applied between the source and drain, a high electric field is applied to the drain end,
The electric field emission current between the band gaps causes a leak current. In the case of crystalline silicon, such a leak current between bands is small, so that it does not usually cause a problem. However, in polycrystalline silicon, many grain boundary traps exist in the band gap, and leak current between the bands is likely to flow therethrough. Therefore, a sudden increase in leak current is observed when a high voltage is applied. Such leak current is essentially unavoidable in polycrystalline silicon. However, since this current depends on the electric field applied to the depletion layer at the drain end, the leak current can be reduced by weakening the electric field applied to the drain end. Therefore, various structures for weakening the electric field at the drain end have been devised. For example, when an offset gate structure is formed in which the gate and the drain are formed to be offset, the electric field applied between the drain and gate is reduced, and the leak current can be suppressed. However, if this offset region becomes long, the on-current will be limited at the same time,
The transistor characteristics deteriorate. Therefore, as shown in FIG. 2, a second electrode 801 is separately provided on this offset region, and a voltage is applied to weakly invert this offset region to suppress the leak current without degrading the on-current characteristics. You can However, this method complicates the structure and requires one more power supply line, so that it is very difficult to apply it to an LCD or the like.

Further, as shown in FIG. 3, it is known that the same effect can be realized even if the second electrode 802 is connected to the drain to have the same potential. In the off state where no voltage is applied to the drain, this transistor has the same offset gate structure as the leak current. on the other hand,
Since a voltage is applied to the drain when the transistor is in the on state, a voltage is applied to the offset region to form a weak inversion region. As a result, the same effect as that of the transistor of FIG. 2 can be obtained in almost the same manufacturing process as that of the conventional transistor.
Low leakage current can be achieved.

[0004]

However, in this method,
The electric field applied to the offset region is applied through the two layers of the gate insulating film 301 and the interlayer insulating film 701. Further, unlike the structure shown in FIG. 2, since the potential of the second electrode 802 is the same as the drain voltage, a sufficient electric field is not applied to the offset region at a low drain voltage, so that a sufficient effect cannot be obtained. It was

[0005]

The gist of the present invention is to provide a gate electrode layer provided on an insulating substrate, an insulating film layer formed on the gate electrode layer, and an insulating film layer formed on the insulating layer. A thin film semiconductor active layer, an insulating film layer formed so as to cover the semiconductor thin film active layer, and a source formed on the insulating film on the semiconductor active layer through a contact hole with the semiconductor thin film active layer. In a staggered thin film transistor including a drain electrode, the gate electrode and the source / drain electrode are formed to overlap each other, and the thin film semiconductor active layer is insulated from the source / drain electrode. The polycrystalline silicon thin film transistor is characterized in that it is connected through a contact hole outside the overlap region.

[0006]

Since the cause of the leak current depends on the voltage applied to the drain end as described in the prior art, the structure for reducing the voltage applied to the drain end is effective for reducing the leak current. Like the transistor of FIG. 2, the second electrode 80
By using 1, the electric field applied to the depletion layer at the drain end is reduced, and a low leak current is achieved. Furthermore, FIG.
It is known that the same effect can be realized even if the second electrode is connected to the drain to have the same potential as shown in FIG. Therefore, the same effect can be realized by using the second electrode below the semiconductor layer. In the case of the stagger structure, source / drain electrodes are formed below the semiconductor layer. By separating the source / drain from the active layer only in the end region of the gate, a second electrode is simultaneously formed by using this electrode layer,
It is possible to easily realize a transistor having the same effect as that of the structure shown in FIG.

As the voltage applied to the offset region is low in the off state and high in the on state, both characteristics are improved, and a transistor having a large on / off current ratio can be realized. In the conventional structure (FIGS. 2 and 3), the insulating film interposed between the offset region and the electrode has two layers of the gate insulating film and the interlayer insulating film, so it is difficult to make it too thin. However, the structure of the present invention In this structure, the insulating film pressure can be controlled independently, and the film thickness can be reduced. Therefore, it is possible to increase the electric field applied to the offset region in the ON state, and it is possible to realize a transistor having a larger ON / OFF current ratio.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the accompanying drawings. 1A and 1B are a structural view and a manufacturing method of a transistor of the present invention. First, a doped polycrystalline silicon thin film 201 serving as a gate electrode was formed on the glass substrate 101. After patterning into an electrode shape, a gate insulating film 301 was formed on the glass substrate 101 and the gate electrode, and polycrystalline silicon 401 to be an active layer was formed on the gate insulating film 301 (FIG. 1).
(A)). After that, an insulating film 501 was formed and a contact hole 901 was formed (FIG. 1B). At this time, it is necessary to form the contact hole so as not to overlap the gate electrode. After that, the doped polycrystalline silicon 601a for the source and drain regions and the aluminum 60
The source / drain electrode 601 is made of a two-layer film made of 1b.
Was formed (FIG. 1 (c)). At this time, the source / drain electrode 601 was formed so as to overlap with the gate electrode 201 and offset from the contact pole. In this case, the gate electrode 201 of the polycrystalline silicon thin film (active layer) 401 and the contact hole 90
The region 100 between 1 and 1 is an offset region and is a region that is weakly inverted by the drain electrode on the upper side of the insulating film. In this way, it becomes possible to fabricate a low leakage current structure transistor in almost the same process as a normal stagger structure transistor fabrication process.

[0009]

As described in detail above, according to the present invention, a low leakage current polycrystalline silicon thin film transistor can be manufactured with good reproducibility by a simple manufacturing process. In this structure, the electric field applied to the offset region from the drain electrode is at least twice as high as that of the conventional structure shown in FIG. 3, and as a result, a structure having an on / off current ratio as compared with the conventional structure was obtained.

[Brief description of drawings]

FIG. 1 is a diagram showing a structure and a manufacturing method showing an embodiment of the present invention.

FIG. 2 is a diagram showing a structure of a conventional polycrystalline thin film transistor.

FIG. 3 is a cross-sectional view of a conventional polycrystalline thin film transistor.

[Explanation of symbols]

101 glass substrate 201 doped polycrystalline silicon thin film (gate electrode) 301 gate insulating film 401 polycrystalline silicon thin film (active layer) 501 insulating film 601 source / drain electrode (Al / doped silicon layer) 701 interlayer insulating film layer 801 second Electrode 802 Second electrode

Claims (1)

[Claims] 1. A gate electrode layer provided on an insulating substrate, an insulating film layer formed on the gate electrode layer, a thin film semiconductor active layer formed on the insulating layer, and the semiconductor thin film active layer. In the staggered thin film transistor comprising an insulating film layer thus formed and a source / drain electrode formed through a contact hole with the semiconductor thin film active layer on the insulating film on the semiconductor active layer, The gate electrode and the source / drain electrode are formed to overlap each other, and the thin film semiconductor active layer is insulated from the source / drain electrode, and is connected through a contact hole outside the gate / drain overlap region. And a polycrystalline silicon thin film transistor.