JP4056988B2 - Buffer circuit and display device - Google Patents

Description

  The invention disclosed in this specification relates to a display device including a semiconductor device using a crystalline thin film semiconductor and a manufacturing method thereof. In particular, the present invention relates to an active matrix liquid crystal display device.

  A liquid crystal display device has a structure in which a liquid crystal layer is sandwiched between a pair of glass substrates, and modulates visible light transmitted through the liquid crystal layer by applying an electric field to the liquid crystal layer to change its optical characteristics. This is an image display device having a function.

  An electric field that changes the optical characteristics of the liquid crystal layer is formed between the pixel electrode and the common electrode, and a desired gradation display can be performed by controlling the amount of charge entering and exiting the pixel electrode in accordance with an image signal. .

  For this reason, recently, active matrix display devices have become representatives of next-generation displays, and research and development have been promoted.

  An active matrix display device is a device in which a thin film transistor (TFT) is arranged in each of millions of pixels arranged in a matrix, and the electric charge entering and exiting each pixel electrode is controlled by the switching function of the TFT. .

  Each pixel TFT (the plurality of pixel TFTs are collectively referred to as an active matrix circuit) is controlled by a circuit TFT disposed in a peripheral drive circuit region formed around the pixel region. In addition, the circuit TFT constitutes various circuits such as a buffer circuit and a shift register circuit by the combination.

  That is, the active matrix display device has a configuration in which pixel TFTs arranged in a matrix in the pixel region and circuit TFTs arranged in the peripheral drive circuit region are all integrated on the same substrate.

  However, the current active matrix type liquid crystal display device has a problem in that display is uneven or striped. In particular, this striped pattern is extremely detrimental to the visual appearance during image display.

  Then, as a result of repeated research on display defects (display defects) that look like striped patterns generated when the display device is driven, the cause of this is the LDD formed in the active layer of the pixel TFT. Found it in the area. The reason is as follows.

  When an active matrix liquid crystal display device is constructed, a crystalline silicon film is generally used for the active layer of the thin film transistor. The crystalline silicon film is generally obtained by crystallizing an amorphous silicon film.

  As the crystallization means, excimer laser annealing, which has the advantage that it can be crystallized at a low temperature, is frequently used. Crystallization by laser annealing is performed by irradiating a laser beam processed into a linear or rectangular shape. In general, it is known that a crystalline silicon film crystallized by laser annealing is difficult to obtain uniform crystallinity.

  In addition, a molten silicon film that is pushed between crystal grains that instantaneously grow crystals becomes a solid phase in a state of rising just like a wave. Then, such a portion is confirmed as a hill-shaped projection (hereinafter, this projection is called a ridge) on the surface of the obtained crystalline silicon film.

  Thus, the crystalline silicon film obtained by laser annealing is in a state where the crystallinity and the surface state are variously different in the substrate plane.

  When forming the LDD region, since the crystalline silicon film is implanted with impurity ions, the crystallinity is disturbed and temporarily becomes amorphous. At this time, the impurity ion concentration varies due to the influence of the difference in crystallinity and the existence probability of ridges.

  As a result, when the impurity ions are activated by laser annealing and the silicon film is recrystallized, the sheet resistance of the LDD region reflects the variation in the impurity ions concentration due to the crystallinity variation and the presence of the ridge. Variations occur.

  That is, the variation due to laser annealing has a great influence on the variation in sheet resistance in the LDD region. The variation in sheet resistance in the LDD region corresponds to the variation in on-current during TFT operation.

  If the variation in on-current is large, charge accumulation on the pixel electrode is insufficient, and a desired image display becomes impossible. In addition, since the variation in on-current affects the amount of charge accumulated in the pixel electrode, the holding voltage level of the pixel electrode changes in accordance with the variation in on-current, causing a problem that a desired gradation display cannot be obtained.

  On the other hand, in circuit TFTs that require high speed operation and high output, deterioration due to heat generation and hot carriers is an important problem, and therefore the LDD region is inevitably an essential configuration.

  Therefore, as described in Japanese Patent Laid-Open No. 1-289917, when the pixel TFT and the circuit TFT are configured with TFTs having the same structure, the pixel TFT is always provided with an LDD region.

  That is, when applying TFTs having the same structure to all the circuits (active matrix circuit and peripheral drive circuit), if the peripheral drive circuit is kept in mind, the LDD region is inevitably configured with emphasis on degradation resistance. This, on the contrary, causes variations in the on-currents of the pixel TFTs and causes display defects such as stripes.

  On the other hand, when the LDD region is arranged in a circuit TFT constituting a buffer circuit that requires a high breakdown voltage of about 16 V, there is a problem that the operation speed is reduced and the circuit characteristics are deteriorated.

An object of the invention disclosed in this specification is to provide a buffer circuit having a high withstand voltage and a high-speed operation and a large on-current characteristic by solving the above-described problems, and a technology for realizing the same.

The buffer circuit disclosed in this specification includes:
A source region exhibiting a first conductivity type, a drain region exhibiting a first conductivity type, and a source region and a drain region existing in an island-shaped semiconductor layer of a thin film transistor. What is intrinsic or first conductivity type? A base region exhibiting a reverse conductivity type, a floating island region exhibiting a first conductivity type, wherein the source region and the drain region are separated by the base region;
The shortest distance from the source region to the drain region via only the base region is larger than the shortest distance from the source region to the drain region via the base region and the floating island region.

That is, the buffer circuit disclosed in this specification is characterized in that the on-current path and the off-current path of the thin film transistor are different.

In the buffer circuit disclosed in this specification, the off-state current of the thin film transistor flows through only the base region, and the on-state current of the thin film transistor flows through the base region and the floating island region.

  Here, FIG. 1 shows a simplified circuit configuration of a substrate (referred to as an active matrix substrate) on the side constituting an integrated circuit of an active matrix liquid crystal display device.

  In FIG. 1, reference numeral 100 denotes an active matrix circuit, which is composed of a plurality of pixel TFTs arranged in a matrix. This pixel TFT is formed so as not to provide the LDD region as described above.

  An area surrounded by a dotted line 101 is a vertical scanning driving circuit area, and an area surrounded by a dotted line 102 is a horizontal scanning driving circuit area. The vertical scan drive circuit area 101 and the horizontal scan drive circuit area 102 are classified into the following circuits for each function.

  First, the vertical scanning drive circuit includes a shift register circuit 103, a level shifter circuit 104, a buffer circuit 105, and a sampling circuit 106. Note that the shift register circuit 103 may be used in combination with a counter circuit and a decoder circuit.

  Here, the level shifter circuit 104 is a circuit that amplifies the drive voltage. For example, since the shift register circuit is driven at 10V at present, the level shifter circuit 104 needs to perform voltage conversion from 10V to 16V in order to drive the buffer circuit 105 at 16V.

  The horizontal scanning drive circuit is composed of a shift register circuit 107, a level shifter circuit 108, and a buffer circuit 109. Of course, the shift register circuit 107 can be combined with a counter circuit and a decoder circuit.

  In recent years, research on system-on-glass that constructs all systems on the same substrate has been rapidly advanced, and in the near future, in addition to the above circuits, a memory circuit 110, a CPU circuit 111, and a digital / analog conversion circuit 112. It is also expected that a control circuit region 113 composed of, for example, will be formed.

  Since these circuits usually require low power, they operate with a drive voltage of about 3 to 10V. If the driving voltage is at this level, it is not necessary to require a particularly high breakdown voltage for the TFT constituting the circuit.

  However, the buffer circuits 105 and 109 need to be driven at a higher voltage (for example, 16 V) than 5 V or more than the above-mentioned circuit due to their functions. Therefore, in that case, the buffer circuits 105 and 109 must be formed of TFTs having a high breakdown voltage.

  However, since the buffer circuits 105 and 109 are required to operate at the same time as the high breakdown voltage, there is a limit to improving the breakdown voltage by arranging a buffer region such as an LDD region or an offset gate region.

  This is because if the LDD region and the offset gate region are arranged, the resistance between the source / drain regions is increased, and the on-current and mobility cannot be increased, resulting in a disadvantageous structure for high-speed operation.

  The buffer circuits 105 and 109 that require such a high breakdown voltage and high-speed operation and a large on-current characteristic have an active layer composed of a source region, a floating island region, a base region, and a drain region invented by the present inventors. Use TFT.

  The TFT having an active layer composed of the source region, the floating island region, the base region, and the drain region is a thin film transistor having characteristics as schematically described below. This description will be given with reference to FIGS.

  This TFT basically has a configuration of an insulated gate type field effect transistor. The path through which the on current flows during the on operation and the path through which the off current flows during the off operation operate differently.

  That is, the moving path of carriers (electrons if N-channel type) during the on operation and the moving path of carriers (holes if N-channel type) during the off operation are different.

  With such a structure, a structure with low off-state current characteristics, high withstand voltage, and high reliability can be obtained. Further, it can be operated at high speed, and a larger on-current can flow.

  A specific configuration example of the TFT having the above configuration will be described with reference to FIGS. FIG. 2A shows an island-shaped semiconductor layer that becomes an active layer of a thin film transistor. A region 200 sandwiched between the source region 201 and the drain region 202 of the island-like semiconductor layer is selectively ion-implanted to give one conductivity (this region is particularly called a floating island region). ) 203 to 205 are formed.

The conductivity of the floating island regions 203 to 205 is equal to the conductivity of the region 201 serving as the source and the region 202 serving as the drain. For example, when an N-channel TFT is manufactured, P + ions are 1 × 10 ¹² to 1 × 10 ¹⁴ atoms. Ions are implanted at a dose of / cm ² , preferably 3 × 10 ^{12 to} 3 × 10 ¹³ atoms / cm ² .

  At this time, the floating island regions 203 to 205 are not necessarily in contact with the outer edge of the island-shaped semiconductor layer as shown in FIG. That is, a state where islands are scattered in the region 200 may be used.

  Further, the region 206 in which no ion implantation is performed in the region 200 is substantially intrinsic, and becomes a region for forming a channel (this region is particularly referred to as a base region).

  An outline of electrical characteristics of a thin film transistor manufactured using an island-shaped semiconductor layer subjected to such ion implantation will be described below. The following description will be made with an N-channel TFT as an example unless otherwise noted.

  In the island-shaped semiconductor layer having the structure illustrated in FIG. 2A, when the thin film transistor is in an off state, the boundary between the base region 206 and the floating island regions 203 to 205 has a high potential barrier (energy barrier), There is little movement. Therefore, the carriers move using only the base region 206 as a route, and a current (off-state current) due to the movement of the carriers is observed along the arrow.

  However, when the thin film transistor is in the on state, the base region 206 is inverted and the boundary between the floating island regions 203 to 205 is in a very small potential barrier state. As a result, carriers easily move between the base region 206 and the floating island regions 203 to 205, and a current (on-current) due to carrier movement is observed along the path indicated by the arrow in FIG. Is done.

  The manner in which the potential barrier changes between the off state and the on state of the thin film transistor in this way will be schematically described with reference to FIG. In FIG. 3, Vg represents a gate voltage (Vg> 0), Ec represents a conduction band, Ev represents a valence band, and Ef represents a Fermi level.

  First, when the thin film transistor is in an off state (a state where a negative voltage is applied to the gate), the base region 206 is in a band state as shown in FIG. That is, since holes that are minority carriers gather on the semiconductor surface and electrons are removed, the holes move slightly between the source and drain. This is observed as an off-current.

  On the other hand, since the floating island regions 203 to 205 are implanted with P + ions, the Fermi level Ef is pushed closer to the conduction band Ec. At this time, the floating island regions 203 to 205 are in a band state as shown in FIG.

  As shown in FIG. 3B, in the floating island regions 203 to 205 which are N-type semiconductor layers, even if a negative voltage is applied to the gate, the energy band is bent only slightly.

  Therefore, the energy difference between the energy of the valence band on the semiconductor surface in FIG. 3A and the energy of the valence band on the semiconductor surface in FIG. 3B corresponds to the potential barrier. Therefore, holes do not reciprocate between the base region 206 and the floating island regions 203 to 205.

  Next, when the thin film transistor is in an on state (a state where a positive voltage is applied to the gate), the base region 206 is in a band state as shown in FIG. That is, electrons, which are majority carriers, are accumulated on the semiconductor surface, so that electrons move between the source and drain.

  At this time, the floating island regions 203 to 205 are in a band state as shown in FIG. As shown in FIG. 3D, as in the case where a negative voltage is applied to the gate described above, in the floating island regions 203 to 205 that are N-type semiconductor layers, even if a positive voltage is applied to the gate, the energy band is almost constant. Unyielding.

  However, since the Fermi level Ef is originally pushed up near the conduction band Ec in FIG. 3D, a large number of electrons are always present in the conduction band.

  Therefore, when a positive voltage is applied to the gate, the base region 206 and the floating island regions 203 to 205 are both in a band state in which electrons easily move, so the potential barrier at the boundary between the base region 206 and the floating island regions 203 to 205 is Can be ignored.

  As described above, in the off state, only the base region 206 is a carrier movement path, and in the on state, the base area 206 and the floating island areas 203 to 205 are carrier movement paths. This situation is summarized below using a simplified model.

  FIG. 4A shows the same semiconductor layer as FIG. A gate electrode 400 is shown above the base region through a gate insulating film.

  When the thin film transistor is in the on state, that is, when a positive voltage is applied to the gate electrode, an on current flows in the direction of the solid line indicated by A-A ′ in FIG. At this time, the cross section along A-A ′ is the structure of FIG. 4B, and the circuit diagram is as shown in FIG. Note that an inversion layer 402 is formed in the base region under the gate electrode 401 in FIG.

  Further, when the thin film transistor is in an off state, that is, when a negative voltage is applied to the gate electrode, an off current flows along a broken line indicated by B-B ′ illustrated in FIG. At this time, the cross section taken along the line B-B 'is the structure shown in FIG. 4D, and the circuit diagram is as shown in FIG. That is, it can be considered that a long base region exists under one long gate electrode 403 and a transistor having a substantially long channel length is formed.

  Therefore, when the thin film transistor is in the on state, carriers move through the shortest distance, the channel length is substantially short, and the channel width is widened, so that the observed on current has a large value.

  On the other hand, when the thin film transistor is in an off state, it can be considered that carriers move only in the base region, the channel length is substantially long, and the channel width is narrowed. That is, the resistance component of the channel region is substantially increased, and the observed off-current is a small value.

  With the structure as described above, the effect of significantly reducing the off-current and increasing the on-current, that is, improving the on / off ratio, can be obtained without changing the occupied area of the island-shaped semiconductor layer. An active layer having performance can be formed.

  In addition, it is important to improve the breakdown voltage and the reliability that the path of carriers conducted through the side surface of the region 200 in FIG.

  On the side surface of the active layer, there are high-density traps formed at the time of patterning, and a carrier movement path through the trap is easily formed. In particular, the cause of the off-current during the off-operation is largely due to carrier movement via the side surface of the active layer. Further, the carrier movement path on the side surface of the active layer is unstable and causes a decrease in TFT reliability.

  Therefore, setting the carrier movement path in the off operation as shown by the arrow in FIG. 2A is useful for increasing the withstand voltage during the off operation and providing high reliability.

  In addition, since the thin film transistor as described above has high pressure resistance and deterioration resistance, sufficient reliability can be obtained without providing a buffer region such as an LDD region.

According to the present invention, by configuring the buffer circuit with the TFT described with reference to FIGS. 2 to 4, it is possible to configure a highly reliable circuit that can operate at high speed and has high withstand voltage. Become.

As described above, the high breakdown voltage and high speed operation by utilizing the present invention, it is possible to realize a buffer circuit is further required a large on-current characteristic. Therefore, the present invention is very useful industrially.

  In FIG. 1, the pixel TFT disposed in the active matrix circuit 100 is configured not to have an LDD region.

  Among the various circuits constituting the peripheral drive circuits 101 and 102, the buffer circuits 105 and 109 that require high withstand voltage characteristics and high operating speed have higher withstand voltage and higher reliability than conventional TFTs. The TFT described with reference to FIG.

  Therefore, a normal thin film transistor in which an LDD region is arranged and a TFT described with reference to FIGS. 2 to 4 are arranged in the peripheral drive circuit. The two types of thin film transistors have different structures and operating principles.

In the active matrix circuit, a normal thin film transistor without an LDD region is disposed. This thin film transistor (pixel TFT) is different from both of the two types of TFTs arranged in the peripheral drive circuit due to the presence or absence of the LDD region or the difference in operating principle.
By adopting a configuration in which the LDD region is not disposed in the pixel TFT, a display device that does not cause an image display defect recognized as a striped pattern can be manufactured.

  In addition, by configuring the buffer circuit with the TFTs described with reference to FIGS. 2 to 4, a high-speed operation and a high withstand voltage buffer circuit can be formed.

  That is, according to the present invention, a display device having high definition and high reliability can be manufactured.

  The details of the present invention configured as described above will be described with reference to the embodiments described below.

[Example 1]
In this embodiment, a CMOS structure in which an N-channel TFT and a P-channel TFT are complementarily combined, a TFT constituting a buffer circuit, and a multi-gate TFT having a plurality of gate electrodes are formed on the same substrate. Each manufacturing process in the case of performing is shown.

  At this time, in this embodiment, a part of the anodizing wiring is divided, and the electrical connection with a part of the gate electrode is selectively disconnected, and only the gate electrode electrically connected to the anodizing wiring is used. An example of anodizing is shown. The description will be given with reference to FIG.

  First, in FIG. 5A, an insulating substrate, typically a substrate 501 in which an insulating film such as a silicon oxide film is formed over a glass substrate, is prepared. Then, an amorphous silicon film (not shown) is formed thereon to a thickness of 200 to 1000 mm by plasma CVD or low pressure thermal CVD.

  The amorphous silicon film (not shown) is crystallized by an appropriate crystallization method to obtain a crystalline silicon film (not shown). As a crystallization method, heat treatment may be performed at a temperature of 500 to 700 ° C., typically 600 ° C. for about 1 to 24 hours, or annealing with an excimer laser of KrF or XeCl may be performed. It is also effective to use both means together.

  In addition, it is preferable to introduce a metal element that promotes crystallization at the time of crystallization because excellent crystallinity can be obtained at a low temperature in a short time.

  Next, the obtained crystalline silicon film (not shown) is patterned to form active layers 502 to 505.

  Reference numeral 502 denotes an active layer for forming a P-channel TFT and 503 for an N-channel TFT in a CMOS structure, and forms a peripheral drive circuit such as a shift register circuit.

  Reference numeral 504 denotes an active layer for forming the TFT described with reference to FIGS. 2 to 4, and forms a buffer circuit.

  Reference numeral 505 denotes an active layer for forming a multigate TFT, which forms a pixel TFT arranged in an active matrix circuit.

When each of the active layers 502 to 505 is formed, a gate insulating film 506 made of a silicon oxide film is formed to a thickness of 1200 mm so as to cover it. As the gate insulating film 506, an insulating film such as a silicon nitride film or a silicon oxynitride film indicated by SiO _X N _Y can be used.

  Next, an aluminum film containing 0.2 wt% scandium is formed to a thickness of 2500 to 4000 mm (not shown). Scandium has the effect of suppressing the occurrence of protrusions in the form of stabs such as hillocks and whiskers in the subsequent heat treatment step.

  Next, an extremely thin anodic oxide film (not shown) is formed on the surface of the aluminum film. This anodic oxide film is obtained by neutralizing an ethylene glycol solution containing 3% tartaric acid with aqueous ammonia as an electrolytic solution. That is, in this electrolytic solution, anodization is performed using an aluminum film as an anode and platinum as a cathode.

  The anodic oxide film formed in this step has a dense film quality and functions to improve adhesion to a resist mask formed when patterning the aluminum film. The film thickness of the anodic oxide film (not shown) is about 100 mm. The film thickness can be controlled by the applied voltage.

  Next, an aluminum film (not shown) is patterned by using the resist mask 507 to form aluminum film patterns 508 to 511 to be a base of the gate electrode.

  In addition, when the pattern indicated by 510 is viewed from the top, it has a shape in which a part of one gate electrode is cut out like the gate electrode 400 of FIG. Therefore, in the cross-sectional view, it seems that it is divided into three gate electrodes, but all are part of one gate electrode.

  In addition, the cross-sectional view of the aluminum pattern indicated by reference numeral 511 seems to be divided as shown in FIG. 5A. In general, a multigate type TFT has an active layer formed in a zigzag winding with a single gate. This is because the structure is such that the line (substantially the gate electrode) crosses.

  Note that the drawings of the multigate TFT shown in FIGS. 5 and 6 express that this TFT can be regarded as a structure in which a plurality of TFTs are equivalently connected in series.

  Reference numeral 512 denotes a pattern that becomes a base of a capacitance line that forms an auxiliary capacitance between the active layer 505 and the gate insulating film 506 later.

  Although not shown, anodizing wiring is formed of the same material other than the aluminum pattern. This anodic oxidation wiring capacitance is electrically connected to all the gate electrodes, gate lines and capacitance lines.

  As described above, patterning is performed by patterning an aluminum film (not shown). In the present invention, it is important at this time to divide a part of the anodizing wiring at the same time as the pattern formation.

  That is, a part of the anodic oxidation wiring is divided so that only a specific aluminum pattern is electrically separated. In this embodiment, the aluminum patterns 509, 510, and 511 are separated from an anodic oxidation wiring (not shown).

  In this way, the state shown in FIG. In the state shown in FIG. 5A, only the aluminum film patterns 508 and 509 are connected to the anodizing wiring.

  Next, anodization is performed again using the aluminum film patterns 508 and 509 as anodes. Here, a 3% oxalic acid aqueous solution is used as an electrolytic solution for anodization.

  In this anodic oxidation process, since the resist mask 507 is present, the anodic oxidation proceeds only on the side surfaces of the aluminum patterns 508 and 509. Accordingly, an anodic oxide film is formed as indicated by 513 and 514 in FIG.

  Further, the anodic oxide films 513 and 514 formed in this step have a porous shape, and the growth distance can be increased to several μm. In this embodiment, the thickness of the porous anodic oxide films 513 and 514 is 7000 mm. The thickness of the anodic oxide films 513 and 514 can be controlled by the anodic oxidation time.

  At this time, since the aluminum patterns 509, 510, and 511 are separated from the anodizing wiring by the above-described dividing step, anodization is not performed. That is, as shown in FIG. 5B, a porous anodic oxide film is not formed.

  Next, after the formation of the porous anodic oxide films 513 and 514 shown in FIG. 5B, the resist mask 507 is removed. Then, dense anodic oxide films 515 and 516 are formed by performing anodic oxidation again. This anodic oxidation step is performed under the same conditions as those for forming the above-described dense anodic oxide film.

  However, the film thickness to be formed is 500 to 2000 mm. In this step, since the electrolytic solution enters the porous anodic oxide films 513 and 514, dense and strong anodic oxide films 515 and 516 are formed as shown in FIG.

  When the thickness of the anodic oxide film is increased to 1500 mm or more, an offset gate region can be formed in a subsequent impurity ion implantation step.

  The dense anodic oxide films 515 and 516 function to suppress generation of hillocks on the surfaces of the gate electrodes 517 and 518 in a later step.

  Note that the patterns 510 to 512 on the other aluminum film separated from the anodizing wiring are naturally not formed in this process. Therefore, the aluminum patterns 510 and 511 later become gate electrodes as they are, and 512 becomes a capacitance line.

  Next, impurity ions are implanted to form source / drain regions in this state. First, P (phosphorus) ions are implanted in order to manufacture an N-channel thin film transistor.

This ion implantation is performed by an ion implantation method (ion doping method) at a high dose of 0.2 to 5 × 10 ¹⁵ / cm ² , preferably 1 to 2 × 10 ¹⁵ / cm ² . In this step, regions 519 to 531 to which impurities are added at a high concentration are formed.

  At this time, reference numerals 519 and 520 denote areas which will be called contact pads later, and reference numerals 521 and 522 denote a drain area and a source area of an N-channel TFT constituting a CMOS structure, respectively.

  Reference numerals 523 and 526 denote TFT source and drain regions described with reference to FIGS. 2 to 4, respectively. Reference numerals 524 and 525 denote floating island regions.

  Reference numerals 527 and 531 denote a source region and a drain region of the multigate TFT, and reference numerals 528, 529 and 530 denote conductive regions which function like wirings connecting channels of the active layer.

  Thus, a state in which the high concentration impurity regions 519 to 531 are formed as shown in FIG. Next, the porous anodic oxide films 513 and 514 are selectively removed using a mixed acid in which acetic acid, phosphoric acid and nitric acid are mixed, and then a resist mask 532 is formed on the element constituting the P-channel TFT. Then, ion implantation of P ions is performed again.

This ion implantation is performed with a lower dose than in the previous formation of the source / drain regions. In this embodiment, the ion implantation is performed at a low dose of 0.1 to 5 × 10 ¹⁴ / cm ² , preferably 0.3 to 1 × 10 ¹⁴ / cm ² .

  Then, low-concentration impurity regions 533 and 534 having a lower impurity concentration than the high-concentration impurity regions 519 to 531 are formed in the N-channel TFT constituting the CMOS structure. Further, a channel region 535 is formed in a self-aligning manner. Note that the low-concentration impurity region 533 disposed between the channel region 535 and the drain region 521 is a region generally referred to as an LDD region. (Fig. 5 (D))

  Next, as shown in FIG. 6A, a resist mask 536 is provided on an element constituting the N-channel TFT (in this embodiment, only one TFT constituting the CMOS structure is P-type), Impurity ions that impart P-type conductivity are implanted. At this time, since it is necessary to invert the high-concentration impurity regions 519 and 520 in FIG. 5C from N-type to P-type, ion implantation is performed with a dose amount higher than the first P ion implantation.

In this embodiment, implantation of B (boron) ions as impurity ions imparting P-type conductivity is performed at a high dose of 0.1 to 2.5 × 10 ¹⁶ / cm ² , preferably 0.5 to 1 × 10 ¹⁶ / cm ^2. Performed by ion implantation.

  By the impurity ion (B ion) implantation step, P-type regions 537 and 538, stronger P-type regions 539 and 540, and a channel region 541 are formed in the active layer constituting the P-channel TFT. Is done.

  Note that the present inventors have defined the regions 537 and 538 as pads (referred to as contact pads) for making electrical contact with the source / drain electrodes that will be formed later. Further, the region 539 is defined as a source region and 540 is defined as a drain region.

  As described above, the source region 539 and the drain region 540 are formed by implanting only B ions into a substantially intrinsic region. Therefore, since other ions are not mixed, the impurity concentration can be controlled and a PI junction with good matching can be realized. Moreover, the crystallinity disturbance due to ion implantation can be relatively small.

  Therefore, in the structure of this embodiment, the LDD region is not arranged for the P-channel TFT. However, since the P-channel TFT itself is excellent in deterioration resistance, there is no problem even if the LDD region is not provided.

  Further, for example, an element on the P-channel TFT side is hidden with a resist mask at the stage of ion implantation in FIG. 5C, and an N-channel TFT is completed according to the process described in FIGS. 5C and 5D. Thereafter, a P-channel TFT can be formed in the same process by hiding the element on the N-channel TFT side with a resist mask.

  Then, although the number of processes is somewhat increased, LDD regions can be formed in both the N-channel TFT and the P-channel TFT.

  Next, a region 542 is a TFT base region described with reference to FIGS. 2 to 4 and substantially functions as a channel region. The base region 542 seems to be divided by the floating island regions 524 and 525, but is formed in a self-aligned manner under the gate electrode 510 and thus is connected together as in the base region 206 of FIG.

  A region indicated by 543 to 545 is a channel region of the multigate TFT, and is formed in a self-aligned manner by the gate electrode 511.

  Note that the region indicated by 546 is a substantially intrinsic region, but when the TFT is actually driven, a fixed voltage is always applied to the capacitor line 512, so that the channel is always on. It will be in the state which has electroconductivity.

  Further, after the impurity ion implantation step, laser light, infrared light, or ultraviolet light irradiation is performed to anneal the region where the ions have been implanted. The damage received by the active layer can be recovered simultaneously with the activation of the impurity ions implanted by this annealing.

  When the state shown in FIG. 6A is obtained as described above, the first interlayer insulating film 547 is formed to a thickness of 3000 mm. As the first interlayer insulating film 547, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like can be used.

  Next, contact holes are formed in the first interlayer insulating film 547 to form source electrodes 548 to 551 and drain electrodes 552 to 554. Note that, as indicated by 552, the drain electrodes of the N-channel TFT and the P-channel TFT constituting the CMOS structure are connected.

  Next, a second interlayer insulating film 555 is formed to a thickness of 0.3 to 5 μm. As the second interlayer insulating film 555, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an organic resin material, or the like can be used. (Fig. 6 (B))

  In particular, when an organic resin material typified by polyimide or the like is used, a film thickness can be easily obtained, and formation of parasitic capacitance through the second interlayer insulating film 555 is problematic because of a low relative dielectric constant. There can be no level.

  In addition, since the organic resin material can easily increase the film thickness, it has not only a great effect as a planarizing film but also an advantage that the throughput of the manufacturing process is improved.

  Next, a contact hole is formed in the second interlayer insulating film 555, and a pixel electrode 556 made of a transparent conductive film is formed thereon. In this embodiment, a 1000-thick ITO (Indium Tin Oxide) film is used as the pixel electrode 556.

  Note that the pixel electrode 556 is formed so as to be electrically connected to the drain electrode 554 of the multigate TFT. The contact resistance between the pixel electrode (ITO film) 556 and the drain region (silicon film) 531 is non-linear.

  Therefore, when the structure is electrically connected to the drain region 531 through the drain electrode 554 as in this embodiment, a good ohmic contact without contact failure can be obtained.

  In addition, it is an advantage that only the second interlayer insulating film 555 needs to be removed by etching when forming the contact hole. Then, the manufacturing process can be facilitated rather than connecting directly to the drain region 531 and the contact hole can be formed without breaking the shape.

  As described above, a CMOS structure in which an N-channel TFT and a P-channel TFT are complementarily combined as shown in FIG. 6C and a buffer circuit are described with reference to FIGS. A TFT and a multigate TFT (a pixel TFT in this embodiment) having a plurality of gate electrodes can be formed on the same substrate.

  The CMOS structure as shown in FIG. 6C is mainly used for a low voltage driving circuit such as a shift register circuit, a level shifter circuit, a sampling circuit, a memory circuit, a CPU circuit and a digital / analog conversion circuit.

  Also, the TFT described with reference to FIGS. 2 to 4 is exclusively used for a high voltage driving circuit that requires high withstand voltage performance such as a buffer circuit. In FIG. 6C, only the N-channel TFT is shown, but when actually configuring a circuit, it is also possible to form a CMOS structure by simultaneously forming a P-channel TFT. Needless to say.

  In addition, a multigate type TFT without an LDD region is exclusively used as a pixel TFT constituting an active matrix circuit. The absence of the LDD region is a measure for preventing display defects that appear to be a striped pattern, and the use of a multigate TFT is a measure for increasing the breakdown voltage.

[Example 2]
In this embodiment, an example in which means different from that in Embodiment 1 is used as means for selectively forming an LDD region will be described. Specifically, this is an example in which a porous anodic oxide film is once formed on all aluminum film side faces and then selectively removed.

  Since the basic description is the same as that of the first embodiment, only the changes will be described here with reference to FIG.

  First, the same state as that shown in FIG. At this time, it is desirable to form all the aluminum patterns slightly thicker than the design dimensions of the gate electrode in consideration of the fact that the thickness of the porous anodic oxide film is later thinned inward. .

  Next, anodization is performed under the same conditions as the second anodization in Example 1, and porous anodic oxide films 701 to 705 are formed on the side surfaces of all the aluminum patterns. (Fig. 7 (A))

  Next, the resist mask 507 arranged on the aluminum pattern is removed, and a dense anodic oxide film is formed again. In this embodiment, unlike the first embodiment, the anodizing wiring is not divided, so that dense anodic oxide films 706 to 710 are formed on all the aluminum patterns. (Fig. 7 (B))

  Next, a resist mask 711 is formed again to cover the N-channel TFT and the P-channel TFT constituting the CMOS structure. (Fig. 7 (C))

  In this state, the porous anodic oxide films 708 to 710 are removed using a mixed acid obtained by mixing acetic acid, phosphoric acid and nitric acid.

  Through the above process, a structure as shown in FIG. 7D is obtained. This structure is basically the same as that shown in FIG. 5C (differing only in that dense anodic oxide films 708 to 710 are formed).

  Accordingly, in the subsequent steps, the state shown in FIG. 6C is basically obtained according to the first embodiment. However, this embodiment is different from the first embodiment in that dense anodic oxide films 706 to 710 are formed on all gate electrodes, gate wirings, and capacitor lines.

  That is, according to the present embodiment, it is possible to effectively suppress hillocks and whiskers generated in the gate electrode, the gate wiring, etc., and to prevent a short circuit between the wirings caused by these protrusions. it can.

Example 3
In the first embodiment, the active matrix circuit, that is, the example in which all of the pixel TFTs are configured by N-channel TFTs is shown, but the pixel TFTs may be configured by P-channel TFTs.

  In order to make the pixel TFT a P-channel TFT, a resist mask 536 is not provided in a region to be the pixel TFT in the process shown in FIG. 6A, and B ions may be implanted.

  When the pixel TFT is a P-channel TFT, the deterioration resistance of the pixel TFT is improved, so that a highly reliable image display region can be configured.

Example 4
In the first embodiment, an example in which the TFT described with reference to FIGS. 2 to 4 constituting the buffer circuit is configured with an N-channel TFT is shown, but it may be configured with a P-channel TFT. It is also possible to form a CMOS structure by forming both an N channel type and a P channel type.

  In order to configure the buffer circuit with a P-channel TFT, a resist mask 536 is not disposed in a region to be a TFT constituting the buffer circuit in the step shown in FIG. 6A, and B ions may be implanted. .

  When the buffer circuit is composed of a P-channel TFT, the deterioration resistance is further improved in addition to the conventional high voltage resistance, so that a highly reliable image display region can be formed.

Example 5
As described above, the reason why the LDD region is not provided for the pixel TFT constituting the active matrix circuit in the present invention is that the variation in on-current due to the LDD region causes a display defect that looks like a striped pattern. .

  However, even if the LDT region is not arranged in the pixel TFT according to the present invention, for example, if the conductivity of the source region and the drain region varies, the on-current also varies due to the influence.

  Therefore, the sheet resistance of the N-type or P-type conductive layer forming the source region and the drain region must be sufficiently small to the extent that the influence of the variation does not adversely affect the gradation display.

According to the analysis results of the present inventors, when the sheet resistance of the source region and the drain region is 1 × 10 ³ Ω / □ or less, preferably 0.5 × 10 ³ Ω / □ or less, a display device that does not cause the above problem Can be configured.

  When impurity ion implantation was performed under the conditions shown in Example 1, the sheet resistance of both the N-type and P-type source region and drain region was within the range of 300 to 500 Ω / □. .

Example 6
In the first or second embodiment, as shown in FIG. 6C, the TFT described with reference to FIGS. 2 to 4 has a configuration in which the low concentration impurity region is not disposed, but the low concentration impurity region is disposed. It is also possible to adopt the configuration described above.

  In the case where a low concentration impurity region is selectively provided in accordance with the method described in the first embodiment, an aluminum pattern that does not form a porous anodic oxide film will be described with reference to FIGS. It is sufficient that the aluminum pattern that becomes the gate electrode of the TFT is not cut off.

  By doing so, a porous anodic oxide film is formed at the time of the second anodic oxidation, so that the low-concentration impurity region can be arranged by performing the same ion implantation process as in the first embodiment.

  In the case where a low concentration impurity region is selectively provided according to the method described in Embodiment 2, the TFT described with reference to FIGS. 2 to 4 may be covered with a resist mask 712 in the process of FIG. good.

  By doing so, the porous anodic oxide film 703 can be left, so that the low-concentration impurity region can be disposed by performing the same ion implantation process as in the first embodiment.

  FIG. 8 shows the configuration of the active layer when the low concentration impurity region is arranged in the TFT described with reference to FIGS.

  In FIG. 8, a source region 802, floating island regions 803 to 805, and a drain region 806 are formed in the active layer 801 by implanting impurity ions of the same concentration. Further, a base region 807 is formed in a region which is shielded by a gate electrode (not shown) and is not implanted with impurity ions.

  Then, low concentration impurity regions 808 to 812 are formed around the floating island regions 803 to 805 by implanting impurity ions at a low concentration by the above two methods.

  The TFT described with reference to FIGS. 2 to 4 has a PN junction between the floating island regions 803 to 805 and the base region (in this case, the opposite conductivity type to that of the floating island region) during the off operation. Is formed. When the semiconductor film is in a polycrystalline state or a microcrystalline state, deterioration due to a strong electric field or a change in the bonding state is likely to occur at this bonding portion.

  In such a case, the low-concentration impurity regions 808 to 812 shown in FIG. 8 are significant in that the strong electric field formed in the PN junction portion can be relaxed.

  The low-concentration impurity region 812 serves as an LDD region that relieves a strong electric field formed between the conductive region 813 and the drain 806 during the on operation. Here, the conductive region 812 means a region composed of floating island regions 803 to 805 and an inverted base region 807.

  In addition to the above method, the LDD region can be formed by other means. For example, after forming an island-shaped semiconductor layer that constitutes the active layer, impurity ions are selectively implanted into a desired position by hiding a portion other than a necessary portion with a resist mask or the like. However, the dose amount of impurity ions is lower than that of a source / drain region to be formed later.

  As described above, when a thin film transistor having an active layer as shown in FIG. 8 is formed according to this embodiment and a buffer circuit is formed using the thin film transistor, a highly reliable circuit can be formed.

Example 7
In Example 1, the metal element used as a catalyst for promoting crystallization when crystallizing the amorphous silicon film may be adversely affected by remaining in the crystallized silicon film, which is preferable. It is not a thing.

  According to the study by the present inventors, there is a possibility that when a metal element is segregated, it becomes a current flow path and the off-current increases.

  In particular, an increase in off-current is a fatal problem for pixel TFTs that require a low off-current, which affects the charge retention time of the pixel electrode and thus the image display capability of the liquid crystal display device.

  Therefore, in this embodiment, when adopting a crystallization method in which a metal element for promoting crystallization is introduced into an amorphous silicon film, a metal element is not introduced into an active matrix circuit, and a metal element is introduced into a peripheral drive circuit. An example of introduction is shown.

  Details of a method for forming a crystalline silicon film using a metal element that promotes crystallization are described in Japanese Patent Laid-Open Nos. 6-232509 and 7-321339 by the present inventors. The description will be omitted. According to the publication, it is preferable to use Ni (nickel) element as the metal element.

  In this embodiment, when the amorphous silicon film is formed according to the same process as in the first embodiment, a silicon oxide film is deposited to a thickness of 500 to 1000 mm. This silicon oxide film functions as a mask material for selectively introducing a metal element (in this embodiment, nickel is taken as an example).

  After the silicon oxide film is deposited, a window is selectively provided only in a region constituting the peripheral drive circuit, and nickel element is introduced thereon. The nickel element is introduced by spin-coating a nickel salt solution to form a water film containing nickel element on the surface of the amorphous silicon film.

  When heat treatment is performed at 600 ° C. for about 4 hours in this state, nickel element is introduced only in the region where the window is opened, and crystallization proceeds only in that region. That is, the region that becomes the peripheral drive circuit is a crystalline silicon film, and the region that becomes the active matrix circuit remains an amorphous silicon film.

  Thereafter, the mask material made of the silicon oxide film is removed, and the entire substrate is subjected to laser annealing with an excimer laser, thereby simultaneously improving the crystallization of the crystalline silicon film and the crystallization of the amorphous silicon film. .

  Through the above process, the peripheral drive circuit can be composed of a crystalline silicon film containing nickel element, and the active matrix circuit can be composed of a crystalline silicon film not containing nickel element.

  With the structure shown in this embodiment, the active layer of the pixel TFT constituting the active matrix circuit does not contain a metal element such as nickel. Accordingly, since a pixel TFT having a low off-state current characteristic can be formed, a display device having high image display capability can be manufactured.

Example 8
In this embodiment, an example in which a silicon gate type TFT using a crystalline silicon film imparted with conductivity is used as a gate electrode is shown. In the silicon gate type TFT, the method of forming the LDD region is different from that in the first and second embodiments, and therefore, description will be made with attention to that. The description will be given with reference to FIG.

  First, in FIG. 9, a buffer layer 902 made of a silicon oxide film is formed on a glass substrate 901 with a thickness of 2000 mm, and an active layer 903 of a TFT constituting a peripheral drive circuit and an active matrix circuit are formed thereon. The active layer 904 of the TFT to be formed is formed. (Fig. 9 (A))

  Since the means for forming the active layer has already been described in Example 1, the description thereof is omitted here.

  Next, a gate insulating film 905 made of a silicon oxide film is formed to a thickness of 1200 mm so as to cover the active layers 903 and 904.

  Then, a crystalline silicon film having conductivity (not shown) is formed on the gate insulating film 905 and patterned to form gate electrodes 906 and 907. A crystalline silicon film imparted with conductivity (not shown) may be formed by implanting impurity ions imparting one conductivity after forming an intrinsic crystalline silicon film.

  When the gate electrodes 906 and 907 are thus obtained, impurity ions are implanted to form source regions 908 and 911 and drain regions 910 and 913. For example, when an N-channel TFT is manufactured, P ions may be used as impurity ions.

  Immediately below the gate electrodes 906 and 907, impurity ions are not implanted, and substantially intrinsic regions 909 and 912 are formed in a self-aligned manner. Note that part of the region 909 and the region 912 will be channel formation regions later.

  In this way, the state of FIG. 9B is obtained. When the state of FIG. 9B is obtained, the resist mask (not shown) used for forming the gate electrodes 906 and 907 is removed, and resist masks 914 and 915 are formed again. The feature of this embodiment is that the resist mask 914 is formed so as to cover only the gate electrode 906, and the resist mask 915 is formed so as to cover the entire element on the active matrix circuit side.

  In this state, isotropic etching of the gate electrode 906 is performed by a dry etching method using a fluorine-based gas. At this time, since the resist mask 914 exists on the upper surface of the gate electrode 906, the etching proceeds in the direction indicated by the arrow in FIG.

  Next, when the etching of the gate electrode 906 is completed, the resist masks 914 and 915 are removed, and impurity ions are implanted again. In this impurity ion implantation step, the same impurity ions as in the previous impurity ion implantation step are performed at a dose lower than the previous time. (Figure 9 (D))

  Thus, low concentration impurity regions into which impurity ions are implanted at a lower concentration than the source region 908 and the drain region 910 are formed in the regions indicated by 916 and 917. Note that a region 918 sandwiched between the low-concentration impurity regions 916 and 917 serves as a channel formation region.

  At this time, the low concentration impurity region 917 disposed between the channel formation region 918 and the drain region 910 is generally called an LDD region. The LDD region 917 has an effect of relaxing a strong electric field applied to the channel / drain junction.

  If the second impurity ion implantation step is not performed, the regions 916 and 917 remain substantially intrinsic and can be offset gate regions to which no voltage is applied by the gate electrode 906.

  Even when the regions 916 and 917 are offset gate regions, the regions 916 and 917 function as simple resistance components, and have an effect of reducing a strong electric field applied to the channel / drain junction.

  As described above, the state shown in FIG. 9D is obtained. Since the subsequent steps are the same as those in the first embodiment, no description will be given. According to this embodiment, it is possible to selectively dispose the LDD region when manufacturing a silicon gate type TFT, and the present invention can be carried out.

Example 9
In the first and second embodiments, an example in which a planar TFT is formed as a thin film transistor has been described. However, the present invention can be implemented using another type of TFT, for example, an inverted staggered TFT.

  For example, even when a TFT having a CMOS structure as shown in FIG. 6C is formed or when the TFT described with reference to FIGS. 2 to 4 is formed, an inverted stagger type TFT is basically formed by the same means. Can be configured.

  Therefore, in this embodiment, an example of a manufacturing process of an inverted staggered TFT having a general structure will be described by distinguishing between an active matrix circuit and a peripheral driver circuit. The description will be given with reference to FIG. The details of the manufacturing process of the inverted stagger type TFT are described in Japanese Patent Application Laid-Open No. 5-275252.

  First, in FIG. 10A, reference numeral 11 denotes a substrate having an insulating surface (for example, a glass substrate or a quartz substrate provided with a buffer layer). Gate electrodes 12 and 13 made of a conductive material are formed thereon.

  The gate electrodes 12 and 13 are preferably made of a material having excellent heat resistance in consideration of later crystallization of the silicon film. The gate electrode 12 is used for a TFT constituting a peripheral drive circuit, and 13 is used for a TFT constituting an active matrix circuit.

  Further, an anodic oxide film may be formed on the surfaces and side surfaces of the gate electrodes 12 and 13 by an anodic oxidation method which is a known technique in order to increase the breakdown voltage.

  Next, a silicon oxide film 14 functioning as a gate insulating film is formed by a plasma CVD method, and an amorphous silicon film (not shown) is formed thereon by a plasma CVD method or a low pressure thermal CVD method. This amorphous silicon film (not shown) is crystallized by the means shown in the first embodiment, and becomes a crystalline silicon film 15 constituting an active layer. (Fig. 10 (A))

  It is also possible to directly form a crystalline silicon film instead of crystallizing the amorphous silicon film. The crystalline silicon film may be formed by using a low pressure thermal CVD method.

  Next, when the crystalline silicon film 15 is obtained, patterning is performed to form an active layer 16 used for the TFT constituting the peripheral drive circuit and an active layer 17 used for the TFT constituting the active matrix circuit.

  The method of forming the active layer is not limited to the above-described means. For example, a resist mask is disposed on the channel formation region (on the gate electrode), impurity ions are implanted from the resist mask, and the resist is removed and patterned. Then, laser annealing may be performed to simultaneously perform crystallization and formation of the source region and the drain region.

  Further, in the above means, an amorphous silicon film imparted with conductivity is deposited in a state where a resist mask is arranged instead of impurity ion implantation, and the source region and the drain region are formed using the amorphous silicon film as a source of impurity ions. How to do is taken.

  Next, the active layers 16 and 17 are irradiated with UV light, and a thin oxide film (not shown) is formed on the surfaces of the active layers 16 and 17. This oxide film (not shown) functions as a protective film for preventing a resist mask to be formed later and the active layers 16 and 17 from directly touching each other.

  Next, a resist mask (not shown) is formed, and is patterned by a backside exposure method to leave the resist masks 18 and 19 only on the channel formation region. The resist masks 18 and 19 formed in this manner function as a mask material in a later ion implantation process. (Fig. 10 (B))

  Next, an impurity imparting one conductivity is implanted into the exposed active layers 16 and 17. This step may be performed by a known ion implantation method.

  Thus, source regions 20 and 22 and drain regions 21 and 23 are formed in the active layers 16 and 17. (Fig. 10 (C))

  Next, the resist masks 18 and 19 are once removed, and resist masks 24 and 25 are formed again. At this time, it is important that the resist mask 24 is formed thinner than the resist mask 18 previously formed. This thinned portion becomes the region width of the LDD region to be formed later.

  The resist mask 25 is formed so as to cover the entire surface of the TFT constituting the active matrix circuit. That is, the mask is formed so that the LDD region is not formed.

  Then, impurity ions imparting the same conductivity are implanted with a lower dose than the previous time to form the low concentration impurity regions 26 and 27. At this time, the region where the impurity ions are not implanted by the resist mask 24 becomes the channel formation region 28.

  Note that the low-concentration impurity region disposed between the channel formation region 28 and the drain region 21 is generally called an LDD region.

  In this way, the state shown in FIG. 10D is obtained. In this state, the source region 20, the channel formation region 28, the drain region 21, and the concentration impurity regions 26 and 27 are arranged in the TFT constituting the peripheral driver circuit (mainly a shift register circuit or a sampling circuit). .

  In addition, a source region 22, a channel formation region 29, and a drain region 23 are arranged in the TFT constituting the active matrix circuit on the right side in the drawing.

  Next, after removing the resist masks 24 and 25, impurity ions are activated by laser annealing or the like. Damage caused to the active layer during ion implantation is also recovered by this laser annealing.

  Next, a silicon oxide film is formed as the interlayer insulating film 30 to form a contact hole. Then, source electrodes 31 and 33 and drain electrodes 32 and 34 made of a conductive material are formed to complete an inverted staggered TFT as shown in FIG.

  As described above, the present invention can be satisfactorily implemented even when an inverted staggered TFT is used. In the inverted stagger type TFT, the gate electrodes 12 and 13 are disposed below the active layer. Therefore, when laser annealing is used for the activation of impurity ions, etc., the gate electrode 12 and 13 is not shielded by the gate electrodes 12 and 13 and the entire active layer There is an advantage that uniform processing can be performed across.

  Further, because of its structure, there is an advantage that a highly reliable transistor that is resistant to contamination from the base 11 and the like can be configured.

Example 10
When a CMOS structure is manufactured by the process shown in Embodiment 1, no LDD region is formed in either the N-channel TFT or the P-channel TFT.

  Therefore, in this embodiment, an example of a manufacturing process in which an LDD region is arranged for both an N-channel TFT and a P-channel TFT will be described with reference to FIGS. The description will be given only for the CMOS structure.

  First, a region forming the CMOS structure in the state shown in FIG. 5C is shown in FIG. In addition, each code | symbol quotes what is used in FIG. 5, FIG.

  Next, the gate insulating film 506 is dry-etched using the gate electrodes 517 and 518 and the porous anodic oxide films 513 and 514 as masks to form island-like gate insulating films 41 and 42.

  Next, the porous anodic oxide films 513 and 514 are removed using a mixed acid to obtain the state shown in FIG.

  In this state, P ions are implanted first. By this ion implantation, high concentration impurity regions 43 to 46 into which P ions are implanted at a high concentration are formed. Further, in the region where P ions are implanted through the gate insulating films 41 and 42, low concentration impurity regions 47 to 50 in which P ions are implanted at a lower concentration than the regions 43 to 46 are formed. The regions 51 and 52 are substantially intrinsic regions without being implanted with P ions.

  Thus, the state shown in FIG. 11C is obtained. In this state, a source region 45, a channel formation region 52, a drain region 46, and low-concentration impurity regions 49 and 52 are formed on the N-channel TFT side.

  In this case, the low concentration impurity region 50 formed between the channel formation region 52 and the drain region 46 is called an LDD region.

  Next, a resist mask 53 is provided on the N-channel TFT side, and B ions for imparting P-type conductivity are implanted. This ion implantation is performed with a higher dose than the P ion implantation.

  As a result, the conductivity type of the regions 43, 44, 47, 48, 51 is reversed from N-type to P-type, and the source region 54, channel formation region 55, drain region 56, and low-concentration impurity region 57 of the P-channel TFT. , 58 are formed.

  In this case, the low concentration impurity region 58 formed between the channel formation region 55 and the drain region 56 becomes an LDD region.

  The subsequent steps may be in accordance with the first embodiment. After removing the resist mask 53, the first interlayer insulating film 547, the source electrodes 548 and 549, and the drain electrode 552 are formed, and the CMOS structure shown in FIG. Can be configured.

  In this embodiment, there is no problem even if the order of the P ion implantation step and the B ion implantation step is changed.

  When the CMOS structure shown in this embodiment is configured, an LDD region can be disposed also in a P-channel TFT, so that the reliability of a circuit configured with the CMOS structure can be improved.

[Device Description 1]
FIG. 12 shows an apparatus for performing annealing by irradiating spot-like laser light.

  In the drawing, a state in which a rectangular laser beam 70 is reflected by a mirror 71 and irradiated to an amorphous silicon film 74 is schematically shown.

  In the figure, a state in which the amorphous silicon film 74 is transformed into a crystalline silicon film 75 by irradiating a laser beam with a locus as indicated by 77 is shown.

  The silicon film is formed on the glass substrate 73. By moving the stage 72 in the two-dimensional XY direction as indicated by 76, the laser beam is irradiated along a locus as indicated by 77.

  The configuration as shown in FIG. 12 is disadvantageous for irradiation to a large area, but has a feature that the optical system is simple and maintenance and adjustment are easy.

[Device Description 2]
The outline of an apparatus for irradiating linear laser light is shown below. FIG. 13 is a schematic diagram showing a state in which the amorphous silicon film 1204 is irradiated with laser light 1200 processed into a linear shape by an optical system to be transformed into a crystalline silicon film 1205.

  In FIG. 13, the amorphous silicon film 1204 is formed on the glass substrate 1203, and the stage 1202 on which the substrate 1203 is placed moves in the direction of the arrow 1206, so that the laser beam reflected by the mirror 1201 is scanned. It is configured to be irradiated.

  Such a configuration has an advantage that laser light can be irradiated to a large area. However, there are drawbacks that the optical system becomes complicated and that adjustment takes time.

  As a laser beam used in such an apparatus, a KrF excimer laser (wavelength 248 nm) or a XeCl excimer laser (wavelength 308 nm) can be used.

  As a form of annealing, there are a step of transforming an amorphous silicon film into a crystalline silicon film, a step of further promoting the crystallinity of the crystalline silicon film, an activation step after implantation of impurity ions, and the like.

The figure which shows the outline of the circuit structure of an active matrix substrate. The figure which shows the structure of an active layer. The figure which shows the energy state of an active layer. The figure which shows the outline of the principle of operation of an active layer. 10A and 10B illustrate a manufacturing process of a thin film transistor. 10A and 10B illustrate a manufacturing process of a thin film transistor. 10A and 10B illustrate a manufacturing process of a thin film transistor. The figure which shows the structure of an active layer. 10A and 10B illustrate a manufacturing process of a thin film transistor. 10A and 10B illustrate a manufacturing process of a thin film transistor. 10A and 10B illustrate a manufacturing process of a thin film transistor. The figure which shows a state of irradiation of a laser beam. The figure which shows a state of irradiation of a laser beam.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Active matrix circuit 101 Vertical scanning drive circuit area 102 Horizontal scanning drive circuit area 103, 107 Shift register circuit 104, 108 Level shifter circuit 105, 109 Buffer circuit 106 Sampling circuit 110 Memory circuit 111 CPU circuit 112 Digital / analog conversion circuit 113 Control circuit region

Claims (5)

The island-shaped semiconductor layer of the thin film transistor is present between the source region exhibiting the first conductivity type, the drain region exhibiting the first conductivity type, and between the source region and the drain region. A base region exhibiting a conductivity type opposite to the conductivity type and the first conductivity type are exhibited, and the source region and the drain region are alternately arranged on one and the other outer edges of the island-shaped semiconductor layer by the base region. A floating island region separated so as to touch,
A path from the source region to the drain region via only the base region is larger than a route from the source region to the drain region via the base region and the floating island region in order. Buffer circuit. In claim 1,
The buffer circuit according to claim different from the route of the path and the off current of the ON current before Symbol thin film transistor. In claim 1 or 2,
Off current before Symbol thin film transistor buffer circuit, characterized in that flow through only the base region as a route. In any one of Claim 1 thru | or 3,
The buffer circuit according to claim 1, wherein an on-current of the thin film transistor flows through the base region and the floating island region. A display device comprising the buffer circuit according to claim 1.