CN104538402A - Array substrate, manufacturing method thereof and display device - Google Patents
Array substrate, manufacturing method thereof and display device Download PDFInfo
- Publication number
- CN104538402A CN104538402A CN201410841072.9A CN201410841072A CN104538402A CN 104538402 A CN104538402 A CN 104538402A CN 201410841072 A CN201410841072 A CN 201410841072A CN 104538402 A CN104538402 A CN 104538402A
- Authority
- CN
- China
- Prior art keywords
- thin
- film transistor
- channel region
- array base
- base palte
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Thin Film Transistor (AREA)
- Recrystallisation Techniques (AREA)
Abstract
The invention discloses an array substrate and a manufacturing method of the array substrate and a display device with the array substrate. The array substrate comprises a substrate body, polycrystalline silicon thin films and a plurality of thin film transistors. The polycrystalline silicon thin films each comprise a plurality of main grain boundaries arranged in parallel and stretching in the first direction. Active layers of all the thin film transistors are formed by the polycrystalline silicon thin films. Each thin film transistor comprises at least one channel region. The main grain boundaries penetrating through each channel region are the same in number. According to the array substrate and the manufacturing method of the array substrate and the display device with the array substrate, the main grain boundaries penetrating through each channel region are the same in number, so that the influences of the main grain boundaries on the electronic mobility of all the thin film transistors are basically the same, the performance difference of all the thin film transistors is lowered, and the uniformity of the performance is improved.
Description
Technical field
Embodiments of the invention relate to a kind of display unit, particularly relate to a kind of array base palte based on low-temperature polysilicon film transistor and preparation method thereof and comprise the display unit of this array base palte.
Background technology
The thin-film transistor (TFT) extensively adopted in Thin Film Transistor-LCD (Thin Film Transistor Liquid CrystalDisplay (TFT-LCD)) and active matrix organic light-emitting diode (Active MatrixOrganic Light Emitting Diode (AMOLED)) display unit at present mainly comprises amorphous silicon film transistor and polycrystalline SiTFT.Wherein, low temperature polycrystalline silicon (Low Temperature Poly-Silicon; LTPS) technology has also been applied in TFT thin film transistor monitor manufacturing process, and it mainly changes amorphous silicon (a-Si) film into polysilicon (Poly-Si) film by quasi-molecule laser annealing technique (Excimer LaserAnneal).Compare amorphous silicon (a-Si), in the polysilicon made like this, electron mobility has the increase of more than 100 times.Such as, electron mobility reaches 200cm
2/ more than V-sec, can effectively reduce the area of thin-film transistor, thus improves the aperture opening ratio of display, and can also reduce overall power consumption while promoting display brightness.In addition, the display unit of LTPS technology is adopted to have the response time faster, higher resolution, better picture display quality.
Summary of the invention
Embodiments of the invention provide a kind of array base palte and preparation method thereof and comprise the display unit of this array base palte, the impact of crystal boundary on the electron mobility of two thin-film transistors can be reduced, and then reduce the performance difference of different thin-film transistor, put forward high performance homogeneity.
According to the present invention's inventive embodiment, a kind of array base palte is provided, comprises: substrate; Polysilicon membrane, described polysilicon membrane comprises multiple oikocrysts circle be arranged in parallel extended along first direction; And multiple thin-film transistor, the active layer of each thin-film transistor is formed by described polysilicon membrane, and each thin-film transistor comprises at least one channel region, and the quantity through oikocryst circle of each channel region is equal.
According to the array base palte of an embodiment of the present invention, the channel current direction in described channel region tilts relative to the bearing of trend of described oikocryst circle.
According to the array base palte of an embodiment of the present invention, the angle between the channel current direction of described channel region and the bearing of trend of described oikocryst circle to be spent or in scope that 125 degree-145 is spent at 35 degree-55.
According to the array base palte of an embodiment of the present invention, the angle between the channel current direction of described channel region and the bearing of trend of described oikocryst circle is approximately 45 degree or 135 degree.
According to the array base palte of an embodiment of the present invention, each thin-film transistor is double gate transistor, the channel current direction in described channel region with and the bearing of trend of oikocryst circle between the equal mode of angle tilt.
According to the array base palte of an embodiment of the present invention, the channel current direction in two channel regions of described double gate transistor is parallel to each other.
According to the array base palte of an embodiment of the present invention, the angle of the channel current direction in two channel regions of described double gate transistor and the same bearing of trend of oikocryst circle is roughly complementary.
Embodiment according to a further aspect of the invention, provides a kind of method making array base palte, comprises the steps: to form amorphous silicon layer on substrate; Adopt repeatedly quasi-molecule laser annealing technique, make described amorphous silicon layer form the polysilicon membrane comprising multiple oikocrysts circle extended along first direction; And utilize described polysilicon membrane to form the active layer of multiple thin-film transistor, wherein, each thin-film transistor comprises at least one channel region, and the quantity through oikocryst circle of each channel region is equal.
According to the method for an embodiment of the present invention, adopt repeatedly quasi-molecule laser annealing technique, the step making described amorphous silicon layer form the polysilicon membrane comprising multiple oikocrysts circle extended along first direction comprises the steps: to utilize excimer laser source to perform quasi-molecule laser annealing technique, to form the first crystal region on substrate to described amorphous silicon layer region; Described substrate longitudinal direction or move excimer laser source in a lateral direction, and quasi-molecule laser annealing technique is performed again to another region of described amorphous silicon layer, to form the second crystal region, thus be formed in oikocryst circle that the first direction vertical with described longitudinal direction or horizontal direction extends in the marginal portion of described first and second crystal regions; And repeat the step of formation second crystal region, and to form multiple crystal region, multiple crystal region composition polysilicon membrane.
According to the method for an embodiment of the present invention, the step utilizing described polysilicon membrane to form the active layer of multiple thin-film transistor comprises the steps: to utilize the first mask plate to perform patterning processes to the polysilicon membrane formed, to form the multiple active layers being used for multiple thin-film transistor, wherein said first mask plate is provided with multiple first figures corresponding with described active layer, described first mask plate is arranged on substrate, and the bearing of trend of described first figure to be tilted identical angle relative to described first direction.
According to the method for an embodiment of the present invention, the angle that the bearing of trend of described first figure tilts relative to described first direction is in 35 degree of-55 degree or 125 degree-145 scope spent.
According to the method for an embodiment of the present invention, the bearing of trend of described first figure is about 45 degree or 135 degree relative to the angle that described first direction tilts.
According to the embodiment of the present invention further aspect, a kind of display unit is provided, comprises the array base palte described in above-mentioned various embodiment.
Array base palte according to the above embodiment of the present invention and preparation method thereof and comprise the display unit of this array base palte, due to the having the greatest impact of electron mobility of oikocryst bound pair thin-film transistor, equal by the quantity of oikocryst circle making the channel region through each thin-film transistor, make the impact of the electron mobility of each thin-film transistor of oikocryst bound pair substantially the same, and then reduce the performance difference of each thin-film transistor, put forward high performance homogeneity.
Accompanying drawing explanation
For making the object, technical solutions and advantages of the present invention clearly understand, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in further detail, wherein:
Fig. 1 is the principle schematic of the channel region of the thin-film transistor that prior art is shown and the set-up mode of channel region on polysilicon membrane according to the thin-film transistor of the embodiment of the present invention;
Fig. 2 is the principle schematic be arranged on according to a single gate thin-film transistors of the array base palte of the first exemplary embodiment of the present invention on polysilicon membrane;
The schematic cross-section in channel current flow direction when Fig. 3 is the single gate thin-film transistors work illustrated shown in Fig. 2;
Fig. 4 is the principle schematic of position relationship that the channel region of the single gate thin-film transistors shown in Fig. 2, oikocryst circle and channel current direction are shown;
Fig. 5 utilizes excimer laser source along the horizontal direction scanning amorphous silicon membrane of substrate to form the principle schematic of polysilicon membrane;
Fig. 6 utilizes excimer laser source along the longitudinal direction scanning amorphous silicon membrane of substrate to form the principle schematic of polysilicon membrane;
Fig. 7 is the principle schematic of position relationship in the channel region of single gate thin-film transistors according to the second exemplary embodiment of the present invention, oikocryst circle and channel current direction;
Fig. 8 is the partial sectional view comprising the array base palte of single gate thin-film transistors according to the first exemplary embodiment of the present invention;
Fig. 9 is the principle schematic of position relationship in the channel region of double gate thin-film transistor according to the third exemplary embodiment of the present invention, oikocryst circle and channel current direction;
Figure 10 is the principle schematic of position relationship in the channel region of double gate thin-film transistor according to the 4th kind of exemplary embodiment of the present invention, oikocryst circle and channel current direction;
Figure 11 is the principle schematic of position relationship in the channel region of double gate thin-film transistor according to the 5th kind of exemplary embodiment of the present invention, oikocryst circle and channel current direction; And.
Figure 12 is the partial sectional view comprising the array base palte of double gate thin-film transistor according to the second exemplary embodiment of the present invention;
Embodiment
Below by embodiment, and by reference to the accompanying drawings, technical scheme of the present invention is described in further detail.In the description, same or analogous drawing reference numeral indicates same or analogous parts.The explanation of following reference accompanying drawing to embodiment of the present invention is intended to make an explanation to present general inventive concept of the present invention, and not should be understood to one restriction of the present invention.
According to the inventive concept generally of various exemplary embodiment of the present invention, a kind of array base palte is provided, comprises: substrate; Polysilicon membrane, described polysilicon membrane comprises multiple oikocrysts circle be arranged in parallel extended along first direction; And multiple thin-film transistor, the active layer of each thin-film transistor is formed by described polysilicon membrane, and each thin-film transistor comprises at least one channel region, and the quantity through oikocryst circle of each channel region is equal.Equal by the quantity of oikocryst circle making the channel region through each thin-film transistor, make the impact of the electron mobility of each thin-film transistor of oikocryst bound pair substantially the same, and then reduce the performance difference of each thin-film transistor, put forward high performance homogeneity.
In the following detailed description, for ease of explaining, many concrete details have been set forth to provide the complete understanding to this disclosure embodiment.But significantly, one or more embodiment also can be implemented when not having these details.In other cases, known construction and device diagrammatically embodies to simplify accompanying drawing.
Fig. 1 is the principle schematic of the channel region of the thin-film transistor that prior art is shown and the set-up mode of channel region on polysilicon membrane according to the thin-film transistor of the embodiment of the present invention; Fig. 2 is the principle schematic be arranged on according to a single gate thin-film transistors of the array base palte of the first exemplary embodiment of the present invention on polysilicon membrane.
See Fig. 1,2 and 4, the array base palte according to a kind of exemplary embodiment of the present invention comprises: the substrate 10 (see Fig. 9) be such as made up of glass or transparent resin material and the multiple thin-film transistors 50 formed on the substrate 10.Substrate is rectangle roughly, polysilicon membrane 11 is formed by utilizing accurate laser to irradiate formation amorphous silicon on the substrate 11 (A-Si) film in the mode that pulse scans, and comprise multiple oikocrysts circle 60 extended along first direction (left and right directions of Fig. 1), between adjacent oikocryst circle, also form multiple crystal boundaries 64.The active layer of each thin-film transistor 50 is formed by polysilicon membrane 11, and each thin-film transistor 11 comprises at least one channel region 51 ', and the quantity through oikocryst circle 60 of each channel region 51 ' is equal.
Usually, see Fig. 1,5 and 6, oikocryst circle 60 is being utilize excimer laser source 61 to change in the process of polysilicon membrane 11 by quasi-molecule laser annealing technique by amorphous silicon membrane, formed at two adjacent crystal regions 62 (62 ') and the marginal portion of 63 (63 ').Those skilled in the art will recognize that the bearing of trend of oikocryst circle 60 and excimer laser source 61 are be transitioned into direct of travel when once scanning from single pass vertical.
Array base palte according to the above embodiment of the present invention, due to the having the greatest impact of electron mobility of oikocryst bound pair thin-film transistor, equal by the quantity of oikocryst circle making the channel region through each thin-film transistor, make the impact of the electron mobility of each thin-film transistor of oikocryst bound pair substantially the same, and then reduce the performance difference of each thin-film transistor, put forward high performance homogeneity.
In a kind of exemplary embodiment, the channel current direction in the channel region 51 ' of each thin-film transistor 50 tilts relative to the bearing of trend of described oikocryst circle.
See Fig. 2-4 and 8, according to a kind of exemplary embodiment of the present invention, each thin-film transistor 50 is single gridistor, and comprises: the active layer 51 formed by polysilicon membrane; Be formed in the first insulating barrier 42 on active layer 51, described first insulating barrier 42 is provided with at least two the first via holes extending to active layer 51; Be formed in the grid 54 on the first insulating barrier 42; And be respectively formed at the both sides of grid 54 and the source electrode 52 be electrically connected with active layer 51 by the first via hole and drain 53.Usually, drain electrode 53 applies high level, grid 54 applies high level, when voltage Vgs between grid 54 and source electrode 52 is greater than or equal to threshold voltage vt h (being generally 0-3.0V), free migration electronics 55 near grid 54 surface in active layer 51 flows thus forms channel current 56, makes thin-film transistor conducting.In a kind of exemplary embodiment of the present invention, the flow direction of channel current 56 points to source electrode 52 from drain electrode 53.Be appreciated that the material according to forming thin-film transistor is different, the flow direction of channel current 56 can point to drain electrode 53 from source electrode 52.
Usually, see Fig. 1 and 2, thin-film transistor 50 shown in Fig. 2 is a kind of double gate transistors, the channel region 51 ' that the active layer 51 of this double gate transistor is formed comprises rectangular first channel region 511 ' and the second channel region 512 ', the first channel region 511 ' that have roughly and the second channel region 512 ' all has length L and width W.In the case, the flow direction of the channel current 56 in channel region is identical with length direction.In a kind of exemplary embodiment, the length of the channel region 51 ' between the source electrode 52 and drain electrode 53 of thin-film transistor 50 is 2-10 micron (μm), be such as 8 or 9 microns, the distance lambda between adjacent Liang Ge oikocryst circle 60 is such as 3.5 microns.
Left side in Fig. 1 illustrates a kind of arrangement of double gate transistor of the prior art, this double gate transistor comprises the first channel region 511 ' and the second channel region 512 ', and the length L of the first channel region 511 ' and the second channel region 512 ' is perpendicular to the bearing of trend (namely described first direction) of oikocryst circle 60.Be all about 4 microns at the length L of the first and second channel regions, when the distance lambda between adjacent Liang Ge oikocryst circle 60 is such as about 3.5 microns, the first and second channel regions can cross at most 2 oikocrysts circle 60 in the longitudinal direction.But, if the restriction due to manufacture craft causes the first channel region 511 ' and the second channel region 512 ' not with identical regular arrangement, the quantity of oikocryst circle then likely causing them to cross over is different, such as the first channel region 511 ' crosses over oikocryst circle 60, and the second channel region 512 ' crosses over Liang Ge oikocryst circle 60.Because the quantity of crossed over oikocryst circle is different, the impact of the electron mobility of the channel region of oikocryst bound pair two thin-film transistors is not identical, and then the performance causing two thin-film transistors there are differences, reduce the homogeneity of the performance of two thin-film transistors.
Right side in Fig. 1 illustrates the another kind of arrangement of identical double gate transistor, the first channel region 511 ' of this double gate transistor and the second channel region 512 ' be all arranged to relative to oikocryst circle 60 tilt such as roughly 45 degree angle θ.It is all about 4 microns at the length L of the first and second channel regions, when distance lambda between adjacent Liang Ge oikocryst circle 60 is such as about 3.5 microns, the length L bearing of trend of the first channel region 511 ' and the second channel region 512 ' tilts relative to the bearing of trend (i.e. first direction) of oikocryst circle, add the size of the first channel region 511 ' and the second channel region 512 ' leap oikocryst circle 60, can guarantee that the first channel region 511 ' and the second channel region 512 ' can both cross over 2 oikocrysts circle 60.Even if the restriction due to manufacture craft causes the first channel region 511 ' and the second channel region 512 ' not with identical regular arrangement, also can guarantee that the quantity of oikocryst circle that they are crossed over is identical, such as the first channel region 511 ' and the second channel region 512 ' all cross over Liang Ge oikocryst circle 60.Because the quantity of crossed over oikocryst circle is identical, the impact of the electron mobility of the channel region of oikocryst bound pair two thin-film transistors is roughly the same, and then the performance causing two thin-film transistors has homogeneity.
In a kind of exemplary embodiment, the length direction of the channel region 51 ' of each thin-film transistor is arranged to tilt relative to oikocryst circle 60, if length L is 8-9 micron, distance lambda between adjacent Liang Ge oikocryst circle 60 is approximately 3.5 microns, and whole channel region 51 ' can cross over 4 oikocrysts circle 60.First channel region 511 ' and the second channel region 512 ' can both cross over 2 oikocrysts circle 60
In one embodiment, between the length direction (or flow direction of channel current 56) of channel region 51 ' and the bearing of trend of oikocryst circle 60, angle to be spent or in scope that 125 degree-145 is spent at 35 degree-55, such as, 45 degree or 135 degree are approximately.See Fig. 3,5 and 6, owing to being formed in the process for the formation of the polysilicon membrane of active layer 51, longitudinal direction or the horizontal direction of the roughly foursquare substrate in excimer laser source edge carry out motion scan, and the bearing of trend of crystal boundary 60 is vertical with scanning direction.Be appreciated that, no matter excimer laser source be transitioned into from single pass once scan time along the longitudinal direction or horizontal direction moves, the channel current direction 56 of thin-film transistor 50 all becomes the angle of about 45 degree with the long limit of substrate and short side direction, simultaneously also with ELA scanning direction all in angle of 45 degrees, make the angle in the channel region of the crystal boundary 60 and each thin-film transistor extended at first direction between channel current direction be respectively about 45 degree.Like this, when performing quasi-molecule laser annealing technique to amorphous silicon membrane, the scanning direction of excimer laser source can not be considered, increase the alternative of this scanning direction.Such as, considering the factors such as the matrix arrangement on the size of dissimilar excimer laser source, substrate and substrate, can choose reasonable scanning direction be horizontal direction 12 or longitudinal direction 13, to obtain best crystallization effect.
According to the array base palte of the embodiment of the present invention, because the angle between the channel current direction of each thin-film transistor 50 and first direction is approximately 45 degree, the possibility that the quantity of oikocryst circle of the channel region leap of each thin-film transistor 50 is equal can be improved, make the impact of oikocryst circle 60 on the electron mobility of each thin-film transistor substantially the same, and then the performance difference reduced between thin-film transistor, improve performance uniformity.
When thin-film transistor 50 is single gridistor, as shown in Fig. 3,4 and 7, by arranging source electrode 52, drain electrode 53 and grid 54, the quantity of oikocryst circle that the channel region 51 ' formed by the active layer 51 between source electrode 52 and drain electrode 53 is crossed over is equal, such as, and the flow direction of the channel current in channel region 51 ' tilts relative to oikocryst circle, and tilt 45 (Fig. 4) or 135 degree (Fig. 7).
Fig. 9-11 is the principle schematic of position relationship in the channel region of double gate thin-film transistor according to exemplary embodiment of the present invention, oikocryst circle and channel current direction; Figure 12 is the partial sectional view comprising the array base palte of double gate thin-film transistor according to the second exemplary embodiment of the present invention.For ease of describing, in Fig. 9-12, adopt identical Reference numeral with the same parts shown in Fig. 1-8.
According to the second exemplary embodiment of the present invention, see 9 and 12, each thin-film transistor 50 is double gate transistor, and comprises: the active layer 51 formed by polysilicon membrane; Be formed in the first insulating barrier 42 on active layer 51, described first insulating barrier 42 is provided with at least two the first via holes extending to active layer 51; Be formed in two grids 54 ' be arranged in parallel on the first insulating barrier 42; And be respectively formed at the both sides of grid 54 ' and the source electrode 52 ' be electrically connected with active layer 51 by the first via hole with drain 53 '.Usually, drain electrode 53 ' applies high level, grid 54 ' applies high level, when voltage Vgs ' between grid 54 ' and source electrode 52 ' is greater than or equal to threshold voltage vt h ', in active layer 51 near grid 54 ' surface free migration electron flow thus formed channel current, make double-gate film transistor turns.
Double-gate film transistor application is in array base palte according to an embodiment of the invention, can improve Circuit responce speed, by the driving force to pixel electrode, and reduces leakage current.
According to the array base palte of the embodiment of the present invention, quantity through oikocryst circle of the channel region corresponding with two grids 54 ' of each thin-film transistor is equal, and the channel current direction in two described channel regions with and the bearing of trend of oikocryst circle between the equal mode of angle tilt, such as angle of inclination, in 35 degree of-55 degree or 125 degree-145 scope spent, is preferably approximately 45 degree or be approximately 135 degree.Like this, the impact of the electron mobility of two channel regions of oikocryst bound pair each double-gate film transistor is substantially the same, and then reduces the performance difference between two channel regions, improves performance uniformity.Channel current direction relative to first direction with equal angular slope, the possibility that the quantity of oikocryst circle of the channel region leap of each thin-film transistor 50 is equal can be improved, make the impact of oikocryst circle 60 on the electron mobility of each thin-film transistor substantially the same, and then the performance difference reduced between thin-film transistor, improve performance uniformity.
As shown in Figures 9 and 10, two channel regions 51 of double gate transistor " in channel current direction parallel to each other, such as angle of inclination is for being approximately 45 degree (Fig. 9) or being approximately 135 degree (Figure 10).
As shown in figure 11, two channel regions 51 of double gate transistor " in channel current direction and the angle of same bearing of trend of oikocryst circle roughly complementary; such as an angle of inclination is for being approximately 45 degree (channel regions in left side), and another angle of inclination is approximately 135 degree (channel regions on right side).
See Figure 12, two grids 54 ' are provided with middle dielectric layer 43, are formed with the second via hole in described middle dielectric layer 43, source electrode 52 ' and drain electrode 53 ' are electrically connected respectively by the second via hole active layer 51.First ohm of doped layer 58 is provided with in the position that drain electrode 53 ' is electrically connected with pixel electrode 46.In addition, the position be electrically connected with data wire (not shown) at source electrode 52 ' is also provided with first ohm of doped layer 58.Further, second ohm of doped layer 57 is respectively equipped with at source electrode 52 ' with between drain electrode 53 ' and active layer 51.First ohm of doped layer 58 and second ohm of doped layer 57 are such as phosphorus or boron-dopped layer, can reduce source electrode 52 ' and drain electrode 53 ' and contact impedance between active layer 51 and pixel electrode 46.
Array base palte according to the embodiment of the present invention can be applied to such as liquid crystal indicator.These liquid crystal indicators, under the driving of the thin-film transistor of array base palte, can realize Presentation Function.In the alternative embodiment, the array base palte of the embodiment of the present invention can be applied to the array base palte of liquid crystal indicator and AMOLED (Active Matrix Organic Light Emitting Diode, active matrix organic light-emitting diode) display unit.Embodiments of the invention are illustrated for the thin-film transistor being applied to liquid crystal panel, are appreciated that the thin-film transistor in AMOLED display device also can be arranged according to the mode described by the embodiment of the present invention.
In a kind of exemplary embodiment, as illustrated in FIG 8 and FIG 12, each described thin-film transistor comprises: the active layer 51 formed by polysilicon membrane; Be formed in the first insulating barrier 42 on active layer 51, described first insulating barrier 42 is provided with at least two the first via holes extending to active layer; To be formed on the first insulating barrier 42 and one or two grids 54 or 54 between described first via hole '; And be respectively formed at the both sides of grid 54 and the source electrode 52 or 52 be electrically connected with active layer 51 by the first via hole ' and drain 53 or 53 '.Such as, the first insulating barrier 42 can comprise silica (SiOx) insulating barrier 421 and silicon nitride (SiNx) insulating barrier 422.
In a kind of exemplary embodiment, the first resilient coating 15 be such as made up of silicon nitride (SiNx) material is also provided with, the ionic soil polysilicon membrane in the substrate 10 made to prevent glass between substrate 10 and the polysilicon membrane for the formation of active layer 51.Further, the second resilient coating 14 be made up of such as silica (SiOx) material can also be formed on the first resilient coating 15.Such as, the thickness of the first resilient coating 15 and the second resilient coating 14 be approximately respectively 500 and 3000 dusts (
).Like this, the both sides of active layer 51 are all provided with the layer be made up of silica material.
Array base palte according to an embodiment of the present invention also comprises: cover grid 54 or 54 ' on middle dielectric layer 43; Be formed in first ohm of doped layer 58 on middle dielectric layer 43, grid and drain electrode are electrically connected with first ohm of doped layer 58 respectively by the second via hole be formed in described middle dielectric layer 43.Further, at described source electrode be respectively equipped with second ohm of doped layer 57 between drain electrode and active layer.Such as, middle dielectric layer 43 can comprise silica (SiOx) dielectric layer 432 and silicon nitride (SiNx) dielectric layer 431, and first ohm of doped layer 58 is formed on silicon nitride (SiNx) dielectric layer 431.
Array base palte according to an embodiment of the present invention also comprises: be formed in the planarization layer 44 be made up of acrylic (Acryl) material on middle dielectric layer 43, such as its thickness is approximately 17000 dusts; Be formed at least one public electrode 45 on planarization layer 44; Cover the second insulating barrier be made up of silicon nitride (SiNx) material on described public electrode 44 or passivation layer 47, such as its thickness is approximately 1100 dusts; And the multiple pixel electrodes 46 be formed on the second insulating barrier 47, each pixel electrode is electrically connected with corresponding first ohm of doped layer 58 by the 3rd via hole be formed in planarization layer 44 and the second insulating barrier 47.Like this, the drain electrode 53 of thin-film transistor is electrically connected with pixel electrode 46 by first ohm of doped layer 58, the electric conducting material be formed in the 3rd via hole, to be provided for the driving voltage driving liquid crystal material luminescence to pixel electrode 46.Usually, pixel electrode 46 comprises the strip shaped electric poles be such as made up of tin indium oxide (ITO) material be arranged in parallel with equal intervals.
Be appreciated that the thin-film transistor described by above-described embodiment is top gate-type transistors.But the present invention is not limited thereto.Those skilled in the art will appreciate that, in the interchangeable embodiment of one, thin-film transistor is bottom gate thin film transistor.When bottom gate thin film transistor, the active layer of each thin-film transistor is formed by described polysilicon membrane, and the quantity through oikocryst circle of the channel region of each thin-film transistor is equal.Equal by the quantity of oikocryst circle making the channel region through each thin-film transistor, make the impact of the electron mobility of each thin-film transistor of oikocryst bound pair substantially the same, and then reduce the performance difference of each thin-film transistor, put forward high performance homogeneity.
According to the embodiment of the present invention further aspect, a kind of display unit is provided, comprises the array base palte as described in above-mentioned various embodiment.Described display unit can be any product or parts with Presentation Function such as mobile phone, panel computer, television set, display, notebook computer, DPF, navigator, Electronic Paper.
Although illustrate and describe the embodiment that array base palte is applied to display unit, but those skilled in the art can understand, the array base palte of the embodiment of the present invention also can be applicable to have in the electronic installation of the thin-film transistor of arranged in arrays outside display unit, and the active layer of these thin-film transistors is formed by forming polysilicon membrane by quasi-molecule laser annealing technique.Whole like this array base palte integrates the switching device as with multiple switching channels, and wherein each switching channels comprises a thin-film transistor.
According to the embodiment of the further aspect of the present invention, provide a kind of method making array base palte, comprise the steps: to form amorphous silicon layer 10 by deposition on roughly rectangular substrate; Adopt repeatedly quasi-molecule laser annealing technique, make described amorphous silicon layer 10 form the polysilicon membrane 11 comprising multiple oikocrysts circle extended along first direction; And utilize described polysilicon membrane 11 to form the active layer of multiple thin-film transistor 50, wherein, the quantity through oikocryst circle of the channel region of each thin-film transistor 50 is equal.
In one embodiment, adopt repeatedly quasi-molecule laser annealing technique, the step making described amorphous silicon layer form the polysilicon membrane comprising multiple oikocrysts circle extended along first direction comprises the steps:
Excimer laser source 61 (see Figure 4 and 5) is utilized to perform quasi-molecule laser annealing technique, to form the first crystal region 62 on the substrate 10 to amorphous silicon layer region; Substrate 10 longitudinal direction or move excimer laser source 61 in a lateral direction, and quasi-molecule laser annealing technique is performed again to another region of amorphous silicon layer, to form the second crystal region 63, thus be formed in the crystal boundary 60 that the first direction vertical with described longitudinal direction or horizontal direction extends in the marginal portion of described first and second crystal regions; And repeat the step of formation first crystal region or the second crystal region, and to form multiple crystal region, multiple crystal region composition polysilicon membrane 11.
Specifically, first, buffer layer on the substrate 10, then deposition of amorphous silicon layers, perform high-temperature dehydrogenation process afterwards, reduce amorphous silicon become in hydrogen content, to reduce the raw possibility of hydrogen outburst when performing quasi-molecule laser annealing (ELA) afterwards.Such as at the temperature of about 450 DEG C of temperature, perform 30 minutes high-temperature dehydrogenation process, make hydrogen content < 2% (before dehydrogenation 16% ~ 17%) in amorphous silicon layer.
Afterwards, as shown in Figure 4, prepare in the process of low temperature polycrystalline silicon in employing quasi-molecule laser annealing (ELA) technique, use the accurate laser produced by excimer laser source 61, the accurate laser XeCl that such as wavelength is 308nm, energy is 0-1000 millijoule/pulse (mj/pulse), irradiate in the mode of pulse scanning the region being formed in substrate amorphous silicon membrane, in irradiated region, form a crystal region 62, the grain size of generation is 0.3 ~ 0.5um; Crystal grain protrude control about 200 dusts (
), folded rate (Overlap) is approximately 96%; Then transversely direction (Width of substrate) 13 rectilinear movement excimer laser source 61, then with the next region of pulsed laser irradiation amorphous silicon membrane, to form next crystal region 63.Because when accurate laser irradiates, the homogeneity of its laser intensity exists Light Difference, therefore the crystallization degree of the marginal portion of two adjacent crystal regions 62 and 63 has different, the grain size formed is inconsistent, thus forms multiple oikocryst circle (grain boundary) 60.The bearing of trend of these oikocrysts circle 60 and scanning direction of advancing (the i.e. horizontal direction 13) perpendicular of excimer laser source.
Similarly, see Fig. 5, if use the excimer laser source 61 mode sequential illumination amorphous silicon membrane that scans with pulse of (length direction of substrate) 12 along the longitudinal direction, then the marginal portion two adjacent crystal regions 62 ' and 63 ' is formed multiple oikocryst circle.The bearing of trend of these oikocrysts circle and scanning direction of advancing (the i.e. longitudinal direction 12) perpendicular of excimer laser source 61.Multiple crystal region forms crystalline membrane 11.
Further, utilize polysilicon membrane 11 to form the active layer of multiple thin-film transistor 50, the quantity through oikocryst circle 60 of the channel region of each thin-film transistor 50 is equal.
The method of making array base palte according to the above embodiment of the present invention, due to the having the greatest impact of electron mobility of oikocryst bound pair thin-film transistor, equal by the quantity of oikocryst circle making the channel region through each thin-film transistor, make the impact of the electron mobility of each thin-film transistor of oikocryst bound pair substantially the same, and then reduce the performance difference of each thin-film transistor, put forward high performance homogeneity.
In a kind of exemplary embodiment, the step that polysilicon membrane 11 is formed multiple thin-film transistor comprises the steps: that utilizing the first mask plate to perform the crystallizing layer formed such as comprises coating photoresist, exposure, etching, the patterning processes such as stripping, to form the multiple active layers 51 being used for multiple thin-film transistor 50, wherein said first mask plate is provided with multiple first figures corresponding with active layer 51, described first mask plate is arranged on the substrate 10, the bearing of trend of described first figure to be tilted identical angle relative to described first direction (bearing of trend of oikocryst circle 60).In one embodiment, the angle that the bearing of trend of the first figure tilts relative to described first direction is in 35 degree of-55 degree or 125 degree-145 scope spent, such as, the bearing of trend of the first figure is about 45 degree or 135 degree relative to the angle that described first direction tilts.Like this, the channel current direction be about in the channel region 51 ' of each thin-film transistor 50 formed can be made to tilt identical angle relative to the bearing of trend of described oikocryst circle 60.Like this, the possibility that the quantity of oikocryst circle that the channel region that improve each thin-film transistor 50 is crossed over is identical, make the impact of the electron mobility of the channel region of oikocryst bound pair two thin-film transistors roughly the same, and then the performance causing two thin-film transistors have homogeneity.
Those skilled in the art understands, the first figure on first mask is corresponding with the shape of the active layer that will be formed, can according to the type of photoresist, such as positive photoresist or negative photoresist, first figure can be the slit allowing light transmission, or does not allow the shading graph of light transmission.
The step that described polysilicon membrane is formed multiple thin-film transistor also comprises the steps: at active layer 51 depositing first insulator layer 42, such as, thickness is approximately silicon nitride or the silicon oxide layer of 1000 dusts, or thickness be approximately 400 silicon nitride dielectric layer and thickness be approximately silica (SiOx) insulating barrier of 800 dusts; First insulating barrier 42 forms multiple grid 54 or 54 by patterning processes '; First insulating barrier 42 forms cover gate 54 or 54 ' middle dielectric layer 43, such as middle dielectric layer 43 comprise thickness be approximately 3000 silicon nitride medium layer and thickness be approximately silica (SiOx) dielectric layer of 2000 dusts; At one or two grids 54 or 54 ' the middle dielectric layer 43 of both sides and the first insulating barrier 42 on form by patterning processes multiple first via holes arriving described active layer; At one or two grids 54 or 54 ' both sides middle dielectric layer 43 on form source electrode 52 or 52 respectively by patterning processes ' and, drain electrode 53 or 53 ', wherein source electrode 52 or 52 ' and, draining 53 or 53 ' is electrically connected with active layer 51 respectively by corresponding first via hole.Such as, source electrode 52 or 52 ' figure and drain electrode 53 or 53 ' the angle of figure between the long limit or minor face of channel part and substrate 10 be approximately 45 degree, to ensure that the direction of the channel current 56 of all thin-film transistors 50 and the angle between oikocryst circle 60 are that the quantity of oikocryst circle 60 that about 45 degree and each channel region are crossed over is identical.
In an embodiment of the present invention, the figure of source electrode, drain electrode and active layer 51 can be set to parallelogram, to ensure that source electrode and drain electrode are consistent with the lap area of active layer.When being formed with active layer 51, usually according to thin-film transistor is the light dope that P type or N-type carry out channel part.Grid 54 or 54 ' figure also can be set to parallelogram, to ensure that grid 54 and active layer overlapping area remain unchanged.
In a kind of exemplary embodiment, before formation first via hole, at grid 54 or 54 ' both sides active layer 51 is adulterated, will described source electrode and the first ohmic contact layer 57 between drain electrode and active layer 51 be laid respectively to be pre-formed.Electron gun such as can be used at corresponding position bombardment insulating barrier 42, to form the first ohmic contact layer 57 of Doping Phosphorus or boron element.Like this, in channel region, form a low-doped drain region near the position of drain electrode, allow this impure drain region also receiving portion component voltage, this structure can prevent hot electron degradation effect, reduces low-temperature polysilicon film electric leakage.
Be appreciated that the thin-film transistor obtained according to above-mentioned manufacture method is top gate-type transistors.In the interchangeable embodiment of one, before execution forms the step of amorphous silicon layer on the substrate 10, described substrate 10 forms the multiple grids being respectively used to multiple thin-film transistor.Like this, the thin-film transistor obtained is bottom-gate-type transistor.
Array base palte according to the above embodiment of the present invention and preparation method thereof, comprise the display unit of this array base palte, due to the having the greatest impact of electron mobility of oikocryst bound pair thin-film transistor, equal by the quantity of oikocryst circle making the channel region through each thin-film transistor, make the impact of the electron mobility of each thin-film transistor of oikocryst bound pair substantially the same, and then reduce the performance difference of each thin-film transistor, put forward high performance homogeneity.Further, by making the channel region run-off the straight of each thin-film transistor, channel current direction and oikocryst circle angled, the main number of grain boundaries in the channel region of each thin-film transistor is reached unanimity.In addition, the available high-quality polysilicon membrane of method according to the present invention, its crystallite dimension is comparatively large, is evenly distributed, and there is low-down surface roughness, the problem of mobility and threshold voltage inhomogeneities in low temperature polycrystalline silicon display pannel can be solved.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (13)
1. an array base palte, is characterized in that, comprising:
Substrate;
Polysilicon membrane, described polysilicon membrane comprises multiple oikocrysts circle be arranged in parallel extended along first direction; And
Multiple thin-film transistor, the active layer of each thin-film transistor is formed by described polysilicon membrane, and each thin-film transistor comprises at least one channel region, and the quantity through oikocryst circle of each channel region is equal.
2. array base palte as claimed in claim 1, it is characterized in that, the channel current direction in described channel region tilts relative to the bearing of trend of described oikocryst circle.
3. array base palte as claimed in claim 2, is characterized in that, the angle between the channel current direction of described channel region and the bearing of trend of described oikocryst circle to be spent or in scope that 125 degree-145 is spent at 35 degree-55.
4. array base palte as claimed in claim 3, it is characterized in that, the angle between the channel current direction of described channel region and the bearing of trend of described oikocryst circle is approximately 45 degree or 135 degree.
5. the array base palte according to any one of claim 1-3, is characterized in that, each thin-film transistor is double gate transistor, the channel current direction in described channel region with and the bearing of trend of oikocryst circle between the equal mode of angle tilt.
6. array base palte as claimed in claim 5, it is characterized in that, the channel current direction in two channel regions of described double gate transistor is parallel to each other.
7. array base palte as claimed in claim 5, it is characterized in that, the angle of the channel current direction in two channel regions of described double gate transistor and the same bearing of trend of oikocryst circle is roughly complementary.
8. make a method for array base palte, it is characterized in that, comprise the steps:
Substrate forms amorphous silicon layer;
Adopt repeatedly quasi-molecule laser annealing technique, make described amorphous silicon layer form the polysilicon membrane comprising multiple oikocrysts circle extended along first direction; And
Utilize described polysilicon membrane to form the active layer of multiple thin-film transistor, wherein, each thin-film transistor comprises at least one channel region, and the quantity through oikocryst circle of each channel region is equal.
9. method as claimed in claim 8, is characterized in that, adopt repeatedly quasi-molecule laser annealing technique, and the step making described amorphous silicon layer form the polysilicon membrane comprising multiple oikocrysts circle extended along first direction comprises the steps:
Excimer laser source is utilized to perform quasi-molecule laser annealing technique, to form the first crystal region on substrate to described amorphous silicon layer region;
Described substrate longitudinal direction or move excimer laser source in a lateral direction, and quasi-molecule laser annealing technique is performed again to another region of described amorphous silicon layer, to form the second crystal region, thus be formed in oikocryst circle that the first direction vertical with described longitudinal direction or horizontal direction extends in the marginal portion of described first and second crystal regions; And
Repeat the step of formation second crystal region, to form multiple crystal region, multiple crystal region composition polysilicon membrane.
10. method as claimed in claim 9, it is characterized in that, the step utilizing described polysilicon membrane to form the active layer of multiple thin-film transistor comprises the steps:
The first mask plate is utilized to perform patterning processes to the polysilicon membrane formed, to form the multiple active layers being used for multiple thin-film transistor, wherein said first mask plate is provided with multiple first figures corresponding with described active layer, described first mask plate is arranged on substrate, and the bearing of trend of described first figure to be tilted identical angle relative to described first direction.
11. methods as claimed in claim 10, is characterized in that, the angle that the bearing of trend of described first figure tilts relative to described first direction is in 35 degree of-55 degree or 125 degree-145 scope spent.
12. methods as claimed in claim 11, is characterized in that, the bearing of trend of described first figure is about 45 degree or 135 degree relative to the angle that described first direction tilts.
13. 1 kinds of display unit, comprise the array base palte as described in any one in claim 1-7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410841072.9A CN104538402B (en) | 2014-12-30 | 2014-12-30 | Array base palte and preparation method thereof and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410841072.9A CN104538402B (en) | 2014-12-30 | 2014-12-30 | Array base palte and preparation method thereof and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104538402A true CN104538402A (en) | 2015-04-22 |
| CN104538402B CN104538402B (en) | 2018-01-23 |
Family
ID=52853905
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410841072.9A Active CN104538402B (en) | 2014-12-30 | 2014-12-30 | Array base palte and preparation method thereof and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104538402B (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104779171A (en) * | 2015-05-05 | 2015-07-15 | 京东方科技集团股份有限公司 | Low-temperature polycrystalline silicon thin film transistor, manufacturing method thereof, array substrate and display device |
| CN105185792A (en) * | 2015-09-30 | 2015-12-23 | 深圳市华星光电技术有限公司 | LCD panel, array substrate and manufacturing method thereof |
| CN105759527A (en) * | 2016-04-26 | 2016-07-13 | 上海天马有机发光显示技术有限公司 | Array substrate, manufacturing method of array substrate and display panel |
| CN106684101A (en) * | 2017-02-15 | 2017-05-17 | 厦门天马微电子有限公司 | Array substrate, display panel and display device |
| CN106684091A (en) * | 2015-11-09 | 2017-05-17 | 上海和辉光电有限公司 | Display panel, array substrate and manufacturing method of array substrate |
| CN109003579A (en) * | 2018-07-12 | 2018-12-14 | 武汉华星光电半导体显示技术有限公司 | Dot structure |
| CN109659326A (en) * | 2019-01-02 | 2019-04-19 | 京东方科技集团股份有限公司 | A kind of array substrate and micro-total analysis device |
| CN109962114A (en) * | 2019-04-17 | 2019-07-02 | 京东方科技集团股份有限公司 | Double grid TFT, pixel circuit and its control method |
| WO2020186448A1 (en) * | 2019-03-19 | 2020-09-24 | 深圳市柔宇科技有限公司 | Transparent display panel and display device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1433084A (en) * | 2002-01-18 | 2003-07-30 | 三星Sdi株式会社 | Polysilicon film for film transistor and display device with the polysilicon film |
| CN1503376A (en) * | 2002-11-19 | 2004-06-09 | ����Sdi��ʽ���� | Thin film transistor and organic electroluminescence equipment |
| CN101168474A (en) * | 2006-10-27 | 2008-04-30 | 群康科技(深圳)有限公司 | Method for manufacturing polycrystalline silicon thin film at low temperature |
| CN101325155A (en) * | 2008-07-24 | 2008-12-17 | 友达光电股份有限公司 | Mask and method for forming polycrystalline silicon layer using the same |
| CN101355090A (en) * | 2008-09-19 | 2009-01-28 | 友达光电股份有限公司 | Thin-film transistor array substrate and preparation method thereof |
-
2014
- 2014-12-30 CN CN201410841072.9A patent/CN104538402B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1433084A (en) * | 2002-01-18 | 2003-07-30 | 三星Sdi株式会社 | Polysilicon film for film transistor and display device with the polysilicon film |
| CN1503376A (en) * | 2002-11-19 | 2004-06-09 | ����Sdi��ʽ���� | Thin film transistor and organic electroluminescence equipment |
| CN101168474A (en) * | 2006-10-27 | 2008-04-30 | 群康科技(深圳)有限公司 | Method for manufacturing polycrystalline silicon thin film at low temperature |
| CN101325155A (en) * | 2008-07-24 | 2008-12-17 | 友达光电股份有限公司 | Mask and method for forming polycrystalline silicon layer using the same |
| CN101355090A (en) * | 2008-09-19 | 2009-01-28 | 友达光电股份有限公司 | Thin-film transistor array substrate and preparation method thereof |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104779171A (en) * | 2015-05-05 | 2015-07-15 | 京东方科技集团股份有限公司 | Low-temperature polycrystalline silicon thin film transistor, manufacturing method thereof, array substrate and display device |
| US9911618B2 (en) | 2015-05-05 | 2018-03-06 | Boe Technology Group Co., Ltd. | Low temperature poly-silicon thin film transistor, fabricating method thereof, array substrate and display device |
| CN105185792B (en) * | 2015-09-30 | 2018-11-23 | 深圳市华星光电技术有限公司 | Liquid crystal display panel, array substrate and its manufacturing method |
| CN105185792A (en) * | 2015-09-30 | 2015-12-23 | 深圳市华星光电技术有限公司 | LCD panel, array substrate and manufacturing method thereof |
| WO2017054259A1 (en) * | 2015-09-30 | 2017-04-06 | 深圳市华星光电技术有限公司 | Liquid crystal display panel, array substrate, and manufacturing method therefor |
| US10042211B2 (en) | 2015-09-30 | 2018-08-07 | Shenzhen China Star Optoelectronics Technology Co., Ltd | Liquid crystal display panel, array substrate and manufacturing method thereof |
| CN106684091A (en) * | 2015-11-09 | 2017-05-17 | 上海和辉光电有限公司 | Display panel, array substrate and manufacturing method of array substrate |
| CN105759527A (en) * | 2016-04-26 | 2016-07-13 | 上海天马有机发光显示技术有限公司 | Array substrate, manufacturing method of array substrate and display panel |
| CN106684101A (en) * | 2017-02-15 | 2017-05-17 | 厦门天马微电子有限公司 | Array substrate, display panel and display device |
| CN109003579A (en) * | 2018-07-12 | 2018-12-14 | 武汉华星光电半导体显示技术有限公司 | Dot structure |
| CN109659326A (en) * | 2019-01-02 | 2019-04-19 | 京东方科技集团股份有限公司 | A kind of array substrate and micro-total analysis device |
| CN109659326B (en) * | 2019-01-02 | 2021-05-18 | 京东方科技集团股份有限公司 | Array substrate and micro total analysis device |
| US11493435B2 (en) | 2019-01-02 | 2022-11-08 | Beijing Boe Technology Development Co., Ltd. | Array substrate and micro total analysis device |
| WO2020186448A1 (en) * | 2019-03-19 | 2020-09-24 | 深圳市柔宇科技有限公司 | Transparent display panel and display device |
| CN109962114A (en) * | 2019-04-17 | 2019-07-02 | 京东方科技集团股份有限公司 | Double grid TFT, pixel circuit and its control method |
| CN109962114B (en) * | 2019-04-17 | 2021-02-02 | 京东方科技集团股份有限公司 | Double-gate TFT, pixel circuit and control method thereof |
| US11475833B2 (en) | 2019-04-17 | 2022-10-18 | Beijing Boe Technology Development Co., Ltd. | Semiconductor apparatus, pixel circuit and control method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104538402B (en) | 2018-01-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104538402A (en) | Array substrate, manufacturing method thereof and display device | |
| US5895935A (en) | Display device having a switch with floating regions in the active layer | |
| TWI509810B (en) | Thin-film transistor,manufacturing method thereof, and liquid crystal display | |
| KR101827848B1 (en) | Thin film transistor and display divce using the same | |
| CN110164923B (en) | OLED display panel and preparation method thereof | |
| CN103472646A (en) | Array substrate, manufacturing method thereof and display device | |
| US10978495B2 (en) | Array substrate and method of manufacturing the same, and display device | |
| CN110676253B (en) | Electrostatic discharge circuit, array substrate, display panel and display device | |
| US20180197960A1 (en) | TFT array substrate, manufacturing method thereof, and liquid crystal display apparatus | |
| CN103996716A (en) | Poly-silicon thin film transistor and preparation method thereof, and array substrate | |
| US10042211B2 (en) | Liquid crystal display panel, array substrate and manufacturing method thereof | |
| WO2021073253A1 (en) | Thin film transistor and manufacturing method therefor, array substrate, and display apparatus | |
| CN104465673B (en) | Array base palte and its manufacture method and display device | |
| CN105304500A (en) | Manufacture method of N-type TFT (Thin Film Transistor) | |
| CN203480182U (en) | Array substrate and display device | |
| CN106505071B (en) | thin film transistor array substrate and manufacturing method thereof | |
| WO2022001468A1 (en) | Thin film transistor, display substrate and display apparatus | |
| JP3934173B2 (en) | Display device | |
| CN104538306A (en) | Manufacturing technology for transistor | |
| US20200105796A1 (en) | Array substrate, method for fabricating array substrate and display | |
| US9876120B2 (en) | Low temperature poly-silicon TFT substrate and manufacturing method thereof | |
| KR20150066134A (en) | Array substrate and method of fabricating the same | |
| CN114005881B (en) | Thin film transistor, preparation method thereof and pixel circuit | |
| CN112271185B (en) | Array substrate and preparation method thereof | |
| KR101001430B1 (en) | Thin film transistor and fabricating method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |