CN101355090A - Thin-film transistor array substrate and preparation method thereof - Google Patents
Thin-film transistor array substrate and preparation method thereof Download PDFInfo
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- CN101355090A CN101355090A CNA2008101615027A CN200810161502A CN101355090A CN 101355090 A CN101355090 A CN 101355090A CN A2008101615027 A CNA2008101615027 A CN A2008101615027A CN 200810161502 A CN200810161502 A CN 200810161502A CN 101355090 A CN101355090 A CN 101355090A
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Abstract
The invention provides a substrate for a thin film transistor (TFT) array and a method for manufacturing the same. The substrate for the TFT array comprises the substrate, a plurality of multicrystal silicon islands and a plurality of grid electrodes, wherein the substrate has a display zone, a grid electrode drive zone and a source electrode drive zone; the multicrystal silicon islands are arranged on the substrate, and each multicrystal silicon island has a source electrode zone, a drain electrode zone and a channel zone positioned between the source electrode zone and the drain electrode zone; moreover, the multicrystal silicon islands comprise a plurality of first multicrystal silicon islands and second multicrystal silicon islands, wherein the first multicrystal silicon islands are arranged inside the display zone and the grid electrode drive zone, and have major grain boundaries and minor grain boundaries, and the major grain boundaries is only positioned inside the source electrode zone and/or the drain electrode zone; the second multicrystal silicon islands are arranged inside the source electrode drive zone; the size of grain inside the first multicrystal silicon islands is different from that inside the second multicrystal silicon islands; and the grid electrodes are arranged on the substrate and are corresponding to the channel zone.
Description
Technical field
The invention relates to the manufacture method of a kind of semiconductor device array substrate and semiconductor device array substrate, and particularly relevant for the manufacture method of thin-film transistor array base-plate and thin-film transistor array base-plate.
Background technology
In recent years, increasingly mature along with photoelectric technology and semiconductor fabrication, flat-panel screens is just flourish, wherein LCD is based on advantage such as its low voltage operating, radiationless line scattering, in light weight and volume be little, replaces traditional cathode-ray tube display more gradually and becomes the main flow of display product in recent years.
Generally speaking, LCD can be divided into two kinds of amorphous silicon film transistor (amorphous silicon thinfilm transistor) LCD and low-temperature polysilicon film transistor (low temperaturepoly-silicon thin film transistor) LCD etc.Low-temperature polysilicon film transistor is compared to amorphous silicon film transistor, has higher electron mobility (approximately than high 2～3 orders of magnitude of amorphous silicon film transistor), therefore polycrystalline SiTFT is except as the pixel switch, more can be applicable to periphery circuit region, as the circuit that drives LCD.
In practical operation, as pixel switch with different as the required tft characteristics of drive circuit.Generally speaking, have relatively high expectations for the electrical uniformity as the thin-film transistor of pixel switch, as the thin-film transistor of drive circuit then need have high carrier transport factor (mobility) and high-reliability (reliability) electrically.Wherein, the element characteristic of thin-film transistor is relevant with crystalline form and crystallization position in its polysilicon film, and the crystalline form of polysilicon layer can be controlled according to different technology.Polysilicon membrane low temperature crystallization technology wherein, is the crystallization technique of present main flow with excimer laser crystallization (Excimer Laser Crystallization) again by extensive studies in recent years.
In order to obtain the good thin-film transistor of element characteristic, a kind of light pencil directivity crystallization (ThinBeam Directional X ' tallization, TDX) process quilt proposes, it mainly utilizes is to be installed additional by original excimer laser system to have time micron baseplate carrier that moves and high-accuracy optical system, again via following dual mode: (1) utilizes the mask slits size that laser beam is graphical, make and carried out side crystallization by both sides toward beginning central authorities by the amorphous silicon layer zone of laser radiation, and before oikocryst circle in the irradiated area forms as yet, mobile mask and make this sweep span be not more than 1/2nd of mask slits zone in single scanning spacing (scan pitch).(2) narrow with the laser beam length elongation and with width, make and carried out side crystallization by the minor axis both sides toward beginning central authorities by the amorphous silicon layer zone of laser radiation, and before oikocryst circle in the irradiated area forms as yet, in single scanning spacing (scan pitch) moving substrate microscope carrier and make this sweep span be not more than 1/2nd of laser minor axis width regions.Carry out above-mentioned (1) or (2) step so repeatedly, can control the zone of film lateral solidifcation crystallization, and make polysilicon grain grow up continuously and can not form oikocryst circle (main grain boundary), thereby can make polysilicon membrane with high crystalline quality, this polysilicon grain size can be greater than the crystal grain that utilizes traditional excimer laser crystallization gained.
Yet, in above-mentioned TDX laser crystallization technology, because laser beam irradiation is at the amorphous silicon layer that is positioned on the substrate, and moving substrate to be when carrying out the scan operation in the TDX laser crystal method, only can move the substrate that is not more than 1/2nd laser irradiation area territories during each moving substrate.So, when carrying out the scanning of TDX laser crystal method in one direction, not only need more laser radiation number of times (laser shot), it is many that the total degree of required moving substrate also becomes, thus, though can obtain high-quality polysilicon film, because the growth of process time is unfavorable for the lifting of production capacity.In addition, be all the single scanning spacing on moving substrate or the mask, though on the substrate polysilicon on the zones of different all identical, but need more laser radiation number of times (laser shot), it is many that the total degree of required moving substrate or mask also becomes, thus, though can obtain the polysilicon film of quality homogeneous, just oikocryst circle of the polysilicon of all positions all is that homogeneous distributes on substrate, still owing to the growth of process time, is unfavorable for the lifting of production capacity on the substrate.
Summary of the invention
The invention provides a kind of thin-film transistor array base-plate, described thin-film transistor array base-plate has the thin-film transistor of high carrier transport factor, and can promote the production capacity of product.
The invention provides a kind of manufacture method of thin-film transistor array base-plate, can make thin-film transistor, and improve process efficiency and promote production capacity with high carrier transport factor.
The present invention proposes a kind of thin-film transistor array base-plate, and this thin-film transistor array base-plate comprises substrate, a plurality of polysilicon island (poly-silicon islands) and a plurality of grid.Substrate has viewing area, gate driving district and source drive district.Polysilicon island is disposed on the substrate, and each polysilicon island has source area, drain region and the channel region between source area and drain region, polysilicon island comprises a plurality of first polysilicon islands and a plurality of second polysilicon island, wherein first polysilicon island is disposed in viewing area and the gate driving district, first polysilicon island has oikocryst circle and inferior crystal boundary, and oikocryst circle of first polysilicon island only is positioned at source area and/or drain region.Second polysilicon island is disposed in the source drive district, and the crystallite dimension in first polysilicon island is different from the crystallite dimension in second polysilicon film.Gate configuration is on substrate, and corresponding to channel region.
The present invention proposes a kind of manufacture method of thin-film transistor array base-plate in addition, and it comprises the following steps.At first, provide a substrate, and have viewing area, gate driving district and source drive district on the substrate.Afterwards, form amorphous silicon layer on substrate.Then, by laser radiation amorphous silicon tunic, to form polysilicon layer, wherein have a plurality of oikocrysts circle and a plurality of crystal boundaries in the polysilicon layer, and the crystallite dimension that is positioned at the polysilicon layer in viewing area and gate driving district is different from the crystallite dimension of the polysilicon layer that is positioned at the source drive district.Afterwards, the patterned polysilicon layer is to form a plurality of polysilicon islands, and the polysilicon island that wherein is positioned at viewing area and gate driving district constitutes a plurality of first polysilicon islands, and the polysilicon island that is positioned at the source drive district constitutes a plurality of second polysilicon islands.Then, respectively at defining source area, drain region and the channel region between source area and drain region in each first polysilicon island and in each second polysilicon island, wherein oikocryst circle of each first polysilicon island only is positioned at the source area and/or the drain region of each first polysilicon island.Afterwards, form a plurality of grids on substrate, with corresponding to channel region.
In one embodiment of this invention, above-mentionedly form in the step of polysilicon layer by laser radiation amorphous silicon tunic, the crystallite dimension of the formed polysilicon layer of zones of different in viewing area and gate driving district is multiple.At this moment, viewing area and gate driving district comprise a first area and a second area at least, first polysilicon island that wherein is formed in the first area has first crystallite dimension, first polysilicon island that is formed in the second area has second crystallite dimension, and first crystallite dimension is different from second crystallite dimension.
In one embodiment of this invention, the above-mentioned method that forms polysilicon layer by the laser radiation amorphous silicon layer comprises the following steps.At first, provide a laser, laser has the light beam district that width is W.Then, make the laser radiation amorphous silicon layer, so that by a part of fusion of amorphous silicon layer.Afterwards, make laser with respect to amorphous silicon layer displacement D1, D1＜0.5W wherein, and make the laser radiation amorphous silicon layer.Then, make laser with respect to amorphous silicon layer displacement D2, D2 〉=0.5W wherein, and make the laser radiation amorphous silicon layer.Wherein, above-mentioned make laser with respect to amorphous silicon layer displacement D1 and the step that makes the laser radiation amorphous silicon layer for example for repeatedly.In addition, laser with respect to amorphous silicon layer displacement D1 and the step that makes the laser radiation amorphous silicon layer in fact more than laser with respect to amorphous silicon layer displacement D2.
In one embodiment of this invention, the manufacture method of thin-film transistor array base-plate more comprises a plurality of source electrodes of formation and a plurality of drain electrode, and source electrode is electrically connected with the source area of polysilicon island respectively, and drain electrode is electrically connected with the drain region of polysilicon island respectively.In addition, the manufacture method of thin-film transistor array base-plate can also be after forming source electrode and drain electrode, more form dielectric layer with cover gate and gate insulation layer, wherein dielectric layer has a plurality of openings, and source electrode is electrically connected with the drain region with corresponding source area via opening respectively with drain electrode.
In one embodiment of this invention, the manufacture method of thin-film transistor array base-plate more comprises a plurality of pixel electrodes of formation, is electrically connected with drain electrode respectively.
Based on above-mentioned, in thin-film transistor array base-plate of the present invention, because oikocryst circle of first polysilicon island only is arranged in the source area and the drain region of thin-film transistor, there is not oikocryst circle in channel region in the thin-film transistor, so the carrier transport factor height of channel region, the element characteristic of thin-film transistor is good.And the manufacture method of thin-film transistor array base-plate of the present invention so thin-film transistor array base-plate of the present invention and preparation method thereof can be taken into account the carrier transport factor of channel layer in the thin-film transistor simultaneously, and the output usefulness of product.
Description of drawings
Figure 1A is the schematic diagram of the thin-film transistor array base-plate of one embodiment of the invention.
Figure 1B is along the generalized section of AA, BB and CC hatching among Figure 1A.
Fig. 2 illustrates the crystal grain ordered state figure of polysilicon film after crystallization into the thin-film transistor of first embodiment of the invention.
Fig. 3 A～Fig. 3 F is the manufacture method of the thin-film transistor array base-plate of one embodiment of the invention.
Fig. 4 A～Fig. 4 D is a kind of method that forms polysilicon layer by laser L irradiation amorphous silicon layer of the present invention.
Fig. 5 A is that the thin-film transistor array base-plate of second embodiment of the invention is along AA, the BB of Figure 1A, the generalized section of CC hatching.
Fig. 5 B is the crystal grain ordered state figure of polysilicon film after crystallization of the thin-film transistor of second embodiment of the invention.
Fig. 6 A is that the thin-film transistor array base-plate of third embodiment of the invention is along AA, the BB of Figure 1A, the generalized section of CC hatching.
Fig. 6 B is the crystal grain ordered state figure of polysilicon film after crystallization of the thin-film transistor of third embodiment of the invention.
Fig. 7 A is the thin-film transistor array base-plate of fourth embodiment of the invention along the generalized section of AA, the BB of Figure 1A, CC, DD hatching.
Fig. 7 B is the crystal grain ordered state figure of polysilicon film after crystallization of the thin-film transistor of fourth embodiment of the invention.
Drawing reference numeral
200,300,400,500: thin-film transistor array base-plate
210: substrate
210D: viewing area
210G: gate driving district
210S: source drive district
220: polysilicon island
220A, 220A ', 320A, 420A, 520A: first polysilicon island
220B, 320B, 420B, 520B: second polysilicon island
222: source area
224: the drain region
226: channel region
230: grid
240: gate insulation layer
250: dielectric layer
250H: opening
260S: source electrode
260D: drain electrode
270: pixel electrode
280: mask
280T: transparent area
290,390,490,590: amorphous silicon layer
292,392,492,592: polysilicon layer
MGB: oikocryst circle
SGB: inferior crystal boundary
D1, D2: relative movement distance
G1: first crystallite dimension
G2: second crystallite dimension
R1: first area
R2: second area
W: transparent area width
Embodiment
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, a plurality of embodiment cited below particularly, and cooperate appended accompanying drawing, be described in detail below.
First embodiment
Figure 1A is the schematic diagram of the thin-film transistor array base-plate of one embodiment of the invention, and Figure 1B is along the generalized section of AA, BB and CC hatching among Figure 1A.Please be simultaneously with reference to Figure 1A and Figure 1B, this thin-film transistor array base-plate 200 comprises substrate 210, a plurality of polysilicon island 220 and a plurality of grid 230 that is disposed on the substrate 210, wherein mainly be divided into viewing area 210D, gate driving district 210G and source drive district 210S on the substrate 210, and polysilicon island 220 comprises that a plurality of first polysilicon island 220A and a plurality of second polysilicon island 220B, the first polysilicon island 220A are disposed in viewing area 210D and the gate driving district 210G, and the second polysilicon island 220B is disposed in the source drive district 210S.
Please continue with reference to Figure 1B, each polysilicon island 220A, 220B have source area 222, drain region 224 and the channel region 226 between source area 222 and drain region 224 respectively, the first polysilicon island 220A has oikocryst circle MGB and inferior crystal boundary SGB, and the oikocryst circle MGB of the first polysilicon island 220A only is positioned at source area 222 and/or drain region 224.The second polysilicon island 220B is disposed in the source drive district 210S, and be different in essence crystallite dimension in second polysilicon film of the crystallite dimension among the first polysilicon island 220A.Grid 230 is disposed on the substrate 210, and in the present embodiment, grid 230 is to be disposed at channel region 226 tops accordingly, and gate insulation layer 240 is disposed between grid 230 and polysilicon layer 220A, the 220B.In the present embodiment, grid 230, channel region 226, source area 222 and drain region 224 constitute the thin-film transistor of a kind of top grid kenel, in other embodiments, grid 230 also can be disposed at channel region 226 belows accordingly, and constituting a kind of thin-film transistor of bottom-gate kenel, the present invention is not as limit.
In addition, thin-film transistor array base-plate 200 can optionally cover dielectric layer 250 in grid 230 and gate insulation layer 240 tops, and wherein dielectric layer 250 for example has a plurality of opening 250H.And on this dielectric layer 250, optionally dispose a plurality of source electrode 260S and a plurality of drain electrode 260D, wherein source electrode 260S is electrically connected with the source area 222 of polysilicon island 220 respectively, and drain electrode 260D is electrically connected with the drain region 224 of polysilicon island 220 respectively.In the present embodiment, thin-film transistor array base-plate 200 more comprises a plurality of pixel electrodes 270 that are electrically connected with drain electrode 260D respectively.
Specifically, shown in Figure 1B, the oikocryst circle MGB of the first polysilicon island 220A of the present invention only is positioned at source area 222 and/or drain region 224, in other words, in the channel region 226 of the first polysilicon island 220A, the interface of crystal grain and intergranule is mainly time crystal boundary SGB, there is no to have oikocryst circle MGB.Here be noted that herein so-called oikocryst circle MGB be polysilicon island 220 surfaces because of formed prominence in the crystal grain-growth process, as the A place among Figure 1B, and inferior crystal boundary SGB mostly is the recessed limit place on the surface of polysilicon island 220.Therefore, when the thin-film transistor with first polysilicon island 220A is in opening, carrier in the channel region 226 can successfully move in described district and can not sunk in the defective of (trap) oikocryst circle MGB, therefore the thin-film transistor that has the first polysilicon island 220A among the present invention has high carrier transport factor, make that be arranged in viewing area 210D has better display quality in order to the thin-film transistor as the switch of display unit, and, improve and to be arranged in gate driving district 210G in order to driving efficient as the thin-film transistor of gate driver circuit.
On the other hand, in order to promote the making production capacity of thin-film transistor array base-plate 200, during the layout designs of the thin-film transistor of designer on carrying out substrate 210 (layout design), the collocation polysilicon layer 220 crystallization processes and optionally allow the oikocryst circle MGB of the first polysilicon island 220A only appear at source area 222 and/or drain region 224, by this, significantly promote the production capacity of thin-film transistor array base-plate 200, about the technology of thin-film transistor array base-plate 200 will in after explanation in detail.Moreover, because carrier mainly is that doping content by the admixture in the polysilicon layer (dopant) is determined in source area 222 and mobility in the drain region 224, so oikocryst circle MGB comes across the element characteristic that can influence thin-film transistor in source area 222 and the drain region 224 hardly.Thus, compared to known technology, thin-film transistor array base-plate 200 of the present invention not only has the thin-film transistor of high mobility at viewing area 210D and gate driving district 210G, simultaneously can be so that the total degree of moving substrate 210 and laser radiation number of times tail off, and then significantly promote production capacity.
It should be noted that in the present embodiment in fact only have inferior crystal boundary SGB among the second polysilicon island 220B, meaning is that source area 222, drain region 224 only have inferior crystal boundary SGB with channel region 226.In other words, do not have oikocryst circle MGB among the second polysilicon island 220B, thereby the crystallite dimension of the second polysilicon island 220B is roughly along the length distance L on its channel direction, and, in the present embodiment, the crystallite dimension of the second polysilicon island 220B is in fact greater than the crystallite dimension in first polysilicon film.Therefore for the thin-film transistor among the source drive district 210S, the second polysilicon island 220B that does not have oikocryst circle MGB provides the conducting path of carrier one ultralow resistance, make carrier be able to migration in channel region 226 successfully, thereby help to promote the element characteristic of thin-film transistor, especially for for the thin-film transistor of source electrode drive circuit, this polycrystalline silicon membrane that does not have oikocryst circle MGB more can be at shorter thin-film transistor in the opening time, predetermined data voltage promptly is passed in the pairing plurality of source regions 222 of viewing area 210D, helps the lifting of the display quality of viewing area 210D.
For clearly demonstrating the first polysilicon island 220A and the crystal grain ordered state of the second polysilicon island 220B on substrate 210, Fig. 2 illustrates the crystal grain ordered state figure of polysilicon film 292 after crystallization into the thin-film transistor of first embodiment of the invention.Please refer to Fig. 2, be arranged in source drive district 210S, the predetermined polysilicon film 292 that forms the second polysilicon island 220B does not have oikocryst circle MGB, so behind the polysilicon island 220 in this district of patterning, promptly constitutes the second polysilicon island 220B that does not have oikocryst circle MGB shown in Figure 1A and Figure 1B.As shown in Figure 2, be arranged in viewing area 210D and gate driving district 210G, oikocryst circle MGB in the polysilicon film of the predetermined formation first polysilicon island 220A is to be the spacing periodic arrangement of S1 with length, therefore as long as the formation position of suitable layout thin-film transistor on substrate 210, can be behind the polysilicon island 220 that patterning should be distinguished, constitute the first polysilicon island 220A that oikocryst circle MGB only comes across source area 222 and/or drain region 224, certainly, can also not have oikocryst circle MGB among the first polysilicon island 220A of part, as the predetermined formation location mark place of the first polysilicon island 220A ' that is arranged in the viewing area among Fig. 2, the present invention is not as limit.
To be example with the thin-film transistor array base-plate 200 of Figure 1A and Figure 1B below, the crystalline state schematic diagram of polysilicon film of collocation Fig. 2 illustrates the manufacture method of thin-film transistor array base-plate 200.Fig. 3 A～Fig. 3 F is the manufacture method of the thin-film transistor array base-plate of one embodiment of the invention.
Please refer to Fig. 3 A, substrate 210 at first be provided, and have viewing area 210D on the substrate 210, gate driving district 210G and source drive district 210S.Afterwards, form amorphous silicon layer 290 on substrate 210.Then, by laser L irradiation amorphous silicon layer 290.Afterwards, shown in Fig. 3 B, form polysilicon layer 292, wherein the vertical view of this polysilicon layer 292 as shown in Figure 2.Please be simultaneously with reference to Fig. 2 and Fig. 3 B, have a plurality of oikocryst circle MGB and a plurality of crystal boundary SGB in the polysilicon layer 292, and the crystallite dimension S1 that is positioned at the polysilicon layer 292 of viewing area 210D and gate driving district 210G is different in essence in the crystallite dimension S2 of the polysilicon layer 292 that is positioned at source drive district 210S.In the present embodiment, in source drive district 210S, only has inferior crystal boundary SGB in the formed polysilicon layer 292 and dereliction crystal boundary MGB.And the crystallite dimension S2 among the second polysilicon island 220B is in fact greater than the crystallite dimension S1 among the first polysilicon island 220A.
Afterwards, please refer to Fig. 3 C, after patterned polysilicon layer 292, form a plurality of polysilicon islands 220, the polysilicon island 220 that wherein is positioned at viewing area 210D and gate driving district 210G constitutes a plurality of first polysilicon island 220A, and the polysilicon island 220 that is positioned at source drive district 210S constitutes a plurality of second polysilicon island 220B.
Then, please refer to Fig. 3 D, respectively at defining source area 222 among each first polysilicon island 220A with among each second polysilicon island 220B, the channel region 226 of drain region 224 and between source area 222 and drain region 224, make the oikocryst circle MGB of each first polysilicon island 220A only be positioned at source area 222 and/or the drain region 224 of each first polysilicon island 220A, and it is above-mentioned in order to definition source area 222, the method of drain region 224 and channel region 226 for example is via ion doping technology, wherein this ion doping technology for example is to use a patterning photoresist layer (not illustrating) that exposes source area 222 and drain region 224 to be the cover curtain, and being patterned photoresist layer (not illustrating), channel region 226 do not expose, undertaken after an energetic ion impacts polysilicon surface by sputtering technology, remove described patterning photoresist layer again, to form source area 222, drain region 224 and the channel region 226 between source area 222 and drain region 224.
Afterwards, please refer to Fig. 3 E, in the first polysilicon island 220A and second polysilicon island 220B top covering gate insulating barrier 240, wherein gate insulation layer 240 for example is by chemical vapour deposition technique (chemicalvapor deposition, CVD) or other suitable film deposition techniques form, and gate insulation layer 240 is the single or multiple lift structure, and its material for example is a silica, silicon nitride, silicon oxynitride, photoresist, benzocyclobutene, the cyclenes class, polyimide, polyamide-based, polyesters, polyalcohols, the poly(ethylene oxide) class, the polyphenyl class, resinae, polyethers, dielectric materials such as polyketone class, or other suitable material, or above-mentioned combination.And, form a plurality of grids 230 accordingly in channel region 226 tops, make grid 230, channel region 226, source area 222 and drain region 224 constitute thin-film transistor, wherein grid 230 for example is by sputter (sputtering), evaporation (evaporation) or other film deposition techniques form, grid 230 is the single or multiple lift structure, and its material for example is aluminium (Al), molybdenum (Mo), titanium (Ti), neodymium (Nd), above-mentioned nitride such as molybdenum nitride (MoN), titanium nitride (TiN), its laminated, above-mentioned alloy or other electric conducting materials.
Then, please refer to Fig. 3 F, in the present embodiment, on thin-film transistor, optionally form dielectric layer 250, with cover gate 230 and gate insulation layer 240, and the described dielectric layer 250 of patterning, make dielectric layer 250 have a plurality of opening 250H.Then, optionally form source electrode 260S and drain electrode 260D on dielectric layer 250, make source electrode 260S be electrically connected with the source area 222 of polysilicon island 220 respectively, drain electrode 260D is electrically connected with the drain region 224 of polysilicon island 220 respectively.Be electrically connected with drain region 224 with corresponding source area 222 via opening 250H respectively.Then, in the present embodiment, more can in the 210D of viewing area, form one and expose the protective layer 268 of drain electrode 260D, and on protective layer 268, form a pixel electrode 270 that is electrically connected with drain electrode 260D.Must it should be noted that, the described manufacturing process of Fig. 3 A～3F of present embodiment, constitute the thin-film transistor of a kind of top grid kenel with grid 230, channel region 226, source area 222 and drain region 224, in other embodiments, grid 230 also can be disposed at channel region 226 belows accordingly, and constituting a kind of thin-film transistor of bottom-gate kenel, the present invention is not as limit.
More specifically, Fig. 4 A～Fig. 4 D is a kind of method that forms polysilicon layer by laser L irradiation amorphous silicon layer of the present invention.Please, for example comprise the following steps earlier with reference to Fig. 4 A.At first, mask 280 is provided, wherein mask 280 has the transparent area 280T that width is W, and make laser L via transparent area 280T irradiation amorphous silicon layer 290, so that amorphous silicon layer 290 fusions of being shone by laser L, and the amorphous silicon layer 290 of fusion can be a crystal seed with the solid-state amorphous silicon of both sides, irradiated area, by two side direction irradiated area center side to growth.
Afterwards, the step shown in Fig. 4 B (A), wherein step (A) is for making mask 280 with respect to amorphous silicon layer 290 displacement D1, wherein D1＜0.5W earlier.Afterwards, make laser L via transparent area 280T irradiation amorphous silicon layer 290.Implementation step (A) will make the zone of being shone by laser L continue side direction along the polysilicon grain of having grown up to grow up, so repeat above-mentioned (A) step, can so that crystal grain continuity ground under the situation that does not form oikocryst circle MGB grow up.Wherein, mask 280 is with respect to amorphous silicon layer 290 situation of movement, comprise: mask 280 moves amorphous silicon layer 290 moves and the motionless situation of amorphous silicon layer 290 or mask 280 are motionless situation or mask 280 and moves and amorphous silicon layer 290 moves to other direction to a certain direction, and wherein other direction is different in essence in the situation of a certain direction.Embodiments of the invention move with mask 280, and amorphous silicon layer 290 motionless be example, but be not limited thereto.
Then, the step shown in Fig. 4 C (B), wherein step (B) is for making mask 280 with respect to amorphous silicon layer 290 displacement D2, wherein D2 〉=0.5W earlier.Afterwards, make laser L via transparent area 280T irradiation amorphous silicon layer 290.Because the rate of travel of mask 280 and amorphous silicon layer 290 is in fact greater than 1/2nd of transparent area 280T, so during implementation step (B), the central authorities of once irradiated amorphous silicon layer 290 before oikocryst circle MGB will be formed at.
Afterwards, shown in Fig. 4 D, step (A) back collocation step (B) of Repeated m time, and the program of step (A) back step of collocation (B) that will above-mentioned Repeated m time operates for several times back and forth, and formation oikocryst circle MGB is that periodic arrangement and constant spacing are the polysilicon layer 290 of S1.
It should be noted that above-mentioned recrystallized amorphous silicon mode also can not use mask, but the width that laser beam is parallel to moving direction is narrowed, and elongate the length of laser beam vertical moving direction, reach identical purpose.In other words, do not use mask to make the step of polysilicon, comprise that (A) provides a laser, described laser has the light beam district that a width is W; (B) make the described amorphous silicon layer of described laser radiation, so that by a part of fusion of described amorphous silicon layer; (C) make described laser move a distance D 1 with respect to described amorphous silicon layer, D1＜0.5W wherein, and make the described amorphous silicon layer of described laser radiation; And (D) make described laser move a distance D 2 with respect to described amorphous silicon layer, D2 〉=0.5W wherein, and make this amorphous silicon layer of described laser radiation.Other step or detailed step are same as step that need to use mask, in this superfluous words no longer.Must it should be noted that the light beam district chi inch of laser is same as the above-mentioned transparent area 280T chi inch that needs to use mask in fact.
On the practice, can be according to substrate size, thin-film transistor size and the predetermined position that forms, and repeatedly use above-mentioned steps (A) repeatedly so that crystal grain under the situation that does not form oikocryst circle MGB, grow up, and according to the predetermined formation position of oikocryst circle MGB the in good time once above-mentioned step (B) of collocation, with the formation of oikocryst circle MGB in the control polysilicon layer 292 and shorten and make time-histories.For example, in the present embodiment, amorphous silicon layer 290 among the source drive district 210S is transformed in the step of polysilicon layer 292, for example be repeatedly to use above-mentioned steps (A), only have inferior crystal boundary SGB and dereliction crystal boundary MGB so that be arranged in the structure of the polysilicon layer 292 of source drive district 210S.On the other hand, amorphous silicon layer 290 among viewing area 210D and the gate driving district 210G is transformed in the step of polysilicon layer 292, it for example is inferior step (A) the back collocation step (B) of Repeated m, and the program of a step of collocation (B) is operated for several times back and forth after the step (A) that above-mentioned Repeated m is inferior, is that periodic arrangement and spacing are the polysilicon layer 292 of S1 to form oikocryst circle MGB.
The user can arrange in pairs or groups according to product resolution, product size, production production capacity or other demands and select above-mentioned suitable polysilicon crystal step for use, so that the oikocryst circle MGB among the first polysilicon island 220A only comes across source area 222 and/or drain region 224, thus, not only can obtain the thin-film transistor of high carrier migration, on the other hand, can promote the making usefulness of thin-film transistor array base-plate 200.Below enumerate several thin-film transistor array base-plates of the present invention 200 again, and the crystal grain ordered state figure of polysilicon film after crystallization of the thin-film transistor of collocation different embodiments of the invention, to clearly demonstrate the crystalline form of polysilicon on different substrate 210.
Second embodiment
Fig. 5 A is that the thin-film transistor array base-plate of second embodiment of the invention is along AA, the BB of Figure 1A, the generalized section of CC hatching.Please refer to Fig. 5 A, be simplified illustration, no longer described these and aforementioned similar member are explained.Compare with previous embodiment, the second polysilicon island 320B of the thin-film transistor array base-plate 300 of present embodiment has oikocryst circle MGB and inferior crystal boundary SGB, and the oikocryst circle MGB of the second polysilicon island 320B only is positioned at source area 222 and/or drain region 224, in other words, there is no oikocryst circle MGB in the channel region 226 of the second polysilicon island 320B exists.The oikocryst circle MGB of the second polysilicon island 320B and the formation position of inferior crystal boundary SGB for example can be controlled by the aforesaid sweep span of modulation.And in the present embodiment, the crystallite dimension among the second polysilicon island 320B of thin-film transistor array base-plate 300 is in fact greater than the crystallite dimension in first polysilicon film.
Fig. 5 B illustrates the crystal grain ordered state figure of polysilicon film after crystallization into the thin-film transistor of second embodiment of the invention.Please refer to Fig. 5 B, be arranged in source drive district 210S, the predetermined polysilicon film that forms the second polysilicon island 320B has oikocryst circle MGB and inferior crystal boundary SGB, therefore behind the polysilicon island that patterning should be distinguished, the oikocryst circle MGB that promptly constitutes shown in Fig. 5 A only is positioned at the source area 222 of the second polysilicon island 320B and/or the kenel of drain region 224 with time crystal boundary SGB, and the oikocryst circle MGB of the second polysilicon island 320B is to be the spacing periodic arrangement of S2 with length.Shown in Fig. 5 A, be arranged in viewing area 210D and gate driving district 210G, the oikocryst circle MGB in the polysilicon film of the predetermined formation first polysilicon island 320A is to be the spacing periodic arrangement of S1 with length, and S2＞S1.Therefore as long as the formation position of suitable layout thin-film transistor on substrate 210, can be behind the polysilicon island that patterning should be distinguished, constitute the first polysilicon island 320A that oikocryst circle MGB only comes across source area 222 and/or drain region 224, and oikocryst circle MGB only comes across the second polysilicon island 320B of source area 222 and/or drain region 224.
When making the polysilicon layer 392 of present embodiment such as Fig. 5 B with aforementioned method by laser L irradiation amorphous silicon layer 290, it for example is step (A) back collocation step (B) of n time, and the program of step (A) the back step of collocation (B) of above-mentioned repetition n time operated for several times back and forth, to form oikocryst circle MGB is that periodic arrangement and spacing are the polysilicon layer 392 of S2, make the polysilicon layer 392 in this district behind follow-up Patternized technique, form the second polysilicon island 320B as Fig. 5 A, wherein the oikocryst circle MGB among the second polysilicon island 320B only is arranged in source area 222 and/or drain region 224.So, can further promote the production capacity of thin-film transistor, and obtain the thin-film transistor of high element characteristic.On the other hand, amorphous silicon layer 390 among viewing area 210D and the gate driving district 210G is transformed in the step of polysilicon layer 392, it for example is inferior step (A) the back collocation step (B) of Repeated m, and the program of the step (A) that above-mentioned Repeated m is an inferior back step of collocation (B) is operated for several times back and forth, to form oikocryst circle MGB is that periodic arrangement and spacing are the polysilicon layer 392 of S1, make the polysilicon layer 392 in this district behind follow-up Patternized technique, form the first polysilicon island 220A as Fig. 5 B, wherein the oikocryst circle MGB among the first polysilicon island 220A only is arranged in source area 222 and/or drain region 224.And, in the present embodiment, in the crystallisation step of above-mentioned polysilicon layer 392, n＞m, so, oikocryst circle MGB interval S 2＞S1 in the polysilicon layer 392 after the crystallization makes that the crystallite dimension among the second polysilicon island 320B is in fact greater than the crystallite dimension in first polysilicon film after the patterned polysilicon layer 392.
The 3rd embodiment
Fig. 6 A is that the thin-film transistor array base-plate of third embodiment of the invention is along AA, the BB of Figure 1A, the generalized section of CC hatching.Please refer to Fig. 6 A, be simplified illustration, no longer described these and aforementioned similar member are explained.Compare with second embodiment, the oikocryst circle MGB of the second polysilicon island 420B of the thin-film transistor array base-plate 400 of present embodiment only is positioned at source area 222 and/or drain region 224, in other words, there is no oikocryst circle MGB in the channel region 226 of the second polysilicon island 420B exists.And in the present embodiment, the crystallite dimension among the second polysilicon island 420B of thin-film transistor array base-plate 400 is in fact less than the crystallite dimension in first polysilicon film.
Fig. 6 B illustrates the crystal grain ordered state figure of polysilicon film after crystallization into the thin-film transistor of third embodiment of the invention.Please refer to Fig. 6 B, be arranged in source drive district 210S, have oikocryst circle MGB and inferior crystal boundary SGB in the polysilicon film of the predetermined formation second polysilicon island 420B, therefore behind the polysilicon island that patterning should be distinguished, the oikocryst circle MGB that promptly constitutes as shown in Figure 6A only is positioned at the source area 222 of the second polysilicon island 420B and/or the kenel of drain region 224 with time crystal boundary SGB, and the oikocryst circle MGB of the second polysilicon island 420B is to be the spacing periodic arrangement of S2 with length.As shown in Figure 6A, be arranged in viewing area 210D and gate driving district 210G, the oikocryst circle MGB in the polysilicon film of the predetermined formation first polysilicon island 420A is to be the spacing periodic arrangement of S1 with length, and S2＜S1.
When making the polysilicon layer 492 of present embodiment such as Fig. 6 B with aforementioned method by laser L irradiation amorphous silicon layer 290, it for example is step (A) back collocation step (B) of n time, and the program of step (A) the back step of collocation (B) of above-mentioned repetition n time operated for several times back and forth, be that periodic arrangement and spacing are the polysilicon layer 492 of S2 to form oikocryst circle MGB.On the other hand, amorphous silicon layer 490 among viewing area 210D and the gate driving district 210G is transformed in the step of polysilicon layer 492, it for example is inferior step (A) the back collocation step (B) of Repeated m, and the program of a step of collocation (B) is operated for several times back and forth after the step (A) that above-mentioned Repeated m is inferior, is that periodic arrangement and spacing are the polysilicon layer 492 of S1 to form oikocryst circle MGB.And, in the present embodiment, in the crystallisation step of above-mentioned polysilicon layer 492, n＜m, so, oikocryst circle MGB interval S 2＜S1 in the polysilicon layer 492 after the crystallization makes that the crystallite dimension among the second polysilicon island 420B is in fact less than the crystallite dimension in first polysilicon film after the patterned polysilicon layer 492.
The 4th embodiment
Fig. 7 A is that the thin-film transistor array base-plate of fourth embodiment of the invention is along AA, the CC of Figure 1A, the generalized section of DD hatching.Please refer to Fig. 7 A, be simplified illustration, no longer described these and aforementioned similar member are explained.Compare with previous embodiment, the second polysilicon island 520B of the thin-film transistor array base-plate 500 of present embodiment only has inferior crystal boundary SGB, and the crystallite dimension of the first polysilicon island 520A is multiple.
Fig. 7 B illustrates the crystal grain ordered state figure of polysilicon film after crystallization into the thin-film transistor of fourth embodiment of the invention.Please refer to Fig. 7 B, be arranged in source drive district 210S in the present embodiment, the predetermined polysilicon film that forms the second polysilicon island 520B only has inferior crystal boundary SGB, and its explanation and production method repeat no more with in the preamble explanation.Specifically, please be simultaneously with reference to Figure 1A, Fig. 7 A and Fig. 7 B, viewing area 210D and gate driving district 210G comprise a first area R1 and a second area R2, the first polysilicon island 520A that wherein is arranged in first area R1 has the first crystallite dimension G1, the first polysilicon island 520A that is arranged in second area R2 has one second crystallite dimension G2, and the first crystallite dimension G1 is different from the second crystallite dimension G2.Wherein, first area R1 and the layout type of second area R2 on thin-film transistor array base-plate are decided on the element demand.
In detail, when making the polysilicon film of present embodiment such as Fig. 7 B with aforementioned method by laser L irradiation amorphous silicon layer 290, amorphous silicon layer among the R1 of first area is transformed in the step of polysilicon layer 592, it for example is step (A) back collocation step (B) of Repeated m 1 time, and the program of step (A) the back step of collocation (B) of above-mentioned Repeated m 1 time operated for several times back and forth, be that periodic arrangement and spacing are the polysilicon layer 592 of S1 to form oikocryst circle MGB.And, amorphous silicon layer among the second area R2 is being transformed in the step of polysilicon layer 592, it for example is step (A) back collocation step (B) of Repeated m 2 times, and the program of step (A) the back step of collocation (B) of above-mentioned Repeated m 2 times operated for several times back and forth, with form oikocryst circle MGB be periodic arrangement and spacing be S3 polysilicon layer 592 in the present embodiment, m1＜m2 in the crystallisation step of above-mentioned polysilicon layer 592, so, oikocryst circle MGB interval S 1＜S3 in the polysilicon layer 592 after the crystallization, make after the patterned polysilicon layer 592 that the crystallite dimension G1 of the first polysilicon island 520A that is arranged in first area R1 is in fact less than the crystallite dimension G2 of first polysilicon film that is arranged in second area R2.
Certainly, in the crystallisation step of above-mentioned polysilicon layer 592, m1 also can be greater than m2, and make the crystallite dimension of the first polysilicon island 520A be arranged in first area R1 in fact greater than the crystallite dimension of first polysilicon film that is arranged in second area R2, look closely product demand and decide, the present invention is not as limit.
In sum, thin-film transistor array base-plate of the present invention and preparation method thereof comprises the whole or a part of of following advantage at least:
(1) because oikocryst circle of first polysilicon island only is arranged in the source area and/or the drain region of thin-film transistor, there is not oikocryst circle in channel region in the thin-film transistor, so the carrier transport factor height of channel region, the thin-film transistor on the thin-film transistor array base-plate has high mobility and high reliability.
(2) because the manufacture method of thin-film transistor array base-plate of the present invention can be carried out the step of different scanning spacing according to the layout designs of thin-film transistor.Therefore, and reduce laser radiation number of times and moving substrate number of times, to promote process efficiency and production capacity effectively.
(3) in thin-film transistor array base-plate of the present invention, oikocryst circle of polysilicon is visual should the transistorized electrical demand in zone and optionally be disposed in the specific localized areas, in other words, the grain size of polysilicon is for changing according to each different operating characteristic in zone on the thin-film transistor array base-plate, and therefore thin-film transistor array base-plate of the present invention can have element characteristic performance and process efficiency concurrently.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any affiliated technical field technical staff, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion with claim institute confining spectrum.
Claims (25)
1. a thin-film transistor array base-plate is characterized in that, described thin-film transistor array base-plate comprises:
One substrate has a viewing area, a gate driving district and one source pole and drives the district;
A plurality of polysilicon islands are disposed on the described substrate, and each described polysilicon island has one source pole district, the channel region of a drain region and between described source area and described drain region, and described these polysilicon islands comprise:
A plurality of first polysilicon islands, be disposed in described viewing area and the described gate driving district, described these first polysilicon islands have oikocryst circle and a crystal boundary, and oikocryst circle of described these first polysilicon islands only is positioned at described these source areas and/or described these drain regions;
A plurality of second polysilicon islands are disposed in the described source drive district, and the crystallite dimension in described first polysilicon island is different from the crystallite dimension in described second polysilicon film; And
A plurality of grids are disposed on the described substrate, and corresponding to described these channel regions.
2. thin-film transistor array base-plate as claimed in claim 1 is characterized in that, in fact only has inferior crystal boundary in described these second polysilicon islands.
3. thin-film transistor array base-plate as claimed in claim 1 is characterized in that, the crystallite dimension of each described second polysilicon island is along the length distance on its channel direction.
4. thin-film transistor array base-plate as claimed in claim 1, it is characterized in that, described these second polysilicon islands have oikocryst circle and a crystal boundary, and oikocryst circle of wherein said these second polysilicon islands only is positioned at described these source areas or described these drain regions.
5. thin-film transistor array base-plate as claimed in claim 4 is characterized in that, the crystallite dimension in described these second polysilicon islands is in fact greater than the crystallite dimension in described first polysilicon film.
6. thin-film transistor array base-plate as claimed in claim 4 is characterized in that, the crystallite dimension in described these second polysilicon islands is in fact less than the crystallite dimension in described first polysilicon film.
7. thin-film transistor array base-plate as claimed in claim 1 is characterized in that, the crystallite dimension of described these first polysilicon islands is multiple.
8. thin-film transistor array base-plate as claimed in claim 7, it is characterized in that, described viewing area and described gate driving district comprise the first area and the second area away from described source drive district in a contiguous described source drive district, described these first polysilicon islands that wherein are arranged in described first area have one first crystallite dimension, described these first polysilicon islands that are arranged in described second area have one second crystallite dimension, and described first crystallite dimension is different from described second crystallite dimension.
9. thin-film transistor array base-plate as claimed in claim 1, it is characterized in that, described thin-film transistor array base-plate more comprises a plurality of source electrodes and a plurality of drain electrode, wherein said these source electrodes are electrically connected with the source area of described these polysilicon islands respectively, and described these drain electrodes are electrically connected with the drain region of described these polysilicon islands respectively.
10. thin-film transistor array base-plate as claimed in claim 9, it is characterized in that, described thin-film transistor array base-plate more comprises a dielectric layer, cover described these grids and described gate insulation layer, wherein said dielectric layer has a plurality of openings, and described these source electrodes are electrically connected with described drain region with corresponding described source area via described these openings respectively with described these drain electrodes.
11. thin-film transistor array base-plate as claimed in claim 1 is characterized in that, described thin-film transistor array base-plate more comprises a plurality of pixel electrodes, and wherein said these pixel electrodes are electrically connected with described these drain electrodes respectively.
12. the manufacture method of a thin-film transistor array base-plate is characterized in that, the manufacture method of described thin-film transistor array base-plate comprises:
One substrate is provided, has a viewing area, a gate driving district and one source pole on the described substrate and drive the district;
Form an amorphous silicon layer on described substrate;
Shine described amorphous silicon tunic by a laser L, to form a polysilicon layer, have a plurality of oikocrysts circle and a plurality of crystal boundaries in the wherein said polysilicon layer, and the crystallite dimension that is positioned at the polysilicon layer in described viewing area and described gate driving district is different from the crystallite dimension of the polysilicon layer that is positioned at described source drive district;
The described polysilicon layer of patterning is to form a plurality of polysilicon islands, described these polysilicon islands that wherein are positioned at described viewing area and described gate driving district constitute a plurality of first polysilicon islands, and described these polysilicon islands that are positioned at described source drive district constitute a plurality of second polysilicon islands;
Respectively at defining one source pole district, the channel region of a drain region and between described source area and drain region in each described first polysilicon island and in each described second polysilicon island, wherein oikocryst circle of each described first polysilicon island only is positioned at the source area and/or the drain region of each described first polysilicon island; And
Form a plurality of grids on described substrate, with corresponding to described these channel regions.
13. the manufacture method of thin-film transistor array base-plate as claimed in claim 12 is characterized in that, the method that defines described these source areas, described these drain regions and described these channel regions comprises via an ion doping technology.
14. the manufacture method of thin-film transistor array base-plate as claimed in claim 12, it is characterized in that, shine described amorphous silicon tunic by described laser L and form in the step of described polysilicon layer, formed described polysilicon layer only has inferior crystal boundary in described source drive district.
15. the manufacture method of thin-film transistor array base-plate as claimed in claim 12 is characterized in that, the crystallite dimension of each described second polysilicon island is along the length distance on its channel direction.
16. the manufacture method of thin-film transistor array base-plate as claimed in claim 12, it is characterized in that, shine described amorphous silicon tunic by described laser L and form in the step of described polysilicon layer, described oikocryst circle in described source drive district in the formed described polysilicon layer only is positioned at described these source areas or described these drain regions of described these second polysilicon islands.
17. the manufacture method of thin-film transistor array base-plate as claimed in claim 16 is characterized in that, the crystallite dimension in described these second polysilicon islands is in fact greater than the crystallite dimension in described these first polysilicon islands.
18. the manufacture method of thin-film transistor array base-plate as claimed in claim 16 is characterized in that, the crystallite dimension in described these second polysilicon islands is in fact less than the crystallite dimension in described these first polysilicon films.
19. the manufacture method of thin-film transistor array base-plate as claimed in claim 12, it is characterized in that, shine described amorphous silicon tunic by described laser L and form in the step of described polysilicon layer, the crystallite dimension of the formed described polysilicon layer of zones of different in described viewing area and described gate driving district is multiple.
20. the manufacture method of thin-film transistor array base-plate as claimed in claim 19, it is characterized in that, described viewing area and described gate driving district comprise a first area and a second area, described these first polysilicon islands that wherein are formed in the described first area have one first crystallite dimension, described these first polysilicon islands that are formed in the described second area have one second crystallite dimension, and described first crystallite dimension is different from described second crystallite dimension.
21. the manufacture method of thin-film transistor array base-plate as claimed in claim 12 is characterized in that, shines the method that described amorphous silicon layer forms described polysilicon layer by described laser L and comprises:
One laser is provided, and described laser has the light beam district that a width is W;
Make the described amorphous silicon layer of described laser radiation, so that by a part of fusion of described amorphous silicon layer;
Make described laser move a distance D 1 with respect to described amorphous silicon layer, D1＜0.5W wherein, and make the described amorphous silicon layer of described laser radiation; And
Make described laser move a distance D 2 with respect to described amorphous silicon layer, D2 〉=0.5W wherein, and make the described amorphous silicon layer of described laser radiation.
22. the manufacture method of thin-film transistor array base-plate as claimed in claim 21 is characterized in that, make described laser move described distance D 1 with respect to described amorphous silicon layer and the step of shining described laser for repeatedly.
23. the manufacture method of thin-film transistor array base-plate as claimed in claim 12, it is characterized in that, the manufacture method of described thin-film transistor array base-plate more comprises a plurality of source electrodes of formation and a plurality of drain electrode, described these source electrodes are electrically connected with the source area of described these polysilicon islands respectively, and described these drain electrodes are electrically connected with the drain region of described these polysilicon islands respectively.
24. the manufacture method of thin-film transistor array base-plate as claimed in claim 23, it is characterized in that, the manufacture method of described thin-film transistor array base-plate more forms a dielectric layer to cover described these grids and described gate insulation layer, wherein said dielectric layer has a plurality of openings, and described these source electrodes are electrically connected with described drain region with corresponding described source area via described these openings respectively with described these drain electrodes.
25. the manufacture method of thin-film transistor array base-plate as claimed in claim 12 is characterized in that, the manufacture method of described thin-film transistor array base-plate more comprises a plurality of pixel electrodes of formation, is electrically connected with described these drain electrodes respectively.
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| CN102379041A (en) * | 2010-06-21 | 2012-03-14 | 松下电器产业株式会社 | Thin film transistor array device, organic el display device, and method for manufacturing thin film transistor array device |
| CN103295543A (en) * | 2012-12-28 | 2013-09-11 | 上海中航光电子有限公司 | Noncrystalline silicon gate driver |
| WO2015021708A1 (en) * | 2013-08-16 | 2015-02-19 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method therefor, display panel, and display apparatus |
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| US6602765B2 (en) * | 2000-06-12 | 2003-08-05 | Seiko Epson Corporation | Fabrication method of thin-film semiconductor device |
| JP2003332350A (en) * | 2002-05-17 | 2003-11-21 | Hitachi Ltd | Thin film semiconductor device |
| CN1265430C (en) * | 2003-04-09 | 2006-07-19 | 友达光电股份有限公司 | Low-temp. polycrystalline silicon film transistor and its polycrystalline silicon layer making method |
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| CN102379041A (en) * | 2010-06-21 | 2012-03-14 | 松下电器产业株式会社 | Thin film transistor array device, organic el display device, and method for manufacturing thin film transistor array device |
| CN103295543A (en) * | 2012-12-28 | 2013-09-11 | 上海中航光电子有限公司 | Noncrystalline silicon gate driver |
| CN103295543B (en) * | 2012-12-28 | 2016-02-24 | 上海中航光电子有限公司 | Amorphous silicon gate driver |
| WO2015021708A1 (en) * | 2013-08-16 | 2015-02-19 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method therefor, display panel, and display apparatus |
| US9508757B2 (en) | 2013-08-16 | 2016-11-29 | Boe Technology Group Co., Ltd. | Array substrate and manufacturing method thereof, display panel and display apparatus |
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| CN108962957A (en) * | 2018-07-27 | 2018-12-07 | 京东方科技集团股份有限公司 | Display base plate and its manufacturing method, display device |
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| US11302761B2 (en) | 2018-07-27 | 2022-04-12 | Boe Technology Group Co., Ltd. | Display substrate assembly and method of manufacturing the same, and display apparatus |
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