JP4566294B2 - Continuous grain boundary crystalline silicon film, semiconductor device - Google Patents

Description

【０１０３】
ここで本願発明の半導体薄膜の配向性をＸ線回折で測定した結果の一例を図２４に示す。なお、Ｘ線回折パターンには（２２０）面に相当するピークが現れているが、｛１１０｝面と等価であることは言うまでもない。この測定の結果、｛１１０｝面が主たる配向であり、配向比率は０．７以上（典型的には０．９以上）であることが判明した。
【０１０４】
以上に示してきた通り、本願発明の結晶性珪素膜と従来のポリシリコン膜とは全く異なる結晶構造（結晶構成）を有していることが判る。この点からも本願発明の結晶性珪素膜は全く新しい半導体膜であると言える。
【０１０５】
なお、本発明の半導体薄膜を形成するにあたって結晶化温度以上の温度でのアニール工程（本実施例の場合、図８（Ｃ）に示す工程）は、結晶粒内の欠陥低減に関して重要な役割を果たしている。その事について説明する。
【０１０６】
図２１（Ａ）は図８（Ｂ）に示した結晶化工程までを終了した時点での結晶シリコン膜を２５万倍に拡大したＴＥＭ写真であり、結晶粒内（黒い部分と白い部分はコントラストの差に起因して現れる）に矢印で示される様なジグザグ状に見える欠陥が確認される。
【０１０７】
この様な欠陥は主としてシリコン結晶格子面の原子の積み重ね順序が食い違っている積層欠陥であるが、転位などの場合もある。図２１（Ａ）は｛１１１｝面に平行な欠陥面を有する積層欠陥と思われる。その事は、ジグザグ状に見える欠陥が約７０°の角をなして折れ曲がっていることから推測できる。
【０１０８】
一方、図２１（Ｂ）に示す様に、同倍率で見た本発明の結晶シリコン膜は、結晶粒内には殆ど積層欠陥や転位などに起因する欠陥が見られず、非常に結晶性が高いことが確認できる。この傾向は膜面全体について言えることであり、欠陥数をゼロにすることは現状では困難であるが、実質的にゼロと見なせる程度にまで低減することができる。
【０１０９】
即ち、図２１（Ｂ）に示す結晶シリコン膜は結晶粒内の欠陥が殆ど無視しうる程度にまで低減され、且つ、結晶粒界が高い連続性によってキャリア移動の障壁になりえないため、単結晶または実質的に単結晶と見なせる。
【０１１０】
この様に、図２１（Ａ）と（Ｂ）の写真に示した結晶シリコン膜は結晶粒界はほぼ同等の連続性を有しているが、結晶粒内の欠陥数には大きな差がある。本発明の結晶シリコン膜が図２１（Ａ）に示した結晶シリコン膜よりも遙に高い電気特性を示す理由はこの欠陥数の差によるところが大きい。
【０１１１】
以上の事から、本発明にとって図８（Ｃ）に示した工程は必要不可欠な工程であることが判る。本出願人は、この工程によって起こる現象について次の様なモデルを考えている。
【０１１２】
まず、図２１（Ａ）に示す状態では結晶粒内の欠陥（主として積層欠陥）には触媒元素（代表的にはニッケル）が偏析している。即ち、Si-Ni-Siといった形の結合が多数存在していると考えられる。
【０１１３】
しかしながら、触媒元素のゲッタリングプロセスを行うことで欠陥に存在するNiが除去されると、Si-Ni 結合は切れる。そのため、シリコンの余った結合手はすぐにSi-Si 結合を形成して安定する。こうして欠陥が消滅する。
【０１１４】
勿論、高い温度での熱アニールによって結晶シリコン膜中の欠陥が消滅することは知られているが、本発明ではニッケルとの結合が切れて未結合手が多く発生するためシリコンの再結合がさらにスムーズに行われると推測できる。
【０１１５】
また、同時に結晶シリコン膜が熱酸化される際に発生する余剰シリコン原子が欠陥へと移動し、Si-Si 結合の生成に大きく寄与していると考えられる。この概念は高温ポリシリコン膜の結晶粒内に欠陥が少ない理由として知られている。
【０１１６】
また、本出願人は結晶化温度を超える温度（代表的には 700〜1100℃）で加熱処理を行うことで結晶シリコン膜とその下地との間が固着し、密着性が高まることで欠陥が消滅するというモデルを考えている。
【０１１７】
結晶シリコン膜と下地となる石英基板とでは、熱膨張係数に１０倍近くの差がある。従って、非晶質シリコン膜から結晶シリコン膜に変成した段階（図２１（Ａ））では、結晶シリコン膜が冷却される時に非常に大きな応力が結晶シリコン膜にかかる。
【０１１８】
この事について、図２２を用いて説明する。図２２（Ａ）は結晶化工程後の結晶シリコン膜にかかる熱履歴を示している。まず、温度（ｔ₁ ）で結晶化された結晶シリコン膜は冷却期間（ａ）を経て室温まで冷やされる。
【０１１９】
ここで図２２（Ｂ）に示すのは冷却期間（ａ）にある時の結晶シリコン膜であり、１０５０は石英基板、１０５１は結晶シリコン膜である。この時、結晶シリコン膜１０５１と石英基板１０５０との界面１０５２における密着性はあまり高くなく、それが原因となって多数の粒内欠陥を発生していると考えられる。
【０１２０】
即ち、熱膨張係数の差によって引っ張られた結晶シリコン膜１０５１は石英基板１０５０上で非常に動きやすく、引っ張り応力などの力によって積層欠陥や転位などの欠陥１０５３を容易に生じてしまうと考えられる。
【０１２１】
こうして得られた結晶シリコン膜が図２１（Ａ）に示した様な状態となるのである。そしてその後、図２２（Ａ）に示す様に温度（ｔ₂ ）で触媒元素のゲッタリング工程が施され、その結果、結晶シリコン膜中の欠陥が前述の理由によって消滅する。
【０１２２】
ここで重要なことは触媒元素のゲッタリング工程が行われると同時に結晶シリコン膜石英基板に固着され、石英基板との密着性が高まる点である。即ち、このゲッタリング工程は結晶シリコン膜と石英基板（下地）との固着工程を兼ねていると考えられる。
【０１２３】
こうしてゲッタリング＋固着工程を終了すると冷却期間（ｂ）を経て室温まで冷やされる。ここで結晶化工程の後の冷却期間（ａ）と異なる点は、石英基板１０５０とアニール後の結晶シリコン膜１０５４との界面１０５５が非常に密着性の高い状態となっている点である。（図２２（Ｃ））
【０１２４】
この様に密着性が高いと石英基板１０５０に対して結晶シリコン膜１０５４が完全に固着されるので、結晶シリコン膜の冷却段階において結晶シリコン膜に応力が加わっても欠陥を発生するには至らない。即ち、再び欠陥が発生する様なことを防ぐことができる。
【０１２５】
なお、図２２（Ａ）では結晶化工程後に室温まで下げるプロセスを例にとっているが、結晶化が終了したらそのまま温度を上げてゲッタリング＋固着工程を行うこともできる。その様なプロセスを経ても本発明の結晶シリコン膜を得ることは可能である。
【０１２６】
こうして得られた本発明の結晶シリコン膜（図２１（Ｂ））は、単に結晶化を行っただけの結晶シリコン膜（図２１（Ａ））に較べて格段に結晶粒内の欠陥数が少ないという特徴を有している。
【０１２７】
この欠陥数の差は電子スピン共鳴分析（Electron Spin Resonance ：ＥＳＲ）によってスピン密度の差となって現れる。現状では本発明の結晶シリコン膜のスピン密度は少なくとも 5×10¹⁷spins/cm³ 以下（好ましくは 3×10¹⁷spins/cm³ 以下）であることが判明している。ただし、この測定値はは現存する測定装置の検出限界に近いので、実際のスピン密度はさらに低いと予想される。
【０１２８】
以上の様な結晶構造および特徴を有する本発明の結晶シリコン膜は、連続粒界結晶シリコン（Continuous Grain Silicon：ＣＧＳ）と呼ばれる。
【０１２９】
〔ＴＦＴの電気特性に関する知見〕
上述の様な結晶性珪素膜を活性層として作製したＴＦＴは図４に示す様な電気特性を示す。図４に示すのは横軸にゲイト電圧（Ｖｇ）、縦軸にドレイン電圧（Ｉｄ）の対数をとってプロットしたＮチャネル型ＴＦＴのId-Vg 曲線（Id-Vg 特性）である。なお、電気特性の測定は市販の装置（ヒューレットパッカード社製：型番４１４５Ｂ）を用いて行った。
【０１３０】
図４において、４０１は上記工程で得られた活性層を利用したＴＦＴの電気特性であり、４０２は従来のＴＦＴの電気特性を示している。ここでは従来のＴＦＴとして実施例１においてゲイト絶縁膜形成後の熱処理（ゲッタリングプロセス）を行わなかったＴＦＴを挙げている。
【０１３１】
両方のトランジスタ特性を比較すると、まず同じゲイト電圧でも４０１で示される特性の方が 2〜4 桁近く大きいオン電流が流れることが確認できる。なお、オン電流とはＴＦＴがオン状態（図４においてゲイト電圧が約０〜５Ｖの範囲）にある時に流れるドレイン電流のことを指す。
【０１３２】
また、４０１で示される特性の方が優れたサブスレッショルド特性を有していることも確認できる。サブスレッショルド特性とはＴＦＴのスイッチング動作の急峻性を示すパラメータであり、ＴＦＴがオン又はオフ状態にスイッチングする際のId-Vg 曲線の立ち上がりが急峻である程、サブスレッショルド特性は良いと言える。
【０１３３】
なお、本発明で得られるＴＦＴの代表的な電気特性は次に示す様なものであった。
（１）ＴＦＴのスイッチング性能（オン／オフ動作の切り換えの俊敏性）を示すパラメータであるサブスレッショルド係数が、Ｎ型ＴＦＴおよびＰ型ＴＦＴともに60〜100mV/decade（代表的には60〜85mV/decade ）と小さい。なお、このデータ値は単結晶シリコンを用いた絶縁ゲイト型電界効果トランジスタ（ＩＧＦＥＴ）の場合とほぼ同等である。
（２）ＴＦＴの動作速度の速さを示すパラメータである電界効果移動度（μ_FE）が、Ｎ型ＴＦＴで200 〜650cm²/Vs （代表的には250 〜300cm²/Vs ）、Ｐ型ＴＦＴで100 〜300cm²/Vs （代表的には150 〜200cm²/Vs ）と大きい。
（３）ＴＦＴの駆動電圧の目安となるパラメータであるしきい値電圧（Ｖ_th）が、Ｎ型ＴＦＴで-0.5〜1.5 Ｖ、Ｐ型ＴＦＴで-1.5〜0.5 Ｖと小さい。この事は小さい電源電圧で駆動して消費電力を小さくできることを意味している。
【０１３４】
以上の様に、本発明で得られるＴＦＴは極めて優れたスイッチング特性および高速動作特性を有している。
【０１３５】
（本発明のＴＦＴで構成した回路の特性）
次に、本発明者らが本発明で得られるＴＦＴを用いて作製したリングオシレータによる周波数特性を示す。リングオシレータとはＣＭＯＳ構造でなるインバータ回路を奇数段リング状に接続した回路であり、インバータ回路１段あたりの遅延時間を求めるのに利用される。実験に使用したリングオシレータの構成は次の様になっている。
段数：９段
ＴＦＴのゲイト絶縁膜の膜厚：30nm及び50nm
ＴＦＴのゲイト長： 0.6μｍ
【０１３６】
上記リングオシレータの電源電圧５Ｖの時の発振周波数をスペクトラムアナライザーで測定した結果を図５に示す。図５において、横軸は電源電圧（Ｖ_DD）、縦軸は発振周波数（ｆ_osc ）である。図５が示す様に、ゲイト絶縁膜が30nmのＴＦＴを用いた場合において１ＧＨｚ以上の発振周波数を実現している。
【０１３７】
図６に示すのは1.04ＧＨｚの発振周波数を得た際のスペクトラムアナライザーの出力スペクトルの様子である。横軸は 1〜1.1 ＧＨｚまでの周波数であり、縦軸はログスケールでとった電圧（出力振幅）である。図６に明らかな様に、約 1.04 ＧＨｚのところで出力スペクトルのピークが現れている。なお、出力スペクトルがテールを引いているのは装置の分解能によるものであり、実験結果に影響するものではない。
【０１３８】
また、実際にＬＳＩ回路のＴＥＧの一つであるシフトレジスタを作製して動作周波数を確認した。その結果、ゲイト絶縁膜の膜厚30nm、ゲイト長 0.6μｍ、電源電圧５Ｖ、段数５０段のシフトレジスタ回路において動作周波数100 ＭＨｚの出力パルスが得られた。
【０１３９】
以上の様なリングシレータおよびシフトレジスタの驚異的なデータは、本発明のＴＦＴが単結晶シリコンを利用したＩＧＦＥＴに匹敵する、若しくは凌駕する性能を有していることを示している。
【０１４０】
それを裏付ける証拠として次の様なデータがある。図７に示すデータは横軸に電源電圧（Ｖ_DD）、縦軸にＦ／Ｏ＝１（ファンアウト比が１）のインバータの１段当たりの遅延時間（τ_pd）をとったグラフである（ロジックＬＳＩ技術の革新，前口賢二他，ｐ１０８，株式会社サイエンスフォーラム，1995）。
【０１４１】
なお、図中の様々な曲線（点線で示されるもの）は、単結晶シリコンを利用したＩＧＦＥＴを様々なデザインルールで作製した時のデータであり、いわゆるスケーリング則を示している。
【０１４２】
この図に上述のリングオシレータを用いて得たインバータの遅延時間と電源電圧との関係を当てはめると、図７において実線で示される曲線となる。注目すべきはチャネル長が 0.5μｍ、ゲイト絶縁膜の膜厚（ｔ_OX）が１１nmのＩＧＦＥＴで作製したインバータよりも、チャネル長が 0.6μｍ、ゲイト絶縁膜の膜厚が３０nmのＴＦＴで作製したインバータの方が優れた性能を有している点である。
【０１４３】
この事は本発明者で得られるＴＦＴがＩＧＦＥＴよりも優れた性能を有していることを如実に示している。例えば、上記ＴＦＴを構成するゲイト絶縁膜の膜厚をＩＧＦＥＴの３倍以上としても、性能的に同等もしくはそれ以上のものが得られるのである。即ち、本発明のＴＦＴは同等の特性を動作性能を有するＩＧＦＥＴよりも優れた絶縁耐圧を有していると言える。
【０１４４】
また同時に、本発明のＴＦＴがスケーリング則に従って微細化されればさらに高い性能を実現することが可能である。例えば、リングオシレータを0.2 μｍルールで作製すればスケーリング則によると９ＧＨｚの動作周波数を実現しうると予想される（動作周波数ｆがチャネル長Ｌの二乗に反比例するため）。
【０１４５】
以上の様に、本発明のＴＦＴは極めて優れた特性を有し、そのＴＦＴを用いて形成した半導体回路は１０ＧＨｚ以上の高速動作を実現しうる全く新しいＴＦＴであることが確認された。
【０１４６】
〔ＴＦＴ特性とＣＧＳの関係に関する知見〕
上述の様な優れたＴＦＴ特性及び回路特性は、ＴＦＴの活性層として、結晶粒界において結晶格子に連続性を有する半導体薄膜を利用している点によるところが大きい。その理由について以下に考察する。
【０１４７】
結晶粒界における結晶格子の連続性は、その結晶粒界が「平面状粒界」と呼ばれる粒界であることに起因する。本明細書における平面状粒界の定義は、「Characterization of High-Efficiency Cast-Si Solar Cell Wafers by MBIC Measurement ；Ryuichi Shimokawa and Yutaka Hayashi，Japanese Journal of Applied Physics vol.27，No.5，pp.751-758，1988」に記載された「Planar boundary 」である。
【０１４８】
上記論文によれば、平面状粒界には｛１１１｝双晶粒界、｛１１１｝積層欠陥、｛２２１｝双晶粒界、｛２２１｝twist 粒界などが含まれる。この平面状粒界は電気的に不活性であるという特徴を持つ。即ち、結晶粒界でありながらキャリアの移動を阻害するトラップとして機能しないため、実質的に存在しないと見なすことができる。
【０１４９】
特に｛１１１｝双晶粒界はΣ３の対応粒界、｛２２１｝双晶粒界はΣ９の対応粒界とも呼ばれる。Σ値は対応粒界の整合性の程度を示す指針となるパラメータであり、Σ値が小さいほど整合性の良い粒界であることが知られている。
【０１５０】
本出願人が本願発明の半導体薄膜を詳細にＴＥＭで観察した結果、結晶粒界の殆ど（９０％以上、典型的には９５％以上）がΣ３の対応粒界、即ち｛１１１｝双晶粒界であることが判明した。
【０１５１】
二つの結晶粒の間に形成された結晶粒界において、両方の結晶の面方位が｛１１０｝である場合、｛１１１｝面に対応する格子縞がなす角をθとすると、θ＝70.5°の時にΣ３の対応粒界となることが知られている。
【０１５２】
従って、図１（Ａ）のＴＥＭ写真に示された結晶粒界では、隣接する結晶粒の各格子縞が約70°の角度で連続しており、この結晶粒界は｛１１１｝双晶粒界であると容易に推察することができる。
【０１５３】
なお、θ＝ 38.9 °の時にはΣ９の対応粒界となるが、この様な他の結晶粒界も存在した。
【０１５４】
この様な対応粒界は、同一面方位の結晶粒間にしか形成されない。即ち、本願発明の半導体薄膜は面方位が概略｛１１０｝で揃っているからこそ、広範囲に渡ってこの様な対応粒界を形成しうるのである。この特徴は、面方位が不規則な他のポリシリコン膜ではあり得ることではない。
【０１５５】
ここで、本願発明の半導体薄膜を１万５千倍に拡大したＴＥＭ写真（暗視野像）を図２５（Ａ）に示す。白く見える領域と黒く見える領域とが存在するが、同色に見える部分は配向性が同一であることを示している。
【０１５６】
図２５（Ａ）で特筆すべきはこれだけ広範囲の暗視野像において、白く見える領域がかなりの割合で連続的にまとまっている点である。これは配向性の同じ結晶粒がある程度の方向性をもって存在し、隣接する結晶粒同士で殆ど同一の配向性を有していることを意味している。
【０１５７】
他方、従来の高温ポリシリコン膜を１万５千倍に拡大したＴＥＭ写真（暗視野像）を図２５（Ｂ）に示す。従来の高温ポリシリコン膜では同一面方位の部分はばらばらに点在するのみであり、図２５（Ａ）に示す様な方向性のあるまとまりは確認できない。これは隣接する結晶粒同士の配向性が全く不規則であるためと考えられる。
【０１５８】
また、本出願人は図１に示した測定点以外にも多数の領域に渡って観察と測定を繰り返し、ＴＦＴを作製するのに十分な広い領域において、結晶粒界における結晶格子の連続性が保たれていることを確認している。
【０１５９】
〔実施例２〕
実施例１では半導体膜として珪素膜を用いる例を示したが、Ｓｉ_X Ｇｅ_1-X （０＜Ｘ＜１、好ましくは0.9 ≦Ｘ≦0.99）で示される様にゲルマニウムを１〜１０％含有した珪素膜を用いることも有効である。
【０１６０】
この様な化合物半導体膜を用いた場合、Ｎ型ＴＦＴおよびＰ型ＴＦＴを作製した際にしきい値電圧を小さくできる。また、電界効果移動度（モビリティと呼ばれる）を大きくできる。
【０１６１】
〔実施例３〕
実施例１では活性層に対して意図的に不純物を添加しないのでチャネル形成領域が真性または実質的に真性となる。なお、実質的に真性であるとは、▲１▼珪素膜の活性化エネルギーがほぼ1/2 である（フェルミレベルが禁制体のほぼ中央に位置する）こと、▲２▼スピン密度よりも不純物濃度が低いこと、▲３▼意図的に不純物を添加していないこと、のいずれかを満たすことである。
【０１６２】
しかし、本願発明のＴＦＴは公知のチャネルドープ技術を利用することも可能である。チャネルドープ技術とは、しきい値制御のために少なくともチャネル形成領域に対して不純物を添加する技術である。
【０１６３】
本願発明はもともとしきい値が非常に小さいので不純物を添加する濃度は非常に微量なもので良い。添加濃度が微量ですむということは、キャリアの移動度を落とさずにしきい値制御が可能となるため非常に好ましい。
【０１６４】
〔実施例４〕
本実施例では、実施例１に示したハロゲン元素によるゲッタリング効果に加えてリン元素によるゲッタリング効果を得るための構成について説明する。説明には図１０を用いる。
【０１６５】
まず、実施例１の工程に従ってハロゲン元素によるゲッタリングプロセスまで行い、図８（Ｃ）の状態を得る。次に、タンタルまたはタンタルを主成分とする材料でなるゲイト電極１１を形成する。
【０１６６】
次に、ゲイト電極１１の表面を陽極酸化することによって陽極酸化膜１２を形成する。陽極酸化膜１２は保護膜として機能する。（図１０（Ａ））
【０１６７】
次に、ゲイト電極１１をマスクとしてゲイト絶縁膜８０８をドライエッチング法によりエッチングする。そして、その状態でリンまたは砒素イオン注入法により添加して不純物領域１３、１４を形成する。（図１０（Ｂ））
【０１６８】
次に、窒化珪素膜を厚く形成した後、ドライエッチング法によるエッチバックを行い、サイドウォール１５を形成する。そして、サイドウォール１５を形成した後、再びリンまたは砒素イオンを添加してソース領域１６、ドレイン領域１７を形成する。（図１０（Ｃ））
【０１６９】
なお、サイドウォール１５の下は２度目のリン元素が添加されず、ソース領域およびドレイン領域よりも低濃度にリン元素を含む一対の低濃度不純物領域１８となる。また、ゲイト電極１１の下は真性または実質的に真性、或いはしきい値制御のために微量の不純物が添加されたチャネル形成領域１９となる。
【０１７０】
こうして図１０（Ｃ）の状態が得られたら、４５０〜６５０℃（代表的には６００℃）で８〜２４時間（代表的には１２時間）の加熱処理を行う。
【０１７１】
この加熱処理はリン元素による触媒元素（ここではニッケル）のゲッタリングを目的とした工程であるが、同時に不純物の活性化、活性層が受けたイオン注入時の損傷の回復が行われる。
【０１７２】
この工程では、加熱処理を行うことでチャネル形成領域１９に残存するニッケルがソース／ドレイン領域１６、１７に移動し、そこでゲッタリングされて不活性化する。即ち、チャネル形成領域１９内部に残存するニッケルを除去することが可能である。
【０１７３】
なお、ソース／ドレイン領域１６、１７は導電性を有していれば電極としての機能を果たすのでニッケルの有無が電気特性に影響を与える恐れがない。そのため、ゲッタリングサイトとして機能させうるのである。
【０１７４】
以上の様にして図１０（Ｄ）の状態が得られたら、実施例１と同様に層間絶縁膜２０、ソース電極２１、ドレイン電極２２を形成して図１０（Ｅ）に示す薄膜トランジスタが完成する。
【０１７５】
なお、本実施例ではゲイト電極としてタンタルを用いているが、導電性を有する結晶性珪素膜を用いても良い。また、低濃度不純物領域の形成方法は本実施例の手段に限定されるものではない。
【０１７６】
本実施例で最も重要な構成は、チャネル形成領域に残存する触媒元素をソース領域およびドレイン領域に移動させてゲッタリングすることにある。これは、リンまたは砒素による金属元素のゲッタリング効果に着目した発明である。
【０１７７】
なお、本実施例ではＮ型ＴＦＴの例を示したが、Ｐ型ＴＦＴの場合、ボロン元素だけではゲッタリング効果が得られないので、リン元素とボロン元素の両方をソース／ドレイン領域に添加することが必要である。
【０１７８】
〔実施例５〕
本実施例では、実施例１と異なる構造の薄膜トランジスタに本願発明を適用した場合の例について説明する。説明には図１１を用いる。
【０１７９】
まず、石英基板３１上にゲイト電極３２を形成する。ゲイト電極３２は後の熱酸化工程に耐えられる様にタンタル、シリコン等の耐熱性の高い電極を利用することが必要である。
【０１８０】
次に、ゲイト電極３２を覆う様にしてゲイト絶縁膜３３を形成する。その上には、後に活性層となる非晶質珪素膜を50nmの厚さに形成する。そして、実施例１と同様に開口部を有するマスク絶縁膜３５を形成した後、ニッケル含有層３６を形成する。（図１１（Ａ））
【０１８１】
こうして図１１（Ａ）の状態が得られたら、結晶化のための加熱処理を行い、横成長領域でなる結晶性珪素膜３７を得る。（図１１（Ｂ））
【０１８２】
次に、マスク絶縁膜３５を除去してハロゲン元素を含む雰囲気中で加熱処理を行う。条件は実施例１に従えば良い。この工程によって結晶性珪素膜３７中からニッケルがゲッタリングされ、気相中へと除去される。（図１１（Ｃ））
【０１８３】
こうしてゲッタリングプロセスが完了したら、パターニングにより横成長領域のみでなる活性層３８を形成し、その上に窒化珪素膜でなるチャネルストッパー３９を形成する。（図１１（Ｄ））
【０１８４】
図１１（Ｄ）の状態が得られたら、Ｎ型を呈する結晶性珪素膜を形成してパターニングを施し、ソース領域４０、ドレイン領域４１を形成する。さらに、ソース電極４２、ドレイン電極４３を形成する。
【０１８５】
最後に、素子全体に対して水素雰囲気中で加熱処理を行い、図１１（Ｅ）に示す様な構造の逆スタガ型ＴＦＴが完成する。なお、本実施例に示した構造は逆スタガ型ＴＦＴの一例であり、本実施例の構造に限定されるものではない。また、他のボトムゲイト型ＴＦＴに適用することも可能である。
【０１８６】
〔実施例６〕
本実施例では絶縁表面を有する基板上に本発明によるＴＦＴを形成し、画素マトリクス回路と周辺回路とをモノリシックに構成する例を図１２〜１４に示す。
なお、本実施例ではドライバー回路やロジック回路等の周辺回路の例として、基本回路であるＣＭＯＳ回路を示す。
【０１８７】
まず、石英基板５１上に75nm厚の非晶質珪素膜５２、マスク絶縁膜５３を形成し、スピンコート法によりニッケル含有層５４を形成する。これらの工程は実施例１に示した通りである。（図１２（Ａ））
【０１８８】
次に、450 ℃１時間程度の水素出しの後、窒素雰囲気中において590 ℃ 8時間の加熱処理を行い、結晶性領域５５〜５８を得る。なお、５５、５６はニッケル添加領域であり、５７、５８は横成長領域である。（図１２（Ｂ））
【０１８９】
結晶化のための加熱処理が終了したら、マスク絶縁膜５３を除去してパターニングを行い、横成長領域５７、５８のみでなる島状半導体層（活性層）５９〜６１を形成する。（図１２（Ｃ））
【０１９０】
ここで５９はＣＭＯＳ回路を構成するＮ型ＴＦＴの活性層、６０はＣＭＯＳ回路を構成するＰ型ＴＦＴの活性層、６１は画素マトリクス回路を構成するＮ型ＴＦＴ（画素ＴＦＴ）の活性層である。
【０１９１】
活性層５９〜６１を形成したら、その上に珪素を含む絶縁膜でなるゲイト絶縁膜６２を成膜する。そして、次に触媒元素のゲッタリングプロセスを行う。この工程の条件は実施例１に従えば良い。（図１２（Ｄ））
【０１９２】
次に、図示しないアルミニウムを主成分とする金属膜を成膜し、パターニングによって後のゲイト電極の原型６３〜６５を形成する。本実施例では２wt% のスカンジウムを含有したアルミニウム膜を用いる。（図１３（Ａ））
【０１９３】
次に、実施例１と同様に特開平7-135318号公報記載の技術により多孔性の陽極酸化膜６６〜６８、無孔性の陽極酸化膜６９〜７１、ゲイト電極７２〜７４を形成する。（図１３（Ｂ））
【０１９４】
こうして図１３（Ｂ）の状態が得られたら、次にゲイト電極７２〜７４、多孔性の陽極酸化膜６６〜６８をマスクとしてゲイト絶縁膜６２をエッチングする。
そして、多孔性の陽極酸化膜６６〜６８を除去して図１３（Ｃ）の状態を得る。
なお、図１３（Ｃ）において７５〜７７で示されるのは加工後のゲイト絶縁膜である。
【０１９５】
次に、実施例１と同様の手順に従ってＮ型を付与する不純物イオンを２回に分けて添加する。まず１回目の不純物添加を高加速電圧で行い、ｎ^- 領域を形成し、次に２回目の不純物添加を低加速電圧で行い、ｎ⁺ 領域を形成する。
【０１９６】
以上の工程を経て、ＣＭＯＳ回路を構成するＮ型ＴＦＴのソース領域７８、ドレイン領域７９、低濃度不純物領域８０、チャネル形成領域８１が形成される。
また、画素ＴＦＴを構成するＮ型ＴＦＴのソース領域８２、ドレイン領域８３、低濃度不純物領域８４、チャネル形成領域８５が画定する。（図１３（Ｄ））
【０１９７】
なお、図１３（Ｄ）に示す状態ではＣＭＯＳ回路を構成するＰ型ＴＦＴの活性層もＮ型ＴＦＴの活性層と同じ構成となっている。
【０１９８】
次に、Ｎ型ＴＦＴを覆ってレジストマスク８６を設け、Ｐ型を付与する不純物イオン（本実施例ではボロンを用いる）の添加を行う。
【０１９９】
この工程も前述の不純物添加工程と同様に２回に分けて行うが、Ｎ型をＰ型に反転させる必要があるため、前述のＰイオンの添加濃度の数倍程度の濃度のＢ（ボロン）イオンを添加する。
【０２００】
こうしてＣＭＯＳ回路を構成するＰ型ＴＦＴのソース領域８７、ドレイン領域８８、低濃度不純物領域８９、チャネル形成領域９０が形成される。（図１４（Ａ））
【０２０１】
以上の様にして活性層が完成したら、ファーネスアニール、レーザーアニール、ランプアニール等の組み合わせによって不純物イオンの活性化を行う。それと同時に添加工程で受けた活性層の損傷も修復される。
【０２０２】
次に、層間絶縁膜９１として酸化珪素膜と窒化珪素膜との積層膜を形成し、コンタクトホールを形成した後、ソース電極９２〜９４、ドレイン電極９５、９６を形成して図１４（Ｂ）に示す状態を得る。
【０２０３】
なお、本実施例では画素ＴＦＴのドレイン電極９６を補助容量の下部電極として利用するので、それに対応する様な形状に加工しておく。
【０２０４】
次に、10〜50nmの厚さの窒化珪素膜９７を形成し、その上に補助容量を形成するための容量電極９８を 100nmの厚さに形成する。本実施例では容量電極９８としてチタン膜を用い、ドレイン電極９６との間で補助容量を形成する。
【０２０５】
前述の窒化珪素膜９７は比誘電率が高いので誘電体として好適である。また、容量電極９８としてはチタン膜以外にもアルミニウム膜やクロム膜等を用いても構わない。
【０２０６】
なお、本実施例は反射型液晶表示装置のアクティブマトリクス基板（ＴＦＴ側基板）を作製する例であるので、透過型と違って後に形成される画素電極の下を自由に利用できる（開口率を気にする必要がない）。それ故に上述の様な補助容量の形成が可能となる。
【０２０７】
次に、有機性樹脂膜でなる第２の層間絶縁膜９９を 0.5〜3 μｍの厚さに形成する。そして、層間絶縁膜９９上に導電膜を形成してパターニングにより画素電極１００を形成する。本実施例は反射型の例であるため画素電極１００を構成する導電膜としてアルミニウムを主成分とする材料を用い、画素電極１００に反射膜としての機能を持たせる。
【０２０８】
次に、基板全体を350 ℃の水素雰囲気で１〜２時間加熱し、素子全体の水素化を行うことで膜中（特に活性層中）のダングリングボンド（不対結合手）を補償する。以上の工程を経て同一基板上にＣＭＯＳ回路および画素マトリクス回路を作製することができる。
【０２０９】
〔実施例７〕
本実施例では、実施例６とは異なるＴＦＴ構造を採用した場合の例について説明する。まず、図１５（Ａ）は低濃度不純物領域を形成するにあたってサイドウォールを利用する例である。
【０２１０】
この場合、図１３（Ａ）に示す状態で無孔性の陽極酸化膜を形成し、ゲイト電極とその陽極酸化膜をマスクとしてゲイト絶縁膜をエッチングする。その状態でｎ^- 領域およびｐ^- 領域を形成するための不純物添加を行う。
【０２１１】
次に、サイドウォール１００１〜１００３をエッチバック法で形成した後、ｎ⁺ 領域およびｐ⁺ 領域を形成するための不純物添加を行う。この様な工程でサイドウォール１００１〜１００３の下には低濃度不純物領域（ｎ^- 領域およびｐ^- 領域）が形成される。
【０２１２】
また、図１５（Ａ）では公知のサリサイド技術を利用して金属シリサイド１００４〜１００６を形成している。シリサイド化するための金属としてはチタン、タンタル、タングステン、モリブデン等を用いることができる。
【０２１３】
また、図１５（Ｂ）に示す構成は、ゲイト電極１００７〜１００９が一導電性を付与した結晶性珪素膜で形成されている点に特徴がある。通常、Ｎ型導電性を持たせるが、Ｎ型ＴＦＴとＰ型ＴＦＴとで導電性を異ならせるデュアルゲイト型ＴＦＴとすることも可能である。
【０２１４】
さらに、図１５（Ｂ）に示す構造でもサリサイド構造を適用しているが、この場合、ゲイト電極１００７〜１００９の上面にも金属シリサイド１０１０〜１０１２が形成される。
【０２１５】
本実施例に示した構造は、動作速度の速いＴＦＴに適した構造となる様に設計されている。特に、サリサイド構造は数ＧＨｚレベルの動作周波数を実現する上で非常に有効な技術である。
【０２１６】
〔実施例８〕
本実施例では、実施例６とは異なる構成で補助容量を形成する場合の例について説明する。
【０２１７】
まず、図１６（Ａ）は活性層のドレイン領域１０２０を大きめに形成しておき、その一部を補助容量の下部電極として活用する。この場合、ドレイン領域１０２０の上にはゲイト絶縁膜１０２１があり、その上に容量電極１０２２が形成される。この容量電極１０２２はゲイト電極と同一材料で形成される。
【０２１８】
この時、ドレイン領域１０２０のうち補助容量を形成する部分は、予め不純物を添加して導電性を持たせておいても良いし、容量電極１０２２に定電圧をかけて形成される反転層を利用しても良い。
【０２１９】
図１６（Ａ）は反射型液晶表示装置の例であるため、画素電極の裏側を最大限に活用して補助容量を形成できる。そのため、非常に大きな容量を確保することができる。勿論、透過型液晶表示装置にも適用できるが、その場合、補助容量の占有面積を大きくしてしまうと開口率が落ちるので注意が必要である。
【０２２０】
次に、図１７（Ｂ）は透過型液晶表示装置の例である。図１７（Ｂ）の構成ではドレイン電極１０２３を補助容量の下部電極とし、その上に窒化珪素膜１０２４、ブラックマスク１０２５を形成し、ドレイン電極１０２３とブラックマスク１０２５との間で補助容量を形成する。
【０２２１】
この様に、図１６（Ｂ）の構成ではブラックマスク１０２５が補助容量の上部電極を兼ねる点が特徴である。
【０２２２】
また、１０２６は画素電極であり、透過型であるので透明導電膜（例えばＩＴＯ膜）を用いる。
【０２２３】
図１６（Ｂ）に示す様な構成では、広い面積を占めやすい補助容量をＴＦＴの上に形成することで開口率を広くすることが可能である。また、誘電率の高い窒化珪素膜を25nm程度の薄さで利用できるので、少ない面積で非常に大きな容量を確保することが可能である。
【０２２４】
〔実施例９〕
本実施例では、画素マトリクス回路を構成する画素ＴＦＴの構造について説明する。本実施例の画素ＴＦＴの断面構造を図２６（Ａ）に示す。図２６（Ａ）において、３００１は活性層、３００２はソース線、３００３はゲイト線、３００４はドレイン電極、３００５はブラックマスク、３００６はドレイン電極３００４と画素電極３００７とを接続するためのコンタクトホールである。
【０２２５】
本実施例の特徴は、画素ＴＦＴの上方においてドレイン電極３００４とブラックマスク３００５との間で補助容量を形成する点にある。
【０２２６】
また、図２６（Ａ）をＡ−Ａ’で示される破線で切断した時の断面図を図２６（Ｂ）に示す。なお、図２６（Ａ）と図２６（Ｂ）には共通の符号を用いる。
【０２２７】
この様に、ゲイト線３００３と重なる様な配置でドレイン電極３００５が形成され、誘電体３００８を挟んで対向するブラックマスク３００５との間に補助容量が形成されている。なお、本実施例ではドレイン電極３００５としてチタン膜をアルミニウム膜で挟んだ三層構造を採用している。
【０２２８】
本実施例の場合、ドレイン電極３００５を形成した後で窒化珪素膜／酸化珪素膜／アクリル膜の三層構造でなる層間絶縁膜を形成し、その上にブラックマスク３００５を形成する。
【０２２９】
この時、ブラックマスク３００５の形成前に、後に補助容量となる領域のアクリル膜のみを除去して開口部を形成しておく。すると、開口部の底には酸化珪素膜と窒化珪素膜しか残らず、この二層構造でなる絶縁層が補助容量の誘電体３００８として機能するのである。
【０２３０】
〔実施例１０〕
本実施例では本願発明を利用して液晶パネルを構成する場合の例を示す。図１７に示すのはアクティブマトリクス型液晶パネルの断面を簡略化した図であり、ドライバー回路やロジック回路を構成する領域にはＣＭＯＳ回路を、画素マトリクス回路を構成する領域には画素ＴＦＴを示している。
【０２３１】
なお、実施例６〜９でＣＭＯＳ回路と画素マトリクス回路の構造（ＴＦＴ構造）に関する説明を既に行ったので、本実施例では必要な箇所のみを説明することにする。
【０２３２】
まず、実施例６に示した作製工程に従って図１４（Ｃ）の状態を得る。なお、画素ＴＦＴをマルチゲイト構造とするなどの変更は実施者の自由である。
【０２３３】
そして、アクティブマトリクス基板の準備として配向膜１０３０を形成する。
次に、対向基板を用意する。対向基板は、ガラス基板１０３１、透明導電膜１０３２、配向膜１０３３とで構成される。なお、対向基板側には必要に応じてブラックマスクやカラーフィルターが形成されるがここでは省略する。
【０２３４】
こうして用意したアクティブマトリクス基板と対向基板とを公知のセル組み工程によって貼り合わせる。そして、両基板の間に液晶材料１０３４を封入して図１７に示す様な液晶パネルが完成する。
【０２３５】
液晶材料１０３４は液晶の動作モード（ＥＣＢモード、ゲストホストモード等）によって自由に選定することができる。
【０２３６】
また、図１４（Ｃ）に示した様なアクティブマトリクス基板の外観を図１８に簡略化して示す。図１８において、１０４０は石英基板、１０４１は画素マトリクス回路、１０４２はソースドライバー回路、１０４３はゲイトドライバー回路、１０４４はロジック回路である。
【０２３７】
ロジック回路１０４４は広義的にはＴＦＴで構成される論理回路全てを含むが、ここでは従来から画素マトリクス回路、ドライバー回路と呼ばれている回路と区別するため、それ以外の信号処理回路（メモリ、Ｄ／Ａコンバータ、パルスジェネレータ等）を指す。
【０２３８】
また、こうして形成された液晶パネルには外部端子としてＦＰＣ（Flexible Print Circuit）端子が取り付けられる。一般的に液晶モジュールと呼ばれるのはＦＰＣを取り付けた状態の液晶パネルである。
【０２３９】
本出願人は実際に対角2.6 インチ、1280×1024画素で、画素サイズが45μｍ×32μｍの液晶モジュールを作製している。開口率は63％、コントラスト比は 300:1を実現している。
【０２４０】
〔実施例１１〕
本願発明は実施例１０に示した液晶表示装置以外にも、アクティブマトリクス型のＥＬ（エレクトロルミネッセンス）表示装置やＥＣ（エレクトロクロミクス）表示装置等の他の電気光学装置を作製することも可能である。
【０２４１】
〔実施例１２〕
本実施例では、本発明を利用した電気光学装置を利用する電子デバイス（応用製品）の一例を図１９に示す。本発明を利用した応用製品としてはビデオカメラ、スチルカメラ、プロジェクター、ヘッドマウントディスプレイ、カーナビゲーション、パーソナルコンピュータ、携帯情報端末（モバイルコンピュータ、携帯電話等）などが挙げられる。
【０２４２】
図１９（Ａ）は携帯電話であり、本体２００１、音声出力部２００２、音声入力部２００３、表示装置２００４、操作スイッチ２００５、アンテナ２００６で構成される。本発明は表示装置２００４に適用することができる。
【０２４３】
図１９（Ｂ）はビデオカメラであり、本体２１０１、表示装置２１０２、音声入力部２１０３、操作スイッチ２１０４、バッテリー２１０５、受像部２１０６で構成される。本発明は表示装置２１０２に適用することができる。
【０２４４】
図１９（Ｃ）はモバイルコンピュータ（モービルコンピュータ）であり、本体２２０１、カメラ部２２０２、受像部２２０３、操作スイッチ２２０４、表示装置２２０５で構成される。本発明は表示装置２２０５に適用できる。
【０２４５】
図１９（Ｄ）はヘッドマウントディスプレイであり、本体２３０１、表示装置２３０２、バンド部２３０３で構成される。本発明は表示装置２３０２に適用することができる。
【０２４６】
図１９（Ｅ）はリア型プロジェクターであり、本体２４０１、光源２４０２、表示装置２４０３、偏光ビームスプリッタ２４０４、リフレクター２４０５、２４０６、スクリーン２４０７で構成される。本発明は表示装置２４０３に適用することができる。
【０２４７】
図１９（Ｆ）はフロント型プロジェクターであり、本体２５０１、光源２５０２、表示装置２５０３、光学系２５０４、スクリーン２５０５で構成される。本発明は表示装置２５０３に適用することができる。
【０２４８】
以上の様に、本発明の応用範囲は極めて広く、あらゆる分野の表示媒体に適用することが可能である。また、本発明のＴＦＴはＩＣ、ＬＳＩといった半導体回路を構成することもできるので、その様な半導体回路を必要とする製品であれば用途を問わない。
【０２４９】
【発明の効果】
本明細書で開示する発明によれば、実質的に単結晶半導体に匹敵する結晶性を有する半導体薄膜を実現することができる。そして、その様な半導体薄膜を利用することで単結晶上に作製したＩＧＦＥＴ（ＭＯＳＦＥＴ）に匹敵する、或いは凌駕する高い性能を有したＴＦＴを実現することができる。
【０２５０】
以上の様なＴＦＴを用いて構成される半導体回路や電気光学装置およびそれらを具備した電子デバイスは、極めて高い性能を有し、機能性、携帯性、信頼性の面で非常に優れたものとなる。
【図面の簡単な説明】
【図１】 半導体薄膜の結晶粒界を拡大したＨＲーＴＥＭ写真。
【図２】 結晶の方位関係を模式的に表した図。
【図３】 電子線回折パターンを表す写真および模式図。
【図４】 薄膜トランジスタの電気特性を示す図。
【図５】 リングオシレータの周波数特性を示す図。
【図６】 リングオシレータの出力スペクトルを示す写真。
【図７】 スケーリング則を示す図。
【図８】 薄膜トランジスタの作製工程を示す図。
【図９】 薄膜トランジスタの作製工程を示す図。
【図１０】 薄膜トランジスタの作製工程を示す図。
【図１１】 薄膜トランジスタの作製工程を示す図。
【図１２】 アクティブマトリクス基板の作製工程を示す図。
【図１３】 アクティブマトリクス基板の作製工程を示す図。
【図１４】 アクティブマトリクス基板の作製工程を示す図。
【図１５】 アクティブマトリクス基板の構造を示す図。
【図１６】 アクティブマトリクス基板の構造を示す図。
【図１７】 液晶表示装置の断面を示す図。
【図１８】 アクティブマトリクス基板を上面から見た図。
【図１９】 電子デバイス（応用製品）の一例を示す図。
【図２０】 結晶成長の様子を模式的に表した図。
【図２１】 結晶シリコン膜の結晶粒を示すＴＥＭ写真。
【図２２】 欠陥の生成および消滅に関するモデルを説明するための図。
【図２３】 Ｃ、Ｎ、Ｏの濃度分布を示す図。
【図２４】 Ｘ線回折の結果を示す図。
【図２５】 半導体薄膜の暗視野像を示すＴＥＭ写真。
【図２６】 画素ＴＦＴの上面及び断面構造を示す図。[0001]
[Technical field to which the invention belongs]
The invention disclosed in this specification relates to a semiconductor thin film formed over a substrate having an insulating surface and a semiconductor device using the semiconductor thin film as an active layer. In particular, the present invention relates to a configuration in which a material containing silicon as a main component is used as a semiconductor thin film.
[0002]
Note that in this specification, “semiconductor device” refers to all devices that function using semiconductors, and the following are included in the category of semiconductor devices.
(1) A single element such as a thin film transistor (TFT).
(2) Semiconductor circuit using single element of (1)
(3) An electro-optical device constituted by (1) and (2).
(4) An electronic device comprising (2) and (3).
[0003]
[Prior art]
2. Description of the Related Art In recent years, a technique for forming a thin film transistor (TFT) using a semiconductor thin film (having a thickness of about several hundred to several thousand Å) formed on a substrate having an insulating surface has attracted attention. Thin film transistors are widely applied to electronic devices such as ICs and electro-optical devices, and development of switching devices for image display devices is urgently required.
[0004]
For example, in a liquid crystal display device, a pixel matrix circuit that individually controls pixel areas arranged in a matrix, a drive circuit that controls the pixel matrix circuit, and a logic circuit (processor circuit or memory circuit) that processes an external data signal Attempts have been made to apply TFTs to all electrical circuits.
[0005]
At present, TFTs using an amorphous silicon film (amorphous silicon film) as an active layer have been put into practical use. However, electrical circuits that require higher speed operation performance, such as drive circuits and logic circuits, are used. A TFT using a crystalline silicon film (polysilicon film, polycrystalline silicon film, etc.) is required.
[0006]
For example, as a method for forming a crystalline silicon film on a glass substrate, techniques described in Japanese Patent Application Laid-Open Nos. 7-130652 and 8-78329 by the present applicant are known. The techniques described in these publications form a crystalline silicon film having excellent crystallinity by heating at 500 to 600 ° C. for about 4 hours by using a catalytic element that promotes crystallization of the amorphous silicon film. It is possible to do that.
[0007]
In particular, the technique described in Japanese Patent Application Laid-Open No. 8-78329 applies the above technique to perform crystal growth substantially parallel to the substrate surface. Or a lateral growth region).
[0008]
However, even if a drive circuit is configured using such TFTs, it still does not fully satisfy the required performance. In particular, it is currently impossible to construct a high-speed logic circuit that requires extremely high-speed operation from megahertz to gigahertz using conventional TFTs.
[0009]
[Problems to be solved by the invention]
The present inventors have repeatedly made various thoughts and errors in order to improve the crystallinity of a crystalline silicon film having a grain boundary (referred to as a polycrystalline silicon film). Examples thereof include semi-amorphous semiconductors (Japanese Patent Laid-Open No. 57-160121, etc.) and monodomain semiconductors (Japanese Patent Laid-Open No. 8-39019, etc.).
[0010]
The concept common to the semiconductor films described in the above publication is to make the grain boundaries substantially harmless. That is, the biggest problem is to substantially eliminate crystal grain boundaries and to smoothly move carriers (electrons or holes).
[0011]
However, even with the semiconductor film described in the above publication, it can be said that it is insufficient for the high-speed operation required by the logic circuit. In other words, in order to realize a system-on-panel with a built-in logic circuit, development of a completely new material that has not been heretofore required is required.
[0012]
The present invention responds to such a demand, and provides a semiconductor thin film for realizing an extremely high performance semiconductor device capable of constituting a high-speed logic circuit that cannot be manufactured by a conventional TFT. Is an issue. Another object is to provide a semiconductor device using such a semiconductor thin film.
[0013]
[Means for Solving the Problems]
The configuration of the invention disclosed in this specification is as follows.
A semiconductor thin film comprising an aggregate of a plurality of rod-like or flat rod-like crystals,
The plane orientation is approximately {110} orientation, and most crystal lattices are continuous at an arbitrary grain boundary.
[0014]
In addition, the configuration of other inventions is as follows:
A semiconductor thin film comprising an aggregate of a plurality of rod-like or flat rod-like crystals,
The plane orientation is roughly {110} orientation, and most of the lattice fringes observed as crossing an arbitrary grain boundary are linearly continuous between different crystal grains forming the crystal grain boundary. It is characterized by that.
[0015]
The present invention is a technique for realizing a semiconductor thin film having the above-described configuration. A semiconductor device manufactured using such a semiconductor thin film has the following characteristics.
[0016]
(1) At least the channel formation region is composed of a semiconductor thin film made of an aggregate of a plurality of rod-like or flat rod-like crystals, the plane orientation of the semiconductor thin film is approximately {110} orientation, and almost at any grain boundary The crystal lattice is continuous.
(2) At least the channel formation region is composed of a semiconductor thin film composed of an aggregate of a plurality of rod-like or flat rod-like crystals, and the plane orientation of the semiconductor thin film is approximately {110} orientation and crosses an arbitrary grain boundary. In this way, most of the lattice fringes observed are linearly continuous between different crystal grains forming the crystal grain boundary.
[0017]
The configuration of the present invention as described above will be described in detail in the embodiments described below.
[0018]
【Example】
[Example 1]
In this embodiment, a manufacturing process of a semiconductor thin film according to the present invention and a semiconductor device (specifically, a TFT) using the semiconductor thin film as an active layer will be described. Further, after the description of the manufacturing process, the knowledge obtained from the viewpoint of the crystal structure and electrical characteristics of the TFT of the present invention will be described.
[0019]
First, a quartz substrate 801 is prepared as a substrate having an insulating surface. A silicon substrate on which a thermal oxide film is formed can be used instead of the quartz substrate. Alternatively, a method may be employed in which an amorphous silicon film is once formed on a quartz substrate and is completely thermally oxidized to form an insulating film. Further, a quartz substrate, a ceramic substrate, or a silicon substrate on which a silicon nitride film is formed as an insulating film may be used.
[0020]
Reference numeral 802 denotes an amorphous silicon film, which is adjusted so that the final film thickness (thickness considering the film reduction after thermal oxidation) is 10 to 75 nm (preferably 15 to 45 nm). It is important to thoroughly control the impurity concentration in the film during film formation.
[0021]
In this embodiment, the concentrations of C (carbon), N (nitrogen), O (oxygen), and S (sulfur), which are typical impurities, in the amorphous silicon film 802 are all 5 × 10 5. ¹⁸ atoms / cm ^Three Less than (preferably 1x10 ¹⁸ atoms / cm ^Three The following is managed. If each impurity is present at a concentration higher than this, it may adversely affect crystallization and cause deterioration in film quality after crystallization.
[0022]
FIG. 23 shows the result of examining the impurity concentration in the amorphous silicon film manufactured under the conditions of this example by SIMS (mass secondary ion analysis). The sample used was an amorphous silicon film having a thickness of 0.5 μm formed on a silicon wafer. As a result, as shown in FIG. 23, it was confirmed that all elements of C, N, and O were within the above concentration range. However, in this specification, the element concentration in the film is defined by the minimum value in the SIMS measurement result.
[0023]
In order to keep all the elements of C, N, and O within the above-mentioned concentration range, the low-pressure thermal CVD furnace used in this embodiment periodically performs dry cleaning to clean the film formation chamber. Dry cleaning is performed in a furnace heated to about 200 to 400 ° C. and 100 to 300 sccm of ClF. _Three A (chlorine fluoride) gas is allowed to flow, and the film formation chamber may be cleaned with fluorine generated by thermal decomposition.
[0024]
According to the knowledge of the present inventors, the furnace temperature was set to 300 ° C., and ClF _Three When the flow rate of (chlorine fluoride) gas is set to 300 sccm, deposits having a thickness of about 2 μm (mainly containing silicon as a main component) can be completely removed in 4 hours.
[0025]
Note that the hydrogen concentration in the amorphous silicon film 802 is also a very important parameter, and it seems that a film with better crystallinity can be obtained by keeping the hydrogen content low. Therefore, the amorphous silicon film 802 is preferably formed by a low pressure thermal CVD method. Note that the plasma CVD method can be used by optimizing the film formation conditions.
[0026]
Next, a crystallization process of the amorphous silicon film 802 is performed. As a means for crystallization, the technique described in Japanese Patent Application Laid-Open No. 7-130652 by the present inventor is used. Either means of Example 1 and Example 2 of the publication can be used, but it is preferable to use the technical contents described in Example 2 (detailed in JP-A-8-78329) in the present invention.
[0027]
According to the technique described in Japanese Patent Laid-Open No. 8-78329, first, a mask insulating film 803 for selecting a region where a catalyst element is added is formed. The mask insulating film 803 has a plurality of openings for adding a catalytic element. The position of the crystal region can be determined by the position of the opening.
[0028]
Then, a solution containing nickel (Ni) as a catalyst element for promoting crystallization of the amorphous silicon film is applied by a spin coating method to form a Ni-containing layer 804. In addition to nickel, cobalt (Co), iron (Fe), palladium (Pd), platinum (Pt), copper (Cu), gold (Au), germanium (Ge), or the like may be used as the catalyst element. it can. (Fig. 8 (A))
[0029]
The catalyst element addition step may be performed by an ion implantation method or a plasma doping method using a resist mask. In this case, since the occupied area of the added region can be reduced and the growth distance of the lateral growth region can be easily controlled, this is an effective technique for configuring a miniaturized circuit.
[0030]
Next, after the catalyst element addition process is completed, after dehydrogenation at 450 ° C. for about 1 hour, a temperature of 500 to 700 ° C. (typically 550 to 650 ° C.) in an inert atmosphere, hydrogen atmosphere or oxygen atmosphere Then, the amorphous silicon film 802 is crystallized by applying heat treatment for 4 to 24 hours. In this embodiment, heat treatment is performed at 570 ° C. for 14 hours in a nitrogen atmosphere.
[0031]
At this time, crystallization of the amorphous silicon film 802 proceeds preferentially from nuclei generated in the region 805 to which nickel is added, and a crystal region 806 that grows substantially parallel to the substrate surface of the substrate 801 is formed. . The inventors refer to this crystal region 306 as a lateral growth region. Since the lateral growth regions are relatively aligned and individual crystals are gathered, there is an advantage that the overall crystallinity is excellent. (Fig. 8 (B))
[0032]
Even when the technique described in Example 1 of the above-mentioned Japanese Patent Application Laid-Open No. 7-306052 is used, a region that can be microscopically referred to as a lateral growth region is formed. However, since nucleation occurs non-uniformly in the plane, there is a difficulty in controlling the grain boundary.
[0033]
After the heat treatment for crystallization is completed, the mask insulating film 803 is removed and patterning is performed, so that an island-shaped semiconductor layer (active layer) 807 including only the lateral growth region 806 is formed.
[0034]
Next, a gate insulating film 808 made of an insulating film containing silicon is formed. The thickness of the gate insulating film 808 may be adjusted in the range of 20 to 250 nm in consideration of the increase due to the subsequent thermal oxidation process. As a film formation method, a known vapor phase method (plasma CVD method, sputtering method, or the like) may be used.
[0035]
Next, as shown in FIG. 8C, heat treatment (catalyst element gettering process) for removing or reducing the catalytic element (nickel) is performed. In this heat treatment, a halogen element is included in the treatment atmosphere, and the gettering effect of the metal element by the halogen element is used.
[0036]
Note that the heat treatment is preferably performed at a temperature exceeding 700 ° C. in order to sufficiently obtain the gettering effect by the halogen element. Below this temperature, decomposition of the halogen compound in the processing atmosphere becomes difficult, and the gettering effect may not be obtained.
[0037]
Therefore, in this embodiment, this heat treatment is performed at a temperature exceeding 700 ° C., preferably 800 to 1000 ° C. (typically 950 ° C.), and the treatment time is 0.1 to 6 hr, typically 0.5 to 1 hr.
[0038]
In this example, heat treatment is performed at 950 ° C. for 30 minutes in an atmosphere containing hydrogen chloride (HCl) at a concentration of 0.5 to 10% by volume (3% by volume in this example) with respect to the oxygen atmosphere. An example of performing If the HCl concentration is equal to or higher than the above concentration, the surface of the active layer 807 is not preferable because unevenness of about the film thickness occurs.
[0039]
In addition, an example in which HCl gas is used as a compound containing a halogen element has been shown, but as other gases, typically HF, NF _Three , HBr, Cl ₂ , ClF _Three , BCl _Three , F ₂ , Br ₂ One or more compounds selected from halogen-containing compounds such as the above can be used.
[0040]
In this step, it is considered that nickel in the active layer 807 is gettered by the action of chlorine, becomes volatile nickel chloride and is separated into the atmosphere and removed. By this step, the concentration of nickel in the active layer 807 is 5 × 10 ¹⁷ atoms / cm ^Three Reduced to:
[0041]
5 × 10 ¹⁷ atoms / cm ^Three The value is the detection lower limit of SIMS (mass secondary ion analysis). As a result of analyzing the TFT prototyped by the inventors, 1 × 10 ¹⁸ atoms / cm ^Three Below (preferably 5 × 10 ¹⁷ atoms / cm ^Three In the following, no influence of nickel on TFT characteristics was confirmed. However, the impurity concentration in this specification is defined by the minimum value of the measurement result of SIMS analysis.
[0042]
In addition, a thermal oxidation reaction proceeds at the interface between the active layer 807 and the gate insulating film 808 by the heat treatment, and the thickness of the gate insulating film 808 is increased by the thermal oxide film. When the thermal oxide film is formed in this way, a semiconductor / insulating film interface with very few interface states can be obtained. In addition, there is an effect of preventing formation defects (edge thinning) of the thermal oxide film at the end portion of the active layer.
[0043]
Further, it is also effective to improve the film quality of the gate insulating film 808 by performing heat treatment in a nitrogen atmosphere and then performing heat treatment in a nitrogen atmosphere for about 1 hour at 950 ° C. for about 1 hour.
[0044]
Note that the halogen element used in the gettering process is 1 × 10 6 in the active layer 807 by SIMS analysis. ¹⁵ ~ 1 × 10 ²⁰ atoms / cm ^Three It has also been confirmed that it remains at a concentration of. At that time, SIMS analysis has confirmed that the halogen element described above is distributed in a high concentration between the active layer 807 and the thermal oxide film formed by heat treatment.
[0045]
In addition, as a result of conducting SIMS analysis for other elements, typical impurities C (carbon), N (nitrogen), O (oxygen), and S (sulfur) are all 5 × 10 5. ¹⁸ atoms / cm ^Three Less than (typically 1x10 ¹⁸ atoms / cm ^Three The following was confirmed.
[0046]
Next, a metal film mainly composed of aluminum (not shown) is formed, and a gate electrode prototype 809 is formed by patterning. In this embodiment, an aluminum film containing 2 wt% scandium is used. In addition, a tantalum film, a conductive silicon film, or the like can be used. (Fig. 8 (D))
[0047]
Here, the technique described in Japanese Patent Laid-Open No. 7-13518 by the present inventors is used. This publication discloses a technique for forming source / drain regions and low-concentration impurity regions in a self-aligning manner using an oxide film formed by anodic oxidation.
[0048]
First, a porous anodic oxide film 810 is formed by anodizing in a 3% oxalic acid aqueous solution while leaving a resist mask (not shown) used for patterning the aluminum film.
[0049]
The thickness of the porous anodic oxide film 810 increases in proportion to time. Further, since the resist mask remains on the upper surface, it is formed only on the side surface of the gate electrode prototype 809. In the technique described in Japanese Patent Laid-Open No. 7-13318, this film thickness later becomes the length of a low concentration impurity region (also referred to as an LDD region). In this embodiment, the anodic oxidation process is performed under the condition that the film thickness is 700 nm.
[0050]
Next, after removing a resist mask (not shown), anodization is performed in an electrolytic solution in which 3% tartaric acid is mixed with an ethylene glycol solution. In this process, a dense non-porous anodic oxide film 811 is formed. In addition, since the electrolytic solution permeates into the porous anodic oxide film, it is also formed inside the porous anodic oxide film.
[0051]
The film thickness of the nonporous anodic oxide film 811 is determined according to the applied voltage. In this embodiment, the anodic oxidation treatment is performed at an applied voltage of 80 V so as to be formed with a film thickness of about 100 nm.
[0052]
The aluminum film 812 remaining after the above two anodic oxidation processes substantially functions as a gate electrode.
[0053]
When the state of FIG. 8E is thus obtained, the gate insulating film 808 is then etched by dry etching using the gate electrode 812 and the porous anodic oxide film 810 as a mask. Then, the porous anodic oxide film 810 is removed. The end portion of the gate insulating film 813 thus formed is exposed by the thickness of the porous anodic oxide film 810. (Fig. 9 (A))
[0054]
Next, an impurity element adding step for imparting one conductivity is performed. As the impurity element, P (phosphorus) or As (arsenic) may be used for the N type, and B (boron) may be used for the P type.
[0055]
In this embodiment, first impurity addition is performed at a high acceleration voltage, and n ^- Regions 814 and 815 are formed. At this time, since the acceleration voltage is as high as about 80 keV, the impurity element is added not only to the active layer surface but also to the exposed end portion of the gate insulating film. This n ^- The regions 814 and 815 have an impurity concentration of 1 × 10 ¹⁸ ~ 1 × 10 ¹⁹ atoms / cm ^Three Adjust so that (Figure 9 (B))
[0056]
Further, the second impurity addition is performed at a low acceleration voltage, and n ⁺ Regions 816 and 817 are formed. At this time, since the acceleration voltage is as low as about 10 keV, the gate insulating film functions as a mask. This n ⁺ The regions 816 and 817 are adjusted so that the sheet resistance is 500Ω or less (preferably 300Ω or less). (Figure 9 (C))
[0057]
The impurity region formed by the above steps is n ⁺ The region becomes a source region 816 and a drain region 817, and n ^- The region becomes a low concentration impurity region 818. In addition, the region immediately below the gate electrode is not added with an impurity element, and becomes a substantially intrinsic channel formation region 819.
[0058]
Note that the low-concentration impurity region 818 has an effect of relaxing a high electric field applied between the channel formation region 819 and the drain region 817 and is also referred to as an LDD (lightly doped drain) region.
[0059]
When the active layer is completed as described above, the impurity element is activated by a combination of furnace annealing, laser annealing, lamp annealing and the like. At the same time, the damage of the active layer received in the addition process is also repaired.
[0060]
Next, an interlayer insulating film 820 is formed to a thickness of 500 nm. As the interlayer insulating film 820, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an organic resin film, or a stacked film thereof can be used.
[0061]
Note that polyimide, acrylic, polyamide, polyimide amide, or the like is used as the organic resin film. The advantages of the organic resin film are as follows: (1) the film forming method is simple, (2) the film thickness can be easily increased, (3) the parasitic capacitance can be reduced because the relative dielectric constant is low, and (4) ▼ It has excellent flatness.
[0062]
Next, after forming contact holes, a source electrode 821 and a drain electrode 822 are formed. Finally, the entire substrate is heated in a hydrogen atmosphere at 350 ° C. for 1 to 2 hours, and the entire device is hydrogenated to terminate dangling bonds (unpaired bonds) in the film (particularly in the active layer).
[0063]
Through the above steps, a TFT having a structure as shown in FIG. 9D can be manufactured. The characteristics of the TFT thus obtained will be described below.
[0064]
[Knowledge about the crystal structure of the active layer]
When viewed microscopically, the active layer formed in accordance with the above manufacturing process has a crystal structure in which a plurality of rod-like or flat rod-like crystals are arranged in parallel to each other with regularity in a specific direction. This can be easily confirmed by observation with a TEM (transmission electron microscope).
[0065]
Here, FIG. 1 shows an HR-TEM photograph in which the grain boundary between rod-like or flat rod-like crystals is enlarged 8 million times. In the present specification, a crystal grain boundary is defined as a grain boundary formed at a boundary where a rod-shaped or flat rod-shaped crystal is in contact. Therefore, for example, it is considered to be distinguished from a grain boundary in a macro sense such that the laterally grown regions collide with each other.
[0066]
By the way, the above-mentioned HR-TEM (High Resolution Transmission Electron Microscopy) is a method in which an electron beam is irradiated perpendicularly to a sample and the atomic / molecular arrangement is evaluated using interference of transmitted electrons and elastically scattered electrons. It is.
[0067]
In HR-TEM, it is possible to observe the arrangement state of crystal lattices as lattice fringes. Therefore, by observing the crystal grain boundary, it is possible to infer the bonding state between atoms at the crystal grain boundary. Note that the lattice stripes appear as white and black stripes, but they are different in contrast and do not indicate the position of atoms.
[0068]
FIG. 1A is a typical TEM photograph of a crystalline silicon film obtained by the present invention, in which two different crystal grains are in contact with each other at the grain boundary seen from the upper left to the lower right of the photograph. . At this time, the two crystal grains had a roughly {110} orientation although the crystal axes included some deviation.
[0069]
As will be described later, as a result of examining a plurality of crystal grains, it has been confirmed by X-ray diffraction and electron beam diffraction that almost all have a substantially {110} orientation.
[0070]
It should be noted that although there are many (011) planes and (101) planes among many observed, these equivalent planes are collectively expressed as {110} planes. This point will be briefly described with reference to FIG.
[0071]
FIG. 2A is an example schematically showing crystal grains whose crystal plane is {110} plane (crystal axis is <110>). The {111} crystal plane includes the <111> axis, the <100> axis, and the like.
[0072]
The notation method as shown in FIG. 2A is an example of collective exponential notation. When this is expressed in strict exponent notation, it becomes as shown in FIGS. 2 (B) and 2 (C). For example, the crystal axis [110] and the crystal axis [01-1] are both equivalent and are summarized by <110>.
[0073]
In addition, although it describes with [01-1] on account of a format, (-) of -1 is used instead of the logic symbol showing inversion.
[0074]
As described above, various discussions can be made by discussing with a strict crystal orientation (crystal axis). For the sake of simplification, the following descriptions are all expressed in collective exponential notation. Of course, similar physical properties can be obtained on all equivalent crystal planes.
[0075]
By the way, as shown in FIG. 1A, lattice fringes corresponding to the {111} plane and the {100} plane are observed in the plane. Note that the lattice stripe corresponding to the {111} plane refers to a lattice stripe such that a {111} plane appears in a cross section when crystal grains are cut along the lattice stripe. It can be simply confirmed from the interval between the lattice fringes what surface the lattice fringes correspond to. In the case of FIG. 1A, the interval between the lattice stripes corresponding to the {111} plane is about 0.3 nm.
[0076]
In addition, while the upper crystal grains in FIG. 1A can confirm a plurality of lattice stripes in the vertical, horizontal, and diagonal directions, only one lattice stripe is visible in the lower crystal grains. The reason is considered that the irradiation direction of the electron beam at the time of TEM observation has an influence. In other words, the upper crystal grains are perpendicular to the crystal plane, so that a plurality of in-plane lattice stripes can be seen, but the lower crystal grains are slightly inclined when the upper crystal is used as a reference. Is not perpendicular, and only a specific checkered pattern is visible.
[0077]
Here, attention is paid to the lattice pattern corresponding to the {111} plane. As apparent from FIG. 1 (A), the lattice stripes corresponding to the {111} plane of the upper crystal grain (two of which are visible in the figure but one of them) and the {111} plane of the lower crystal grain The checkered stripes are parallel to each other.
[0078]
Regardless of the existence of the crystal grain boundary, lattice fringes of two different crystal grains are connected so as to cross the crystal grain boundary. That is, it can be confirmed that most of the lattice fringes observed across the grain boundary are linearly continuous despite the fact that they are lattice fringes of different crystal grains. This is the same at an arbitrary crystal grain boundary, and 90% or more (typically 95% or more) of the lattice fringes keeps continuity at the crystal grain boundary.
[0079]
Such a crystal structure is the greatest feature of the crystalline silicon film of the present invention, and is a crystal structure that realizes the crystal grain boundary sought by the present inventors.
[0080]
Such a crystal structure (exactly, the structure of the crystal grain boundary) indicates that two different crystal grains are joined with extremely good consistency at the crystal grain boundary. That is, the crystal lattice is continuously connected at the crystal grain boundary, and the trap level caused by crystal defects or the like is very difficult to create. In other words, it can be said that the crystal lattice has continuity at the grain boundaries.
[0081]
For reference, an HR-TEM photograph of a conventional high-temperature polysilicon film is shown in FIG. In the case of FIG. 1B, although described later, there is no regularity in the crystal plane, and the orientation was not mainly the {110} plane. However, here, for comparison with FIG. 1A, crystal grains in which lattice fringes corresponding to the {111} plane appear were observed.
[0082]
In the lattice fringes in FIG. 1B, only one upper and lower crystal grains are visible. The reason for this is as described above. Moreover, as a result of measuring the lattice fringe spacing by the same method as before, it can be confirmed that the lattice fringes seen in the upper and lower crystal grains are lattice fringes corresponding to the {111} plane as shown in FIG. It was.
[0083]
However, as shown in FIG. 1B, the lattice fringes are not parallel to each other, and it was found that the crystal structure is clearly different from that shown in FIG.
[0084]
Further, as indicated by arrows in the figure, a large number of portions where lattice fringes are interrupted can be confirmed at the crystal grain boundaries. In such a portion, a dangling bond (which can be called a crystal defect) is present, and there is a high possibility of inhibiting the movement of carriers as a trap level.
[0085]
As described above, in the crystalline silicon film of the present invention, the lattice has continuity even at the crystal grain boundary, and such crystal defects could hardly be confirmed. Also from this point, it is proved that the crystalline silicon film of the present invention is a semiconductor film clearly different from the conventional high-temperature polysilicon.
[0086]
Next, the result of examining the crystalline silicon film of the present invention by electron beam diffraction is shown in FIG. Here, FIG. 3A shows a typical electron diffraction pattern of the crystalline silicon film of the present invention, and FIG. 3B shows a typical electron diffraction pattern of a conventional high-temperature polysilicon film as a reference. Show.
[0087]
3A and 3B are measured with the diameter of the electron beam irradiation spot being 1.35 μm, it can be considered that information of a sufficiently macro region is picked up compared to the lattice fringe level.
[0088]
FIG. 3C shows an electron beam diffraction pattern when an electron beam is irradiated perpendicularly to the {110} plane of single crystal silicon. Usually, such an electron diffraction pattern is compared with the observation result to infer what the orientation of the observation sample is.
[0089]
In the case of FIG. 3 (A), diffraction spots corresponding to <110> incidence as shown in FIG. 3 (C) appear relatively cleanly, and the crystal axis is the <110> axis (the crystal plane is {110} Can be confirmed.
[0090]
Each spot has a slightly concentric spread, which is presumed to have a certain rotation angle distribution around the crystal axis. The extent of the spread is within 5 ° even if estimated from the pattern.
[0091]
In addition, there were cases where the diffraction spots were partially invisible while many observations were made (a part of the diffraction spots could not be seen in FIG. 3A). Although it is probably {110} orientation, the diffraction pattern seems to be invisible because the crystal axis is slightly shifted.
[0092]
Based on the fact that the {111} plane is almost always included in the crystal plane, the present inventors presume that such a phenomenon is probably caused by a shift in the rotation angle around the <111> axis.
[0093]
On the other hand, in the case of the electron beam diffraction pattern shown in FIG. 3B, no clear regularity is seen in the diffraction spots, and it can be confirmed that they are oriented almost randomly. That is, it is expected that crystals having a plane orientation other than the {110} plane are irregularly mixed.
[0094]
As shown by these results, the crystalline silicon film of the present invention is characterized in that almost all crystal grains are oriented substantially in the {110} plane and that the lattice is continuous at the grain boundaries. . This feature is not present in conventional polysilicon films.
[0095]
The reason why almost all crystal grains are oriented in the {110} plane is presumed as follows from the contents described in JP-A-7-321339 by the present inventors.
[0096]
When the amorphous silicon film is crystallized, the growth direction of a rod-like or flat rod-like crystal (sometimes called a needle-like or columnar crystal) that grows substantially parallel to the substrate is the <111> axis according to a TEM photograph. It has been confirmed. This situation is schematically shown in FIG.
[0097]
When crystallizing an amorphous silicon film using Ni as a catalyst element, NiSi ₂ Crystals grow along the <111> axis direction with the precipitate as a medium. This is NiSi ₂ This is probably because the {111} faces of the crystal planes of Si and Si are structurally consistent.
[0098]
In addition, since the inside of the grown rod-shaped or flat rod-shaped crystal can be regarded as a single crystal substantially, it is indicated as c-Si (crystal silicon) in FIG.
[0099]
At this time, various surfaces can be formed on the side surface (surface parallel to the growth direction) of the rod-like or flat rod-like crystal grown along the <111> axis direction, but the surface most likely to appear is the {110} plane That's it. This is considered because the {110} plane has the highest atomic density among several planes that can be formed on the side face.
[0100]
For these reasons, in the crystal grains grown from the {111} plane as in the present invention (crystal grains grown along the <111> axis direction), the {110} plane is the surface (meaning the observation plane). Will appear.
[0101]
The present inventors performed X-ray diffraction according to the method described in JP-A-7-321339, and calculated the orientation ratio of the crystalline silicon film of the present invention. In this publication, the orientation ratio is defined by a calculation method as shown in the following equation (1).
[0102]
[Expression 1]

[0103]
Here, an example of the result of measuring the orientation of the semiconductor thin film of the present invention by X-ray diffraction is shown in FIG. In the X-ray diffraction pattern, a peak corresponding to the (220) plane appears, but it goes without saying that it is equivalent to the {110} plane. As a result of this measurement, it was found that the {110} plane was the main orientation, and the orientation ratio was 0.7 or more (typically 0.9 or more).
[0104]
As described above, it can be seen that the crystalline silicon film of the present invention and the conventional polysilicon film have completely different crystal structures (crystal structures). Also from this point, it can be said that the crystalline silicon film of the present invention is a completely new semiconductor film.
[0105]
In forming the semiconductor thin film of the present invention, the annealing step at a temperature higher than the crystallization temperature (in this example, the step shown in FIG. 8C) plays an important role in reducing defects in crystal grains. Plays. Explain that.
[0106]
FIG. 21A is a TEM photograph in which the crystalline silicon film at the time when the crystallization process shown in FIG. 8B is completed is enlarged by 250,000 times. Defects appearing in a zigzag pattern as shown by arrows in FIG.
[0107]
Such defects are mainly stacking faults in which the stacking order of atoms on the silicon crystal lattice plane is different, but there are also cases such as dislocations. FIG. 21A seems to be a stacking fault having a defect plane parallel to the {111} plane. This can be inferred from the fact that the zigzag defect is bent at an angle of about 70 °.
[0108]
On the other hand, as shown in FIG. 21B, the crystalline silicon film of the present invention viewed at the same magnification has very little crystallinity and no defects due to stacking faults or dislocations are observed in the crystal grains. It can be confirmed that it is expensive. This tendency is true for the entire film surface, and it is difficult to reduce the number of defects to zero, but it can be reduced to a level that can be regarded as substantially zero.
[0109]
That is, in the crystalline silicon film shown in FIG. 21B, defects in the crystal grains are reduced to an almost negligible level, and the crystal grain boundary cannot be a barrier for carrier movement due to high continuity. It can be regarded as a crystal or substantially a single crystal.
[0110]
As described above, the crystal silicon films shown in the photographs of FIGS. 21A and 21B have substantially the same continuity in the crystal grain boundaries, but there is a large difference in the number of defects in the crystal grains. . The reason why the crystalline silicon film of the present invention shows much higher electrical characteristics than the crystalline silicon film shown in FIG. 21A is largely due to the difference in the number of defects.
[0111]
From the above, it can be seen that the process shown in FIG. 8C is an indispensable process for the present invention. The present applicant considers the following model for the phenomenon caused by this process.
[0112]
First, in the state shown in FIG. 21A, a catalyst element (typically nickel) is segregated in defects (mainly stacking faults) in crystal grains. That is, it is considered that there are many bonds in the form of Si-Ni-Si.
[0113]
However, when Ni present in the defect is removed by performing the gettering process of the catalytic element, the Si—Ni bond is broken. As a result, the excess bond in silicon immediately forms a Si-Si bond and stabilizes. Thus, the defect disappears.
[0114]
Of course, it is known that defects in the crystalline silicon film disappear by thermal annealing at a high temperature. However, in the present invention, the bond with nickel is broken and a lot of dangling bonds are generated, so that the recombination of silicon is further increased. It can be estimated that it is performed smoothly.
[0115]
At the same time, it is thought that surplus silicon atoms generated when the crystalline silicon film is thermally oxidized move to defects and contribute greatly to the generation of Si-Si bonds. This concept is known as the reason why there are few defects in the crystal grains of the high-temperature polysilicon film.
[0116]
In addition, the present applicant performs a heat treatment at a temperature exceeding the crystallization temperature (typically 700 to 1100 ° C.), so that the crystalline silicon film and its base are fixed, and the adhesion is increased, so that defects are increased. I'm thinking of a model that disappears.
[0117]
Crystal silicon film and below With the ground Become Quartz substrate There is a difference of nearly 10 times in the thermal expansion coefficient. Therefore, at the stage where the amorphous silicon film is transformed to the crystalline silicon film (FIG. 21A), a very large stress is applied to the crystalline silicon film when the crystalline silicon film is cooled.
[0118]
This will be described with reference to FIG. FIG. 22A shows the thermal history of the crystalline silicon film after the crystallization process. First, the temperature (t ₁ The crystallized silicon film crystallized in step) is cooled to room temperature through a cooling period (a).
[0119]
Here, FIG. 22B shows a crystalline silicon film during the cooling period (a), where 1050 is a quartz substrate and 1051 is a crystalline silicon film. At this time, the adhesiveness at the interface 1052 between the crystalline silicon film 1051 and the quartz substrate 1050 is not so high, and it is considered that many intragranular defects are generated due to this.
[0120]
That is, it is considered that the crystalline silicon film 1051 pulled due to the difference in thermal expansion coefficient is very easy to move on the quartz substrate 1050, and defects 1053 such as stacking faults and dislocations are easily generated by a force such as tensile stress.
[0121]
The crystalline silicon film thus obtained is in a state as shown in FIG. Then, as shown in FIG. 22 (A), the temperature (t ₂ ), A catalytic element gettering step is performed, and as a result, defects in the crystalline silicon film disappear for the reasons described above.
[0122]
What is important here is that the crystalline silicon film is fixed to the quartz substrate at the same time as the catalytic element gettering step is performed, and the adhesion to the quartz substrate is enhanced. That is, it is considered that this gettering step also serves as a fixing step between the crystalline silicon film and the quartz substrate (base).
[0123]
When the gettering + adhering step is completed in this way, it is cooled to room temperature through a cooling period (b). Here, the difference from the cooling period (a) after the crystallization step is that the interface 1055 between the quartz substrate 1050 and the annealed crystalline silicon film 1054 is in a highly adhesive state. (Fig. 22 (C))
[0124]
When the adhesion is high, the crystalline silicon film 1054 is completely fixed to the quartz substrate 1050. Therefore, even if stress is applied to the crystalline silicon film in the cooling stage of the crystalline silicon film, no defect is generated. . That is, it is possible to prevent a defect from occurring again.
[0125]
Note that in FIG. 22A, a process of lowering to room temperature after the crystallization step is taken as an example, but when crystallization is completed, the temperature can be raised as it is to perform the gettering + fixing step. Even through such a process, the crystalline silicon film of the present invention can be obtained.
[0126]
The thus obtained crystalline silicon film of the present invention (FIG. 21B) has a remarkably smaller number of defects in the crystal grains than the crystalline silicon film that has just been crystallized (FIG. 21A). It has the characteristics.
[0127]
The difference in the number of defects appears as a difference in spin density by electron spin resonance analysis (Electron Spin Resonance: ESR). At present, the spin density of the crystalline silicon film of the present invention is at least 5 × 10 ¹⁷ spins / cm ^Three Below (preferably 3 × 10 ¹⁷ spins / cm ^Three The following): However, since this measured value is close to the detection limit of existing measuring devices, the actual spin density is expected to be even lower.
[0128]
The crystalline silicon film of the present invention having the above crystal structure and characteristics is called continuous grain boundary crystalline silicon (CGS).
[0129]
[Knowledge about electrical characteristics of TFT]
A TFT fabricated using the crystalline silicon film as described above as an active layer exhibits electrical characteristics as shown in FIG. FIG. 4 shows an Id-Vg curve (Id-Vg characteristic) of an N-channel TFT plotted with the gate voltage (Vg) on the horizontal axis and the logarithm of the drain voltage (Id) on the vertical axis. The electrical characteristics were measured using a commercially available apparatus (manufactured by Hewlett-Packard Company: Model No. 4145B).
[0130]
In FIG. 4, 401 indicates the electrical characteristics of the TFT using the active layer obtained in the above process, and 402 indicates the electrical characteristics of the conventional TFT. Here, as a conventional TFT, a TFT in which heat treatment (gettering process) after formation of the gate insulating film is not performed in Example 1 is cited.
[0131]
Comparing the characteristics of both transistors, it can be confirmed that even when the gate voltage is the same, the characteristic indicated by 401 flows an on-current that is nearly 2 to 4 digits larger. Note that the on-current refers to a drain current that flows when the TFT is in an on state (a gate voltage in the range of about 0 to 5 V in FIG. 4).
[0132]
It can also be confirmed that the characteristic indicated by 401 has a superior subthreshold characteristic. The subthreshold characteristic is a parameter indicating the steepness of the switching operation of the TFT. It can be said that the subthreshold characteristic is better as the rise of the Id-Vg curve when the TFT is switched to the on or off state is steeper.
[0133]
The typical electrical characteristics of the TFT obtained by the present invention are as follows.
(1) Sub-threshold coefficient, which is a parameter indicating TFT switching performance (agility of switching on / off operation), is 60-100 mV / decade for both N-type TFT and P-type TFT (typically 60-85 mV / decade) and small. This data value is almost equivalent to that of an insulated gate field effect transistor (IGFET) using single crystal silicon.
(2) Field effect mobility (μ) which is a parameter indicating the speed of operation of the TFT _FE ) 200-650cm for N-type TFT ² / Vs (typically 250-300cm ² / Vs), 100-300cm with P-type TFT ² / Vs (typically 150-200cm ² / Vs).
(3) The threshold voltage (V _th ) Is as low as -0.5 to 1.5 V for N-type TFTs and -1.5 to 0.5 V for P-type TFTs. This means that the power consumption can be reduced by driving with a small power supply voltage.
[0134]
As described above, the TFT obtained by the present invention has extremely excellent switching characteristics and high-speed operation characteristics.
[0135]
(Characteristics of the circuit constituted by the TFT of the present invention)
Next, frequency characteristics of a ring oscillator manufactured by the present inventors using the TFT obtained by the present invention will be shown. The ring oscillator is a circuit in which inverter circuits having a CMOS structure are connected in an odd-numbered ring shape, and is used to obtain a delay time per inverter circuit. The structure of the ring oscillator used in the experiment is as follows.
Number of stages: 9 stages
TFT gate insulating film thickness: 30nm and 50nm
TFT gate length: 0.6μm
[0136]
FIG. 5 shows the result of measuring the oscillation frequency of the ring oscillator when the power supply voltage is 5 V with a spectrum analyzer. In FIG. 5, the horizontal axis represents the power supply voltage (V _DD ), The vertical axis represents the oscillation frequency (f _osc ). As shown in FIG. 5, an oscillation frequency of 1 GHz or more is realized when a TFT having a gate insulating film of 30 nm is used.
[0137]
FIG. 6 shows the output spectrum of the spectrum analyzer when an oscillation frequency of 1.04 GHz is obtained. The horizontal axis is the frequency from 1 to 1.1 GHz, and the vertical axis is the voltage (output amplitude) taken on the log scale. As apparent from FIG. 6, the peak of the output spectrum appears at about 1.04 GHz. The output spectrum has a tail due to the resolution of the apparatus, and does not affect the experimental results.
[0138]
In addition, a shift register, which is actually one of the TEGs of the LSI circuit, was manufactured and the operating frequency was confirmed. As a result, an output pulse having an operating frequency of 100 MHz was obtained in a shift register circuit having a gate insulating film thickness of 30 nm, a gate length of 0.6 μm, a power supply voltage of 5 V, and 50 stages.
[0139]
The phenomenal data of the ring oscillator and shift register as described above show that the TFT of the present invention has a performance comparable to or surpassing that of an IGFET using single crystal silicon.
[0140]
There is the following data as evidence to support it. The data shown in FIG. 7 shows the power supply voltage (V _DD ), The vertical axis represents the delay time per stage of the inverter with F / O = 1 (fanout ratio is 1) (τ _pd (Innovation of logic LSI technology, Kenji Maeguchi et al., P108, Science Forum, Inc., 1995).
[0141]
Note that various curves (shown by dotted lines) in the figure are data when IGFETs using single crystal silicon are produced according to various design rules, and show so-called scaling rules.
[0142]
When the relationship between the delay time of the inverter obtained by using the above-described ring oscillator and the power supply voltage is applied to this figure, a curve indicated by a solid line in FIG. 7 is obtained. It should be noted that the channel length is 0.5 μm and the gate insulating film thickness (t _OX ) Is superior in performance to an inverter manufactured with a TFT having a channel length of 0.6 μm and a gate insulating film thickness of 30 nm, compared to an inverter manufactured with an IGFET of 11 nm.
[0143]
This clearly shows that the TFT obtained by the present inventor has performance superior to that of IGFET. For example, even if the thickness of the gate insulating film constituting the TFT is set to be three times or more that of the IGFET, the gate insulating film having the same or higher performance can be obtained. That is, it can be said that the TFT of the present invention has an equivalent breakdown voltage and an insulation voltage superior to that of an IGFET having an operation performance.
[0144]
At the same time, higher performance can be realized if the TFT of the present invention is miniaturized according to the scaling law. For example, if a ring oscillator is made with a 0.2 μm rule, it is expected that an operating frequency of 9 GHz can be realized according to the scaling rule (because the operating frequency f is inversely proportional to the square of the channel length L).
[0145]
As described above, it was confirmed that the TFT of the present invention has extremely excellent characteristics, and the semiconductor circuit formed using the TFT is a completely new TFT capable of realizing a high-speed operation of 10 GHz or more.
[0146]
[Knowledge about the relationship between TFT characteristics and CGS]
The excellent TFT characteristics and circuit characteristics as described above are largely due to the use of a semiconductor thin film having continuity in the crystal lattice at the crystal grain boundary as the active layer of the TFT. The reason is discussed below.
[0147]
The continuity of the crystal lattice at the crystal grain boundary results from the fact that the crystal grain boundary is a grain boundary called “planar grain boundary”. The definition of the planar grain boundary in this specification is “Characterization of High-Efficiency Cast-Si Solar Cell Wafers by MBIC Measurement; Ryuichi Shimokawa and Yutaka Hayashi, Japanese Journal of Applied Physics vol.27, No.5, pp.751”. -758, 1988 ”is the“ Planar boundary ”.
[0148]
According to the above paper, the planar grain boundaries include {111} twin grain boundaries, {111} stacking faults, {221} twin grain boundaries, {221} twist grain boundaries, and the like. This planar grain boundary is characterized by being electrically inactive. That is, although it is a crystal grain boundary, it does not function as a trap that inhibits the movement of carriers, and thus can be regarded as substantially nonexistent.
[0149]
In particular, the {111} twin boundaries are also called Σ3 corresponding grain boundaries, and the {221} twin boundaries are also called Σ9 corresponding grain boundaries. The Σ value is a parameter that serves as a guideline indicating the degree of consistency of the corresponding grain boundary. It is known that the smaller the Σ value, the better the grain boundary.
[0150]
As a result of observing the semiconductor thin film of the present invention in detail by TEM, most of the crystal grain boundaries (90% or more, typically 95% or more) are the corresponding grain boundaries of Σ3, that is, {111} twin grains. Turned out to be a world.
[0151]
In the crystal grain boundary formed between two crystal grains, when the plane orientation of both crystals is {110}, assuming that the angle formed by the lattice stripes corresponding to the {111} plane is θ, θ = 70.5 ° It is known that sometimes it becomes the corresponding grain boundary of Σ3.
[0152]
Accordingly, in the crystal grain boundary shown in the TEM photograph of FIG. 1A, each lattice stripe of adjacent crystal grains is continuous at an angle of about 70 °, and this crystal grain boundary is a {111} twin grain boundary. It can be easily inferred that
[0153]
Incidentally, when θ = 38.9 °, the corresponding grain boundary of Σ9 is obtained, but such other crystal grain boundaries also existed.
[0154]
Such a corresponding grain boundary is formed only between crystal grains having the same plane orientation. That is, because the semiconductor thin film of the present invention has a plane orientation of approximately {110}, such a corresponding grain boundary can be formed over a wide range. This feature is not possible with other polysilicon films with irregular surface orientation.
[0155]
Here, a TEM photograph (dark field image) obtained by enlarging the semiconductor thin film of the present invention 15,000 times is shown in FIG. There are areas that appear white and areas that appear black, but the portions that appear the same color indicate that the orientation is the same.
[0156]
What should be noted in FIG. 25A is that, in such a wide-range dark field image, white-looking regions are continuously gathered at a considerable rate. This means that crystal grains having the same orientation exist with a certain degree of orientation, and adjacent crystal grains have almost the same orientation.
[0157]
On the other hand, FIG. 25B shows a TEM photograph (dark field image) obtained by enlarging a conventional high-temperature polysilicon film by 15,000 times. In the conventional high-temperature polysilicon film, the portions having the same plane orientation are scattered in a scattered manner, and it is not possible to confirm a set of directivity as shown in FIG. This is considered because the orientation of adjacent crystal grains is completely irregular.
[0158]
In addition to the measurement points shown in FIG. 1, the applicant repeated observation and measurement over a large number of regions, and the continuity of the crystal lattice at the crystal grain boundaries was large in a region sufficient to produce a TFT. It is confirmed that it is maintained.
[0159]
[Example 2]
In Example 1, an example in which a silicon film is used as a semiconductor film is shown. _X Ge _1-X It is also effective to use a silicon film containing 1 to 10% germanium as indicated by (0 <X <1, preferably 0.9 ≦ X ≦ 0.99).
[0160]
When such a compound semiconductor film is used, the threshold voltage can be reduced when an N-type TFT and a P-type TFT are manufactured. In addition, field effect mobility (called mobility) can be increased.
[0161]
Example 3
In Example 1, since no impurity is intentionally added to the active layer, the channel formation region becomes intrinsic or substantially intrinsic. In addition, substantially intrinsic means that (1) the activation energy of the silicon film is almost ½ (the Fermi level is located at the center of the forbidden body), and (2) impurities more than the spin density. Either a low concentration or (3) no intentional addition of impurities is satisfied.
[0162]
However, the TFT of the present invention can use a known channel doping technique. The channel doping technique is a technique of adding impurities to at least a channel formation region for threshold control.
[0163]
Since the present invention originally has a very small threshold value, the concentration of the impurity added may be very small. It is very preferable that the addition concentration is very small because the threshold value can be controlled without reducing the carrier mobility.
[0164]
Example 4
In this embodiment, a structure for obtaining a gettering effect by a phosphorus element in addition to the gettering effect by a halogen element shown in the first embodiment will be described. FIG. 10 is used for the description.
[0165]
First, a gettering process using a halogen element is performed according to the steps of Example 1 to obtain the state of FIG. Next, the gate electrode 11 made of tantalum or a material mainly composed of tantalum is formed.
[0166]
Next, the anodized film 12 is formed by anodizing the surface of the gate electrode 11. The anodized film 12 functions as a protective film. (Fig. 10 (A))
[0167]
Next, the gate insulating film 808 is etched by dry etching using the gate electrode 11 as a mask. Then, impurity regions 13 and 14 are formed by adding phosphorus or arsenic ions in this state. (Fig. 10 (B))
[0168]
Next, after forming a thick silicon nitride film, etch back is performed by a dry etching method to form sidewalls 15. After the sidewall 15 is formed, phosphorus or arsenic ions are added again to form the source region 16 and the drain region 17. (Fig. 10 (C))
[0169]
Note that the second phosphorus element is not added below the side wall 15, and a pair of low-concentration impurity regions 18 containing phosphorus element at a lower concentration than the source region and the drain region are formed. Under the gate electrode 11 is a channel formation region 19 to which intrinsic or substantially intrinsic or a trace amount of impurities are added for threshold control.
[0170]
10C is obtained, heat treatment is performed at 450 to 650 ° C. (typically 600 ° C.) for 8 to 24 hours (typically 12 hours).
[0171]
This heat treatment is a process aimed at gettering of the catalytic element (here, nickel) by the phosphorus element, but at the same time, activation of impurities and recovery of damage caused by ion implantation received by the active layer are performed.
[0172]
In this step, the nickel remaining in the channel formation region 19 is moved to the source / drain regions 16 and 17 by heat treatment, where it is gettered and inactivated. That is, it is possible to remove nickel remaining in the channel formation region 19.
[0173]
The source / drain regions 16 and 17 function as electrodes as long as they have conductivity, so that the presence or absence of nickel does not affect the electrical characteristics. Therefore, it can function as a gettering site.
[0174]
When the state of FIG. 10D is obtained as described above, the interlayer insulating film 20, the source electrode 21, and the drain electrode 22 are formed in the same manner as in Example 1 to complete the thin film transistor shown in FIG. .
[0175]
In this embodiment, tantalum is used as the gate electrode, but a conductive crystalline silicon film may be used. Further, the method for forming the low concentration impurity region is not limited to the means of this embodiment.
[0176]
The most important configuration in this embodiment is to getter the catalyst element remaining in the channel formation region by moving it to the source region and the drain region. This is an invention that focuses on the gettering effect of metal elements by phosphorus or arsenic.
[0177]
In this embodiment, an example of an N-type TFT is shown. However, in the case of a P-type TFT, since a gettering effect cannot be obtained only with a boron element, both a phosphorus element and a boron element are added to the source / drain regions. It is necessary.
[0178]
Example 5
In this embodiment, an example in which the present invention is applied to a thin film transistor having a structure different from that of Embodiment 1 will be described. FIG. 11 is used for the description.
[0179]
First, the gate electrode 32 is formed on the quartz substrate 31. The gate electrode 32 needs to use an electrode having high heat resistance such as tantalum or silicon so that it can withstand a subsequent thermal oxidation process.
[0180]
Next, a gate insulating film 33 is formed so as to cover the gate electrode 32. On top of that, an amorphous silicon film to be an active layer later is formed to a thickness of 50 nm. And after forming the mask insulating film 35 which has an opening part similarly to Example 1, the nickel containing layer 36 is formed. (Fig. 11 (A))
[0181]
When the state of FIG. 11A is obtained in this way, heat treatment for crystallization is performed to obtain a crystalline silicon film 37 that is a laterally grown region. (Fig. 11 (B))
[0182]
Next, the mask insulating film 35 is removed and heat treatment is performed in an atmosphere containing a halogen element. The conditions may be according to the first embodiment. Through this step, nickel is gettered from the crystalline silicon film 37 and removed into the gas phase. (Fig. 11 (C))
[0183]
When the gettering process is completed in this manner, an active layer 38 consisting only of a lateral growth region is formed by patterning, and a channel stopper 39 consisting of a silicon nitride film is formed thereon. (Fig. 11 (D))
[0184]
When the state of FIG. 11D is obtained, an N-type crystalline silicon film is formed and patterned to form a source region 40 and a drain region 41. Further, a source electrode 42 and a drain electrode 43 are formed.
[0185]
Finally, the entire device is subjected to a heat treatment in a hydrogen atmosphere to complete an inverted staggered TFT having a structure as shown in FIG. Note that the structure shown in this embodiment is an example of an inverted staggered TFT, and is not limited to the structure of this embodiment. It is also possible to apply to other bottom gate type TFTs.
[0186]
Example 6
In this embodiment, an example in which the TFT according to the present invention is formed on a substrate having an insulating surface and the pixel matrix circuit and the peripheral circuit are configured monolithically is shown in FIGS.
In this embodiment, a CMOS circuit as a basic circuit is shown as an example of a peripheral circuit such as a driver circuit or a logic circuit.
[0187]
First, an amorphous silicon film 52 and a mask insulating film 53 having a thickness of 75 nm are formed on a quartz substrate 51, and a nickel-containing layer 54 is formed by spin coating. These steps are as shown in Example 1. (Fig. 12 (A))
[0188]
Next, after dehydrogenating at 450 ° C. for about 1 hour, heat treatment is performed at 590 ° C. for 8 hours in a nitrogen atmosphere to obtain crystalline regions 55 to 58. 55 and 56 are nickel-added regions, and 57 and 58 are lateral growth regions. (Fig. 12 (B))
[0189]
When the heat treatment for crystallization is completed, the mask insulating film 53 is removed and patterning is performed to form island-like semiconductor layers (active layers) 59 to 61 including only the lateral growth regions 57 and 58. (Figure 12 (C))
[0190]
Here, 59 is an active layer of an N-type TFT constituting a CMOS circuit, 60 is an active layer of a P-type TFT constituting a CMOS circuit, and 61 is an active layer of an N-type TFT (pixel TFT) constituting a pixel matrix circuit. .
[0191]
After the active layers 59 to 61 are formed, a gate insulating film 62 made of an insulating film containing silicon is formed thereon. Then, a catalytic element gettering process is performed. The conditions for this step may be according to Example 1. (Fig. 12D)
[0192]
Next, a metal film mainly composed of aluminum (not shown) is formed, and later gate electrode prototypes 63 to 65 are formed by patterning. In this embodiment, an aluminum film containing 2 wt% scandium is used. (FIG. 13 (A))
[0193]
Next, as in Example 1, porous anodic oxide films 66 to 68, nonporous anodic oxide films 69 to 71, and gate electrodes 72 to 74 are formed by the technique described in Japanese Patent Laid-Open No. 7-13318. (Fig. 13B)
[0194]
13B is obtained, the gate insulating film 62 is then etched using the gate electrodes 72 to 74 and the porous anodic oxide films 66 to 68 as a mask.
Then, the porous anodic oxide films 66 to 68 are removed to obtain the state of FIG.
In FIG. 13C, reference numerals 75 to 77 denote processed gate insulating films.
[0195]
Next, impurity ions imparting N-type are added in two portions according to the same procedure as in Example 1. First, the first impurity addition is performed at a high acceleration voltage, and n ^- A region is formed, and then a second impurity addition is performed at a low acceleration voltage, and n ⁺ Form a region.
[0196]
Through the above steps, the source region 78, drain region 79, low-concentration impurity region 80, and channel formation region 81 of the N-type TFT constituting the CMOS circuit are formed.
In addition, a source region 82, a drain region 83, a low-concentration impurity region 84, and a channel formation region 85 of an N-type TFT constituting the pixel TFT are defined. (Fig. 13D)
[0197]
In the state shown in FIG. 13D, the active layer of the P-type TFT constituting the CMOS circuit has the same configuration as the active layer of the N-type TFT.
[0198]
Next, a resist mask 86 is provided so as to cover the N-type TFT, and impurity ions imparting P-type (boron is used in this embodiment) are added.
[0199]
This process is also performed in two steps, similar to the impurity addition process described above. However, since it is necessary to invert the N-type to the P-type, B (boron) having a concentration several times higher than the aforementioned P-ion addition concentration is required. Add ions.
[0200]
Thus, the source region 87, drain region 88, low-concentration impurity region 89, and channel formation region 90 of the P-type TFT constituting the CMOS circuit are formed. (Fig. 14 (A))
[0201]
When the active layer is completed as described above, impurity ions are activated by a combination of furnace annealing, laser annealing, lamp annealing and the like. At the same time, the damage of the active layer received in the addition process is also repaired.
[0202]
Next, after a stacked film of a silicon oxide film and a silicon nitride film is formed as the interlayer insulating film 91 and contact holes are formed, source electrodes 92 to 94 and drain electrodes 95 and 96 are formed, and FIG. The state shown in is obtained.
[0203]
In this embodiment, since the drain electrode 96 of the pixel TFT is used as the lower electrode of the auxiliary capacitor, it is processed into a shape corresponding to it.
[0204]
Next, a silicon nitride film 97 with a thickness of 10 to 50 nm is formed, and a capacitor electrode 98 for forming an auxiliary capacitor is formed thereon with a thickness of 100 nm. In this embodiment, a titanium film is used as the capacitor electrode 98, and an auxiliary capacitor is formed between the drain electrode 96.
[0205]
The silicon nitride film 97 described above is suitable as a dielectric because of its high relative dielectric constant. In addition to the titanium film, an aluminum film, a chromium film, or the like may be used as the capacitor electrode 98.
[0206]
Note that this embodiment is an example of manufacturing an active matrix substrate (TFT-side substrate) of a reflective liquid crystal display device, and therefore, unlike a transmissive type, a pixel electrode formed later can be freely used (aperture ratio is reduced). No need to worry). Therefore, the auxiliary capacitance as described above can be formed.
[0207]
Next, a second interlayer insulating film 99 made of an organic resin film is formed to a thickness of 0.5 to 3 μm. Then, a conductive film is formed on the interlayer insulating film 99, and the pixel electrode 100 is formed by patterning. Since this embodiment is a reflective example, a material mainly composed of aluminum is used as the conductive film constituting the pixel electrode 100, and the pixel electrode 100 has a function as a reflective film.
[0208]
Next, the entire substrate is heated in a hydrogen atmosphere at 350 ° C. for 1 to 2 hours, and the entire element is hydrogenated to compensate for dangling bonds (unpaired bonds) in the film (particularly in the active layer). Through the above steps, a CMOS circuit and a pixel matrix circuit can be manufactured on the same substrate.
[0209]
Example 7
In this embodiment, an example in which a TFT structure different from that in Embodiment 6 is employed will be described. First, FIG. 15A shows an example in which a sidewall is used to form a low concentration impurity region.
[0210]
In this case, a nonporous anodic oxide film is formed in the state shown in FIG. 13A, and the gate insulating film is etched using the gate electrode and the anodic oxide film as a mask. N in that state ^- Region and p ^- Impurity is added to form a region.
[0211]
Next, after forming the sidewalls 1001 to 1003 by an etch back method, n ⁺ Region and p ⁺ Impurity is added to form a region. In such a process, the low concentration impurity region (n ^- Region and p ^- Region) is formed.
[0212]
In FIG. 15A, metal silicides 1004 to 1006 are formed using a known salicide technique. As the metal for silicidation, titanium, tantalum, tungsten, molybdenum, or the like can be used.
[0213]
The structure shown in FIG. 15B is characterized in that the gate electrodes 1007 to 1009 are formed of a crystalline silicon film imparted with one conductivity. Normally, N-type conductivity is provided, but a dual-gate TFT in which conductivity is different between the N-type TFT and the P-type TFT can also be used.
[0214]
Further, the salicide structure is also applied to the structure shown in FIG. 15B. In this case, metal silicides 1010 to 1012 are also formed on the upper surfaces of the gate electrodes 1007 to 1009.
[0215]
The structure shown in this embodiment is designed to be a structure suitable for a TFT having a high operation speed. In particular, the salicide structure is a very effective technique for realizing an operating frequency of several GHz level.
[0216]
Example 8
In this embodiment, an example in which an auxiliary capacitor is formed with a configuration different from that of the sixth embodiment will be described.
[0217]
First, in FIG. 16A, the drain region 1020 of the active layer is formed larger, and a part thereof is used as the lower electrode of the auxiliary capacitor. In this case, the gate insulating film 1021 is provided on the drain region 1020, and the capacitor electrode 1022 is formed thereon. The capacitor electrode 1022 is made of the same material as the gate electrode.
[0218]
At this time, the portion of the drain region 1020 where the auxiliary capacitance is formed may be made conductive by adding impurities in advance, or an inversion layer formed by applying a constant voltage to the capacitor electrode 1022 is used. You may do it.
[0219]
Since FIG. 16A shows an example of a reflective liquid crystal display device, an auxiliary capacitor can be formed by making maximum use of the back side of the pixel electrode. Therefore, a very large capacity can be secured. Of course, it can also be applied to a transmissive liquid crystal display device. However, in this case, if the area occupied by the auxiliary capacitor is increased, the aperture ratio is lowered.
[0220]
Next, FIG. 17B illustrates an example of a transmissive liquid crystal display device. In the structure of FIG. 17B, the drain electrode 1023 is used as a lower electrode of an auxiliary capacitor, a silicon nitride film 1024 and a black mask 1025 are formed thereon, and an auxiliary capacitor is formed between the drain electrode 1023 and the black mask 1025. .
[0221]
As described above, the structure of FIG. 16B is characterized in that the black mask 1025 also serves as the upper electrode of the auxiliary capacitor.
[0222]
Reference numeral 1026 denotes a pixel electrode, which is a transmission type and uses a transparent conductive film (for example, an ITO film).
[0223]
In the structure as shown in FIG. 16B, it is possible to increase the aperture ratio by forming an auxiliary capacitor on the TFT which easily occupies a large area. In addition, since a silicon nitride film having a high dielectric constant can be used with a thickness of about 25 nm, a very large capacity can be secured with a small area.
[0224]
Example 9
In this embodiment, a structure of a pixel TFT constituting a pixel matrix circuit will be described. A cross-sectional structure of the pixel TFT of this embodiment is shown in FIG. In FIG. 26A, 3001 is an active layer, 3002 is a source line, 3003 is a gate line, 3004 is a drain electrode, 3005 is a black mask, and 3006 is a contact hole for connecting the drain electrode 3004 and the pixel electrode 3007. is there.
[0225]
The feature of this embodiment is that an auxiliary capacitance is formed between the drain electrode 3004 and the black mask 3005 above the pixel TFT.
[0226]
FIG. 26B shows a cross-sectional view when FIG. 26A is cut along the broken line indicated by AA ′. Note that common reference numerals are used in FIGS. 26A and 26B.
[0227]
In this manner, the drain electrode 3005 is formed so as to overlap with the gate line 3003, and an auxiliary capacitance is formed between the black mask 3005 opposed to the dielectric 3008. In this embodiment, the drain electrode 3005 has a three-layer structure in which a titanium film is sandwiched between aluminum films.
[0228]
In this embodiment, after forming the drain electrode 3005, an interlayer insulating film having a three-layer structure of silicon nitride film / silicon oxide film / acrylic film is formed, and a black mask 3005 is formed thereon.
[0229]
At this time, before the black mask 3005 is formed, only an acrylic film in a region that later becomes an auxiliary capacitance is removed to form an opening. As a result, only the silicon oxide film and the silicon nitride film remain at the bottom of the opening, and the insulating layer having this two-layer structure functions as the dielectric 3008 of the auxiliary capacitor.
[0230]
Example 10
In this embodiment, an example in which a liquid crystal panel is configured using the present invention will be described. FIG. 17 shows a simplified cross section of an active matrix type liquid crystal panel. A CMOS circuit is shown in a region constituting a driver circuit and a logic circuit, and a pixel TFT is shown in a region constituting a pixel matrix circuit. Yes.
[0231]
In addition, since the description regarding the structures of the CMOS circuit and the pixel matrix circuit (TFT structure) has already been given in Examples 6 to 9, only necessary portions will be described in this example.
[0232]
First, the state shown in FIG. 14C is obtained in accordance with the manufacturing process shown in Example 6. It should be noted that changes such as the pixel TFT having a multi-gate structure can be freely performed by the practitioner.
[0233]
Then, an alignment film 1030 is formed as a preparation for the active matrix substrate.
Next, a counter substrate is prepared. The counter substrate includes a glass substrate 1031, a transparent conductive film 1032, and an alignment film 1033. A black mask and a color filter are formed on the counter substrate side as needed, but are omitted here.
[0234]
The active matrix substrate thus prepared and the counter substrate are bonded together by a known cell assembling process. Then, a liquid crystal material 1034 is sealed between both substrates to complete a liquid crystal panel as shown in FIG.
[0235]
The liquid crystal material 1034 can be freely selected according to the operation mode (ECB mode, guest host mode, etc.) of the liquid crystal.
[0236]
Further, the appearance of the active matrix substrate as shown in FIG. 14C is simplified and shown in FIG. In FIG. 18, 1040 is a quartz substrate, 1041 is a pixel matrix circuit, 1042 is a source driver circuit, 1043 is a gate driver circuit, and 1044 is a logic circuit.
[0237]
The logic circuit 1044 broadly includes all logic circuits composed of TFTs, but here, in order to distinguish them from circuits conventionally called pixel matrix circuits and driver circuits, other signal processing circuits (memory, D / A converter, pulse generator, etc.).
[0238]
Further, an FPC (Flexible Print Circuit) terminal is attached as an external terminal to the liquid crystal panel thus formed. In general, a liquid crystal module is called a liquid crystal panel with an FPC attached.
[0239]
The present applicant has actually produced a liquid crystal module having a diagonal size of 2.6 inches, 1280 × 1024 pixels, and a pixel size of 45 μm × 32 μm. The aperture ratio is 63% and the contrast ratio is 300: 1.
[0240]
Example 11
In the present invention, in addition to the liquid crystal display device shown in the tenth embodiment, other electro-optical devices such as an active matrix EL (electroluminescence) display device and an EC (electrochromic) display device can be manufactured. is there.
[0241]
Example 12
In this embodiment, an example of an electronic device (applied product) using the electro-optical device using the present invention is shown in FIG. Application products using the present invention include video cameras, still cameras, projectors, head mounted displays, car navigation systems, personal computers, personal digital assistants (mobile computers, mobile phones, etc.), and the like.
[0242]
FIG. 19A illustrates a mobile phone, which includes a main body 2001, an audio output unit 2002, an audio input unit 2003, a display device 2004, operation switches 2005, and an antenna 2006. The present invention can be applied to the display device 2004.
[0243]
FIG. 19B shows a video camera, which includes a main body 2101, a display device 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 2106. The present invention can be applied to the display device 2102.
[0244]
FIG. 19C illustrates a mobile computer, which includes a main body 2201, a camera unit 2202, an image receiving unit 2203, operation switches 2204, and a display device 2205. The present invention can be applied to the display device 2205.
[0245]
FIG. 19D illustrates a head mounted display which includes a main body 2301, a display device 2302, and a band portion 2303. The present invention can be applied to the display device 2302.
[0246]
FIG. 19E shows a rear projector, which includes a main body 2401, a light source 2402, a display device 2403, a polarizing beam splitter 2404, reflectors 2405 and 2406, and a screen 2407. The present invention can be applied to the display device 2403.
[0247]
FIG. 19F illustrates a front projector, which includes a main body 2501, a light source 2502, a display device 2503, an optical system 2504, and a screen 2505. The present invention can be applied to the display device 2503.
[0248]
As described above, the application range of the present invention is extremely wide and can be applied to display media in various fields. In addition, since the TFT of the present invention can constitute a semiconductor circuit such as an IC or an LSI, any application is possible as long as it is a product that requires such a semiconductor circuit.
[0249]
【The invention's effect】
According to the invention disclosed in this specification, a semiconductor thin film having crystallinity substantially comparable to a single crystal semiconductor can be realized. By using such a semiconductor thin film, a TFT having high performance comparable to or surpassing that of an IGFET (MOSFET) fabricated on a single crystal can be realized.
[0250]
Semiconductor circuits and electro-optical devices configured using TFTs as described above and electronic devices equipped with them have extremely high performance and are extremely excellent in terms of functionality, portability, and reliability. Become.
[Brief description of the drawings]
FIG. 1 is an HR-TEM photograph showing an enlarged crystal grain boundary of a semiconductor thin film.
FIG. 2 is a diagram schematically showing a crystal orientation relationship.
FIG. 3 is a photograph and a schematic view showing an electron beam diffraction pattern.
FIG. 4 is a graph showing electrical characteristics of a thin film transistor.
FIG. 5 is a diagram showing frequency characteristics of a ring oscillator.
FIG. 6 is a photograph showing an output spectrum of a ring oscillator.
FIG. 7 is a diagram illustrating a scaling law.
FIG. 8 illustrates a manufacturing process of a thin film transistor.
FIG. 9 illustrates a manufacturing process of a thin film transistor.
10A and 10B illustrate a manufacturing process of a thin film transistor.
FIG. 11 illustrates a manufacturing process of a thin film transistor.
FIGS. 12A and 12B are diagrams illustrating a manufacturing process of an active matrix substrate. FIGS.
FIGS. 13A and 13B are diagrams illustrating a manufacturing process of an active matrix substrate. FIGS.
FIGS. 14A to 14C are diagrams illustrating a manufacturing process of an active matrix substrate. FIGS.
FIG. 15 shows a structure of an active matrix substrate.
FIG. 16 shows a structure of an active matrix substrate.
FIG 17 is a cross-sectional view of a liquid crystal display device.
FIG. 18 is a top view of an active matrix substrate.
FIG. 19 is a diagram showing an example of an electronic device (application product).
FIG. 20 is a diagram schematically showing the state of crystal growth.
FIG. 21 is a TEM photograph showing crystal grains of a crystalline silicon film.
FIG. 22 is a diagram for explaining a model relating to generation and disappearance of defects.
FIG. 23 is a diagram showing a concentration distribution of C, N, and O.
FIG. 24 shows the results of X-ray diffraction.
FIG. 25 is a TEM photograph showing a dark field image of a semiconductor thin film.
FIG. 26 is a diagram showing a top surface and a cross-sectional structure of a pixel TFT.

Claims (4)

It is fixed on a quartz substrate and consists of an aggregate of a plurality of rod-like or flat rod-like crystals, the plane orientation is {110} orientation, the crystal lattice is continuous at the grain boundary, and measured by electron spin resonance analysis A continuous grain boundary crystalline silicon film having a spin density of 5 × 10 ¹⁷ spins / cm ³ or less. It is fixed on a quartz substrate and consists of an aggregate of a plurality of rod-like or flat rod-like crystals, the plane orientation is {110} orientation, the crystal lattice is continuous at the grain boundary, and measured by electron spin resonance analysis A continuous grain boundary crystalline silicon film having a spin density of 5 × 10 ¹⁷ spins / cm ³ or less and containing 1 to 10% germanium. It is fixed on a quartz substrate and consists of an aggregate of a plurality of rod-like or flat rod-like crystals. The plane orientation is {110} orientation. The crystal lattice has continuity at the crystal grain boundary. Measured by electron spin resonance analysis. A semiconductor device formed using a continuous grain boundary crystalline silicon film having a spin density of 5 × 10 ¹⁷ spins / cm ³ or less. It is fixed on a quartz substrate and consists of an aggregate of a plurality of rod-like or flat rod-like crystals, the plane orientation is {110} orientation, the crystal lattice is continuous at the grain boundary, and measured by electron spin resonance analysis The semiconductor device is formed using a continuous grain boundary crystalline silicon film having a spin density of 5 × 10 ¹⁷ spins / cm ³ or less and containing 1 to 10% germanium.

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