JPH118196A - Semiconductor thin film and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a highly efficiently semiconductor device which constitutes a high speed logic circuit, by a method wherein the plane orientation of a semiconductor thin film is formed into about 111} orientation, and the element other than silicon present in the film is selected from one or plurality of kinds selected from the elements other than carbon, nitride, oxygen and sulfur. SOLUTION: A base film is provided on a quartz substrate, an amorphous silicon film is formed, and the amorphous silicon film is heat treated using a catalytic element. After crystallization, the catalytic element is removed, and a crystalline semiconductor thin film is obtained. The crystalline semiconductor thin film is formed into crystal grains having the crystal face of orientation 111}, and the elements other than silicon contained in the film are formed by one or a plurality of kinds of elements selected from the elements other than carbon, nitride, oxygen and sulfur. As a result, a semiconductor thin film having the crystallinity equal to a single crystal semiconductor is manufactured and a highly performance semiconductor device which constitutes a high speed logic circuit can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD [0001] The invention disclosed in the present specification is:
The present invention relates to a semiconductor thin film formed on a substrate having an insulating surface and a semiconductor device using the same as an active layer. In particular, the present invention relates to a configuration in which a material containing silicon as a main component is used as a semiconductor thin film.

[0002]

2. Description of the Related Art In recent years, a technique of forming a thin film transistor (TFT) by using a semiconductor thin film (having a thickness of several hundred to several thousand degrees) formed on a substrate having an insulating surface has attracted attention. Thin film transistors are widely applied to electronic devices such as ICs and electro-optical devices, and are particularly rapidly developed as switching elements for image display devices.

For example, in a liquid crystal display device, a pixel matrix circuit for individually controlling pixel areas arranged in a matrix, a driving circuit for controlling the pixel matrix circuit, and a logic circuit (processor circuit) for processing an external data signal Attempts have been made to apply TFTs to any electric circuit such as a semiconductor device and a memory circuit.

At present, TFTs using an amorphous silicon film (amorphous silicon film) as an active layer have been put into practical use. In the circuit,
A TFT using a crystalline silicon film (polysilicon film, polycrystalline silicon film, etc.) is required.

For example, as a method for forming a crystalline silicon film on a glass substrate, the techniques described in Japanese Patent Application Laid-Open Nos. Hei 7-130652 and Hei 8-78329 by the present applicant are known. The techniques described in these publications use a catalyst element that promotes crystallization of an amorphous silicon film, thereby providing 500
It is possible to form a crystalline silicon film having excellent crystallinity by heat treatment at about 600 ° C. for about 4 hours.

In particular, the technique described in Japanese Patent Application Laid-Open No. 8-78329 is to grow the crystal substantially parallel to the substrate surface by applying the above-mentioned technique. It is called the growth area (or lateral growth area).

However, even if a driving circuit is formed using such TFTs, the required performance is still not completely satisfied. In particular, it is impossible at present to configure a high-speed logic circuit that requires an extremely high-speed operation from megahertz to gigahertz with a conventional TFT.

[0008]

The present inventors have repeated various thoughts and errors in order to improve the crystallinity of a crystalline silicon film having a crystal grain boundary (called a polycrystalline silicon film). . Semi-amorphous semiconductor (JP-A-57-160
No. 121, etc.) and mono-domain semiconductors (JP-A-8-139019)
Publication).

The concept common to the semiconductor films described in the above publication is that the grain boundaries are substantially rendered harmless. That is, the biggest problem was to substantially eliminate crystal grain boundaries and to smoothly move carriers (electrons or holes).

[0010] However, it can be said that the semiconductor film described in the above publication is insufficient for performing the high-speed operation required by the logic circuit. That is, in order to realize a system-on-panel with a built-in logic circuit, it is required to develop a completely new material that has never existed before.

The present invention meets such a demand, and a semiconductor thin film for realizing an extremely high-performance semiconductor device capable of forming a high-speed logic circuit, which cannot be manufactured by a conventional TFT, is provided. The task is to provide.
Another object is to provide a semiconductor device using such a semiconductor thin film.

[0012]

The structure of the invention disclosed in this specification is a semiconductor thin film composed of an aggregate of a plurality of rod-shaped or flat rod-shaped crystals containing silicon as a main component, and has a plane orientation of approximately {111}.元素 Elements that are oriented and present in the film other than silicon are at least C (carbon), N (nitrogen), O
It is one or more elements selected from elements other than (oxygen) and S (sulfur).

In another aspect of the invention, the elements present in the film other than silicon include Ni (nickel), Co (cobalt), Fe (iron), Pd (palladium), and Pt (platinum). ), Cu (copper) or Au (gold), and the concentration of the element is 5 × 10 ¹⁷ atoms / cm ³ or less (or 0.001 atomic% or less). It is characterized by.

According to another aspect of the present invention, there is provided a semiconductor thin film comprising an aggregate of a plurality of rod-shaped or flat rod-shaped crystals containing silicon as a main component, wherein the plane orientation is substantially {111} orientation, and C (carbon), N (nitrogen), O
It is characterized in that the concentrations of (oxygen) and S (sulfur) are below the lower limit of detection by SIMS.

According to another aspect of the invention, there is provided a semiconductor thin film comprising an aggregate of a plurality of rod-shaped or flat rod-shaped crystals containing silicon as a main component, wherein the plane orientation is substantially {111} orientation, and The concentration of C (carbon), N (nitrogen) and S (sulfur) present therein is less than 5 × 10 ¹⁸ atoms / cm ³ (or
01 atomic%) and the concentration of O (oxygen) present in the film is less than 1.5 × 10 ¹⁹ atoms / cm ³ (or 0.03 atomic%).
omic%).

According to another aspect of the present invention, there is provided a semiconductor thin film comprising an aggregate of a plurality of rod-shaped or flat rod-shaped crystals containing silicon as a main component, wherein the plane orientation is substantially {111} orientation, and Most of the crystal lattices are characterized by having continuity at the crystal grain boundaries.

A semiconductor thin film comprising an aggregate of a plurality of rod-shaped or flat rod-shaped crystals containing silicon as a main component, having a plane orientation of substantially {111} orientation and crossing an arbitrary crystal grain boundary. Most of the observed lattice fringes are characterized by being linearly continuous between different crystal grains forming the crystal grain boundary.

Incidentally, in all of the above-mentioned configurations, the approximate $ 1
The 11｝ orientation is defined by the present inventors as {11}.
It means that the 1｝ orientation ratio is 0.9 or more.

A semiconductor device manufactured by using the semiconductor thin film having the above-described structure is a conventional IGFET that constitutes an IC.
It has extremely high performance comparable to or surpasses and has high reliability.

The configuration of the present invention as described above will be described in detail with reference to embodiments described below.

[0021]

[Embodiment 1] In this embodiment, a semiconductor thin film according to the present invention and a semiconductor device using the same as an active layer (specifically, TF
The manufacturing process T) will be described. After the description of the manufacturing process, knowledge obtained from the viewpoint of the crystal structure and the electrical characteristics of the TFT of the present invention will be described.

First, as a substrate having an insulating surface, a substrate having a base film 101 provided on a quartz substrate 100 is prepared. The base film 101 may be formed by a plasma CVD method or a sputtering CVD method. As will be described later, the base film used in this embodiment has an etching rate of 50 nm / min or more for an etchant called LAL500.

In addition, a ceramic substrate, a silicon substrate, a sapphire substrate, or the like can be used instead of the quartz substrate.

Numeral 102 denotes an amorphous silicon film, which is adjusted so that the final film thickness (thickness in consideration of film reduction after thermal oxidation) is 10 to 75 nm (preferably 15 to 45 nm). The film is formed by the reduced pressure thermal CV method under the following conditions. Film forming temperature: 465 ° C. Film forming pressure: 0.5 torr Film forming gas: He (helium) 300 sccm Si ₂ H ₆ (disilane) 250 sccm

It is important to thoroughly control the impurity concentration in the film when forming the film. In the case of this embodiment,
In the amorphous silicon film 102, the concentrations of C (carbon), N (nitrogen), and S (sulfur), which are impurities that inhibit crystallization, are all less than 5 × 10 ¹⁸ atoms / cm ³ , and O (oxygen) is 1.5 × 10 ¹⁹ at
It is managed to be less than oms / cm ³ .

This is because, if each impurity is present at a concentration higher than this, it will have an adverse effect on crystallization and cause deterioration of the film quality after crystallization.

In the low pressure thermal CVD furnace used in this embodiment, dry cleaning is periodically performed to purify the film forming chamber. Dry cleaning is 100-300 sccm ClF ₃ (chlorine fluoride) in a furnace heated to about 200-400 ° C.
A gas is flowed, and the film formation chamber is cleaned with fluorine generated by thermal decomposition.

When the furnace temperature is 300 ° C. and the flow rate of ClF ₃ (chlorine fluoride) gas is 300 sccm, about 2 μm
Thick deposits (mainly composed mainly of silicon) could be completely removed in 4 hours.

Further, the hydrogen concentration in the amorphous silicon film 102 is also a very important parameter, and it seems that a film having good crystallinity can be obtained by keeping the hydrogen content low. for that reason,
The formation of the amorphous silicon film 102 is preferably performed by a low pressure thermal CVD method. Note that the plasma CVD method can be used by optimizing the film formation conditions.

Next, a crystallization step of the amorphous silicon film 102 is performed. As a means of crystallization, JP-A-7-13 by the present inventor
The technique described in Japanese Patent Publication No. 0652 is used. Either of the means of Embodiment 1 and Embodiment 2 of the publication may be used, but in the present invention, it is preferable to use the technical contents described in Embodiment 2 (detailed in JP-A-8-78329).

In the technique described in Japanese Patent Application Laid-Open No. 8-78329, first, a mask insulating film 103 for selecting a region to which a catalytic element is added is formed. The mask insulating film 103 has a plurality of openings for adding a catalytic element. The position of the crystal region can be determined by the position of the opening.

Then, a solution containing nickel (Ni) as a catalyst element for promoting crystallization of the amorphous silicon film is applied by a spin coating method to form a Ni-containing layer 104. In addition, besides nickel, cobalt (Co), iron (Fe), palladium (Pd), platinum (Pt), copper (Cu), gold (Au) and the like can be used in addition to nickel. (Fig. 1 (A))

In the step of adding the catalyst element, an ion implantation method using a resist mask or a plasma doping method can be used. In this case, the reduction of the occupied area of the addition region and the control of the growth distance of the lateral growth region are facilitated, so that this is an effective technique when configuring a miniaturized circuit.

Next, when the step of adding the catalyst element is completed,
After releasing hydrogen at 450 ° C for about 1 hour, heat treatment is performed in an inert atmosphere, a hydrogen atmosphere, or an oxygen atmosphere at a temperature of 500 to 700 ° C (typically 550 to 650 ° C) for 4 to 24 hours. The crystalline silicon film 102 is crystallized. In this embodiment, heat treatment is performed at 570 ° C. for 14 hours in a nitrogen atmosphere.

At this time, the crystallization of the amorphous silicon film 102 proceeds preferentially from the nucleus generated in the nickel-added region 105, and the crystal region 106 grown almost parallel to the substrate surface of the substrate 101 is formed. It is formed. The present inventors call this crystal region 106 a lateral growth region. Since the individual crystals are aggregated in a relatively uniform state in the lateral growth region, there is an advantage that the overall crystallinity is excellent. (FIG. 1 (B))

When the technique described in the first embodiment of Japanese Patent Application Laid-Open No. 7-130652 is used, a region which can be microscopically called a lateral growth region is formed. However,
Since nucleation occurs unevenly in the plane, there is a difficulty in controllability of crystal grain boundaries.

The above-described crystallization temperature and crystallization time are determined in consideration of the film quality of the amorphous silicon film 102. An amorphous silicon film produced by a low pressure thermal CVD method is disclosed in
In the case of crystallization by the technique described in Patent Publication No. 78329, at a temperature of 570 ° C. or higher, natural nuclei are generated, which may hinder the growth of the lateral growth region. At this temperature, a crystallization time of at least 12 hours (preferably 14 hours) is required.

Furthermore, since the amorphous silicon film formed by the plasma CVD method under a condition having a large hydrogen content has a spontaneous nucleation temperature as low as about 20 ° C., the crystallization temperature must be determined accordingly. .

A report on these findings is described in the specification of Japanese Patent Application No. 9-78979 by the present inventors.

As described above, in the present invention, the hydrogen content, C,
Another feature is that an amorphous silicon film in which the contents of impurity elements such as N, O, and S are strictly controlled is used as a starting film, and crystallization conditions are determined in consideration of the film quality.

After the heat treatment for crystallization is completed, the mask insulating film 103 is removed and patterning is performed, and an island-like semiconductor layer (active layer) 107 including only the lateral growth region 106 is formed.
To form

Next, a gate insulating film 108 made of an insulating film containing silicon is formed. The thickness of the gate insulating film 108 may be adjusted in the range of 20 to 250 nm in consideration of the increase due to the subsequent thermal oxidation step. As a film formation method, a known gas phase method (a plasma CVD method, a sputtering method, or the like) may be used.

Next, as shown in FIG. 1C, a heat treatment (a catalytic element gettering process) for removing or reducing the catalytic element (nickel) is performed. In this heat treatment, a halogen element is contained in the treatment atmosphere, and the gettering effect of the metal element by the halogen element is used.

In order to sufficiently obtain the gettering effect by the halogen element, it is preferable to perform the above heat treatment at a temperature exceeding 700 ° C. Below this temperature, the decomposition of the halogen compound in the processing atmosphere becomes difficult, and the gettering effect may not be obtained.

Therefore, in this embodiment, this heat treatment is performed
The reaction is carried out at a temperature higher than 800C, preferably 800 to 1000C (typically 950C), and the treatment time is 0.1 to 6 hours, typically 0.5 to 1 hour.

In this embodiment, hydrogen chloride (HCl) is 0.5 to 10% by volume with respect to the oxygen atmosphere (3% in this embodiment).
Volume%) in an atmosphere containing
An example in which heat treatment is performed at 30 ° C. for 30 minutes will be described. If the HCl concentration is higher than the above-mentioned concentration, the surface of the active layer 107 will be uneven because of the thickness of the film, which is not preferable.

The compound containing a halogen element is HC
Although the example using 1 gas was shown, as other gas,
Typically, HF, NF ₃ , HBr, Cl ₂ , ClF ₃ ,
One or more compounds selected from compounds containing halogen such as BCl ₃ , F ₂ and Br ₂ can be used.

In this step, it is considered that nickel in the active layer 107 is gettered by the action of chlorine, becomes volatile nickel chloride, escapes to the atmosphere and is removed. By this step, the concentration of nickel in the active layer 107 is reduced to 5 × 10 ¹⁷ atoms / cm ³ or less.

The concentration of each element in this specification is defined by the minimum value obtained from the SIMS measurement result. However, the concentration in a region having a large measurement error such as a film interface is not considered as a measurement result.

However, the value of 5 × 10 ¹⁷ atoms / cm ³ is the lower limit of nickel detection in SIMS (Mass Secondary Ion Analysis). As a result of analyzing a TFT prototyped by the present inventors, 1 × 10 ¹⁸ atoms / cm ³ or less (preferably 5 × 10 ¹⁸ atoms / cm ³ or less)
× 10 ¹⁷ atoms / cm ³ or less), the effect of nickel on the TFT characteristics was not confirmed.

The heat treatment causes a thermal oxidation reaction to proceed at the interface between the active layer 107 and the gate insulating film 108, and the thickness of the gate insulating film 108 increases by the amount of the thermal oxide film.
When the thermal oxide film is formed in this manner, a semiconductor / insulating film interface having very few interface states can be obtained. Also,
There is also an effect of preventing poor formation (edge thinning) of a thermal oxide film at the end of the active layer.

Further, it is also effective to improve the film quality of the gate insulating film 108 by performing a heat treatment at 950 ° C. for about 1 hour in a nitrogen atmosphere after the heat treatment in the halogen atmosphere.

According to the SIMS analysis, the active layer 107 contains 1 × 10 halogen elements used for the gettering process.
It has been confirmed that it remains at a concentration of ¹⁵ to 1 × 10 ²⁰ atoms / cm ³ . At this time, it has been confirmed by SIMS analysis that the above-mentioned halogen element is distributed at a high concentration between the active layer 107 and the thermal oxide film formed by the heat treatment.

As a result of SIMS analysis of other elements, C (carbon), N (nitrogen) and S (sulfur) were all less than 5 × 10 ¹⁸ atoms / cm ³ , and O (oxygen) was 1.5 × 10
It was confirmed that it was less than ¹⁹ atoms / cm ³ .

Next, a metal film mainly composed of aluminum (not shown) is formed, and a gate electrode prototype 109 is formed by patterning. In this embodiment, an aluminum film containing 2 wt% of scandium is used. In addition,
Alternatively, a tantalum film, a conductive silicon film, or the like can be used. (Fig. 1 (D))

Here, the technique described in JP-A-7-135318 by the present inventors is used. This publication discloses a technique for forming a source / drain region and a low-concentration impurity region in a self-aligned manner by using an oxide film formed by anodic oxidation.

First, anodization is performed in a 3% oxalic acid aqueous solution while leaving a resist mask (not shown) used for patterning the aluminum film, to form a porous anodic oxide film 110.

The thickness of the porous anodic oxide film 110 increases in proportion to time. Also, since the resist mask remains on the upper surface, it is formed only on the side surface of the prototype 109 of the gate electrode. In the technique described in Japanese Patent Application Laid-Open No. Hei 7-135318, this film thickness later becomes the length of the low-concentration impurity region (also called the LDD region). In this embodiment, the anodic oxidation treatment is performed under the condition that the film thickness becomes 700 nm.

Next, after removing a resist mask (not shown), anodizing is performed in an electrolytic solution obtained by mixing 3% tartaric acid with an ethylene glycol solution. In this process, a dense nonporous anodic oxide film 111 is formed. Since the electrolytic solution also penetrates inside the porous anodic oxide film, it is also formed inside the porous anodic oxide film.

The thickness of the nonporous anodic oxide film 111 is determined according to the applied voltage. In this embodiment, the anodic oxidation treatment is performed at an applied voltage of 80 V so as to form a film having a thickness of about 100 nm.

The aluminum film 112 remaining after the above-described two anodic oxidation processes substantially functions as a gate electrode.

When the state shown in FIG. 1E is obtained,
Next, the gate insulating film 108 is etched by a dry etching method using the gate electrode 112 and the porous anodic oxide film 110 as a mask. Then, the porous anodic oxide film 11
Remove 0. Gate insulating film 113 thus formed
Are exposed by the thickness of the porous anodic oxide film 110. (Fig. 2 (A))

Next, a step of adding an impurity element imparting one conductivity is performed. As an impurity element, P (phosphorus) or As (arsenic) may be used for N type, and B (boron) may be used for P type.

In the present embodiment, first, the first impurity addition is performed at a high accelerating voltage to form n ⁻ regions 114 and 115. At this time, since the accelerating voltage is as high as about 80 keV, the impurity element is added not only on the surface of the active layer but also below the end of the exposed gate insulating film. The n ⁻ regions 114 and 115 are adjusted so that the impurity concentration becomes 1 × 10 ¹⁸ to 1 × 10 ¹⁹ atoms / cm ³ . (FIG. 2 (B))

Further, the second impurity addition is performed at a low acceleration voltage to form n ⁺ regions 116 and 117. At this time, since the acceleration voltage is as low as about 10 keV, the gate insulating film functions as a mask. Also, the n ⁺ regions 116 and 117 are adjusted so that the sheet resistance becomes 500Ω or less (preferably 300Ω or less). (Fig. 2 (C))

The impurity region formed in the above steps has n
^{The +} region becomes the source region 116 and the drain region 117, and the n ⁻ region becomes the low concentration impurity region 118. Also,
The region immediately below the gate electrode is substantially free from the impurity element and becomes a substantially intrinsic channel forming region 119.

The low-concentration impurity region 118 has an effect of relaxing a high electric field applied between the channel formation region 119 and the drain region 117, and is also called an LDD (lightly doped drain) region.

When the active layer is completed as described above, the impurity element is activated by a combination of furnace annealing, laser annealing, lamp annealing and the like. At the same time, the damage of the active layer in the addition step is also repaired.

Next, an interlayer insulating film 120 is formed to a thickness of 500 nm. As the interlayer insulating film 120, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an organic resin film, or a stacked film thereof can be used.

The organic resin film is made of polyimide,
Acrylic, polyamide, polyimide amide and the like are used. The advantages of the organic resin film are that the film formation method is simple, the film thickness can be easily increased, the parasitic capacitance can be reduced because the relative dielectric constant is low, and the flatness is excellent. .

Next, after forming a contact hole, a source electrode 121 and a drain electrode 122 are formed. Finally, the entire substrate is heated in a hydrogen atmosphere at 350 ° C. for 1 to 2 hours to hydrogenate the entire device, thereby terminating dangling bonds (unpaired bonds) in the film (especially in the active layer).

Through the above steps, a TFT having a structure as shown in FIG. 2D can be manufactured. The features of the TFT thus obtained will be described below.

(Knowledge Regarding Impurities Contained in Active Layer) In the active layer (semiconductor thin film) of this embodiment, C (carbon), N (nitrogen), O (oxygen) and S It is characterized in that (sulfur) does not exist or substantially does not exist. This is a configuration that can be achieved by thorough impurity (contaminant) management.

As described above, at least C (carbon), N
If any one element of (nitrogen), O (oxygen) and S (sulfur) is present in the film at the time of crystallization, it adversely affects the crystallization mechanism utilizing the catalytic element.

Since a typical mixing path of these impurity elements is considered when forming an amorphous silicon film on a substrate, the concentration of these impurity elements is minimized (preferably completely eliminated) during initial film formation. This is important to ensure good crystallinity. Of course, it goes without saying that attention should be paid not only during film formation.

In the case of this embodiment, C (carbon), N (nitrogen), O (oxygen), and S (sulfur) are thoroughly avoided in forming the amorphous silicon film. The concentration of C (carbon), N (nitrogen) and S (sulfur) present in a typical semiconductor film is at least less than 5 × 10 ¹⁸ atoms / cm ³ (0.01
atomic%), the concentration of O (oxygen) is at least 1.5 ×
It is less than 10 ¹⁹ atoms / cm ³ (less than 0.03 atomic%).

In a semiconductor film made of pure silicon only, since the concentration of silicon is about 5 × 10 ²² atoms / cm ³ , for example, an impurity element of 5 × 10 ¹⁸ atoms / cm ³ has a concentration of about 0.01 atomic%. It is equivalent to existing in. Therefore, for example, in the case of a semiconductor thin film containing several% of germanium in silicon, the display of "atomic%" is slightly changed.
The absolute concentration of ¹⁸ atoms / cm ³ does not change.

Preferably, the concentrations of C (carbon), N (nitrogen), O (oxygen) and S (sulfur) present in the final semiconductor film are lower than the lower limit of detection in SIMS analysis, more preferably completely. It is considered that it is necessary to make it absent in order to obtain excellent crystallinity.

(Knowledge on Crystal Structure of Active Layer) The active layer formed according to the above-described manufacturing process is a crystal in which a plurality of rod-shaped or flat rod-shaped crystals are microscopically arranged substantially parallel to each other with regularity in a specific direction. Having a structure. This can be easily confirmed by observation with a TEM (transmission electron microscope).

The present inventors have developed an HR-type crystal having a grain boundary formed by contacting rod-shaped or flat rod-shaped crystals with each other by 8 million times.
It was confirmed by a TEM photograph. In this specification, a crystal grain boundary is defined as a grain boundary formed at a boundary where rod-shaped or flat rod-shaped crystals are in contact. Therefore, for example, it is considered separately from a grain boundary in a macro meaning such that the lateral growth region is formed by collision.

The above-mentioned HR-TEM (high-resolution transmission electron microscopy) means that a sample is irradiated with an electron beam perpendicularly, and the atomic / molecular arrangement is made utilizing interference of transmitted electrons and elastic scattered electrons. It is a technique to evaluate.

In the HR-TEM, the arrangement state of the crystal lattice can be observed as lattice fringes. Therefore, by observing the crystal grain boundaries, it is possible to estimate the bonding state between atoms at the crystal grain boundaries.

According to the TEM photograph obtained by the present inventors, a state where two different crystal grains were in contact at the crystal grain boundary was clearly observed. At this time, the two crystal grains had a roughly {111} orientation although some deviation was included in the crystal axes.
This was confirmed by examining a plurality of crystal grains by electron beam diffraction.

In many observations, the (1-11) plane or the (-11-1) plane (for the sake of format, it is described as (1-11), but the (-) symbol of -1 is inverted. Are used as a substitute for the logical symbol representing), but those equivalent planes are collectively represented as {111} planes. This will be described with reference to FIG.

FIG. 17A is an example schematically showing a crystal grain whose crystal plane is a {111} plane (the crystal axis is <111>). <110> in the crystal plane of {111}
The axis is included in multiple directions.

The notation as shown in FIG. 17A is an example of collective exponential notation. When this is expressed in strict exponential notation, it becomes as shown in FIGS. 17 (B) and 17 (C). For example, FIG.
Both the crystal axis [111] shown in FIG. 17B and the crystal axis [−111] shown in FIG.
11>.

As described above, if the discussion is made with strict crystal orientations (crystal axes), various ways can be considered. For the sake of simplification, the following descriptions are all expressed by collective exponential notation. Of course,
Similar physical properties are obtained on all equivalent crystal planes.

By the way, in the lattice fringe observation by the TEM photograph as described above, lattice fringes corresponding to the {110} plane were observed in the {111} plane. The lattice fringe corresponding to the {110} plane refers to a lattice fringe such that a {110} plane appears in a cross section when a crystal grain is cut along the lattice fringe.
The plane to which the grid pattern corresponds can be easily confirmed from the interval between the grid patterns.

At this time, as a result of observing the TEM photograph of the semiconductor thin film of the present invention in detail, the present inventors obtained a very interesting finding. In each of the two different crystal grains seen in the photograph, lattice fringes corresponding to the {110} plane were visible. And it was observed that the grids of each other were running clearly parallel.

Further, regardless of the existence of the crystal grain boundary, lattice fringes of two different crystal grains are connected so as to cross the crystal grain boundary. That is, it was confirmed that most of the lattice fringes observed so as to cross the crystal grain boundaries were linearly continuous in spite of the lattice fringes of different crystal grains. This was similar at any grain boundaries.

Such a crystal structure is a great feature of the crystalline silicon film of the present invention, and realizes the crystal grain boundaries determined by the present inventors.

Such a crystal structure (accurately, a structure of a crystal grain boundary) indicates that two different crystal grains are bonded to each other with extremely high consistency at the crystal grain boundary. That is, the crystal lattice is continuously connected at the crystal grain boundary, and it is very difficult to form a trap level due to a crystal defect or the like. In other words, it can be said that the crystal lattice has continuity at the crystal grain boundaries.

Note that the present inventors have also conducted electron diffraction and H
Analysis by R-TEM observation was performed. As a result, the crystal plane has no regularity, and {111} plane, {110} plane, {31}
The random orientation was such that the 1｝ plane appeared irregularly.

Further, as a result of observing the lattice fringes of two different crystal grains by a TEM photograph, the lattice fringes were completely displaced from each other, and no junction was found to be continuous with good consistency at the crystal grain boundaries. In this observation, a grain boundary in which crystal grains of the {111} orientation are lined up was found, and the {11}
TE photographed under conditions where the checkerboard corresponding to 0 ° can be seen
M photos were examined.

In the case of the conventional high-temperature polysilicon, many portions where lattice fringes were interrupted were found at the crystal grain boundaries. In such a portion, dangling bonds (which can be called crystal defects) are present, and there is a high possibility that the movement of carriers is inhibited as a trap level.

As described above, the crystalline silicon film of the present invention has a lattice continuity even at the crystal grain boundaries, and such crystal defects could hardly be confirmed. From this point, it is proved that the crystalline silicon film of the present invention is a semiconductor film which is clearly different from the conventional high-temperature polysilicon.

By the way, the analysis by the electron beam diffraction described above has obtained interesting findings. In the case of the semiconductor thin film of the present invention, diffraction spots corresponding to <111> incidence appeared relatively clearly, and it was clear that the crystal plane was {111} oriented.

At this time, each spot had a slight concentric spread, which is expected to have a certain degree of rotation angle distribution around the crystal axis. The extent of the spread was within 5 ° as estimated from the pattern.

Further, there were cases where diffraction spots were partially invisible during many observations. Probably roughly $ 11
It is considered that the diffraction pattern was not visible because the crystal axis was slightly deviated, although the orientation was 1 °.

The present inventors have found that almost always {11
Considering the fact that the 0｝ plane is included, probably <11
0> It is speculated that the deviation of the rotation angle around the axis may be the cause of such a phenomenon.

(Knowledge on orientation of semiconductor thin film of the present invention) According to Japanese Patent Application Laid-Open No. 7-321339 disclosed by the present inventors, when an amorphous silicon film is crystallized, it grows substantially parallel to the substrate. The growth direction of the rod-shaped or flat rod-shaped crystal (sometimes called a needle-shaped or columnar crystal) is the <111> axis.

That is, when crystallizing an amorphous silicon film (a-Si) using Ni (nickel) as a catalyst element, NiSi
_{2 The} crystal grows along the <111> axis direction using the precipitate as a medium. This is due to the fact that in the crystal plane of NiSi ₂ and Si,
It is considered that the 11 ° planes have good structural consistency.

At this time, various planes can be formed on the side surfaces (planes parallel to the growth direction) of the rod-shaped or flat rod-shaped crystal grown along the <111> axis direction. 110 ° plane. This is probably because the {110} plane has the highest atomic density among several planes that can be formed on the side surface.

For these reasons, as described in the present invention, $ 11
In the crystal grains grown with the 1} plane at the top (crystal grains grown along the <111> axis direction), the {110} plane appears on the surface (meaning the observation plane). The above opinion is described in the specification filed on June 6, 1997 by the present inventors.

As described above, a crystalline silicon film formed by using the technique described in Japanese Patent Application Laid-Open No. 7-130652 should originally show a roughly {110} orientation. However, the main orientation plane of the crystalline silicon film of the present invention was the {111} plane. For the reason, the present inventors have considered the following model.

The most remarkable difference between the crystalline silicon film described in the specification filed on June 6, 1997 and the crystalline silicon film of the present invention is the nature of the underlayer. That is,
It is considered that what kind of underlayer is a very important parameter in determining the orientation of the crystal plane.

First, it is generally said that the stability of the {111} plane is particularly high at the Si / SiO ₂ (silicon / silicon dioxide) interface. This is considered to be due to the number of bonds on the silicon film side at the interface. Here, shown in Table 1 are the densities of bonds that are considered to be deposited in the bond with silicon dioxide on the crystal plane corresponding to each plane index.

[0108]

[Table 1]

According to Table 1, the {111} plane has the smallest bond density on the crystal plane. In other words, if the bond density is high, the bond angle near the interface is easily distorted when joining with silicon dioxide, which is disadvantageous in terms of energy. Therefore, a {111} plane with a low bond density appears at the Si / SiO ₂ interface. .

However, Japanese Patent Application Laid-Open No.
The crystalline silicon film formed by using the technique described in Japanese Patent Publication No. 52 shows roughly {111} orientation (see the specification of the application filed on June 6, 1997). It seems that the orientation is not determined uniquely.

Therefore, the present inventors considered that not only the density of bonds on the silicon film side but also the density of bonds on the base side are greatly involved in determining the orientation. Needless to say, the bond density on the base side is closely related to the density of the base. That is, it is assumed that there is some correlation between the density of the base and the orientation of the crystalline silicon film formed thereon.

The present inventors examined the etching rate of the base as a means for evaluating the denseness of the base, and examined the correlation between the denseness of the base and the orientation of the semiconductor thin film formed thereon. The etching rate of the underlayer was measured at room temperature using a commercially available etchant LAL500 (a mixture of hydrofluoric acid, ammonium fluoride and a surfactant, manufactured by Hashimoto Kasei). Table 2 shows the results.

[0113]

[Table 2]

As shown in Table 2, in the case of an underlayer generally considered to be dense, such as a thermal oxide film, quartz, or a silicon nitride film, there was a tendency to show a roughly {110} orientation. Conversely, when a silicon dioxide film formed by a sputtering method or a plasma CVD method was used as a base, a tendency to exhibit a substantially {111} orientation was observed. This tendency is considered to be a result of reflecting the difference in etching rate as it is.

That is, when the etching rate of the underlayer is at least as low as 40 to 50 nm / min or less, it can be said that the crystalline silicon film thereover tends to show a substantially {110} orientation.
Conversely, if the etching rate is higher than that value (50 nm / min
In this case, it can be said that a crystalline silicon film having a general {111} orientation as shown in the present invention can be obtained.

The fact that the underlayer is dense means that the density of bonds on the surface of the underlayer is high, and it is easy to bond with the bonds of the silicon film with a small distortion. That is, when the underlayer is dense, it is not necessary to make contact with the underlayer particularly on the {111} plane, and it is considered that the binding force (alignment regulating force) of the underlayer to the orientation of the silicon film is loose.

Therefore, when the underlying layer is made of a very dense insulator such as quartz, the silicon film is not bound by the underlying layer during crystal growth and has a substantially {110} orientation, which is the original orientation. Conceivable.

Conversely, when a crystalline silicon film is formed on a base film having an etching rate of 50 nm / min or more (room temperature) with LAL500 as in the present invention, each crystal grain becomes a base material in the growth process. Under the binding force, it behaves as if it comes in contact with the ground on the most stable surface. As a result, on the surface (or interface) of the crystalline silicon film, a {111} plane that can form a junction with the least distortion appears.

The manner in which the crystal grains bound from the underlayer change to the {111} orientation will be described with reference to FIG. In FIG. 20, the inside of the grains of the rod-shaped or flat rod-shaped crystal can be substantially regarded as a single crystal, and therefore, will be described as c-Si.

In FIG. 20A, the crystal growth plane (tip crystal plane) is roughly along the <111> axis, so that the crystal axis of the crystal plane (surface or interface) immediately after the crystal growth plane is roughly. It is considered that it is the <110> axis.

However, in this state, the crystal grains are displaced when restrained by the base (expected to rotate about 35 °).
However, a substantially {111} plane appears on the crystal plane (the crystal axis shows a <111> axis).

Further, in the case of FIG. 20B, the crystal growth surface is tilted by about 70 ° with respect to the direction parallel to the substrate due to the constraint from the base during the growth process. In this case, the crystal plane appearing on the surface immediately after the crystal growth plane is necessarily a substantially {111} plane due to the relationship of the crystal orientation.

As described above, the crystalline silicon film formed by the technique described in Japanese Patent Application Laid-Open No. Hei 7-130652 is determined by the element of whether the binding force from the underlayer is loose or strong. Is assumed to be determined.

Although the description has been made here focusing on the underlayer, when the lateral growth region is formed as described in Example 2 of JP-A-7-130652, it is formed on the amorphous semiconductor thin film. It is considered that the formed mask insulating film also affects the orientation. Also in that case, it is considered that the orientation is determined by the same model as the base.

In the experience of the present inventors, the discussion so far can be applied to an amorphous semiconductor thin film having a thickness of up to about 80 nm. If the film thickness is larger than this, it is difficult to receive the binding force from the interface between the underlayer and the interface of the mask, and tends to exhibit random orientation.

The present inventors performed X-ray diffraction according to the method described in JP-A-7-321339, and calculated the orientation ratio of the crystalline silicon film of the present invention. In this publication, the orientation ratio is defined by a calculation method as shown in the following Expression 1.

[0127]

(Equation 1)

It should be noted that the {220} plane is observed in the measurement, but it goes without saying that this is equivalent to the {110} plane. As a result of the above measurement, it was found that the {111} plane was the main orientation, and the orientation ratio was 0.7 or more (typically 0.9 or more).

As described above, it can be seen that the crystalline silicon film of the present invention and the conventional polysilicon film have completely different crystal structures (crystal structures). From this point, it can be said that the crystalline silicon film of the present invention is a completely new semiconductor film.

(Knowledge Regarding Electrical Characteristics of TFT) A TFT manufactured using a crystalline silicon film as an active layer as described above is shown in FIG.
The electrical characteristics shown in FIG. FIG. 4 shows an Id-Vg curve (Id-Vg characteristic) of an N-channel TFT in which the abscissa plots the gate voltage (Vg) and the ordinate plots the logarithm of the drain voltage (Id). In addition, the measurement of the electrical characteristics was performed using a commercially available device (manufactured by Hewlett-Packard Company, model number 4145B).
This was performed using

In FIG. 13, reference numeral 1050 denotes the electrical characteristics of the TFT using the active layer obtained in the above-mentioned steps.
Reference numeral 51 indicates the electrical characteristics of the conventional TFT. Here, as a conventional TFT, a TFT which was not subjected to the heat treatment (gettering process) after forming the gate insulating film in Example 1 was used.
FT.

Comparing the characteristics of both transistors, the characteristic indicated by 1050 is 1 at the same gate voltage.
It can be confirmed that an on current that is nearly an order of magnitude larger flows. Note that the ON current indicates a drain current flowing when the TFT is in an ON state (a gate voltage is in a range of about 0 to 20 V in FIG. 13).

It can also be confirmed that the characteristic shown by 1050 has a superior sub-threshold characteristic. The sub-threshold characteristic is a parameter indicating the steepness of the switching operation of the TFT. The steeper the rise of the Id-Vg curve when the TFT switches on or off, the better the sub-threshold characteristic.

Note that typical electrical characteristics of the TFT obtained by the present invention are as follows. (1) The subthreshold coefficient, which is a parameter indicating the switching performance of the TFT (the agility of switching on / off operation), is 60 to 60 for both the N-type TFT and the P-type TFT.
100mV / decade (typically 60-85mV / decade). Note that this data value is almost equivalent to that of an insulated gate field effect transistor (IGFET) using single crystal silicon. (2) The field effect mobility (μ _FE ), which is a parameter indicating the operation speed of the TFT, is 200 to 650 cm ² for an N-type TFT.
/ Vs (typically 250 to 300 cm ² / Vs), 10 for P-type TFT
It is as large as 0 to 300 cm ² / Vs (typically 150 to 200 cm ² / Vs). (3) The threshold voltage (V _th ), which is a parameter of the drive voltage of the TFT, is -0.5 to 1.5 V for the N-type TFT,
It is as small as -1.5 to 0.5 V for P-type TFT. This means that power consumption can be reduced by driving with a small power supply voltage.

As described above, the TFT obtained by the present invention has extremely excellent switching characteristics and high-speed operation characteristics.

(Characteristics of the circuit constituted by the TFT of the present invention)
Next, the frequency characteristics of a ring oscillator manufactured by the present inventors using the TFT obtained in the present invention will be described. The ring oscillator is a circuit in which inverter circuits having a CMOS structure are connected in an odd-numbered stage ring shape, and is used to determine a delay time per one stage of the inverter circuit. The configuration of the ring oscillator used in the experiment is as follows. Number of steps: 9 steps, 19 steps, 51 steps Thickness of gate insulating film (GI) of TFT: 50 nm Gate length of TFT: 0.6 μm Gate width of TFT: 10 μm for NTFT, 20 μm for PTFT
m

FIG. 14 shows the result of measuring the oscillation frequency of the ring oscillator with a spectrum analyzer.
In FIG. 14, the horizontal axis represents the power supply voltage (V _DD ), and the vertical axis represents the oscillation frequency (f _osc ). As shown in FIG. 14, the gate insulating film realizes an oscillation frequency close to 1 GHz in a nine-stage ring oscillator.

FIG. 15 shows a power supply voltage of 5 V and 1.042 G
3 is an output spectrum of a spectrum analyzer when an oscillation frequency of Hz is achieved. The horizontal axis is 10 MHz to 1.
The oscillation frequency up to 2 GHz is taken, and the voltage (output amplitude) taken on a log scale is taken on the vertical axis.

Further, a shift register, which is one of the TEGs of the LSI circuit, was actually manufactured, and the operating frequency was confirmed.
As a result, the thickness of the gate insulating film was 50 nm, and the gate length was 0.6 μm.
m, a power supply voltage of 5 V, and an output pulse having an operation frequency of 100 MHz was obtained in a shift register circuit having 50 stages.

The surprising data of the ring oscillator and the shift register as described above indicate that the TFT of the present invention has performance comparable to or superior to that of the IGFET using single crystal silicon.

The following data is available as evidence to support this. The data shown in FIG. 16 is a graph in which the horizontal axis represents the power supply voltage (V _DD ) and the vertical axis represents the delay time (τ _pd ) per inverter of F / O = 1 (fan-out ratio is 1). (Innovation of logic LSI technology, Kenji Maeguchi et al.,
p108, Science Forum Inc., 1995).

Note that various curves (shown by dotted lines) in the figure are data obtained when IGFETs using single crystal silicon are manufactured according to various design rules, and indicate a so-called scaling rule.

When the relationship between the delay time of the inverter and the power supply voltage obtained by using the above-described ring oscillator is applied to this figure, the curve shown by the solid line in FIG. 16 is obtained. It should be noted that the channel length is 0.6 μm and the thickness of the gate insulating film is 50 nm compared to an inverter made of an IGFET having a channel length of 0.5 μm and a gate insulating film thickness (t _OX ) of 11 nm.
The point is that the inverter manufactured with the TFT has better performance.

This means that the TFT obtained by the present inventor is IG
It clearly shows that it has better performance than FET. For example, even if the thickness of the gate insulating film constituting the TFT is five times or more the thickness of the IGFET, the same or higher performance can be obtained. That is, the TFT of the present invention has the same characteristics as the IGFET having the operation performance.
It can be said that it has an excellent dielectric strength voltage.

At the same time, higher performance can be realized if the TFT of the present invention is miniaturized according to the scaling rule. For example, a ring oscillator of 0.2 μ
9 GHz according to the scaling rule
Is expected to be realized (operating frequency f
Is inversely proportional to the square of the channel length L).

As described above, the TFT of the present invention has extremely excellent characteristics, and a semiconductor circuit formed using the TFT has a completely new TFT capable of realizing a high-speed operation of 10 GHz or more.
It was confirmed to be FT.

[0147] Example 2 has shown an example of using the silicon film as a semiconductor film in Embodiment _{1, Si X Ge 1-X} (0 <X
It is also effective to use a silicon film containing 1 to 10% of germanium as shown by <1, preferably 0.9 ≦ X ≦ 0.99).

When such a compound semiconductor film is used, N
The threshold voltage can be reduced when fabricating TFTs and P-type TFTs. In addition, the field-effect mobility (called mobility) can be increased.

[Embodiment 3] In the embodiment 1, since no impurity is intentionally added to the active layer, the channel forming region becomes intrinsic or substantially intrinsic. The term “substantially intrinsic” means that the activation energy of the silicon film is almost 1/2 (the Fermi level is located almost at the center of the forbidden body), that the impurity concentration is lower than the spin density, That no impurity is added.

However, the TFT of the present invention can use a well-known channel doping technique. The channel doping technique is a technique of adding an impurity to at least a channel formation region for controlling a threshold.

Since the present invention originally has a very small threshold value, the concentration of the impurity to be added may be very small. It is very preferable that a small amount of the additive be used because the threshold value can be controlled without lowering the carrier mobility.

[Embodiment 4] In this embodiment, a structure for obtaining the gettering effect by the phosphorus element in addition to the gettering effect by the halogen element shown in Embodiment 1 will be described. FIG. 3 is used for the description.

First, the steps up to the gettering process using the halogen element are performed in accordance with the steps of the first embodiment to obtain the state shown in FIG. Next, a gate electrode 11 made of tantalum or a material mainly containing tantalum is formed.

Next, anodized film 12 is formed by anodizing the surface of gate electrode 11. The anodic oxide film 12 functions as a protective film. (FIG. 3 (A))

Next, gate insulating film 108 is etched by dry etching using gate electrode 11 as a mask. Then, in this state, the impurity regions 13 and 14 are formed by adding phosphorus or arsenic ions by ion implantation. (FIG. 3 (B))

Next, after forming a thick silicon nitride film, etch back is performed by dry etching to form a sidewall 15. Then, after forming the sidewalls 15, the source region 16 and the drain region 17 are formed by adding phosphorus or arsenic ions again. (FIG. 3
(C))

It is to be noted that the phosphorus element is not added for the second time under the side wall 15 and becomes a pair of low concentration impurity regions 18 containing the phosphorus element at a lower concentration than the source region and the drain region. Below the gate electrode 11 is a channel forming region 19 to which intrinsic or substantially intrinsic or a small amount of impurity is added for controlling a threshold value.

When the state shown in FIG. 3C is obtained,
Heat treatment is performed at 450 to 650 ° C (typically 600 ° C) for 8 to 24 hours (typically 12 hours).

This heat treatment is a step for the purpose of gettering the catalytic element (nickel in this case) with the phosphorus element, but at the same time activates the impurities and recovers the active layer from damage caused by ion implantation. .

In this step, the nickel remaining in the channel formation region 19 moves to the source / drain regions 16 and 17 by performing the heat treatment, where it is gettered and inactivated. That is, nickel remaining inside the channel formation region 19 can be removed.

Since the source / drain regions 16 and 17 function as electrodes as long as they have conductivity, the presence / absence of nickel does not affect the electrical characteristics. Therefore, it can function as a gettering site.

When the state of FIG. 3D is obtained as described above, the interlayer insulating film 20 and the source electrode 2 are formed in the same manner as in the first embodiment.
1. The drain electrode 22 is formed to complete the thin film transistor shown in FIG.

In this embodiment, tantalum is used as the gate electrode, but a crystalline silicon film having conductivity may be used. The method for forming the low-concentration impurity region is not limited to the method of this embodiment.

The most important structure in this embodiment is that gettering is performed by moving the catalyst element remaining in the channel formation region to the source region and the drain region. This is an invention which focuses on the gettering effect of a metal element by phosphorus or arsenic.

In this embodiment, an example of an N-type TFT is shown. However, in the case of a P-type TFT, since a gettering effect cannot be obtained only by a boron element, both a phosphorus element and a boron element are added to a source / drain region. Need to be added.

[Embodiment 5] In this embodiment, an example in which the present invention is applied to a thin film transistor having a structure different from that of Embodiment 1 will be described. FIG. 4 is used for the description.

First, a gate electrode 32 is formed on a quartz substrate 31. For the gate electrode 32, it is necessary to use an electrode having high heat resistance such as tantalum or silicon so as to withstand the subsequent thermal oxidation step.

Next, a gate insulating film 33 is formed so as to cover the gate electrode 32. The gate insulating film 33 is formed by a sputtering method or a plasma CVD method. At this time, in order to obtain a crystalline silicon film having a substantially {111} orientation, the film quality of the gate insulating film 33 needs to be adjusted to the conditions described with reference to Table 2.

Next, an amorphous silicon film to be an active layer later is formed to a thickness of 50 nm thereon. Then, after forming a mask insulating film 35 having an opening as in the first embodiment, a nickel-containing layer 36 is formed. (FIG. 4 (A))

When the state shown in FIG. 4A is obtained,
A heat treatment for crystallization is performed to obtain a crystalline silicon film 37 that is a lateral growth region. (FIG. 4 (B))

Next, the mask insulating film 35 is removed, and a heat treatment is performed in an atmosphere containing a halogen element. The conditions may be in accordance with the first embodiment. By this step, nickel is gettered from inside the crystalline silicon film 37 and is removed into the gas phase. (FIG. 4 (C))

After the gettering process is completed, the active layer 3 consisting of only the lateral growth region is formed by patterning.
8, and a channel stopper 39 made of a silicon nitride film is formed thereon. (FIG. 4 (D))

When the state of FIG. 4D is obtained, an N-type crystalline silicon film is formed and patterned to form a source region 40 and a drain region 41. Further, a source electrode 42 and a drain electrode 43 are formed.

Finally, a heat treatment is performed on the entire device in a hydrogen atmosphere to complete an inverted stagger type TFT having a structure as shown in FIG. Note that the structure shown in this embodiment is an example of an inverted staggered TFT, and is not limited to the structure of this embodiment. Further, the present invention can be applied to other bottom gate type TFTs.

In the case of the above bottom gate type TFT,
Since the insulator serving as a base of the active layer is a gate insulating film (usually a silicon dioxide film is used), it is inevitably subjected to a binding force and tends to have a {111} orientation.

[Embodiment 6] This embodiment shows an example in which a TFT according to the present invention is formed on a substrate having an insulating surface, and a pixel matrix circuit and a peripheral circuit are monolithically constructed.
7 are shown. In this embodiment, as an example of a peripheral circuit such as a driver circuit and a logic circuit, a basic circuit CM
3 illustrates an OS circuit.

First, a base film 51 made of a silicon oxide film is formed on a quartz substrate 50 by a plasma CVD method. Then, a 75 nm thick amorphous silicon film 52 and a mask insulating film 53 are formed thereon, and the nickel-containing layer 5 is formed by spin coating.
4 is formed. These steps are as described in the first embodiment. (FIG. 5 (A))

Next, after dehydration at 450 ° C. for about 1 hour,
Perform heat treatment at 590 ° C for 8 hours in a nitrogen atmosphere.
The crystalline regions 55 to 58 are obtained. 55 and 56 are nickel added regions, and 57 and 58 are lateral growth regions.
(FIG. 5 (B))

After the heat treatment for crystallization is completed, the mask insulating film 53 is removed and patterning is performed, and an island-like semiconductor layer (active layer) 59 consisting only of the lateral growth regions 57 and 58 is formed.
To 61 are formed. (FIG. 5 (C))

Here, 59 is an active layer of an N-type TFT forming a CMOS circuit, and 60 is a P-type TFT forming a CMOS circuit.
An active layer of FT, 61 is an N which constitutes a pixel matrix circuit
It is an active layer of a type TFT (pixel TFT).

After forming the active layers 59 to 61, a gate insulating film 62 made of an insulating film containing silicon is formed thereon.
Then, a catalyst element gettering process is performed.
The conditions of this step may be in accordance with the first embodiment. (FIG. 5
(D))

Next, a metal film (not shown) containing aluminum as a main component is formed, and the gate electrode prototypes 63 to 65 are formed by patterning. 2 wt% in this embodiment
An aluminum film containing scandium is used.
(FIG. 6 (A))

Next, in the same manner as in Example 1, the porous anodic oxide films 66 to 68 were formed by the technique described in JP-A-7-135318.
Non-porous anodic oxide films 69-71, gate electrodes 72-74
To form (FIG. 6 (B))

When the state shown in FIG. 6B is obtained,
Next, the gate electrodes 72 to 74, the porous anodic oxide film 66 to
The gate insulating film 62 is etched using the mask 68 as a mask. Then, the porous anodic oxide films 66 to 68 are removed to obtain the state shown in FIG. The gate insulating films after processing are indicated by 75 to 77.

Next, an impurity ion for imparting N-type is added in two steps according to the same procedure as in Example 1. First, the first doping is performed at a high accelerating voltage to form an n ⁻ region, and then the second doping is performed at a low accelerating voltage.
Form a ⁺ region.

Through the above steps, a source region 78, a drain region 79, a low-concentration impurity region 80, and a channel forming region 81 of an N-type TFT constituting a CMOS circuit are formed. In addition, a source region 82, a drain region 83, a low-concentration impurity region 84, and a channel forming region 85 of an N-type TFT constituting the pixel TFT are defined. (FIG. 6 (D))

Note that, in the state shown in FIG.
The active layer of the P-type TFT constituting the circuit has the same configuration as the active layer of the N-type TFT.

Next, a resist mask 86 is provided so as to cover the N-type TFT, and an impurity ion for imparting P-type (boron is used in this embodiment) is added.

This step is also performed in two steps, similarly to the above-described impurity addition step. However, since it is necessary to invert the N-type to the P-type, the concentration of B (Boron) ions are added.

The P-type TF constituting the CMOS circuit in this manner
A source region 87, a drain region 88, a low concentration impurity region 89, and a channel forming region 90 of T are formed. (FIG. 7
(A))

When the active layer is completed as described above, activation of impurity ions is performed by a combination of furnace annealing, laser annealing, lamp annealing and the like. At the same time, the damage of the active layer in the addition step is also repaired.

Next, a laminated film of a silicon oxide film and a silicon nitride film is formed as an interlayer insulating film 91, and after forming a contact hole, the source electrode 92 to 94, the drain electrode 95,
Forming 96 forms the state shown in FIG.

In this embodiment, since the drain electrode 96 of the pixel TFT is used as the lower electrode of the auxiliary capacitor, it is processed into a shape corresponding to the lower electrode.

Next, a silicon nitride film 97 having a thickness of 10 to 50 nm is formed, and a capacitor electrode 9 for forming an auxiliary capacitor is formed thereon.
8 is formed to a thickness of 100 nm. In this embodiment, the capacitance electrode 9 is used.
A titanium film is used as 8, and an auxiliary capacitance is formed between the titanium film and the drain electrode 96.

The above-mentioned silicon nitride film 97 has a high relative dielectric constant and is therefore suitable as a dielectric. Further, as the capacitor electrode 98, an aluminum film, a chromium film, or the like may be used instead of the titanium film.

Since this embodiment is an example of manufacturing an active matrix substrate (TFT side substrate) of a reflection type liquid crystal display device, it is possible to freely use below a pixel electrode to be formed later unlike a transmission type ( You don't have to worry about the aperture ratio). Therefore, it is possible to form the auxiliary capacitance as described above.

Next, a second interlayer insulating film 99 made of an organic resin film is formed to a thickness of 0.5 to 3 μm. Then, a conductive film is formed on the interlayer insulating film 99, and the pixel electrode 10 is formed by patterning. Since the present embodiment is a reflection type example, a material containing aluminum as a main component is used as a conductive film constituting the pixel electrode 10, and the pixel electrode 10 has a function as a reflection film.

Next, the entire substrate was heated at 350 ° C. in a hydrogen atmosphere for 1 hour.
Dangling bonds (unpaired bonds) in the film (especially in the active layer) by heating the device for about 2 hours and hydrogenating the entire device
To compensate. Through the above steps, a CMOS circuit and a pixel matrix circuit can be manufactured over the same substrate.

[Embodiment 7] In this embodiment, an example in which a TFT structure different from that of Embodiment 6 is adopted will be described. First, FIG. 8A shows an example in which a sidewall is used in forming a low-concentration impurity region.

In this case, a nonporous anodic oxide film is formed in the state shown in FIG. 6A, and the gate insulating film is etched using the gate electrode and the anodic oxide film as a mask. In that state, impurities are added for forming the n ⁻ region and the p ⁻ region.

Next, the side walls 1001 to 1003
Is formed by an etch-back method, and then an impurity is added for forming an n ⁺ region and ap ⁺ region. In such a process, low-concentration impurity regions (n ⁻ region and p ⁻ region) are formed below the sidewalls 1001 to 1003.

In FIG. 8A, metal silicides 1004 to 1006 are formed using a known salicide technique. As a metal for silicidation, titanium, tantalum, tungsten, molybdenum, or the like can be used.

The structure shown in FIG. 8B is characterized in that gate electrodes 1007 to 1009 are formed of a crystalline silicon film provided with one conductivity. Normally, N-type conductivity is provided, but a dual-gate TFT in which conductivity differs between an N-type TFT and a P-type TFT can also be used.

Further, the salicide structure is applied to the structure shown in FIG. 8B, but in this case, the gate electrode 10
Metal silicide 1010-1 on top of 07-1009
012 are formed.

The structure shown in this embodiment is designed so as to be suitable for a TFT having a high operation speed. Especially,
The salicide structure is a very effective technique for realizing an operating frequency on the order of several GHz.

[Embodiment 8] In this embodiment, an example in which an auxiliary capacitance is formed with a configuration different from that of Embodiment 6 will be described.

First, in FIG. 9A, the drain region 1020 of the active layer is formed relatively large, and a part thereof is used as a lower electrode of an auxiliary capacitance. In this case, the drain region 1
A gate insulating film 1021 is provided on the substrate 020, and a capacitor electrode 1022 is formed thereon. This capacitance electrode 1022
Are formed of the same material as the gate electrode.

At this time, a portion of the drain region 1020 which forms an auxiliary capacitance may be made conductive by adding impurities in advance, or may be formed by applying a constant voltage to the capacitance electrode 1022. Layers may be used.

FIG. 9A shows an example of a reflection type liquid crystal display device, so that the auxiliary capacitance can be formed by making the most of the back side of the pixel electrode. Therefore, a very large capacity can be secured. Of course, the present invention can also be applied to a transmissive liquid crystal display device.

Next, FIG. 9B shows an example of a transmission type liquid crystal display device. In the structure of FIG. 9B, the drain electrode 1023
Is the lower electrode of the storage capacitor, and the silicon nitride film 102
4. A black mask 1025 is formed, and a drain electrode 1 is formed.
An auxiliary capacitor is formed between the H.023 and the black mask 1025.

As described above, the configuration of FIG. 9B is characterized in that the black mask 1025 also serves as the upper electrode of the storage capacitor.

Reference numeral 1026 denotes a pixel electrode, which is a transmissive type and uses a transparent conductive film (for example, an ITO film).

In the structure as shown in FIG. 9B, it is possible to increase the aperture ratio by forming an auxiliary capacitor which easily occupies a large area on the TFT. Further, since a silicon nitride film having a high dielectric constant can be used with a thickness of about 25 nm, it is possible to secure a very large capacity with a small area.

[Embodiment 9] This embodiment shows an example in which a liquid crystal panel is constructed by utilizing the present invention. FIG. 10 is a simplified view of the cross section of an active matrix type liquid crystal panel. A CMOS circuit is shown in a region forming a driver circuit or a logic circuit, and a pixel TFT is shown in a region forming a pixel matrix circuit. I have.

Since the structure (TFT structure) of the CMOS circuit and the pixel matrix circuit has already been described in Examples 6 to 8, only the necessary parts will be described in this embodiment.

First, the state shown in FIG. 7C is obtained according to the manufacturing process shown in the sixth embodiment. It is to be noted that the change of the pixel TFT to have a multi-gate structure is at the discretion of the practitioner.

Then, as a preparation for the active matrix substrate, an alignment film 1030 is formed. Next, a counter substrate is prepared. The counter substrate includes a glass substrate 1031, a transparent conductive film 1032, and an alignment film 1033. Note that a black mask and a color filter are formed on the counter substrate side as necessary, but are omitted here.

The thus prepared active matrix substrate and the counter substrate are bonded by a known cell assembling process. Then, a liquid crystal material 1034 is sealed between the two substrates to complete a liquid crystal panel as shown in FIG.

The liquid crystal material 1034 has a liquid crystal operating mode (E
CB mode, guest host mode, etc.).

FIG. 11 shows a simplified appearance of an active matrix substrate as shown in FIG. 7C. FIG.
1, reference numeral 1040 denotes a quartz substrate; 1041, a pixel matrix circuit; 1042, a source driver circuit;
3 is a gate driver circuit, and 1044 is a logic circuit.

The logic circuit 1044 is a TFT in a broad sense.
However, in order to distinguish them from circuits conventionally called pixel matrix circuits and driver circuits, other signal processing circuits (memory,
D / A converter, pulse generator, etc.).

Further, an FPC (Flexible Print Circuit) terminal is attached as an external terminal to the liquid crystal panel thus formed. Generally, a liquid crystal panel is a liquid crystal panel with an FPC attached.

[Embodiment 10] The present invention is not limited to the liquid crystal display device shown in Embodiment 9 but is also applicable to an active matrix type E.
It is also possible to manufacture other electro-optical devices such as an L (electroluminescence) display device and an EC (electrochromic) display device.

[Embodiment 11] In this embodiment, an example of an electronic device (applied product) using an electro-optical device using the present invention is shown in FIG. Examples of applied products using the present invention include a video camera, a still camera, a projector, a head-mounted display, a car navigation, a personal computer, and a portable information terminal (mobile computer, mobile phone, etc.).

FIG. 12 (A) shows a mobile phone,
01, audio output unit 2002, audio input unit 2003, display device 2004, operation switch 2005, antenna 200
6. The present invention can be applied to the display device 2004.

FIG. 12B shows a video camera, which includes a main body 2101, a display device 2102, an audio input unit 2103, an operation switch 2104, a battery 2105, and an image receiving unit 21.
06. The present invention can be applied to the display device 2102.

FIG. 12C shows a mobile computer (mobile computer), which comprises a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, and a display device 2205. The present invention relates to a display device 220.
5 is applicable.

FIG. 12D shows a head mounted display, which comprises a main body 2301, a display device 2302, and a band 2303. The present invention can be applied to the display device 2302.

FIG. 12E shows a rear type projector, which includes a main body 2401, a light source 2402, a display device 2403,
Polarizing beam splitter 2404, reflector 240
5, 2406 and a screen 2407. The invention can be applied to the display device 2403.

FIG. 12F shows a front type projector, which comprises a main body 2501, a light source 2502, and a display device 250.
3. It comprises an optical system 2504 and a screen 2505. The invention can be applied to the display device 2503.

As described above, the applicable range of the present invention is extremely wide, and it can be applied to display media in all fields. Further, since the TFT of the present invention can also constitute a semiconductor circuit such as an IC or an LSI, any application is possible as long as the TFT requires such a semiconductor circuit.

[0232]

According to the invention disclosed in this specification, a semiconductor thin film having substantially the same crystallinity as a single crystal semiconductor can be realized. IGFETs (MOFETs) fabricated on a single crystal by using such a semiconductor thin film
(SFET) can be realized with a TFT having high performance comparable to or surpassing SFET.

A semiconductor circuit and an electro-optical device using the above-described TFT and an electronic device having the same have extremely high performance and are extremely excellent in functionality, portability and reliability. It will be.

[Brief description of the drawings]

FIG. 1 illustrates a manufacturing process of a thin film transistor.

FIG. 2 illustrates a manufacturing process of a thin film transistor.

FIG. 3 illustrates a manufacturing process of a thin film transistor.

FIG. 4 illustrates a manufacturing process of a thin film transistor.

FIG. 5 illustrates a manufacturing process of an active matrix substrate.

FIG. 6 illustrates a manufacturing process of an active matrix substrate.

FIG. 7 illustrates a manufacturing process of an active matrix substrate.

FIG. 8 illustrates a structure of an active matrix substrate.

FIG. 9 illustrates a structure of an active matrix substrate.

FIG. 10 is a diagram illustrating a cross section of a liquid crystal display device.

FIG. 11 is a diagram of the active matrix substrate as viewed from above.

FIG. 12 illustrates an example of an electronic device (applied product).

FIG. 13 illustrates electric characteristics of a thin film transistor.

FIG. 14 is a diagram illustrating frequency characteristics of a ring oscillator.

FIG. 15 is a photograph showing an output spectrum of a ring oscillator.

FIG. 16 is a diagram showing a scaling rule.

FIG. 17 is a diagram schematically showing a crystal orientation relationship.

FIG. 18 is a diagram schematically showing a state of crystal growth.

Continued on the front page (72) Inventor Yasushi Yasushi 398 Hase, Atsugi City, Kanagawa Prefecture Inside Semiconductive Energy Laboratory Co., Ltd. (72) Inventor Shoji Miyanaga 398 Hase, Atsugi City, Kanagawa Prefecture Inside Semiconductive Energy Laboratory Co., Ltd.

Claims (50)

[Claims] 1. A semiconductor thin film comprising an aggregate of a plurality of rod-shaped or flat rod-shaped crystals containing silicon as a main component, the plane orientation being substantially {111} -oriented and existing in the film other than silicon. A semiconductor thin film, wherein the element is at least one or more elements selected from elements other than C (carbon), N (nitrogen), O (oxygen), and S (sulfur). 2. The element present in a film other than silicon is Ni.
(Nickel), Co (cobalt), Fe (iron), Pd
(Palladium), Pt (platinum), Cu (copper), Au
(Gold), and the concentration of the element is 5 × 10 ¹⁷ atoms / cm ³ or less (or
2. The semiconductor thin film according to claim 1, wherein the content is 0.001 atomic% or less. 3. A semiconductor thin film comprising an aggregate of a plurality of rod-shaped or flat rod-shaped crystals containing silicon as a main component, the plane orientation being substantially {111} -oriented, and the presence of C (carbon ), The concentrations of N (nitrogen), O (oxygen) and S (sulfur) are below the lower limit of detection by SIMS. 4. A semiconductor thin film comprising an aggregate of a plurality of rod-shaped or flat rod-shaped crystals containing silicon as a main component, the plane orientation being substantially {111} -oriented, and C (carbon) existing in the film. ), N (nitrogen) and S (sulfur) concentrations are 5
× 10 ¹⁸ atoms / cm ³ (or less than 0.01 atomic%), and the concentration of O (oxygen) existing in the film is 1.5 × 10
A semiconductor thin film having a density of less than ¹⁹ atoms / cm ³ (or less than 0.03 atomic%). 5. A semiconductor thin film comprising an aggregate of a plurality of rod-shaped or flat rod-shaped crystals containing silicon as a main component, wherein the {111} orientation ratio is 0.9 or more and other than silicon, The elements present are at least C (carbon), N
A semiconductor thin film characterized by being one or more elements selected from elements other than (nitrogen), O (oxygen) and S (sulfur). 6. An element other than silicon which is present in a film,
Ni (nickel), Co (cobalt), Fe (iron), P
d (palladium), Pt (platinum), Cu (copper), Au
(Gold), and the concentration of the element is 5 × 10 ¹⁷ atoms / cm ³ or less (or
0.001 atomic% or less). 7. A semiconductor thin film comprising an aggregate of a plurality of rod-shaped or flat rod-shaped crystals containing silicon as a main component, wherein the {111} orientation ratio is 0.9 or more, and C is present in the film. (Carbon), N (nitrogen), O (oxygen) and S
A semiconductor thin film, wherein the concentration of (sulfur) is lower than the lower limit of detection by SIMS. 8. A semiconductor thin film comprising an aggregate of a plurality of rod-shaped or flat rod-shaped crystals containing silicon as a main component, wherein the {111} orientation ratio is 0.9 or more, and C is present in the film. The concentration of (carbon), N (nitrogen) and S (sulfur) is less than 5 × 10 ¹⁸ atoms / cm ³ (or less than 0.01 atomic%)
And the concentration of O (oxygen) present in the film is 1.5
A semiconductor thin film characterized by being less than × 10 ¹⁹ atoms / cm ³ (or less than 0.03 atomic%). 9. The semiconductor thin film according to claim 1, wherein said plurality of rod-shaped or flat rod-shaped crystals are arranged substantially parallel to each other with a specific direction. 10. The method according to claim 1, wherein most of the lattice fringes observed across an arbitrary grain boundary are linearly continuous between different crystal grains forming the grain boundary. The semiconductor thin film according to claim 8. 11. The semiconductor thin film according to claim 1, wherein most crystal lattices have continuity at an arbitrary grain boundary. 12. The semiconductor thin film according to claim 1, wherein specific regularity due to {111} orientation is observed in the electron beam diffraction pattern. 13. An upper surface and / or a lower surface in contact with an insulator having an etching rate of 50 nm / min or more for LAL500 at room temperature.
4. The semiconductor thin film according to claim 1. 14. A semiconductor thin film comprising an aggregate of a plurality of rod-shaped or flat rod-shaped crystals containing silicon as a main component, the plane orientation being substantially {111} -oriented, and almost any crystal grain boundary. A semiconductor thin film characterized in that the crystal lattice has continuity. 15. A semiconductor thin film comprising an aggregate of a plurality of rod-shaped or flat rod-shaped crystals containing silicon as a main component, wherein the plane orientation is substantially {111} orientation and crosses an arbitrary crystal grain boundary. A semiconductor thin film, wherein most of the lattice fringes observed in the following manner are linearly continuous between different crystal grains forming the crystal grain boundary. 16. A semiconductor thin film comprising an aggregate of a plurality of rod-shaped or flat rod-shaped crystals containing silicon as a main component, wherein the {111} orientation ratio is 0.9 or more, and at any crystal grain boundary, A semiconductor thin film characterized in that most crystal lattices have continuity. 17. A semiconductor thin film comprising an aggregate of a plurality of rod-shaped or flat rod-shaped crystals containing silicon as a main component, wherein the {111} orientation ratio is 0.9 or more and an arbitrary crystal grain boundary is formed. Most of the plaids observed across are
A semiconductor thin film characterized by being linearly continuous between different crystal grains forming the crystal grain boundary. 18. The semiconductor thin film according to claim 14, wherein said plurality of rod-shaped or flat rod-shaped crystals are arranged substantially parallel to each other with a specific direction. 19. The element present in the film other than silicon is at least one or more elements selected from elements other than C (carbon), N (nitrogen), O (oxygen) and S (sulfur). 18. The semiconductor thin film according to claim 14, wherein the semiconductor thin film is provided. 20. The elements present in the film other than silicon include Ni (nickel), Co (cobalt), Fe
(Iron), Pd (palladium), Pt (platinum), Cu
(Copper) and one or more elements selected from Au (gold), and the concentration of the element is 5 × 10 ¹⁷ atoms / cm ³
20. The semiconductor thin film according to claim 19, wherein the content is not more than 0.001 atomic%. 21. The method according to claim 14, wherein the concentrations of C (carbon), N (nitrogen), O (oxygen) and S (sulfur) present in the film are lower than the lower limit of detection by SIMS. 18. The semiconductor thin film according to 17. 22. The concentration of C (carbon), N (nitrogen) and S (sulfur) present in the film is less than 5 × 10 ¹⁸ atoms / cm ³ (0.
And the concentration of O (oxygen) present in the film is less than 1.5 × 10 ¹⁹ atoms / cm ³ (0.03 atomic%).
14) to claim 1).
8. The semiconductor thin film according to 7. 23. Ni, Co, Fe, Pd, P
18. One or more elements selected from t, Cu, and Au are present at a concentration of 5 × 10 ¹⁷ atoms / cm ³ or less (or 0.001 atomic% or less). 4. The semiconductor thin film according to claim 1. 24. The semiconductor thin film according to claim 14, wherein a specific regularity due to {111} orientation is observed in the electron beam diffraction pattern. 25. The semiconductor thin film according to claim 14, wherein the semiconductor thin film is in contact with an insulator whose etching rate with respect to LAL500 at room temperature is 50 nm / min or more at an upper surface and / or a lower surface. 26. A semiconductor device comprising a semiconductor thin film comprising an aggregate of a plurality of rod-shaped or flat rod-shaped crystals containing silicon as a main component, wherein the semiconductor thin film has a substantially {111} orientation.
In addition, at least C is present in the film except for silicon.
A semiconductor device comprising one or more elements selected from elements other than (carbon), N (nitrogen), O (oxygen), and S (sulfur). 27. The elements present in the film other than silicon include Ni (nickel), Co (cobalt), Fe
(Iron), Pd (palladium), Pt (platinum), Cu
(Copper) and one or more elements selected from Au (gold), and the concentration of the element is 5 × 10 ¹⁷ atoms / cm ³
27. The semiconductor device according to claim 26, wherein the content is equal to or less than 0.001 atomic%. 28. A semiconductor device comprising a semiconductor thin film composed of an aggregate of a plurality of rod-shaped or flat rod-shaped crystals containing silicon as a main component, wherein the semiconductor thin film has a substantially {111} orientation.
And a concentration of C (carbon), N (nitrogen), O (oxygen), and S (sulfur) present in the film is lower than a lower limit of detection by SIMS. 29. A semiconductor device comprising a semiconductor thin film comprising an aggregate of a plurality of rod-shaped or flat rod-shaped crystals containing silicon as a main component, wherein the plane orientation of the semiconductor thin film is substantially {111} orientation;
And C (carbon), N (nitrogen) and S present in the film
(Sulfur) concentration is less than 5 × 10 ¹⁸ atoms / cm ³ (or 0.01
atomic%) and the concentration of O (oxygen) present in the film is less than 1.5 × 10 ¹⁹ atoms / cm ³ (or 0.03 at.
omic%). 30. A semiconductor device comprising a semiconductor thin film composed of an aggregate of a plurality of rod-shaped or flat rod-shaped crystals containing silicon as a main component, wherein the semiconductor thin film has a {111} orientation ratio of 0.9 or more. And the element present in the film other than silicon is at least one or more elements selected from elements other than C (carbon), N (nitrogen), O (oxygen) and S (sulfur) A semiconductor device characterized by the above-mentioned. 31. Elements present in the film other than silicon include Ni (nickel), Co (cobalt), Fe
(Iron), Pd (palladium), Pt (platinum), Cu
(Copper) and one or more elements selected from Au (gold), and the concentration of the element is 5 × 10 ¹⁷ atoms / cm ³
31. The semiconductor device according to claim 30, wherein the content is not more than 0.001 atomic%. 32. A semiconductor device comprising a semiconductor thin film comprising an aggregate of a plurality of rod-shaped or flat rod-shaped crystals containing silicon as a main component, wherein said semiconductor thin film has a {111} orientation ratio of 0.9 or more. And C (carbon), N (nitrogen), O
A semiconductor device, wherein the concentrations of (oxygen) and S (sulfur) are lower than the lower limit of detection by SIMS. 33. A semiconductor device comprising a semiconductor thin film composed of an aggregate of a plurality of rod-shaped or flat rod-shaped crystals containing silicon as a main component, wherein the {111} orientation ratio of the semiconductor thin film is 0.9 or more. And the concentration of C (carbon), N (nitrogen) and S (sulfur) present in the film is less than 5 × 10 ¹⁸ atoms / cm ³ (or 0.1%).
01 atomic%) and the concentration of O (oxygen) present in the film is less than 1.5 × 10 ¹⁹ atoms / cm ³ (or 0.03 atomic%).
omic%). 34. The semiconductor device according to claim 26, wherein said plurality of rod-shaped or flat rod-shaped crystals are arranged substantially parallel to each other with a specific direction. 35. The method according to claim 35, wherein most of the lattice fringes observed across an arbitrary crystal grain boundary of the semiconductor thin film are linearly continuous between different crystal grains forming the crystal grain boundary. 34. The semiconductor device according to claim 26, wherein 36. The semiconductor thin film according to claim 2, wherein most crystal lattices have continuity at arbitrary crystal grain boundaries.
The semiconductor device according to any one of claims 6 to 33. 37. The semiconductor device according to claim 26, wherein a specific regularity due to {111} orientation is observed in an electron diffraction pattern of the semiconductor thin film. 38. The semiconductor device according to claim 26, further comprising an insulator in contact with an upper surface and / or a lower surface of the semiconductor thin film and having an etching rate of 50 nm / min or more for LAL500 at room temperature. Semiconductor device. 39. A semiconductor device comprising a semiconductor thin film composed of an aggregate of a plurality of rod-shaped or flat rod-shaped crystals containing silicon as a main component, wherein the semiconductor thin film has a substantially {111} orientation.
A semiconductor device characterized in that almost any crystal lattice has continuity at an arbitrary crystal grain boundary. 40. A semiconductor device comprising a semiconductor thin film composed of an aggregate of a plurality of rod-shaped or flat rod-shaped crystals containing silicon as a main component, wherein the semiconductor thin film has a substantially {111} orientation.
In addition, a semiconductor device is characterized in that most of the lattice fringes observed so as to cross any crystal grain boundary are linearly continuous between different crystal grains forming the crystal grain boundary. 41. A semiconductor device comprising a semiconductor thin film comprising an aggregate of a plurality of rod-shaped or flat rod-shaped crystals containing silicon as a main component, wherein said semiconductor thin film has a {111} orientation ratio of 0.9 or more. A semiconductor device, wherein most crystal lattices have continuity at an arbitrary crystal grain boundary. 42. A semiconductor device comprising a semiconductor thin film composed of an aggregate of a plurality of rod-shaped or flat rod-shaped crystals containing silicon as a main component, wherein said semiconductor thin film has a {111} orientation ratio of 0.9 or more. A semiconductor device, wherein almost all of the lattice fringes observed so as to cross an arbitrary crystal grain boundary are linearly continuous between different crystal grains forming the crystal grain boundary. 43. The semiconductor device according to claim 39, wherein specific regularity due to {111} orientation is observed in an electron diffraction pattern of said semiconductor thin film. 44. The semiconductor device according to claim 39, further comprising an insulator in contact with an upper surface and / or a lower surface of the semiconductor thin film, the etching rate of the LAL 500 at room temperature being 50 nm / min or more. Semiconductor device. 45. The semiconductor device according to claim 39, wherein said plurality of rod-shaped or flat rod-shaped crystals are arranged substantially parallel to each other with a specific direction. 46. An element other than silicon that is present in the semiconductor thin film is at least one element selected from elements other than C (carbon), N (nitrogen), O (oxygen) and S (sulfur). 43. The semiconductor device according to claim 39, wherein: 47. Elements other than silicon that are present in the semiconductor thin film include Ni (nickel), Co (cobalt),
Fe (iron), Pd (palladium), Pt (platinum), Cu
(Copper) and one or more elements selected from Au (gold), and the concentration of the element is 5 × 10 ¹⁷ atoms / cm ³
47. The semiconductor device according to claim 46, wherein the content is less than or equal to 0.001 atomic%. 48. The concentration of C (carbon), N (nitrogen), O (oxygen) and S (sulfur) present in the semiconductor thin film is S
43. The semiconductor device according to claim 39, wherein the semiconductor device is equal to or lower than a lower limit of detection by IMS. 49. The concentration of C (carbon), N (nitrogen) and S (sulfur) present in the semiconductor thin film is 5 × 10 ¹⁸ atoms /
cm ³ (or less than 0.01 atomic%), and the concentration of O (oxygen) present in the film is 1.5 × 10 ¹⁹ atoms / cm ³
43. The semiconductor device according to claim 39, wherein said semiconductor device is less than 0.03 atomic%. 50. Ni, Co, F in the semiconductor thin film
e, one or more elements selected from Pd, Pt, Cu, and Au are 5 × 10 ¹⁷ atoms / cm ³ or less (or 0.001a
43. The semiconductor device according to claim 39, wherein the semiconductor device exists at a concentration of tomic% or less.