JP4376331B2 - Method for manufacturing semiconductor device - Google Patents

Description

[0001]
[Technical field to which the invention belongs]
The present invention relates to a semiconductor device including a thin film transistor (hereinafter referred to as TFT) using a semiconductor thin film as a circuit and a technique for manufacturing the semiconductor device. Note that in this specification, a semiconductor device refers to all devices that function using a semiconductor.
[0002]
Therefore, the term “semiconductor device” used in the claims includes not only a single semiconductor element such as a TFT, but also an electro-optical device having a TFT, a semiconductor circuit, and an electronic device on which these are mounted.
[0003]
[Prior art]
In recent years, TFTs used in electro-optical devices such as active matrix liquid crystal display devices have been actively developed. An active matrix liquid crystal display device is a monolithic display device in which a pixel matrix circuit and a driver circuit are provided on the same substrate.
[0004]
Recently, an attempt has been made to form a semiconductor circuit having a function equivalent to that of a conventional IC using TFTs provided on a substrate. For example, development of a system-on-panel that incorporates logic circuits such as a γ correction circuit, a memory circuit, and a clock generation circuit has been studied.
[0005]
Since such a driver circuit or logic circuit needs to operate at high speed, it is inappropriate to use an amorphous semiconductor film (typically an amorphous silicon film) as an active layer. Therefore, at present, crystalline semiconductor films (typically polysilicon films) are being studied.
[0006]
[Problems to be solved by the invention]
However, when circuit performance equal to that of conventional ICs is required for circuits assembled with TFTs, crystalline semiconductor films formed by conventional techniques are sufficient to satisfy circuit specifications. It has become difficult to produce a TFT having performance.
[0007]
Accordingly, an object of the present invention is to realize a high-performance semiconductor device by fabricating a TFT having better electrical characteristics than a TFT using a conventional polysilicon film and assembling a circuit with the TFT.
[0008]
[Means for Solving the Problems]
The gist of the invention disclosed in this specification is as follows:
A first step of forming a semiconductor film containing crystals;
A second step of oxidizing the semiconductor film containing the crystal to reduce the film thickness;
250 to 5000 mJ / cm for the semiconductor film containing crystals after the second step ² A third step of performing a laser annealing treatment with an energy density of
A fourth step of performing a furnace annealing process on the semiconductor film including the crystal after the third step;
It is characterized by including.
[0009]
The gist of other inventions is as follows:
A first step of forming a semiconductor film containing crystals;
A second step of oxidizing the semiconductor film containing the crystal to reduce the film thickness;
250 to 5000 mJ / cm for the semiconductor film containing crystals after the second step ² A third step of performing a laser annealing treatment with an energy density of
A fourth step of performing a furnace annealing treatment at 900 to 1200 ° C. in a reducing atmosphere on the semiconductor film including the crystal after the third step;
It is characterized by including.
[0010]
In the first step, the semiconductor film including a crystal includes all semiconductor films including a crystal component, specifically, only a part of a single crystal semiconductor film, a polycrystalline semiconductor film, a microcrystalline semiconductor film, and an amorphous semiconductor film. Refers to a semiconductor film that is crystallized or a semiconductor film that can be regarded as a substantially single crystal.
[0011]
Note that a semiconductor film that can be substantially regarded as a single crystal is a semiconductor film formed by aggregating a plurality of crystal grains, but has crystallinity such that the plane orientations of the individual crystal grains are aligned, that is, A semiconductor film that exhibits a specific orientation over the entire film surface.
[0012]
A semiconductor film containing an amorphous material includes all semiconductor films containing an amorphous component, and a microcrystalline semiconductor film, an amorphous semiconductor film, or a semiconductor film in which only a part of the amorphous semiconductor film is crystallized. Point to.
[0013]
In this specification, a silicon film is given as a typical example of a semiconductor film, but a germanium film or a silicon germanium film (Si _1-x Ge _x (0 <X It goes without saying that a semiconductor film such as <1) can also be used in the present invention.
[0014]
In the step of performing the laser annealing process in the third step, excimer laser light using KrF (wavelength 248 nm), XeCl (wavelength 308 nm), ArF (wavelength 193 nm) or the like as an excitation gas may be used. The beam shape of the laser light may be linear or planar.
[0015]
The light energy that can be used in the present invention is not limited to excimer laser light, and ultraviolet light or infrared light may be used. In that case, strong light having the same light intensity as the laser light may be emitted from an ultraviolet lamp or an infrared lamp.
[0016]
In addition, the furnace annealing treatment in the fourth step is not particularly limited in the treatment atmosphere, but a reducing atmosphere is preferable. The reducing atmosphere refers to a hydrogen atmosphere, an ammonia atmosphere, an inert atmosphere containing hydrogen or ammonia (a mixed atmosphere of hydrogen and nitrogen, a mixed atmosphere of hydrogen and argon, or the like). Moreover, it is preferable that processing temperature shall be 900-1200 degreeC (preferably 1000-1100 degreeC).
[0017]
This step has an effect of flattening the surface of the semiconductor film containing crystals. This is a result of accelerated surface diffusion of semiconductor atoms that seeks to minimize surface energy. At the same time, this step also has the effect of significantly reducing the defects present in the crystal grain boundaries and crystal grains. This is due to the termination effect of dangling bonds by hydrogen, the effect of removing impurities by hydrogen, and the accompanying recombination of semiconductor atoms. In order to obtain these effects, heat treatment at 900 to 1200 ° C. is required in a reducing atmosphere.
[0018]
Note that the surface of the semiconductor film containing crystals can be planarized even in an inert atmosphere (a nitrogen atmosphere, a helium atmosphere, or an argon atmosphere). However, it is preferable to reduce the natural oxide film by using the reducing action because many silicon atoms with high energy are generated and as a result, the planarization effect is enhanced.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
The embodiment of the present invention having the above-described configuration will be described in detail with the examples described below.
[0020]
【Example】
[Example 1]
In this example, a process for manufacturing a TFT on a substrate by implementing the present invention will be described. FIG. 1 is used for the description.
[0021]
First, a quartz substrate 101 was prepared. As the substrate, a material having high heat resistance must be selected. A material having high heat resistance such as a silicon substrate, a ceramic substrate, a crystallized glass substrate, or a metal substrate can be used instead of the quartz substrate.
[0022]
However, although a base film may or may not be provided when a quartz substrate is used, an insulating film is preferably provided as a base film when other materials are used. As the insulating film, any one of a silicon oxide film (SiOx), a silicon nitride film (Six Ny), a silicon oxynitride film (SiOx Ny), an aluminum nitride film (AlxNy), or a laminated film thereof may be used.
[0023]
In addition, it is effective to use a base film in which a heat-resistant metal layer and a silicon oxide film are laminated, since the heat dissipation effect is greatly enhanced. The heat dissipation effect is sufficient even in the laminated structure of the above-described aluminum nitride film and silicon oxide film.
[0024]
When the quartz substrate 101 was thus prepared, a 90 nm-thick semiconductor film (in this example, an amorphous silicon film) 102 was formed, and a nickel-containing layer 103 was formed on the surface. Regarding the method of forming the nickel-containing layer 103, it is preferable to refer to the technique described in Japanese Patent Laid-Open No. 7-130652. (Fig. 1 (A))
[0025]
In this embodiment, an example in which nickel is added using the technique described in Japanese Patent Laid-Open No. 7-130652 is shown. However, a nickel film is formed and thermally diffused, or an ion implantation method (ion implantation method). (With mass separation), plasma doping method (without mass separation) or laser doping method) may be used.
[0026]
In this embodiment, disilane (Si) is used as a film forming gas for the amorphous silicon film 102. ₂ H ₆ The film was formed by a low pressure thermal CVD method at 450 ° C. At this time, it is important to thoroughly control the concentration of impurities such as C (carbon), N (nitrogen), and O (oxygen) mixed in the film. This is because the presence of a large amount of these impurities hinders the progress of crystallization.
[0027]
The applicant has a carbon and nitrogen concentration of 5 × 10 ¹⁸ atoms / cm ^Three The following (preferably 5 × 10 ¹⁷ atoms / cm ^Three Below), oxygen concentration is 1 × 10 ¹⁹ atoms / cm ^Three The following (preferably 5 × 10 ¹⁸ atoms / cm ^Three The impurity concentration was controlled so that: The metal element is 1 × 10 ¹⁷ atoms / cm ^Three It managed so that it might become the following. If such concentration control is performed in the film formation stage, the impurity concentration does not increase during the TFT manufacturing process as long as external contamination is prevented.
[0028]
The nickel-containing layer 103 was coated with a nickel acetate salt solution containing 10 ppm of nickel in terms of weight on the entire surface (all regions) of the amorphous silicon film 102 by spin coating, and hydrogen was extracted at 450 ° C. for about 1 hour. .
[0029]
Thereafter, a heat treatment is applied for 4 to 24 hours at a temperature of 500 to 700 ° C. (typically 550 to 650 ° C.) in an inert atmosphere, a hydrogen atmosphere, or an oxygen atmosphere to obtain a polysilicon film 104. The polysilicon film 104 has 1 × 10 nickel. ¹⁸ ~ 1x10 ¹⁹ atoms / cm ^Three Remain at a concentration of (Fig. 1 (B))
[0030]
Strictly speaking, no nickel is added to the amorphous silicon film at the time of spin coating. However, since nickel easily diffuses into the amorphous silicon film in the subsequent hydrogen soaking process, it can be considered substantially an addition process.
[0031]
Further, the plasma CVD method may be used as long as a film quality equivalent to the amorphous silicon film formed by the low pressure thermal CVD method can be obtained. Further, it is not necessary to be a completely amorphous semiconductor, and a microcrystalline silicon film or the like may be formed.
[0032]
Further, instead of the silicon film, silicon germanium (Six Ge1-x (0 <X A semiconductor film such as represented by <1) may be used. In that case, it is desirable that germanium contained in silicon germanium be 5 atomic% or less.
[0033]
In addition to nickel, lattice intrusive catalytic elements such as cobalt (Co), iron (Fe), palladium (Pd), platinum (Pt), copper (Cu), gold (Au), germanium (Ge), lead ( One or more kinds selected from lattice substitution (or melting) catalyst elements such as Pb) and tin (Sn) can also be used.
[0034]
FIG. 9 shows the result of examining the temperature at which the amorphous silicon film changes to the polysilicon film by the differential thermal analysis method (more precisely, the differential thermal analysis method). The differential thermal analysis method (also called DTA method) is a method for analyzing the thermal characteristics of a sample substance by measuring the temperature difference between the reference substance and the sample while heating them simultaneously at a constant rate. .
[0035]
As a result of analyzing the phase change from the amorphous silicon film (film thickness 500 nm) to the polysilicon film by using the differential thermal analysis method, the applicant of the present invention has a phase at 686.7 ° C. as indicated by the arrow in FIG. It was confirmed that it would change. However, the results of FIG. 9A are data when crystallized without using a catalyst or the like.
[0036]
On the other hand, FIG. 9B shows a state of phase change when nickel is used as a catalyst element for promoting crystallization of an amorphous silicon film as in this embodiment. At this time, the amount of nickel added is 1-2 × 10. ¹⁹ atoms / cm ^Three It is. In that case, it was confirmed that the temperature at which the phase change (crystallization) occurred decreased to 605.0 ° C.
[0037]
The same experiment was confirmed with other catalyst elements. As a result, it was confirmed that the phase change occurred at around 600 ° C. (550 to 650 ° C.) and crystallization occurred. The reason why the applicant conducts the crystallization process in the temperature range as described above is supported by such data.
[0038]
When the state of FIG. 1B is thus obtained, a furnace annealing treatment (heat treatment using an electric furnace) at 1000 ° C. for 30 minutes is performed in an oxidizing atmosphere. At this time, the thickness of the polysilicon film 104 was reduced by a thermal oxidation process (thinning process), and a polysilicon film 105 having a thickness smaller than that of the polysilicon film 104 was formed. (Figure 1 (C))
[0039]
Although not shown in FIG. 1C, a thermal oxide film is formed on the polysilicon film 105. This thermal oxide film may be removed or used as a protective film in the next laser annealing step.
[0040]
In this thermal oxidation process, defects in the polysilicon film were repaired by surplus silicon atoms generated when the oxidation reaction progressed, and a polysilicon film having very few defects could be obtained. In addition, by reducing the thickness of the polysilicon film, the initial thickness of 90 nm was changed to 60 nm.
[0041]
Furthermore, since the oxidation reaction proceeds while scraping the surface layer of the polysilicon film, the formed polysilicon film 105 is a semiconductor film having a very flat surface. This will work effectively in reducing the level of the TFT active layer / gate insulating film interface in the future.
[0042]
If this thinning process is performed a plurality of times, the flatness of the polysilicon film is further improved. In that case, the thermal oxidation process and the thermal oxide film removal process are repeated alternately.
[0043]
In addition, since the present embodiment uses an amorphous silicon film having a thickness of 90 nm as an initial film, a thinning process is employed. However, if the initial film has a thickness of 50 nm or less and does not need to be further thinned, the thinning process is omitted. It is also possible to do.
[0044]
When the state of FIG. 1C is obtained in this way, the excimer laser beam is then irradiated to the polysilicon film 105. In this embodiment, laser annealing treatment was performed with a pulsed excimer laser beam using XeCl (wavelength 308 nm) as an excitation gas. The beam shape of the excimer laser may be a linear beam, but a planar beam may be used to improve processing uniformity. (Figure 1 (D))
[0045]
In addition, you may use the excimer laser beam which used KrF, KrCl, ArF etc. as excitation gas, and another ultraviolet light laser. When infrared light is used, the polysilicon film 105 may be irradiated with strong light emitted from an infrared lamp.
[0046]
In this example, a linear laser beam having an oscillation frequency of 30 Hz and a beam shape of 145 × 0.41 mm was used. The laser beam was scanned from one end to the other end of the substrate at 1.2 mm / sec, and the overlap of adjacent linear laser beams was set to 92%.
[0047]
In this embodiment, the laser energy density is 250 to 5000 mJ / cm. ² (Preferably 450 to 1000 mJ / cm ² ) Is preferably performed. In this embodiment, the laser energy density is 550 mJ / cm. ² It was. Here, the measuring method of the laser energy density in this specification is demonstrated.
[0048]
First, the light intensity of the laser light oscillated from the laser oscillator (E ₀ ) Is measured with a power meter. However, the laser beam after passing through the power meter is attenuated according to the transmittance (a) of the attenuator and further attenuated according to the transmittance (b) of the optical system. The laser energy density (E) is obtained by dividing the light intensity of the laser light thus attenuated by the laser irradiation area (A). This can be expressed as an equation: E = (E ₀ × a × b) / A.
[0049]
Next, a furnace annealing process at 1000 ° C. for 2 hours was performed on the polysilicon film 106 obtained by performing this laser annealing process. In this embodiment, the treatment atmosphere is a hydrogen atmosphere, but there is no problem if it is a reducing atmosphere. Moreover, the objective of improving crystallinity is achieved even in an inert atmosphere such as a nitrogen atmosphere. (Figure 1 (E))
[0050]
Note that it is desirable to clean the surface of the polysilicon film 106 with a hydrofluoric acid-based etchant before performing this furnace annealing step. That is, it is effective to remove the natural oxide film and to terminate the silicon atoms on the surface with hydrogen to prevent the natural oxide film from being formed before the actual processing.
[0051]
However, it is particularly necessary to keep the concentration of oxygen or oxygen compounds (for example, OH groups) in the atmosphere at 10 ppm or less (preferably 1 ppm or less). Otherwise, the flattening effect due to heat treatment in a reducing atmosphere is weakened.
[0052]
A polysilicon film 107 was thus obtained. The polysilicon film 107 had a very flat surface by hydrogen annealing at a high temperature of 1000 ° C. Further, since annealing was performed at a high temperature, there were almost no stacking faults in the crystal grains.
[0053]
Moreover, as a result of observing the polysilicon film obtained by the applicant in the process of this example by the Raman measurement method, the Raman peak value is 517 to 520 cm. ^-1 (Typically 518-519cm ^-1 )Met. The half width at half maximum is 2.2 to 3.0 cm. ^-1 (Typically 2.4-2.6cm ^-1 )Met.
[0054]
518-519cm ^-1 The Raman peak value is on the very high wavenumber side, and it can be seen that the polysilicon film obtained in this example has a crystal very close to a single crystal. Also, 2.4-2.6cm ^-1 (The single-crystal silicon film measured as a reference is 2.1 cm.) ^-1 Met. ), That is, the crystallinity is high.
[0055]
In this specification, the Raman peak value is a wavelength of 514.5 cm. ^-1 1.0 × 10 Ar laser ^Five ~ 1.3 × 10 ^Five W / cm ² This is a peak value obtained when fitting by a Lorentz distribution to a Raman spectrum obtained when a semiconductor film containing crystals with a light intensity of (a polysilicon film in this embodiment) is irradiated. In the actual measurement, a Raman measuring device called “Ramascope Microscopic Raman System 2000” manufactured by Renishaw was used.
[0056]
The half width at half maximum is a wavelength of 514.5 cm. ^-1 1.0 × 10 Ar laser ^Five ~ 1.3 × 10 ^Five W / cm ² This is a half value of the half-value width obtained when fitting by the Lorentz distribution to the Raman spectrum obtained when the semiconductor film containing crystals is irradiated with the light intensity of. This was also measured with the aforementioned Raman measuring device.
[0057]
Although the Raman peak value and the half width at half maximum defined as described above, the polysilicon film 107 of this embodiment has a ratio between the Raman peak value and the half width at half maximum (Raman peak value / half width at half maximum) of 170 to 240 (typically 190-220).
[0058]
When the polysilicon film 107 having extremely high crystallinity was thus obtained, the polysilicon film 107 was patterned to form the active layer 108. In this embodiment, the heat treatment is performed in a hydrogen atmosphere before forming the active layer, but it can also be performed after forming the active layer. In that case, it is preferable because the stress generated in the polysilicon film is relieved by being patterned.
[0059]
A thermal oxidation process was then performed to form a 10 nm thick silicon oxide film 109 on the surface of the active layer 108. This silicon oxide film 109 functions as a gate insulating film. Further, the active layer 108 is reduced in thickness by 5 nm by this oxidation, so that the film thickness becomes 45 nm. The film thickness of the initial semiconductor film (the first semiconductor film formed) is determined in consideration of film reduction due to thermal oxidation so that an active layer (especially a channel formation region) having a thickness of 10 to 50 nm remains finally. It is necessary to keep it.
[0060]
After the gate insulating film 109 was formed, a conductive polysilicon film was formed thereon, and the gate wiring 110 was formed by patterning. (Fig. 2 (A))
[0061]
In this embodiment, polysilicon having N-type conductivity is used as the gate wiring, but the material is not limited to this. In particular, it is effective to use a tantalum, a tantalum alloy, or a laminated film of tantalum and tantalum nitride to lower the resistance of the gate wiring. Furthermore, if a low resistance gate wiring is aimed, it is effective to use copper or a copper alloy.
[0062]
When the state of FIG. 2A is obtained, an impurity region 111 is formed by adding an impurity imparting N-type conductivity or P-type conductivity. The impurity concentration at this time was determined in view of the impurity concentration of the LDD region later. In this embodiment, 1 × 10 ¹⁸ atoms / cm ^Three Although arsenic was added at a concentration of 5%, the impurity and concentration need not be limited to this embodiment.
[0063]
Next, a thin silicon oxide film 112 having a thickness of about 5 to 10 nm was formed on the surface of the gate wiring 110. This may be formed using a thermal oxidation method or a plasma oxidation method. This silicon oxide film 112 functions as an etching stopper in the next side wall forming step.
[0064]
After the silicon oxide film 112 serving as an etching stopper was formed, a silicon nitride film was formed and etched back to form sidewalls 113. In this way, the state of FIG.
[0065]
In this embodiment, a silicon nitride film is used as the sidewall, but a polysilicon film or an amorphous silicon film can also be used. Of course, if the material of the gate wiring changes, it goes without saying that the material that can be used as the sidewall also changes accordingly.
[0066]
Next, an impurity having the same conductivity type as before was added again. The impurity concentration added at this time was higher than that in the previous step. In this embodiment, arsenic is used as an impurity, and the concentration is 1 × 10. ^{twenty one} atoms / cm ^Three However, it is not necessary to limit to this. A source region 114, a drain region 115, an LDD region 116, and a channel formation region 117 are defined by this impurity addition step. (Fig. 2 (C))
[0067]
After each impurity region was formed in this way, the impurity was activated by heat treatment such as furnace annealing, laser annealing or lamp annealing.
[0068]
Next, the silicon oxide film formed on the surfaces of the gate wiring 110, the source region 114, and the drain region 115 was removed to expose the surfaces. Then, a cobalt film (not shown) of about 5 nm was formed and a heat treatment process was performed. By this heat treatment, a reaction between cobalt and silicon occurred, and a silicide layer (cobalt silicide layer) 118 was formed. (Fig. 2 (D))
[0069]
This technique is a known salicide technique. Therefore, titanium or tungsten may be used in place of cobalt, and known conditions may be referred to for annealing conditions. In this embodiment, infrared annealing was performed to perform a lamp annealing process.
[0070]
When the silicide layer 118 was thus formed, the cobalt film was removed. Thereafter, an interlayer insulating film 119 having a thickness of 1 μm was formed. As the interlayer insulating film 119, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a resin film (polyimide, acrylic, polyamide, polyimide amide, benzocyclobutene (BCB), or the like) may be used. Further, these insulating films may be stacked in any combination.
[0071]
Next, contact holes were formed in the interlayer insulating film 119 to form source wirings 120 and drain wirings 121 made of a material mainly composed of aluminum. Finally, the furnace was annealed at 300 ° C. for 2 hours in a hydrogen atmosphere to complete the hydrogenation.
[0072]
In this way, a TFT as shown in FIG. 2D was obtained. Note that the structure described in this embodiment is merely an example, and the TFT structure to which the present invention can be applied is not limited thereto. Therefore, the present invention can be applied to any known TFT structure. Also, the numerical conditions in the steps after the formation of the polysilicon film 107 need not be limited to this embodiment. Furthermore, there is no problem even if a known channel doping process (impurity addition process for controlling the threshold voltage) is introduced somewhere in this embodiment.
[0073]
In this embodiment, since the concentration of impurities such as C, N, and O is thoroughly managed at the stage of forming an amorphous silicon film as an initial film, each impurity contained in the active layer of the completed TFT Concentration of carbon and nitrogen is 5 × 10 ¹⁸ atoms / cm ^Three The following (preferably 5 × 10 ¹⁸ atoms / cm ^Three Below), oxygen concentration is 5 × 10 ¹⁸ atoms / cm ^Three The following (preferably 5 × 10 ¹⁸ atoms / cm ^Three The following): In addition, metal elements excluding nickel are 1 × 10 ¹⁷ atoms / cm ^Three It was the following.
[0074]
It goes without saying that the present invention can be easily applied not only to the top gate structure but also to a bottom gate structure typified by an inverted staggered TFT.
[0075]
In this embodiment, an N-channel TFT has been described as an example. However, a P-channel TFT can be easily manufactured by combining with a known technique. Further, if a known technique is combined, it is possible to form an N-channel TFT and a P-channel TFT on the same substrate and complementarily combine them to form a CMOS circuit.
[0076]
Further, if a pixel electrode (not shown) electrically connected to the drain wiring 121 in the structure of FIG. 2D is formed by a known means, it is easy to form a pixel switching element of an active matrix display device. is there. That is, the present invention can also be implemented when manufacturing an active matrix type electro-optical device such as a liquid crystal display device or an EL (electroluminescence) display device.
[0077]
(Example 2)
In this embodiment, an example in which the initial film formed first on the substrate is a polysilicon film will be described with reference to FIG.
[0078]
First, a base film 302 made of a silicon oxide film, a 75 nm thick polysilicon film 303, and a protective film 304 are successively laminated on a metal substrate (in this embodiment, a tantalum substrate) 301 without being exposed to the atmosphere. In this embodiment, film formation is performed by a multi-chamber reduced pressure thermal CVD apparatus having a vacuum load lock and a common chamber. (Fig. 3 (A))
[0079]
Next, a thermal oxidation process at 1050 ° C. for 30 minutes is performed. In this embodiment, a wet oxidation method containing water vapor was used to perform heat treatment while relaxing the stress. The thickness of the polysilicon film 305 that has undergone this step is reduced to 50 nm by being oxidized. Further, the thickness of the protective film 306 increases by the amount of the formed thermal oxide film. (Fig. 3 (B))
[0080]
Of course, this thermal oxidation process is performed as a thinning process for further thinning the polysilicon film. Further, if this thinning process is performed a plurality of times, the flatness of the polysilicon film is further improved. In that case, the thermal oxidation process and the thermal oxide film removal process may be repeated alternately.
[0081]
Next, a laser annealing process is performed with KrF excimer laser light while the protective film 306 is left. As the laser irradiation conditions in this example, linear laser light having an oscillation frequency of 30 Hz and a beam shape of 145 × 0.41 mm was used. The laser beam was scanned from one end to the other end of the substrate at 1.2 mm / sec, and the overlap of adjacent linear laser beams was set to 92%.
[0082]
In this embodiment, the laser energy density is 450 to 5000 mJ / cm. ² (Preferably 500 to 1000 mJ / cm ² ) In this embodiment, 600 mJ / cm ² And The method for measuring the laser energy density is the same as in Example 1. A polysilicon film 307 is thus formed. (Figure 3 (C))
[0083]
After the laser annealing step is completed in this way, a furnace annealing process is performed at 1100 ° C. for 2 hours in a nitrogen atmosphere to improve the crystallinity of the polysilicon film 307. By this step, a polysilicon film 308 is obtained. The polysilicon film 308 thus obtained has a specific orientation over the entire film surface, and becomes a semiconductor film that can be regarded substantially as a single crystal.
[0084]
Since the polysilicon film 308 formed as described above is processed without touching the outside air in all steps from FIG. 3A to FIG. 3D, it has an extremely clean interface. Yes. This is the effect of two configurations in this embodiment: (1) the process of FIG. 3 (A) is performed by continuous film formation without opening to the atmosphere, and (2) all processing is performed through the protective film.
[0085]
In addition, the Raman peak value and the half width at half maximum are within the range described in the first embodiment.
[0086]
In this embodiment, a polysilicon film is used as the initial film (the first semiconductor film to be formed). However, a microcrystalline silicon film or an amorphous silicon film can be used for laser crystallization through a protective film. It is. Of course, a semiconductor material other than silicon may be used.
[0087]
After the polysilicon film 308 is obtained in this way, the TFT may be manufactured by the same procedure as in the first embodiment. Of course, not only the first embodiment, but also TFTs are made by known means.
[0088]
(Example 3)
In this embodiment, an example in which crystallization of an amorphous silicon film as an initial film is performed by the technique described in Japanese Patent Laid-Open No. 8-78329 will be described with reference to FIG.
[0089]
First, a quartz substrate 401 provided with an insulating film on the surface is prepared, and an amorphous silicon film (not shown) and a silicon oxide film (not shown) are continuously stacked thereon without being exposed to the atmosphere. Next, the silicon oxide film is patterned to form a mask 402 having an opening.
[0090]
Next, a solution containing nickel of 100 ppm in terms of weight is applied by a spin coating method to obtain a state where the amorphous silicon film and nickel are in contact with each other at the bottom of the opening. Thereafter, a furnace annealing step at 570 ° C. for 14 hours is performed to obtain a lateral growth region 403.
[0091]
In the lateral growth region 403, since rod-like crystals are grown in a direction substantially parallel to the substrate, the number of defects and trap levels is smaller than that of a randomly nucleated polysilicon film.
[0092]
Further, in the state of FIG. 4A, a semiconductor film in which a region remaining as an amorphous component and a lateral growth region (region having a crystal component) are mixed is obtained. In this specification, such a film is also referred to as a semiconductor film (or a semiconductor film including a crystal).
[0093]
When the state of FIG. 4A is obtained in this way, phosphorus is added by the plasma doping method or the ion implantation method using the mask 402 as it is. The amount of phosphorus added is 1 × 10 in terms of SIMS in the silicon film. ¹⁹ ~ 1x10 ^{twenty one} atoms / cm ^Three Adjust so that
[0094]
In this specification, a region to which phosphorus is added at a high concentration is called a gettering region 404 in this specification. (Fig. 4 (B))
[0095]
After the gettering region 404 is formed, a furnace annealing process is performed at 600 ° C. for 12 hours to getter the nickel present in the lateral growth region 403 into the gettering region 404. Thus, the nickel concentration in the film is 1 × 10 ¹⁷ atoms / cm ^Three In the following, a lateral growth region 405 reduced by m is obtained. (Fig. 4 (C))
[0096]
Next, patterning is performed to obtain an island-shaped semiconductor film 406 formed only by the lateral growth region 405. At this time, since the gettering region contains phosphorus and nickel in high concentration, it is desirable to completely remove the gettering region.
[0097]
In this way, the state of FIG. Next, a furnace annealing process is performed in an oxygen atmosphere at 1000 ° C. for 30 minutes, and a thermal oxidation process (thinning process) is performed. The thermal oxide film (not shown) formed at this time may be removed here or left until the next laser annealing process is performed. (Fig. 4 (E))
[0098]
After the island-like semiconductor film 407 having a reduced thickness is obtained by the thinning process, laser annealing is performed using XeCl excimer laser light. The laser irradiation conditions in this example are the same as those in Example 1. (Fig. 4 (F))
[0099]
After obtaining the island-like semiconductor film 408 that has undergone the laser annealing process in this way, a furnace annealing process is further performed at 1100 ° C. for 2 hours in an atmosphere in which hydrogen and nitrogen are mixed. In this way, an island-shaped semiconductor film 409 is obtained. (Fig. 4 (G))
[0100]
The island-shaped semiconductor film 409 formed as described above has the same crystallinity as the polysilicon film described in the first and second embodiments. That is, the entire film surface shows a specific orientation and is a semiconductor film that can be regarded as a substantially single crystal.
[0101]
In addition, the Raman peak value and half width at half maximum obtained by Raman measurement are the same as those described in the first embodiment.
[0102]
(Example 4)
In Example 1 or Example 3, a catalyst element (specifically, nickel) that promotes crystallization is used in crystallization of the initial film, but a polysilicon film crystallized by generation of natural nuclei (also crystal A sufficient effect can be obtained even if the process of the present invention is applied to the semiconductor film including the semiconductor film.
[0103]
In that case, the base film, the amorphous silicon film, and the protective film are continuously laminated without being exposed to the atmosphere, and the amorphous silicon film is crystallized into a polysilicon film by furnace annealing at 600 ° C. for 24 hours to clean the interface. A simple polysilicon film can also be obtained.
[0104]
However, when the semiconductor film is crystallized by generation of natural nuclei as in this embodiment, it is desirable to have a film thickness of 80 to 120 nm (typically 90 to 100 nm). That is, it is empirically known that the crystallization efficiency is reduced when the initial film is thin from the beginning.
[0105]
In such a case, after the crystallization is completed, it is important to perform an thinning (reducing the film thickness) of the semiconductor film including the crystal by including an oxidation step. By doing so, crystallization is efficiently performed, and thereafter a polysilicon film having a desired film thickness can be obtained.
[0106]
The configuration of this embodiment can be combined with either the configuration of Embodiment 1 or Embodiment 3.
[0107]
(Example 5)
In this embodiment, an example of a reflective liquid crystal display device manufactured according to the present invention is shown in FIG. Since a known method may be used for a manufacturing method of a pixel TFT (pixel switching element) and a cell assembly process, detailed description thereof is omitted.
[0108]
In FIG. 5A, 11 is a substrate having an insulating surface (ceramic substrate provided with a silicon oxide film), 12 is a pixel matrix circuit, 13 is a source driver circuit, 14 is a gate driver circuit, 15 is a counter substrate, and 16 is an FPC. (Flexible printed circuit), 17 is a signal processing circuit. As the signal processing circuit 17, it is possible to form a circuit that performs processing such as a D / A converter, a γ correction circuit, a signal division circuit, or the like that has been substituted for a conventional IC. Of course, it is also possible to provide an IC chip on the substrate and perform signal processing on the IC chip.
[0109]
Further, in this embodiment, the liquid crystal display device is described as an example, but the present invention is applied to an EL (electroluminescence) display device and an EC (electrochromic) display device as long as it is an active matrix display device. It goes without saying that it is also possible to do.
[0110]
Here, FIG. 5B shows an example of a circuit constituting the driver circuits 13 and 14 in FIG. Since the TFT portion has already been described in Embodiment 1, only necessary portions will be described here.
[0111]
In FIG. 5B, reference numerals 501 and 502 denote N-channel TFTs, and 503 denotes a P-channel TFT. The TFTs 501 and 503 constitute a CMOS circuit. Reference numeral 504 denotes an insulating layer formed of a laminated film of silicon nitride film / silicon oxide film / resin film, and a titanium wiring 505 is provided on the insulating layer, and the above-described CMOS circuit and the TFT 502 are electrically connected. The titanium wiring is further covered with an insulating layer 506 made of a resin film. The two insulating layers 504 and 506 also have a function as a planarizing film.
[0112]
FIG. 5C illustrates part of a circuit included in the pixel matrix circuit 12 in FIG. In FIG. 5C, reference numeral 507 denotes a pixel TFT formed of an N-channel TFT having a double gate structure, and a drain wiring 508 is formed so as to spread widely in the pixel region. In addition to the double gate structure, a single gate structure or a triple gate structure may be employed.
[0113]
An insulating layer 504 is provided thereon, and a titanium wiring 405 is provided thereon. At this time, a recess is dropped into a part of the insulating layer 504, and only the lowermost silicon nitride and silicon oxide are left. As a result, an auxiliary capacitance is formed between the drain wiring 508 and the titanium wiring 505.
[0114]
The titanium wiring 505 provided in the pixel matrix circuit provides an electric field shielding effect between the source / drain wiring and the subsequent pixel electrode. Further, it functions as a black mask in the gaps between a plurality of pixel electrodes.
[0115]
An insulating layer 506 is provided to cover the titanium wiring 505, and a pixel electrode 509 made of a reflective conductive film is formed thereon. Of course, the surface of the pixel electrode 509 may be devised to increase the reflectance.
[0116]
In addition, an alignment film and a liquid crystal layer are actually provided on the pixel electrode 509, but description thereof is omitted here.
[0117]
A reflection type liquid crystal display device having the above-described configuration can be manufactured using the present invention. Needless to say, a transmission type liquid crystal display device can be easily manufactured by combining with a known technique.
[0118]
Although not distinguished in the drawings, the film thickness of the gate insulating film can be different between the pixel TFT constituting the pixel matrix circuit and the CMOS circuit constituting the driver circuit and the signal processing circuit.
[0119]
In the pixel matrix circuit, since the driving voltage applied to the TFT is high (10 V or more), a gate insulating film having a thickness of 50 to 200 nm (preferably 100 to 150 nm) is required. On the other hand, in the driver circuit and the signal processing circuit, the driving voltage applied to the TFT is low (1 to 5 V), and conversely, high speed operation is required. Therefore, the thickness of the gate insulating film is 3 to 30 nm (preferably 5 to 10 nm). It is effective to make it thinner than the pixel TFT.
[0120]
(Example 6)
The present invention can be applied to all conventional IC technologies. That is, it can be applied to all semiconductor circuits currently on the market. For example, the present invention may be applied to a microprocessor such as a RISC processor or an ASIC processor integrated on one chip, and is represented by a liquid crystal driver circuit (D / A converter, γ correction circuit, signal dividing circuit, etc.). The present invention may be applied to a signal processing circuit and a high-frequency circuit for a portable device (mobile phone, PHS, mobile computer).
[0121]
FIG. 6 shows an example of a microprocessor. The microprocessor typically includes a CPU core 21, a RAM 22, a clock controller 23, a cache memory 24, a cache controller 25, a serial interface 26, an I / O port 27, and the like.
[0122]
Needless to say, the microprocessor illustrated in FIG. 6 is a simplified example, and various circuit designs are performed on an actual microprocessor depending on its application.
[0123]
However, it is an IC (Integrated Circuit) 28 that functions as the center of a microprocessor having any function. The IC 28 is a functional circuit in which an integrated circuit formed on the semiconductor chip 29 is protected with ceramic or the like.
[0124]
The N-channel TFT 30 and the P-channel TFT 31 having the structure of the present invention constitute an integrated circuit formed on the semiconductor chip 29. Note that power consumption can be suppressed by configuring a basic circuit with a CMOS circuit as a minimum unit.
[0125]
The microprocessor shown in this embodiment is mounted on various electronic devices and functions as a central circuit. Typical electronic devices include personal computers, portable information terminal devices, and all other home appliances. Further, a computer for controlling a vehicle (such as an automobile or a train) may be used.
[0126]
(Example 7)
The electro-optical device of the present invention is used as a display of various electronic devices. Such electronic devices include video cameras, digital cameras, front projectors, rear projectors (projection TVs), goggle displays, car navigation systems, personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.), etc. Is mentioned. An example of them is shown in FIG.
[0127]
FIG. 7A illustrates a mobile phone, which includes a main body 2001, an audio output unit 2002, an audio input unit 2003, a display device 2004, operation switches 2005, and an antenna 2006. The present invention can be applied to the audio output unit 2002, the audio input unit 2003, the display device 2004, and other signal control circuits.
[0128]
FIG. 7B illustrates a video camera, which includes a main body 2101, a display device 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 2106. The present invention can be applied to the display device 2102, the voice input unit 2103, and other signal control circuits.
[0129]
FIG. 7C illustrates a mobile computer, which includes a main body 2201, a camera unit 2202, an image receiving unit 2203, operation switches 2204, and a display device 2205. The present invention can be applied to the display device 2205 and other signal control circuits.
[0130]
FIG. 7D illustrates a goggle type display which includes a main body 2301, a display device 2302, and an arm portion 2303. The present invention can be applied to the display device 2302 and other signal control circuits.
[0131]
FIG. 7E illustrates a rear projector, which includes a main body 2401, a light source 2402, a display device 2403, a polarizing beam splitter 2404, reflectors 2405 and 2406, and a screen 2407. The present invention can be applied to the display device 2403 and other signal control circuits.
[0132]
FIG. 7F illustrates a portable book (electronic book) which includes a main body 2501, display devices 2502 and 2503, a storage medium 2504, operation switches 2505, and an antenna 2506. The present invention can be applied to the display devices 2502 and 2503 and other signal control circuits.
[0133]
As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields.
[0134]
(Example 8)
The semiconductor film containing crystals obtained by the steps shown in Examples 1 to 4 exhibits specific orientation over the entire film surface. That is, even if it is in the form of a polycrystalline semiconductor film formed by aggregating individual crystal grains, 80% or more (typically 90% or more) of the entire crystal grains have the same crystal plane (orientation). Surface). A crystal plane that occupies 80% or more of the whole is called a main orientation plane.
[0135]
The main crystal planes that can be taken by the semiconductor film (semiconductor film containing crystals) formed by the process of the present invention are {110} plane, {100} plane, {111} plane, {311} plane, {511} plane, Or, it is one of crystal faces in which {110} face and {100} face are mixed. At present, it is not clear which crystal plane is the main orientation plane.
[0136]
That is, in the semiconductor film (semiconductor film containing crystals) formed by the process of the present invention, any of the above six types of crystal planes is 80% or more (typically 90% or more).
[0137]
As is well known as an example of single crystal silicon, the interface physical properties differ depending on the crystal plane. The plane orientation with the lowest interface state density (Qss) is the {100} plane, followed by the {511} plane, {311} plane, {111} plane, {110} plane, and {100} plane. The size increases in the order of crystal plane and {110} plane. It is known that the {511} plane has an interface state density comparable to the {100} plane.
[0138]
Therefore, if the main orientation plane of the semiconductor film formed by the process of the present invention is the {100} plane, the interface state density at the interface between the active layer and the gate insulating film becomes very small. In that case, a semiconductor device having performance comparable to that of a conventional IC can be realized. As will be described later, a TFT actually fabricated using the present invention can form a circuit having electrical characteristics comparable to a conventional IC.
[0139]
In addition, the furnace annealing treatment in a reducing atmosphere or an inert atmosphere performed after the laser annealing treatment in the process of the present invention is very effective for making the interface between the active layer and the gate insulating film flat. In particular, when performed in a reducing atmosphere, an extremely flat surface can be obtained by accelerated surface diffusion of semiconductor atoms on the surface of the semiconductor film.
[0140]
As a result of measuring the surface irregularities by using the AFM (Intermolecular Force Microscope) by the applicant, 1 μm ² The PV value of the concavo-convex (the difference in height between the top of the convex part and the bottom of the concave part) is 10 nm or less (typically 5 nm or less), and 10 μm ² Within the range, the PV value of the unevenness was 20 nm or less (typically 10 nm or less).
[0141]
Example 9
Typical electrical characteristics of TFTs produced by carrying out the present invention were as follows.
(1) When the drain voltage is 1V, the sub-threshold coefficient, which is an index of switching performance (ON / OFF operation switching agility), is 60 to 150 mV / decade for both N-channel and P-channel TFTs (typically 80-100 mV / decade) and small.
(2) Field-effect mobility (μFE), which is an index of TFT operating speed, is 200 to 500 cm for an N-channel TFT when the drain voltage is 1V. ² / Vs (typically 300-400cm ² / Vs), 100-300cm with P-channel TFT ² / Vs (typically 150-200cm ² / Vs).
(3) When the drain voltage is 14V, the threshold voltage (Vth), which is an indicator of TFT drive voltage, is -1.0 to 2.5V (typically -0.5 to 1.5V), P-channel for N-channel TFT The type TFT is as small as -2.5 to 1.0 V (typically -1.5 to 0.5 V).
[0142]
In addition, a normal probability graph was created based on data obtained by measuring 500 TFTs of the present invention, and characteristic variations were estimated using the graph. As a result, it was found that 90 out of 100 (typically 95) were within the range of the electrical characteristics.
[0143]
As described above, it has been confirmed that extremely excellent switching characteristics and high-speed operation characteristics can be realized.
[0144]
(Example 10)
In this embodiment, a shift register, which is a liquid crystal driver circuit, was manufactured and the operating frequency was confirmed. As a result, an output pulse with an operating frequency of 80 to 200 MHz (typically 100 to 150 MHz) was obtained in a shift register circuit having a power supply voltage of 5 V and 50 stages.
[0145]
Example 11
Although Example 1 shows an example in which nickel is used as a catalyst element for promoting crystallization in crystallization of an amorphous silicon film, FIG. 8 shows an example in which germanium is used as a catalyst element in this example.
[0146]
First, an amorphous silicon film 802 having a thickness of 80 nm is formed on a quartz substrate 801 according to the steps of the first embodiment. Then, germanium is added to the amorphous silicon film 802. (Fig. 8 (A))
[0147]
For the addition of germanium, an ion implantation method, a plasma doping method, or a laser doping method is preferably used.
[0148]
Alternatively, a method of thermally diffusing after forming a germanium film may be adopted, or as in Example 1, a germanium salt solution is spin-coated and germanium is adsorbed on amorphous silicon and then thermally diffused. A method may be adopted. Alternatively, it may be added in advance when the amorphous silicon film is formed.
[0149]
In this embodiment, germane (GeH4) is used as the excitation gas, the acceleration voltage is 30 keV, the RF power is 5 W, and the dose is 1 × 10. ¹⁴ atoms / cm ² Add germanium using the ion implantation method. Of course, it is not necessary to limit to this condition, and the amorphous silicon film 802 is 1 × 10 ¹⁴ ~ 5x10 ¹⁹ atoms / cm ^Three (Typically 1 x 10 ¹⁶ ~ 5x10 ¹⁸ atoms / cm ^Three ) To adjust so that germanium is added.
[0150]
The germanium added to the amorphous silicon film is 1 × 10. ¹⁴ atoms / cm ^Three Above (typically 1 × 10 ¹⁶ atoms / cm ^Three Otherwise, the crystallization promoting effect cannot be utilized as a catalyst. Addition is 5 × 10 ¹⁹ atoms / cm ^Three If it exceeds 1, the melting point of the amorphous silicon film is too low, and it may be melted even at a temperature of about 900 ° C., which is not preferable. Therefore, the upper limit of the amount added is 1 × 10 for safety reasons. ¹⁸ atoms / cm ^Three It is desirable to keep the degree.
[0151]
Next, heat treatment (furnace annealing) is performed at 550 ° C. for 1 hour to change the amorphous silicon film 802 to the polysilicon film 803. Of course, it is not necessary to limit to this condition, and heat treatment in the temperature range as shown in Embodiment 1 may be performed. (Fig. 8 (B))
[0152]
In the case of this embodiment, it is desirable that the processing atmosphere is an inert atmosphere or a reducing atmosphere. The reason for this will be described later.
[0153]
When the crystallization process of the amorphous silicon film is thus completed, a thinning process (thermal oxidation process) of the polysilicon film 803 is performed according to the first embodiment. Although a thermal oxide film is actually formed, it is not shown here. In this way, a polysilicon film 804 having undergone a thinning process is obtained. (Fig. 8 (C))
[0154]
At this time, there is a remarkable feature when germanium is used as a catalyst element. Germanium is sublimated as germanium oxide by heat treatment at 700 ° C. or higher. That is, when the thinning process of the polysilicon film 803 is performed, germanium is inevitably sublimated and detached from the polysilicon film 803.
[0155]
That is, the reason why the crystallization process is desirably an inert atmosphere or a reducing atmosphere as described above is none other than the fact that germanium oxide can be used as efficiently as possible without forming germanium oxide as much as possible. .
[0156]
As described in Example 1, when the catalytic element is used, it has been confirmed that the temperature at which the amorphous silicon film crystallizes is around 600 ° C. Actually, it varies somewhat depending on the treatment temperature, so 550 to 650 ° C. may be considered as the temperature required for crystallization. That is, if the temperature at the time of crystallization is increased only to 650 ° C., it is almost impossible that germanium will be sublimated at the time of crystallization.
[0157]
Thus, in Example 3, since nickel is used as a catalyst element for promoting crystallization, an example in which gettering is performed using phosphorus is shown. An effect equivalent to the gettering step can be obtained.
[0158]
For this heat treatment, any one of furnace annealing, laser annealing, and lamp annealing may be used. Further, it is possible to continuously sublimate germanium without changing to the atmosphere only by changing the heat treatment temperature after the crystallization step.
[0159]
Further, a halogen element may be added to the heat treatment atmosphere. Since the halogen element combines with germanium to form volatile germanium halide, the gettering effect can be promoted.
[0160]
As described above, simultaneously with the thinning process, the catalyst element (germanium) used for crystallization of the amorphous silicon film can be removed from the polysilicon film without increasing the number of processes.
[0161]
Thereafter, a TFT as shown in FIG. 2D may be formed according to the same process as in the first embodiment. Of course, it is possible to combine with the configurations of the second embodiment and the third embodiment, and this embodiment may be used when manufacturing the semiconductor devices shown in the fifth to seventh embodiments.
[0162]
In this embodiment, germanium alone is used as a catalyst element for promoting crystallization of an amorphous silicon film, but other catalyst elements (nickel, cobalt, iron, palladium, platinum, copper, gold, lead, tin) are used. Etc.) and germanium may be used simultaneously. In that case, it may be necessary to combine the gettering means as shown in the third embodiment with this embodiment.
[0163]
Example 12
In the eleventh embodiment, the case where an ion implantation method or the like is used as a means for adding germanium to the amorphous silicon film has been described. However, this embodiment shows an example in which a germanium film is formed and then added by thermal diffusion.
[0164]
In this embodiment, when an amorphous silicon film is formed, a germanium film having a thickness of 1 to 50 nm (typically 10 to 20 nm) is formed thereon. As a film formation method, a vapor phase method such as a plasma CVD method, a low pressure thermal CVD method, or a sputtering method can be used.
[0165]
Note that the germanium film may be formed so as to be in direct contact with the amorphous silicon film, or may be provided via an insulating film. When the insulating film is formed, if the insulating film is too thick, thermal diffusion into the silicon film of germanium is hindered.
[0166]
When the crystallization process is performed in a state where the germanium film is provided, germanium is thermally diffused into the amorphous silicon film by being heated, and serves as a catalytic element for promoting crystallization.
[0167]
The germanium film after the crystallization process may be oxidized and removed, or an aqueous sulfuric acid solution (H ₂ SO _Four : H ₂ O ₂ = 1: 1). Thereafter, if heat treatment is performed at 700 ° C. or higher, germanium in the formed polysilicon film is removed or reduced.
[0168]
The configuration of this embodiment can be combined with any of the embodiments 1 to 11, and can be applied to any of the embodiments.
[0169]
(Example 13)
In this embodiment, a case where a spin coating method by solution coating and a thermal diffusion method are used as means for adding germanium into an amorphous silicon film will be described.
[0170]
In the case of this embodiment, when an amorphous silicon film is formed, a solution containing germanium is applied thereon. Such solutions include germanium oxide (GeOx, typically GeO ₂ ), Germanium chloride (GeCl _Four ), Germanium bromide (GeBr) _Four ), Germanium sulfide (GeS) ₂ ), Germanium acetate (Ge (CH _Three CO ₂ )) And other germanium salt aqueous solutions.
[0171]
Moreover, you may use alcohol type solvents, such as ethanol and isopropyl alcohol, as a solvent.
[0172]
In this embodiment, a germanium oxide aqueous solution having a concentration of 10 to 100 ppm is prepared and applied on an amorphous silicon film (may be provided with an insulating film) and spin-coated to form a germanium-containing layer.
[0173]
Note that since the amorphous silicon film exhibits hydrophobicity, it is effective to increase the wettability by forming an insulating film on the surface of the silicon film before spin coating. In this case, if the insulating film is too thick, thermal diffusion of germanium into the silicon film will be hindered.
[0174]
When the crystallization process is performed with the germanium-containing layer thus provided, the germanium is thermally diffused into the amorphous silicon film by being heated and acts as a catalytic element for promoting crystallization.
[0175]
The configuration of this embodiment can be combined with any of the embodiments 1 to 11, and can be applied to any of the embodiments.
[0176]
【The invention's effect】
By practicing the present invention, a semiconductor film having crystallinity that can be regarded as substantially a single crystal can be obtained. Then, it is possible to realize a high-performance semiconductor device by assembling a circuit with TFTs having such a semiconductor film as an active layer.
[Brief description of the drawings]
FIGS. 1A to 1C illustrate a manufacturing process of a thin film transistor. FIGS.
FIGS. 2A and 2B illustrate a manufacturing process of a thin film transistor. FIGS.
FIG. 3 illustrates a manufacturing process of a thin film transistor.
4A and 4B illustrate a manufacturing process of a thin film transistor.
FIG. 5 is a diagram illustrating a configuration of an electro-optical device.
FIG. 6 is a diagram showing a configuration of a semiconductor circuit.
FIG 7 illustrates a structure of an electronic device.
FIG. 8 illustrates a manufacturing process of a thin film transistor.
FIG. 9 is a diagram showing the results of differential thermal analysis.

Claims (7)

Forming a polysilicon film,
The polysilicon film a thermal oxide film is formed on the thermally oxidized to Rutotomoni the polysilicon film reduces the film thickness,
Removing the thermal oxide film;
Laser annealing treatment is performed on the polysilicon film having a reduced thickness at an energy density of 250 to 5000 mJ / cm ² ,
The surface of the polysilicon film after the laser annealing treatment is washed with a hydrofluoric acid etchant,
A method of manufacturing a semiconductor device, comprising performing a furnace annealing treatment at 900 to 1200 ° C. in a reducing atmosphere on the polysilicon film whose surface has been cleaned . Forming a polysilicon film,
The polysilicon film a thermal oxide film is formed on the thermally oxidized to Rutotomoni the polysilicon film reduces the film thickness,
Removing the thermal oxide film;
Laser annealing treatment is performed on the polysilicon film having a reduced thickness at an energy density of 250 to 5000 mJ / cm ² ,
The surface of the polysilicon film after the laser annealing treatment is washed with a hydrofluoric acid etchant,
A furnace annealing treatment at 900 to 1200 ° C. in a reducing atmosphere is performed on the polysilicon film whose surface has been cleaned ,
Patterning the polysilicon film to form a predetermined pattern;
Forming a gate insulating film on the surface of the polysilicon film formed in the predetermined pattern;
Forming a gate wiring on the gate insulating film;
Impurity imparting N-type conductivity or P-type conductivity is added to a region of the polysilicon film formed in the predetermined pattern that is not covered with the gate wiring to form an impurity region,
Forming a sidewall on a side of the gate wiring and part of the impurity region;
An impurity having the same conductivity type as the impurity is added to a region of the impurity region not covered by the sidewall to form a source region and a drain region, and an LDD region is formed in the impurity region below the sidewall. And
Exposing at least the surfaces of the source region and the drain region;
Forming a silicide layer in each of the exposed source region and drain region;
Forming an interlayer insulating film composed of one layer or a stack so as to cover at least the source region, the drain region, the sidewall, and the gate wiring;
A method for manufacturing a semiconductor device, comprising: forming a contact hole exposing the silicide layer in the interlayer insulating film; and forming a source wiring and a drain wiring on the interlayer insulating film and in the contact hole. According to claim 1 or claim 2, and characterized in that nickel in the semiconductor film containing amorphous, was added cobalt, iron, palladium, platinum, copper, or gold, heat treatment to form the polysilicon film A method for manufacturing a semiconductor device. In any one of claims 1 to 3, the method for manufacturing a semiconductor device characterized by reducing the thickness of the polysilicon film by alternately repeating the removal of the thermal oxide film and the thermal oxidation. In any one of claims 1 to 4, wherein the energy density (E) is a laser beam of the light intensity emitted from the laser oscillator (E _0), the transmittance of the attenuator (a), the transmittance of the optical system (B) A method for manufacturing a semiconductor device, which is expressed by E = (E ₀ × a × b) / A using a laser irradiation area (A).   6. The method for manufacturing a semiconductor device according to claim 1, wherein the concentration of oxygen or an oxygen compound is 10 ppm or less in the reducing atmosphere.   7. The semiconductor device according to claim 1, wherein the reducing atmosphere is a hydrogen atmosphere, an ammonia atmosphere, a mixed atmosphere of hydrogen and nitrogen, or a mixed atmosphere of hydrogen and argon. Manufacturing method.

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