JP4493751B2 - Method for manufacturing semiconductor device - Google Patents

Description

[0001]
[Technical field to which the invention belongs]
The present invention relates to a technique related to a semiconductor device using a semiconductor thin film, and more particularly to a semiconductor device constituted by a thin film transistor (TFT) using a crystalline silicon film and a manufacturing method thereof.
[0002]
Note that in this specification, a semiconductor device refers to all devices that function by utilizing semiconductor characteristics. Accordingly, not only a single semiconductor element such as a TFT but also an electro-optical device having a TFT, a semiconductor circuit, and an electronic device on which these are mounted are semiconductor devices.
[0003]
[Prior art]
In recent years, TFTs used in electro-optical devices such as active matrix liquid crystal display devices have been actively developed.
[0004]
An active matrix liquid crystal display device is a monolithic display device in which a pixel matrix circuit and a driver circuit are provided on the same substrate. In addition, development of a system-on-panel in which logic circuits such as a γ correction circuit, a memory circuit, and a clock generation circuit are incorporated is also underway.
[0005]
Since such a driver circuit or logic circuit needs to operate at high speed, it is inappropriate to use an amorphous silicon film (amorphous silicon film) as an active layer. Therefore, TFTs using a crystalline silicon film (single crystal silicon film or polysilicon film) as an active layer are currently under study.
[0006]
The present applicant has disclosed a technique described in Japanese Patent Laid-Open No. 7-130652 as a technique for obtaining a crystalline silicon film on a glass substrate. The technique described in this publication is to obtain a crystalline silicon film by adding a catalytic element for promoting crystallization to an amorphous silicon film and performing a heat treatment.
[0007]
This technology can lower the crystallization temperature of the amorphous silicon film by 50 to 100 ° C. by the action of the catalytic element, and the time required for crystallization can be reduced to 1/5 to 1/10. .
[0008]
[Problems to be solved by the invention]
However, when circuit performance equal to that of conventional LSIs is required for circuits assembled with TFTs, crystalline silicon films formed by conventional techniques have sufficient performance to meet specifications. It has become difficult to manufacture TFTs having the same.
[0009]
It is an object of the present invention to provide a technique for realizing a single crystal semiconductor thin film or a substantially single crystal semiconductor thin film. Note that a substantial single crystal semiconductor thin film refers to a crystalline semiconductor thin film such as a polycrystalline semiconductor thin film in which a portion functioning as a barrier that hinders the movement of carriers such as crystal grain boundaries and defects is eliminated.
[0010]
A high-performance TFT having a single crystal semiconductor thin film or a substantially single crystal semiconductor thin film of the present invention as a channel formation region is realized, and a high-performance semiconductor device having a circuit assembled with the TFT is provided. Let it be an issue.
[0011]
Note that in this specification, semiconductor thin films having crystallinity such as a single crystal semiconductor thin film, a polycrystalline semiconductor thin film, and a microcrystalline semiconductor thin film are collectively referred to as a crystalline semiconductor thin film.
[0012]
[Means for Solving the Problems]
One of the configurations for carrying out the present invention is:
A step of adding a catalyst element for promoting crystallization of the amorphous semiconductor thin film into the amorphous semiconductor thin film, and irradiation of ultraviolet light or infrared light to change the amorphous semiconductor thin film into a crystalline semiconductor thin film And a second heat treatment step of 900 to 1200 ° C. in a reducing atmosphere with respect to the crystalline semiconductor thin film.
[0013]
In the above structure, the second heat treatment may be performed at a temperature at which a natural oxide film (for example, a silicon oxide film) formed on the surface of the crystalline semiconductor thin film is reduced, and specifically 900 to 1200 ° C. (preferably 1000 to 1000 ° C.). 1100 ° C.). The treatment time is preferably at least 3 minutes or longer, 3 minutes to 2 hours, typically 10 minutes to 30 minutes. This is the time required to exhibit the effect of the second heat treatment.
[0014]
Note that the second heat treatment may be performed after the crystalline semiconductor thin film is processed into an island shape. The heat treatment means is a furnace annealing process (annealing process performed in an electric furnace).
[0015]
A feature of the present invention is that a crystalline semiconductor thin film is formed using a crystallization technique (hereinafter referred to as laser crystallization) by irradiation with ultraviolet light or infrared light, and the crystalline semiconductor thin film is 900 to 1200 ° C. The heat treatment is performed in a reducing atmosphere (typically a hydrogen atmosphere).
[0016]
In this case, when ultraviolet light is used as the crystallization technique, excimer laser light or strong light emitted from an ultraviolet lamp may be used, and when infrared light is used, strong light emitted from an infrared laser or an infrared lamp is used. good.
[0017]
As the excimer laser, KrF, XeCl, ArF or the like may be used as an excitation gas. As the infrared laser, Nd: YAG laser, Nd: glass laser, ruby laser, or the like can be used.
[0018]
The beam shape of the laser beam may be processed into a linear shape or may be processed into a planar shape. When processed into a linear shape, it is preferable to use a laser device that scans laser light from one end of the substrate toward the other end.
[0019]
In the case of processing into a planar shape, processing is performed so that an area of about several tens of cm ² (preferably 10 cm ² or more) can be collectively irradiated, and a total energy of 5 J or more, preferably 10 J or more is used. good. In that case, the energy density is set to 100 to 800 mJ / cm ² , and the output pulse width is set to 100 nsec or more, preferably 200 nsec to 1 msec. In order to realize a pulse width of 200 nsec to 1 msec, a plurality of laser devices are connected, and a state in which a plurality of pulses are mixed is created by shifting the synchronization of the laser devices.
[0020]
Note that high-temperature annealing in a reducing atmosphere performed on a crystalline semiconductor thin film after laser crystallization has an effect of first flattening the surface of the crystalline semiconductor thin film. This is a result of accelerated surface diffusion of semiconductor atoms that seeks to minimize surface energy.
[0021]
This flattening effect is very effective when the crystallinity is irradiated with excimer laser ultraviolet light.
[0022]
When the excimer laser is irradiated, the semiconductor film is instantaneously melted from the surface, and the molten semiconductor film is then cooled and solidified from the substrate side for heat conduction to the substrate. In this solidification process, it is recrystallized to become a crystalline semiconductor film with a large grain size. However, once melted, volume expansion occurs, resulting in irregularities (ridges) on the surface of the semiconductor film. In the case of a top gate type TFT, the uneven surface is an interface with the gate insulating film, so that element characteristics are greatly affected.
[0023]
Hereinafter, the effect of the high temperature annealing of the present invention will be described using the results of experiments by the present inventors.
[0024]
First, the experimental procedure will be described. An amorphous silicon film having a thickness of 50 nm was formed on a quartz substrate. For the film formation, a low pressure CVD method was used, and the film formation gas was disilane (Si ₂ H ₆ ) (flow rate 250 sccm) and helium (He) (flow rate 300 sccm). The substrate temperature was 465 ° C., and the pressure during film formation was 0.5 torr.
[0025]
The surface of the amorphous silicon film was etched with buffered hydrofluoric acid to remove the natural oxide film and contaminants. Next, XeCl excimer laser light was irradiated to crystallize the amorphous silicon film. The atmosphere during laser irradiation is air, the substrate temperature is room temperature, the laser energy density is 400 mJ / cm ² , and the pulse width of the laser light is 150 nsec.
[0026]
Then, the crystalline silicon film was subjected to a high temperature annealing treatment. The conditions for the high-temperature annealing treatment were as follows. The atmosphere was 100% hydrogen, the degree of vacuum was 700 torr, the annealing temperature was 1000 ° C., and the annealing time was 25 minutes. Before the high-temperature annealing treatment, the crystalline silicon film was wet-etched with hydrofluoric acid to remove the surface natural oxide film and contaminants.
[0027]
In order to confirm the effect of the high temperature annealing, the surface of the crystalline silicon film before and after the high temperature annealing was observed by SEM. FIG. 11 shows an observation photograph before the high temperature annealing, and FIG. 12 shows an observation photograph after the high temperature annealing. As apparent from FIGS. 11 and 12, the surface shapes are clearly different before and after the high temperature annealing.
[0028]
Furthermore, the surface shape of the silicon film was also observed with an AFM (atomic force microscope). FIG. 13 shows an AFM observation image of the crystalline silicon film before the high temperature annealing, and FIG. 14 shows an AFM observation image of the crystalline silicon film after the high temperature annealing. The observation range is a rectangular area of 1.5 μm × 1.5 μm in both FIG. 13 and FIG.
[0029]
As apparent from FIGS. 13 and 14, the surface shape of the crystalline silicon film is clearly different before and after the high temperature annealing. The crystalline silicon film surface has irregularities before and after high-temperature annealing, but before the high-temperature annealing, the convex portion is steep and the top is sharp, and has a saw-tooth shape as a whole. It is considered that when the surface having such a convex portion becomes the interface between the gate insulating film and the channel formation region, the characteristics of the element are adversely affected. In contrast, since the convex portion after the high temperature annealing is smooth and the top portion is rounded, the interface characteristics of the gate insulating film / channel formation region are improved as compared with those before the high temperature annealing.
[0030]
From the observation images shown in FIGS. 11 to 14, it can be understood that the surface of the crystallized silicon film is flattened and smoothed by high-temperature annealing. In addition, in order to quantify the difference in surface shape before and after high-temperature annealing. A histogram distribution of the height of the AFM image was calculated. Furthermore, a bearing ratio curve of this histogram distribution was calculated. The Bearing Ratio curve is a curve indicating the cumulative frequency of the histogram distribution.
[0031]
FIGS. 15 and 16 show an AFM image height histogram and a bearing ratio curve. FIG. 15 shows data before high-temperature annealing, and the pitch of the histogram is about 0.16 nm. FIG. 16 shows data after high-temperature annealing, and the pitch of the histogram is about 0.20 nm.
[0032]
The measurement area by AFM is 1.5 μm × 1.5 μm. The Bearing Ratio curve is a curve representing the cumulative frequency of histogram data. The curves in FIG. 15 and FIG. 15 are accumulated from the maximum value of the height, and indicate the ratio (%) of the area of the arbitrary height from the maximum value to the total area. 14 and 15, a horizontal line indicated by a dotted line in the graph indicates a value that is ½ of the PV value (Peak to Valley, the difference between the maximum value and the minimum value of the height).
[0033]
Further, in the silicon film before and after the high temperature annealing, AFM images were observed in 10 regions (rectangular regions of 1.5 μm × 1.5 μm), respectively, and Bearing at 2 ⁻¹ (P−V value) in each observation region. Ratio was calculated. FIG. 17 shows the bearing ratio and its statistical data in each observation region.
[0034]
Comparing the curves of FIGS. 15 and 16, the height distribution before the high temperature annealing is biased toward the low side, but after the high temperature annealing, the bias is shifted to the higher side, and the histogram is 1 / V of PV. It is symmetrical with respect to the position of 2. This can be easily understood from the Bearing Ratio curve.
[0035]
The bearing ratio at a height of 2 ⁻¹ (P−V) is about 20% in FIG. 15 and about 51% in FIG. That is, the ratio of the area of the region whose height is in the range from the highest value to 2 ⁻¹ (P−V value) in the total area is about 20% before the high temperature annealing, but after the high temperature annealing. About 51%. From this difference in ratio, it can be understood that the pointed top is rounded and the surface of the silicon film is smoothed by the high temperature annealing.
[0036]
Therefore, in the present invention, the surface shape of the crystalline silicon film is quantified by the Bearing Ratio at 2 ⁻¹ (P−V value), and the Bearing Ratio at 2 ⁻¹ (P−V value), that is, a predetermined observation region is obtained from the experimental results. The ratio of the region whose height is in the range from the maximum value to 2 ⁻¹ (P−V value) is in the range of 6 to 28% in the film before the high temperature annealing, and in the film after the high temperature annealing is 29 to 29%. Estimated 72%.
[0037]
The range of the bearing ratio is set from the statistical data of FIG. 17, and is a value calculated from the average value ± 3σ of the bearing ratio at 2 ⁻¹ (P−V value). The Bearing Ratio is a value accumulated from the maximum height value.
[0038]
As described above, in the present invention, since the surface of a crystalline semiconductor film crystallized by ultraviolet light such as an excimer laser is melted and crystallized, the height is increased from the maximum value to the maximum value for a predetermined region. The ratio of the region in the range of 1/2 of the difference between the minimum value and the minimum value is 6 to 28%. However, by processing this crystalline semiconductor film by high-temperature annealing, the ratio of the region is 29 to 72%. The top of the convex portion on the film surface can be made gentle.
[0039]
The experiment described above is an example in which an amorphous silicon film is irradiated with an excimer laser, but it is considered that a substantially similar surface shape is obtained when the crystalline silicon film of the present invention is irradiated. In the present invention, the Bearing Ratio before the high temperature annealing is considered to be larger than the experimental result, and the Bearing Ratio after the high temperature annealing is predicted to be in the range of 29 to 72%, typically 35 to 60%.
[0040]
At the same time, this step also has the effect of significantly reducing the defects present in the crystal grain boundaries and crystal grains. This is due to the termination effect of dangling bonds by hydrogen, the effect of removing impurities by hydrogen, and the accompanying recombination of semiconductor atoms. Therefore, in order to efficiently exhibit these effects, the processing time as described above is required.
[0041]
Therefore, the heat treatment step in the reducing atmosphere needs to be performed by furnace annealing. When heat treatment is performed by irradiating with ultraviolet light or infrared light, recrystallization proceeds in a non-equilibrium state, so that stress and defects due to stress are generated in the crystal grain boundaries and crystal grains. In this regard, furnace annealing can avoid such a problem because recrystallization proceeds in an equilibrium state.
[0042]
Note that a catalyst element for promoting crystallization of the amorphous semiconductor thin film may be added to the amorphous semiconductor thin film during laser crystallization.
[0043]
In addition, the configuration of other inventions is as follows:
Forming an amorphous semiconductor thin film over a substrate having an insulating surface;
A first heat treatment step of irradiating ultraviolet light or infrared light to change the amorphous semiconductor thin film into a crystalline semiconductor thin film;
Performing a second heat treatment in a reducing atmosphere containing a halogen element on the crystalline semiconductor thin film,
Before the step of forming the amorphous semiconductor thin film, a step of adding a catalytic element for promoting crystallization of the amorphous semiconductor thin film to the substrate having the insulating surface is provided.
[0044]
In this configuration, the second heat treatment is performed at a temperature of 900 to 1200 ° C. This process is aimed at gettering of metal elements by halogen elements, and halogenates metal elements (including catalytic elements that promote crystallization of amorphous semiconductor thin films) present in crystalline semiconductor thin films. It is intended to be removed.
[0045]
DETAILED DESCRIPTION OF THE INVENTION
The embodiment of the present invention having the above-described configuration will be described in detail with the examples described below.
[0046]
【Example】
(Example 1)
First, a quartz substrate was prepared as the substrate 101. As the substrate 101, a material having high heat resistance must be selected. Instead of the quartz substrate, a material having high heat resistance such as a silicon substrate, a ceramic substrate, or a crystallized glass substrate can be used.
[0047]
However, the base film 102 may or may not be provided when a quartz substrate is used, but an insulating film is preferably provided as the base film when other materials are used. As the insulating film, any one of a silicon oxide film (SiOx), a silicon nitride film (Six Ny), a silicon oxynitride film (SiOx Ny), an aluminum nitride film (AlxNy), or a laminated film thereof may be used.
[0048]
In addition, it is effective to use a base film in which a heat-resistant metal layer and a silicon oxide film are laminated, since the heat dissipation effect is greatly enhanced. The heat dissipation effect is sufficient even in the laminated structure of the above-described aluminum nitride film and silicon oxide film.
[0049]
In this embodiment, the amorphous silicon film is formed by forming the amorphous silicon film 103 having a thickness of 20 to 60 nm by low pressure CVD using disilane (Si ₂ H ₆ ) as a film forming gas. At this time, it is important to control the concentration of impurities such as C (carbon), N (nitrogen), and O (oxygen) mixed in the film. This is because the presence of a large amount of these impurities hinders the progress of crystallization.
[0050]
The applicant has a carbon and nitrogen concentration of 5 × 10 ¹⁸ atoms / cm ³ or less (preferably 1 × 10 ¹⁸ atoms / cm ³ or less, more preferably 5 × 10 ¹⁷ atoms / cm ³ or less, more preferably 2 × 10 ¹⁷ atoms / cm ³ or less) and oxygen concentration is 1.5 × 10 ¹⁹ atoms / cm ³ or less (preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less). The impurity concentration was controlled so that The metal element was controlled to be 1 × 10 ¹⁷ atoms / cm ³ or less. If such concentration control is performed in the film formation stage, the impurity concentration does not increase during the TFT manufacturing process as long as external contamination is prevented.
[0051]
Note that the plasma CVD method may be used as long as a film quality equivalent to the amorphous silicon film formed by the low pressure thermal CVD method can be obtained. In addition, amorphous semiconductor thin films such as silicon germanium (expressed by Si _x Ge _1-x (0 <X <1)) in which germanium is contained in an amorphous silicon film instead of an amorphous silicon film May be used. In that case, it is desirable to keep germanium contained in silicon germanium at 5 atomic% or less.
[0052]
Next, a nickel acetate aqueous solution containing 10 to 10,000 ppm (in this embodiment, 10 ppm) of nickel in terms of weight is applied by a spin coating method to form a layer 104 containing nickel on the amorphous silicon film 103. Note that it is effective to improve wettability by providing a silicon oxide film of about 5 to 10 nm on the amorphous silicon film 103 before performing the spin coating method.
[0053]
When the layer 104 containing nickel is formed, a hydrogen extraction step is performed at 450 ° C. for 1 hour. This step can be considered as a step of adding nickel into the amorphous silicon film 103. At this time, there is also an effect that nickel diffuses into the amorphous silicon film 103 and hydrogen desorption is promoted. (Fig. 1 (A))
[0054]
When the state of FIG. 1A is obtained in this way, the amorphous silicon film 103 is crystallized using X-ray excited XeCl excimer laser light. In this embodiment, the laser irradiation area is 10 cm × 10 cm, the laser energy density is 350 mJ / cm ^2, and the pulse width of the laser beam is 400 nsec. Thus, a crystalline silicon film 105 was obtained. (Fig. 1 (B))
[0055]
In this crystallization process, first, nucleation with nickel silicide as a nucleus occurs, and the nucleus gradually grows to crystallize the whole. In this embodiment, the pulse width of the laser beam is set to be as long as 400 nsec, so that sufficient crystal growth can be performed. In addition, since the heat treatment time is longer than that of laser light irradiation with a short pulse width, there is an advantage that defects caused by stress or the like are hardly generated.
[0056]
Next, a heat treatment step (second heat treatment) in a temperature range of 900 to 1200 ° C. (preferably 1000 to 1150 ° C.) was performed in a reducing atmosphere. In this example, heat treatment was performed at 1050 ° C. for 20 minutes in a hydrogen atmosphere. (Figure 1 (C))
[0057]
The reducing atmosphere is preferably a hydrogen atmosphere, an ammonia atmosphere, or an inert atmosphere containing hydrogen or ammonia (such as a mixed atmosphere of hydrogen and nitrogen or hydrogen and argon), but the surface of the crystalline silicon film can be planarized even in an inert atmosphere. It is. However, it is preferable to reduce the natural oxide film by using the reducing action because many silicon atoms with high energy are generated and as a result, the planarization effect is enhanced.
[0058]
However, it is particularly necessary to keep the concentration of oxygen or oxygen compounds (for example, OH groups) in the atmosphere at 10 ppm or less (preferably 1 ppm or less). Otherwise, the hydrogen reduction reaction will not occur.
[0059]
Thus, a crystalline silicon film 106 was obtained. The surface of the crystalline silicon film 106 was very flattened by hydrogen heat treatment at a high temperature of 900 to 1200 ° C. Further, since the heat treatment was performed at a high temperature, there were almost no stacking faults in the crystal grains.
[0060]
In this embodiment, a plurality of thin film transistors each having the crystalline silicon film 106 thus obtained as a channel formation region are formed, and various circuits are assembled with such thin film transistors to form a semiconductor device such as a semiconductor circuit, an electro-optical device, or an electronic device. Make it.
[0061]
Hereinafter, a manufacturing process of a thin film transistor will be described with reference to FIGS.
[0062]
When the crystalline silicon film 106 that can be regarded as substantially single crystal is obtained in this way, the crystalline silicon film 103 is then patterned to form the active layer 111. In this embodiment, the heat treatment is performed in a hydrogen atmosphere before the active layer 111 is formed. However, the heat treatment may be performed after the active layer is formed. In that case, patterning is preferable because stress generated in the crystalline silicon film is relaxed.
[0063]
A thermal oxidation process was then performed to form a 10 nm thick silicon oxide film 112 on the surface of the active layer 111. This silicon oxide film 112 functions as a gate insulating film. Further, since the active layer 111 is reduced in thickness by 5 nm, the film thickness is 30 nm. The film thickness of the amorphous silicon film 103 (starting film) should be determined in consideration of film reduction due to thermal oxidation so that the active layer 111 (especially the channel formation region) having a thickness of 5 to 40 nm remains finally. is required.
[0064]
After the silicon oxide film 112 was formed, a conductive polycrystalline silicon film was formed thereon, and a gate wiring 113 was formed by patterning. (Fig. 2 (A))
[0065]
In this embodiment, a polycrystalline silicon film having N-type conductivity is used as the gate wiring, but the material is not limited to this. In particular, it is effective to use a tantalum, a tantalum alloy, or a laminated film of tantalum and tantalum nitride to lower the resistance of the gate wiring. Furthermore, if a low resistance gate wiring is aimed, it is effective to use copper or a copper alloy.
[0066]
When the state of FIG. 2A is obtained, an impurity region 114 is formed by adding an impurity imparting N-type conductivity or P-type conductivity. The impurity concentration at this time was determined in view of the impurity concentration of the LDD region later. In this embodiment, arsenic is added at a concentration of 1 × 10 ¹⁸ atoms / cm ³ , but the impurity and the concentration need not be limited to this embodiment.
[0067]
Next, a thin silicon oxide film 115 of about 5 to 10 nm was formed on the surface of the gate wiring 113. This may be formed using a thermal oxidation method or a plasma oxidation method. The formation of the silicon oxide film 115 has the purpose of functioning as an etching stopper in the next sidewall formation step.
[0068]
After the silicon oxide film 115 serving as an etching stopper was formed, a silicon nitride film was formed and etched back to form sidewalls 116. In this way, the state of FIG.
[0069]
In this embodiment, a silicon nitride film is used as a sidewall, but a polycrystalline silicon film or an amorphous silicon film can also be used. Of course, if the material of the gate wiring changes, it goes without saying that the material that can be used as the sidewall also changes accordingly.
[0070]
Next, an impurity having the same conductivity type as before was added again. The impurity concentration added at this time was higher than that in the previous step. In this embodiment, arsenic is used as an impurity and the concentration is 1 × 10 ²¹ atoms / cm ³ , but it is not necessary to be limited to this. The source region 117, the drain region 118, the LDD region 119, and the channel formation region 120 are defined by this impurity addition step. (Fig. 2 (C))
[0071]
After each impurity region was formed in this way, the impurity was activated by heat treatment such as furnace annealing, laser annealing or lamp annealing.
[0072]
Next, the silicon oxide films formed on the surfaces of the gate wiring 113, the source region 117, and the drain region 118 were removed, and the surfaces were exposed. Then, a cobalt film (not shown) of about 5 nm was formed and a heat treatment process was performed. By this heat treatment, a reaction between cobalt and silicon occurred, and a silicide layer (cobalt silicide layer) 121 was formed. (Fig. 2 (D))
[0073]
This technique is a known salicide technique. Therefore, titanium or tungsten may be used instead of cobalt, and heat treatment conditions may be referred to known techniques. In this embodiment, the heat treatment process was performed by irradiating infrared light.
[0074]
When the silicide layer 121 was thus formed, the cobalt film was removed. Thereafter, an interlayer insulating film 122 having a thickness of 1 μm was formed. As the interlayer insulating film 122, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a resin film (such as polyimide, acrylic, polyamide, polyimide amide, or benzocyclobutene (BCB)) may be used. Further, these insulating films may be stacked in any combination.
[0075]
Next, contact holes were formed in the interlayer insulating film 122 to form source wirings 123 and drain wirings 124 made of a material mainly composed of aluminum. Finally, the furnace was annealed at 300 ° C. for 2 hours in a hydrogen atmosphere to complete the hydrogenation.
[0076]
In this way, a TFT as shown in FIG. 2D was obtained. Note that the structure described in this embodiment is merely an example, and the TFT structure to which the present invention can be applied is not limited thereto. Therefore, it can be applied to TFTs having any known structure. Also, the numerical conditions in the steps after the crystalline silicon film 106 is formed need not be limited to this embodiment. Furthermore, there is no problem even if a known channel doping process (impurity addition process for controlling the threshold voltage) is introduced somewhere in this embodiment.
[0077]
In this embodiment, since the concentration of impurities such as C, N, and O is thoroughly controlled at the stage of forming an amorphous silicon film as a starting film, it is included in the active layer of the completed TFT. The concentration of each impurity is such that the concentration of carbon and nitrogen is 5 × 10 ¹⁸ atoms / cm ³ or less (preferably 1 × 10 ¹⁸ atoms / cm ³ or less, more preferably 5 × 10 ¹⁷ atoms / cm ³ or less, more preferably 2 × 10 ¹⁷ or less), and the oxygen concentration remains 1.5 × 10 ¹⁹ atoms / cm ³ or less (preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less). there were. The metal element was 1 × 10 ¹⁷ atoms / cm ³ or less.
[0078]
It goes without saying that the present invention can be easily applied not only to the top gate structure but also to a bottom gate structure typified by an inverted staggered TFT.
[0079]
In this embodiment, an N-channel TFT has been described as an example. However, a P-channel TFT can be easily manufactured by combining with a known technique. Further, if a known technique is combined, it is possible to form an N-channel TFT and a P-channel TFT on the same substrate and complementarily combine them to form a CMOS circuit.
[0080]
Further, if a pixel electrode (not shown) electrically connected to the drain wiring 124 in the structure of FIG. 2D is formed by a known means, it is easy to form a pixel switching element of an active matrix display device. is there.
[0081]
That is, the present invention can also be implemented when manufacturing an active matrix type electro-optical device such as a liquid crystal display device or an EL (electroluminescence) display device.
[0082]
Note that cobalt (Co), iron (Fe), palladium (Pd), platinum (Pt), copper (Cu), gold instead of nickel (Ni) as a catalyst element for promoting crystallization of the amorphous silicon film A lattice interstitial catalyst element such as (Au) or a lattice substitution (or molten) catalyst element such as germanium (Ge), lead (Pb), or tin (Sn) can be used.
[0083]
In this embodiment, an example in which a layer containing nickel is formed on the surface side (interface side with the gate insulating film) after the formation of the amorphous silicon film is shown. Alternatively, a layer containing nickel may be formed, and an amorphous silicon film may be formed thereon to perform laser crystallization. In that case, nickel is added from the back side of the amorphous silicon film (the interface side with the base film).
[0084]
[Knowledge about Crystal Structure of Active Layer] The active layer formed according to the above manufacturing process has a crystal structure in which a plurality of needle-like or rod-like crystals (hereinafter abbreviated as rod-like crystals) are gathered together when viewed microscopically. It is thought to have. This can be easily confirmed by observation with a TEM (transmission electron microscope). It is also predicted that the crystal structure has a very high continuity of crystal lattices at the grain boundaries.
[0085]
The continuity of the grain boundaries can be confirmed using electron diffraction and X-ray diffraction. Although the surface of the active layer made of crystalline silicon having a high crystal lattice continuity (channel forming portion) includes some deviation in the crystal axis, the main orientation plane is the {110} plane, and {110} plane The diffraction spots corresponding to the surface appear neatly, but each spot has a distribution on a concentric circle.
[0086]
This is schematically shown in FIG. FIG. 9A schematically shows a part of the electron diffraction pattern. In FIG. 9A, a plurality of bright spots indicated by 801 are diffraction spots corresponding to <110> incidence. The plurality of diffraction spots 801 are distributed concentrically around the center point 802 of the electron beam irradiation area.
[0087]
Here, FIG. 9B shows an enlarged view of a region 803 surrounded by a dotted line. As shown in FIG. 9B, it can be seen that the diffraction spot 801 has a distribution (fluctuation) with respect to the center point 802 of the irradiation area.
[0088]
The angle formed by the tangent line 804 drawn from the center point 802 of the electron beam irradiation area to the diffraction spot 801 and the line segment connecting the center point 802 of the electron beam irradiation area and the center point 805 of the diffraction spot is 2 ° or less. Become. At this time, since two tangent lines can be drawn, the spread of the diffraction spot 801 is finally within a range of ± 2 °.
[0089]
This tendency is observed in the entire region of the actual electron diffraction pattern, and is generally within ± 2 ° (typically within ± 1.5 °, preferably within ± 0.5 °). The fact that a diffraction spot has a distribution means this.
[0090]
Further, it is known that such a diffraction spot distribution appears when individual crystal grains having the same crystal axis are gathered in an arrangement rotated around the crystal axis. That is, an angle formed by a specific axis (referred to as axis A) included in a crystal plane and an axis (referred to as axis B) equivalent to axis A included in another adjacent crystal plane is defined as a rotation angle. In other words, the position at which the diffraction spot appears is shifted by an amount corresponding to the rotation angle.
[0091]
Therefore, when a plurality of crystal grains are assembled in a positional relationship having a certain rotation angle, one electron beam diffraction pattern can be observed as an aggregate of diffraction spots indicated by the individual crystal grains.
[0092]
When the diffraction spot is spread within a range of ± 2 ° (typically within ± 1.5 °, preferably within ± 0.5 °), the absolute value of the rotation angle formed by the equivalent axis between adjacent crystal grains is It means within 4 ° (typically within 3 °, preferably within 1 °).
[0093]
When the crystal axis is the <110> axis, an equivalent axis included in the crystal plane includes the <111> axis. In the crystalline semiconductor thin film of the present invention, the <111> axes are 70.5 ( (There is also a theory of 70.4). In this case also, it is considered that the equivalent axis has a rotation angle of 70.5 ° ± 2 °.
[0094]
That is, in such a case, the absolute value of the rotation angle formed by an equivalent axis or an axis having a rotational relationship of 70.5 ° with respect to the equivalent axis is within 4 ° between the crystal grains (typically Can be said to be within 3 °, preferably within 1 °.
[0095]
It is also possible to confirm that the crystal lattice is continuous in the crystal grain boundary by observing the crystal grain boundary with HR-TEM (High Resolution Transmission Electron Microscopy). In HR-TEM, it can be easily confirmed whether or not the observed lattice fringes are continuously connected at the crystal grain boundary.
[0096]
Note that the continuity of the crystal lattice at the crystal grain boundary results from the fact that the crystal grain boundary is a grain boundary called a “planar grain boundary”. The definition of the planar grain boundary in this specification is “Characterization of High-Efficiency Cast-Si Solar Cell Wafers by MBIC Measurement; Ryuichi Shimokawa and Yutaka Hayashi, Japanese Journal of Applied Physics vol.27, No.5, pp.751- 758, 1988 ”is“ Planar boundary ”.
[0097]
According to the above paper, planar grain boundaries include twin grain boundaries, special stacking faults, and special twist grain boundaries. This planar grain boundary is characterized by being electrically inactive. That is, although it is a crystal grain boundary, it does not function as a trap that inhibits the movement of carriers, and thus can be regarded as substantially nonexistent.
[0098]
In particular, when the crystal axis (axis perpendicular to the crystal plane) is the <110> axis, the {211} twin grain boundary is also called a corresponding grain boundary of Σ3. The Σ value is a parameter that serves as a guideline indicating the degree of consistency of the corresponding grain boundary. It is known that the smaller the Σ value, the better the grain boundary.
[0099]
In the crystalline silicon film obtained by the applicant of the present invention, most of the crystal grain boundaries (90% or more, typically 95% or more) are the corresponding grain boundaries of Σ3, that is, {211} twins. Can be a grain boundary.
[0100]
In the crystal grain boundary formed between two crystal grains, when the plane orientation of both crystals is {110}, assuming that the angle formed by the lattice stripes corresponding to the {111} plane is θ, θ = 70.5 ° It is known that sometimes it becomes the corresponding grain boundary of Σ3.
[0101]
The crystalline silicon film of the present invention is a crystalline silicon film in which each lattice fringe of adjacent crystal grains is continuous at an angle of about 70.5 °, that is, the crystal grain boundary is a {211} twin grain boundary. I came to the conclusion that.
[0102]
Incidentally, when θ = 38.9 °, the corresponding grain boundary of Σ9 is obtained, but such other crystal grain boundaries also existed.
[0103]
Such a corresponding grain boundary is formed only between crystal grains having the same plane orientation. That is, the corresponding grain boundary is formed over a wide range only when the crystalline silicon film has a substantially {110} plane orientation.
[0104]
Such a crystal structure (exactly, the structure of the crystal grain boundary) indicates that two different crystal grains are joined with extremely good consistency at the crystal grain boundary. That is, the crystal lattice is continuously connected at the crystal grain boundary, and the trap level caused by crystal defects or the like is very difficult to create. Therefore, the crystalline semiconductor thin film having such a crystal structure can be regarded as having substantially no grain boundary.
[0105]
Furthermore, defects present in the crystal grains can be almost eliminated by the heat treatment step in the reducing atmosphere shown in FIG. This can be confirmed from the fact that the number of defects is greatly reduced before and after the heat treatment step.
[0106]
This difference in the number of defects is measured as a difference in spin density by electron spin resonance (ESR). By the manufacturing process of Embodiment 1, the spin density of the crystalline silicon film can be at least 5 × 10 ¹⁷ spins / cm ³ or less (preferably 3 × 10 ¹⁷ spins / cm ³ or less). However, since this measured value is close to the detection limit of existing measuring devices, the actual spin density is expected to be even lower.
[0107]
Further, since this heat treatment step is performed in a reducing atmosphere, particularly in a hydrogen atmosphere, even a slight remaining defect is deactivated by hydrogen termination. Therefore, it can be considered that defects in the crystal grains do not substantially exist.
[0108]
From the above, the crystalline semiconductor thin film obtained by carrying out the invention of the present application is considered to be a single crystal semiconductor thin film or a substantially single crystal semiconductor thin film because there are substantially no crystal grains and no crystal grain boundaries. good.
[0109]
[Findings concerning electrical characteristics of TFT] The TFTs made of the above-described crystalline silicon film having high grain boundary continuity show electrical characteristics comparable to MOSFETs using pure single crystal silicon.
[0110]
(1) Sub-threshold coefficient, which is an indicator of switching performance (ON / OFF operation switching agility), is 60-100 mV / decade for both N-channel and P-channel TFTs (typically 60-85 mV / decade) And small. (2) Field effect mobility (μFE), which is an index of TFT operating speed, is 200 to 650 cm ² / Vs (typically 300 to 500 cm ² / Vs) for N-channel TFTs, and 100 to 100 for P-channel TFTs. It can be increased to 300 cm ² / Vs (typically 150 to 200 cm ² / Vs). (3) The threshold voltage (Vth), which serves as an index of TFT driving voltage, can be reduced to -0.5 to 1.5 V for N-channel TFTs and -1.5 to 0.5 V for P-channel TFTs.
[0111]
As described above, it has been confirmed that extremely excellent switching characteristics and high-speed operation characteristics can be realized.
[0112]
[Knowledge about circuit characteristics] For example, the frequency characteristics of a ring oscillator can be improved. . The ring oscillator is a circuit in which inverter circuits having a CMOS structure are connected in an odd-numbered ring shape, and is used to obtain a delay time per inverter circuit. The structure of the ring oscillator is as follows. Number of stages: 9 stages TFT gate film thickness: 30 nm and 50 nm TFT gate length: 0.6 μm
With such a ring oscillator, the maximum oscillation frequency can be 1.04 GHz.
[0113]
A shift register, which is one of the TEGs of an LSI circuit, is manufactured and the operating frequency is 100 MHz in the case of a shift register circuit having a gate insulating film thickness of 30 nm, a gate length of 0.6 μm, a power supply voltage of 5 V, and 50 stages. Output pulses can be generated.
[0114]
Astonishing data of the ring oscillator and shift register as described above shows that the above-mentioned TFT using crystalline silicon with continuous grain boundaries is comparable to or surpassing IGFET using single crystal silicon. It has shown that it has.
[0115]
(Embodiment 2) In this embodiment, a case will be described in which the heat treatment step at 900 to 1200 ° C. in a reducing atmosphere in Embodiment 1 also serves as a step for removing nickel in the crystalline silicon film.
[0116]
In this example, a heat treatment step at 900 to 1200 ° C. was performed in an atmosphere in which 0.1 to 5 wt% of hydrogen halide (typically hydrogen chloride) was mixed in a hydrogen atmosphere. In addition, NF ₃ and HBr can be used as the hydrogen halide.
[0117]
By employing this embodiment, the catalytic element can be removed or reduced from the crystalline silicon film. Since the concentration of the catalytic element is reduced to 1 × 10 ¹⁷ atoms / cm ³ or less, it is possible to prevent the TFT characteristics (particularly the off-current value) from being varied due to the presence of the catalytic element.
[0118]
Example 3 In this example, an example in which a step of removing nickel from a crystalline silicon film is performed before performing a heat treatment step at 900 to 1200 ° C. in a reducing atmosphere in Example 1 will be described.
[0119]
In the case of this example, the gettering action of a halogen element was used to remove nickel in the film. This is a technology that utilizes the fact that a halogen element and nickel combine to form a volatile nickel halide. Details of this technique are described in JP-A-9-31260. However, a crystalline silicon film is placed in an atmosphere containing a halogen element, and a heat treatment step of 700 to 1150 ° C. (typically 950 to 1100 ° C.). For about 0.5 to 8 hours.
[0120]
In this embodiment, the treatment substrate is placed in a gas in which oxygen and hydrogen chloride are mixed, and a heat treatment step is performed at 950 ° C. for 1 hour. By this step, the nickel concentration remaining in the crystalline silicon film could be reduced to 1 × 10 ¹⁷ atoms / cm ³ or less. Since the vicinity of 1 × 10 ¹⁷ atoms / cm ³ is the lower limit of SIMS (mass secondary ion analysis) measurement, the actual concentration is about 1 × 10 ¹⁴ atoms / cm ³ to 1 × 10 ¹⁶ atoms / cm ^3. Is expected to exist.
[0121]
The gettering step with the halogen element may be performed before or after the heat treatment step at 900 to 1200 ° C. in a reducing atmosphere.
[0122]
By employing this embodiment, the catalytic element can be removed or reduced from the crystalline silicon film. Since the concentration of the catalytic element is reduced to 1 × 10 ¹⁷ atoms / cm ³ or less, it is possible to prevent the TFT characteristics (particularly the off-current value) from being varied due to the presence of the catalytic element. Note that this embodiment may be combined with the second embodiment.
[0123]
(Example 4) In this example, a case will be described in which means different from Example 3 is used to remove nickel before performing the heat treatment step at 900 to 1200 ° C in a reducing atmosphere in Example 1.
[0124]
FIG. 3 is used for the description. First, the amorphous silicon film was crystallized through the steps shown in Example 1. A mask 302 made of a silicon oxide film was formed on the crystalline silicon film 301 thus formed. The mask 302 is provided with an opening 303. (Fig. 3 (A))
[0125]
Next, an element selected from Group 15 (phosphorus in this example) was added using mask 302 as a mask. As the addition method, any known means such as an ion implantation method, a plasma doping method, or a vapor phase diffusion method may be used. (Fig. 3 (B))
[0126]
Thus, a region 304 to which phosphorus was added was formed in the crystalline silicon film exposed through the opening 303 of the mask 302. In this embodiment, this area is called a gettering area for convenience. The amount of phosphorus added was adjusted so that the phosphorus concentration contained in the gettering region 304 was 1 × 10 ¹⁹ to 1 × 10 ²¹ atoms / cm ³ .
[0127]
After the gettering region 304 was formed, a gettering process was performed by performing heat treatment for 2 to 24 hours (preferably 8 to 12 hours) in a temperature range of 550 to 750 ° C. (preferably 600 to 650 ° C.). In this embodiment, a heat treatment process at 600 ° C. for 12 hours was performed. (Figure 3 (C))
[0128]
As a result, nickel contained in the crystalline silicon film 301 was captured (gettered) in the gettering region 304, and a crystalline silicon film 305 having a greatly reduced nickel concentration was obtained. The concentration of nickel contained in the crystalline silicon film 305 was 1 × 10 ¹⁷ atoms / cm ³ or less. However, as described in Example 3, the vicinity of 1 × 10 ¹⁷ atoms / cm ³ is the measurement lower limit of SIMS (mass secondary ion analysis), so in practice up to about 1 × 10 ¹⁶ atoms / cm ³ or less. Expected to be reduced.
[0129]
Next, patterning was performed to form active layers 306 and 307 made of only the crystalline silicon film 305. Then, a heat treatment step at 1050 ° C. for 1 hour was performed in a hydrogen atmosphere to planarize the active layer surface and improve crystallinity. Of course, the heat treatment conditions are not limited to the present embodiment, and can be selected from the same conditions as in the first embodiment.
[0130]
The reason why hydrogen annealing (heat treatment in an atmosphere containing hydrogen) is performed after the active layer is formed is that when heat treatment exceeding 800 ° C. is performed with the gettering region 304 remaining, phosphorus is formed in the crystalline silicon film 305. This is because it will despread in the direction. It is desirable to perform hydrogen annealing after completely removing the gettering region 304 as in this embodiment because phosphorus is not mixed into the channel formation region.
[0131]
After obtaining the state of FIG. 3D in this way, the TFT may be manufactured according to the manufacturing process shown in Embodiment 1. Of course, the effect of the present invention is not impaired even if the TFT is manufactured by other known means.
[0132]
Further, a step of irradiating the crystalline silicon film with ultraviolet light or infrared light may be performed before the step of FIG. 3B (gettering step). By doing so, phosphorus is activated and gettering efficiency is increased.
[0133]
Further, after adding phosphorus, the mask 302 can be removed, and thereafter ultraviolet light or infrared light can be irradiated. By doing so, activation of phosphorus and diffusion of nickel are performed, and it is possible to further improve the gettering efficiency.
[0134]
Further, immediately after the crystallization of the amorphous silicon film is completed, a heat treatment step of 900 to 1200 ° C. in a reducing atmosphere may be performed, and then the gettering step shown in this embodiment may be performed.
[0135]
In addition, you may combine a present Example with Example 2 or Example 3. FIG.
[0136]
(Embodiment 5) In this embodiment, an example in which a source region and a drain region are used when gettering a catalytic element (nickel in this embodiment) using phosphorus will be described. FIG. 4 is used for the description.
[0137]
First, an N-channel TFT 401 and a P-channel TFT 402 were formed according to a TFT manufacturing process including the process described in Example 1. The TFT manufacturing process followed Example 1. Although an example of a manufacturing process of a P-channel TFT is not described in Example 1, the structure is the same as that of the N-channel TFT, and therefore the conductivity type of the impurity added to the active layer is selected from the group 13 What is necessary is just to change to an element (typically boron).
[0138]
In this way, the state of FIG. The source region 403 and the drain region 404 of the N-channel TFT 401 are formed by adding phosphorus at a concentration of 5 × 10 ²⁰ atoms / cm ³ . The source region 405 and the drain region 406 of the P-channel TFT 402 are doped with phosphorus having a concentration of 5 × 10 ²⁰ atoms / cm ³ and boron having a concentration of 1.5 × 10 ²¹ atoms / cm ³ .
[0139]
Next, in the state of FIG. 4A, a heat treatment step (gettering step) of 500 to 650 ° C. for 1 to 12 hours (550 ° C. for 1 hour in this embodiment) was performed. At this time, the source regions 403 and 405 and the drain regions 404 and 406 each function as gettering regions. On the P-channel TFT 405 side, it was possible to getter nickel well despite the higher boron concentration than phosphorus.
[0140]
In this gettering step, nickel is moved and gettered from the channel formation region immediately below the gate wiring toward the adjacent source region and drain region. Therefore, the nickel concentration in the channel formation region was reduced to 1 × 10 ¹⁷ atoms / cm ³ or less (probably 1 × 10 ¹⁶ atoms / cm ³ or less).
[0141]
Note that the gettering step shown in this embodiment can be combined with any of the embodiments 2 to 5.
[0142]
Example 6 In this example, an example of a reflective liquid crystal display device manufactured according to the present invention is shown in FIG. Since a known method may be used for a manufacturing method of a pixel TFT (pixel switching element) and a cell assembly process, detailed description thereof is omitted.
[0143]
In FIG. 5A, 11 is a substrate having an insulating surface (ceramic substrate provided with a silicon oxide film), 12 is a pixel matrix circuit, 13 is a source driver circuit, 14 is a gate driver circuit, 15 is a counter substrate, and 16 is an FPC. (Flexible printed circuit), 17 is a signal processing circuit. As the signal processing circuit 17, it is possible to form a circuit that performs processing such as a D / A converter, a γ correction circuit, a signal division circuit, or the like that has been substituted for a conventional IC. Of course, it is also possible to provide an IC chip on a glass substrate and perform signal processing on the IC chip.
[0144]
Further, in this embodiment, the liquid crystal display device is described as an example. However, the present invention is applied to an EL (electroluminescence) display device and an EC (electrochromic) display device if the display device is an active matrix type. It goes without saying that it is also possible to do.
[0145]
Here, FIG. 5B shows an example of a circuit constituting the driver circuits 13 and 14 in FIG. Since the TFT portion has already been described in Embodiment 1, only necessary portions will be described here.
[0146]
In FIG. 5B, reference numerals 501 and 502 denote N-channel TFTs, and 503 denotes a P-channel TFT. The TFTs 501 and 503 constitute a CMOS circuit. Reference numeral 504 denotes an insulating layer made of a laminated film of silicon nitride film / silicon oxide film / resin film, and a titanium wiring 505 is provided on the insulating layer, and the aforementioned CMOS circuit and TFT 502 are electrically connected. The titanium wiring is further covered with an insulating layer 506 made of a resin film. The two insulating layers 504 and 506 also have a function as a planarizing film.
[0147]
FIG. 5C illustrates part of a circuit included in the pixel matrix circuit 12 in FIG. In FIG. 5C, reference numeral 507 denotes a pixel TFT formed of an N-channel TFT having a double gate structure, and a drain wiring 508 is formed so as to spread widely in the pixel region. In addition to the double gate structure, a single gate structure or a triple gate structure may be employed.
[0148]
An insulating layer 504 is provided thereon, and a titanium wiring 505 is provided thereon. At this time, a recess is dropped into a part of the insulating layer 504, and only the lowermost silicon nitride and silicon oxide are left. As a result, an auxiliary capacitance is formed between the drain wiring 508 and the titanium wiring 505.
[0149]
The titanium wiring 505 provided in the pixel matrix circuit provides an electric field shielding effect between the source / drain wiring and the subsequent pixel electrode. Further, it functions as a black mask in the gaps between a plurality of pixel electrodes.
[0150]
An insulating layer 506 is provided to cover the titanium wiring 505, and a pixel electrode 509 made of a reflective conductive film is formed thereon. Of course, the surface of the pixel electrode 509 may be devised to increase the reflectance. In addition, an alignment film and a liquid crystal layer are actually provided on the pixel electrode 509, but description thereof is omitted here.
[0151]
A reflection type liquid crystal display device having the above-described configuration can be manufactured using the present invention. Needless to say, a transmission type liquid crystal display device can be easily manufactured by combining with a known technique. Further, an active matrix EL display device can be easily manufactured by combining with a known technique.
[0152]
Although not distinguished in the drawings, the film thickness of the gate insulating film can be different between the pixel TFT constituting the pixel matrix circuit and the CMOS circuit constituting the driver circuit and the signal processing circuit.
[0153]
In the pixel matrix circuit, since the driving voltage applied to the TFT is high, a gate insulating film having a thickness of about 50 to 200 nm is required. On the other hand, in the driver circuit and the signal processing circuit, the driving voltage applied to the TFT is low, and conversely, a high-speed operation is required. Therefore, it is effective to make the gate insulating film thinner than the pixel TFT by about 3 to 30 nm. .
[0154]
(Example 7) In the liquid crystal display device manufactured by the said Example, it is possible to use various liquid crystals other than TN liquid crystal. For example, 1998, SID, "Characteristics and Driving Scheme of Polymer-Stabilized Monostable FLCD Exhibiting Fast Response Time and High Contrast Ratio with Gray-Scale Capability" by H. Furue et al., 1997, SID DIGEST, 841, "A Full -Color Thresholdless Antiferroelectric LCD Exhibiting Wide Viewing Angle with Fast Response Time "by T. Yoshida et al., 1996, J. Mater. Chem. 6 (4), 671-673," Thresholdless antiferroelectricity in liquid crystals and its application to The liquid crystal disclosed in "displays" by S. Inui et al. or US Pat. No. 5,945,569 can be used.
[0155]
A liquid crystal exhibiting an antiferroelectric phase in a certain temperature range is called an antiferroelectric liquid crystal. Among mixed liquid crystals having antiferroelectric liquid crystals, there is a so-called thresholdless antiferroelectric mixed liquid crystal that exhibits electro-optic response characteristics in which transmittance continuously changes with respect to an electric field. This thresholdless antiferroelectric mixed liquid crystal has a V-shaped electro-optic response characteristic, and a drive voltage of about ± 2.5 V (cell thickness of about 1 μm to 2 μm) is also found. ing.
[0156]
Here, FIG. 10 shows an example of the light transmittance characteristics of the thresholdless antiferroelectric mixed liquid crystal exhibiting a V-shaped electro-optic response with respect to the applied voltage. The vertical axis of the graph shown in FIG. 10 is the transmittance (arbitrary unit), and the horizontal axis is the applied voltage. The transmission axis of the polarizing plate on the incident side of the liquid crystal display device is set to be substantially parallel to the normal direction of the smectic layer of the thresholdless antiferroelectric mixed liquid crystal that substantially coincides with the rubbing direction of the liquid crystal display device. . Further, the transmission axis of the output-side polarizing plate is set to be substantially perpendicular (crossed Nicols) to the transmission axis of the incident-side polarizing plate.
[0157]
As shown in FIG. 10, it can be seen that when such a thresholdless antiferroelectric mixed liquid crystal is used, low voltage driving and gradation display are possible.
[0158]
When such a low-voltage thresholdless antiferroelectric mixed liquid crystal is used in a liquid crystal display device having an analog driver, the power supply voltage of the image signal sampling circuit is suppressed to about 5V to 8V, for example. Is possible. Therefore, the operating power supply voltage of the driver can be lowered, and low power consumption and high reliability of the liquid crystal display device can be realized.
[0159]
Further, even when such a low-voltage thresholdless antiferroelectric mixed liquid crystal is used in a liquid crystal display device having a digital driver, the output voltage of the D / A conversion circuit can be lowered. The operating power supply voltage of the A conversion circuit can be lowered, and the operating power supply voltage of the driver can be lowered. Therefore, low power consumption and high reliability of the liquid crystal display device can be realized.
[0160]
Therefore, using such a thresholdless antiferroelectric mixed liquid crystal driven at a low voltage makes it possible to use a TFT (for example, 0 nm to 500 nm or 0 nm to 200 nm) having a relatively small LDD region (low concentration impurity region). It is also effective when used.
[0161]
In general, the thresholdless antiferroelectric mixed liquid crystal has a large spontaneous polarization, and the dielectric constant of the liquid crystal itself is high. For this reason, when a thresholdless antiferroelectric mixed liquid crystal is used in a liquid crystal display device, a relatively large storage capacitor is required for the pixel. Therefore, it is preferable to use a thresholdless antiferroelectric mixed liquid crystal having a small spontaneous polarization. Further, the driving method of the liquid crystal display device may be line-sequential driving, so that the period of writing the gradation voltage to the pixel (pixel feed period) may be lengthened to compensate for the small storage capacity. .
[0162]
In addition, since low voltage drive is implement | achieved by using such a thresholdless antiferroelectric mixed liquid crystal, the low power consumption of a liquid crystal display device is implement | achieved.
[0163]
Any liquid crystal having electro-optical characteristics as shown in FIG. 10 can be used as the display medium of the liquid crystal display device of the present invention.
[0164]
(Embodiment 8) The present invention can be applied to all conventional IC technologies. That is, it can be applied to all semiconductor circuits currently on the market. For example, the present invention may be applied to a microprocessor such as a RISC processor or an ASIC processor integrated on a single chip, or from a signal processing circuit such as a D / A converter to a portable device (cell phone, PHS, mobile computer). You may apply to a high frequency circuit.
[0165]
FIG. 6 shows an example of a microprocessor. The microprocessor typically includes a CPU core 21, a RAM 22, a clock controller 23, a cache memory 24, a cache controller 25, a serial interface 26, an I / O port 27, and the like.
[0166]
Of course, the microprocessor shown in FIG. 3 is a simplified example, and various circuit designs are performed on an actual microprocessor depending on its application.
[0167]
However, it is an IC (Integrated Circuit) 28 that functions as the center of a microprocessor having any function. The IC 28 is a functional circuit in which an integrated circuit formed on the semiconductor chip 29 is protected with ceramic or the like.
[0168]
The N-channel TFT 30 and the P-channel TFT 31 having the structure of the present invention constitute an integrated circuit formed on the semiconductor chip 29. Note that power consumption can be suppressed by configuring a basic circuit with a CMOS circuit as a minimum unit.
[0169]
The microprocessor shown in this embodiment is mounted on various electronic devices and functions as a central circuit. Typical electronic devices include personal computers, portable information terminal devices, and all other home appliances. Further, a computer for controlling a vehicle (such as an automobile or a train) may be used.
[0170]
Example 9
The CMOS circuit and pixel matrix circuit formed by implementing the present invention can be used for various electro-optical devices (active matrix liquid crystal display, active matrix EL display, active matrix EC display). That is, the present invention can be implemented in all electronic devices in which these electro-optical devices are incorporated as display media.
[0171]
Such electronic devices include video cameras, digital cameras, projectors (rear type or front type), head mounted displays (goggles type displays), car navigation systems, personal computers, personal digital assistants (mobile computers, mobile phones or electronic books). Etc.). Examples of these are shown in FIGS.
[0172]
FIG. 7A illustrates a personal computer, which includes a main body 2001, an image input portion 2002, a display device 2003, and a keyboard 2004. The present invention can be applied to the image input unit 2002, the display device 2003, and other signal control circuits.
[0173]
FIG. 7B illustrates a video camera, which includes a main body 2101, a display device 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 2106. The present invention can be applied to the display device 2102, the voice input unit 2103, and other signal control circuits.
[0174]
FIG. 7C illustrates a mobile computer, which includes a main body 2201, a camera unit 2202, an image receiving unit 2203, operation switches 2204, and a display device 2205. The present invention can be applied to the display device 2205 and other signal control circuits.
[0175]
FIG. 7D illustrates a goggle type display which includes a main body 2301, a display device 2302, and an arm portion 2303. The present invention can be applied to the display device 2302 and other signal control circuits.
[0176]
FIG. 7E shows a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded. The player 240 includes a main body 2401, a display device 2402, a speaker unit 2403, a recording medium 2404, and operation switches 2405. This apparatus uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display device 2402 and other signal control circuits.
[0177]
FIG. 7F illustrates a digital camera, which includes a main body 2501, a display device 2502, an eyepiece unit 2503, an operation switch 2504, and an image receiving unit (not illustrated). The present invention can be applied to the display device 2502 and other signal control circuits.
[0178]
FIG. 8A illustrates a front type projector, which includes a display device 2601 and a screen 2602. The present invention can be applied to display devices and other signal control circuits.
[0179]
FIG. 8B shows a rear projector, which includes a main body 2701, a display device 2702, a mirror 2703, and a screen 2704. The present invention can be applied to display devices and other signal control circuits.
[0180]
8C illustrates an example of the structure of the display devices 2601 and 2702 in FIGS. 8A and 8B. The display devices 2601 and 2702 include a light source optical system 2801, mirrors 2802, 2805 to 2807, dichroic mirrors 2803 and 2804, optical lenses 2808, 2809, and 2811, a liquid crystal display device 2810, and a projection optical system 2812. The projection optical system 2812 is configured by an optical system including a projection lens. In this embodiment, an example of a three-plate type using three liquid crystal display devices 2810 is shown. However, the present invention is not particularly limited, and for example, a single-plate type may be used. In addition, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the optical path indicated by an arrow in FIG. Good.
[0181]
FIG. 8D shows an example of the structure of the light source optical system 2801 in FIG. In this embodiment, the light source optical system 2801 includes light sources 2813 and 2814, a combining prism 2815, collimator lenses 2816 and 2820, lens arrays 2817 and 2818, and a polarization conversion element 2819. Although the light source optical system shown in FIG. 8D uses two light sources, three or four or more light sources may be used. Of course, one light source may be used. In addition, the practitioner may appropriately provide an optical lens, a film having a polarization function, a film for adjusting a phase difference, an IR film, and the like in the light source optical system.
[0182]
As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. Moreover, the electronic apparatus of a present Example is realizable even if it uses the structure which consists of what combination of Examples 1-8.
[Brief description of the drawings]
FIGS. 1A to 1C illustrate a manufacturing process of a thin film transistor. FIGS.
FIGS. 2A and 2B illustrate a manufacturing process of a thin film transistor. FIGS.
FIG. 3 illustrates a manufacturing process of a thin film transistor.
4A and 4B illustrate a manufacturing process of a thin film transistor.
FIG. 5 is a diagram illustrating a configuration of an electro-optical device.
FIG. 6 is a diagram showing a configuration of a semiconductor circuit.
FIG 7 illustrates a structure of an electronic device.
FIG 8 illustrates a structure of an electronic device.
FIG. 9 is a diagram schematically showing an electron diffraction pattern.
FIG. 10 is a characteristic diagram of a thresholdless antiferroelectric mixed liquid crystal.
FIG. 11 is a SEM observation photograph of the surface of the crystalline silicon film before high-temperature annealing.
FIG. 12 is a SEM observation photograph of the surface of the crystalline silicon film after high-temperature annealing.
FIG. 13 is an AFM image of the surface of a crystalline silicon film before high-temperature annealing.
FIG. 14 is an AFM image of the crystalline silicon film surface after high-temperature annealing.
FIG. 15 is a Histogram distribution of a height of an AFM image before high-temperature annealing, and a Bearing Ratio curve.
FIG. 16 shows a Histogram distribution of a height of an AFM image after high-temperature annealing, and a Bearing Ratio curve.
FIG. 17 is a statistical data of a bearing ratio at 1/2 of the PV value.

Claims (6)

Amorphous semiconductor thin film is formed on a substrate,
Adding a catalyst element for promoting crystallization of the amorphous semiconductor thin film to said amorphous semiconductor thin film,
By irradiating ultraviolet light or infrared light subjected to first heat treatment of the amorphous semiconductor thin film Ru alter the crystalline semiconductor thin film,
A method for manufacturing a semiconductor device, wherein a second heat treatment at 900 to 1200 ° C. is performed on the crystalline semiconductor thin film in a reducing atmosphere which is a hydrogen or ammonia atmosphere . In claim 1,
The method for manufacturing a semiconductor device, wherein the reducing atmosphere contains a halogen element. In claim 1 or claim 2,
The method for manufacturing a semiconductor device, wherein the second heat treatment is furnace annealing. In any one of Claims 1 thru | or 3,
The method for manufacturing a semiconductor device wherein the reducing atmosphere is less than 10ppm concentration of oxygen or oxygen compound. In any one of Claims 1 thru | or 4,
The amorphous semiconductor thin film, the carbon and concentration of 5 × ¹⁰ 18 atoms / cm ³ or less and the concentration of oxygen in nitrogen in the amorphous semiconductor thin film is 1.5 × ¹⁰ 19 atoms / cm ³ or less A method for manufacturing a semiconductor device, wherein the semiconductor device is formed as follows. In any one of Claims 1 thru | or 5 ,
Ni, Co, Fe, Pd, Pt, Cu, Au, Ge, Pb, Sn is used as the catalyst element.

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