JP5250186B2 - Semiconductor device - Google Patents

Description

    The present invention relates to an evaluation element (Test Element Group: hereinafter referred to as TEG) for evaluating the characteristics of a thin film transistor (hereinafter referred to as TFT). Further, the present invention relates to a method for manufacturing the TEG, a method for evaluating electrical characteristics of a semiconductor device using the TEG, and a semiconductor device evaluated using the TEG.

Since a conventional thin film transistor (TFT) is composed of an amorphous semiconductor film, it is almost impossible to obtain a TFT having a field effect mobility of 10 cm ² / V · sec or more. However, TFTs composed of crystalline semiconductor films have appeared, and it has become possible to realize TFTs with high field effect mobility.

Since a TFT of a crystalline semiconductor film has high field effect mobility, various functional circuits can be manufactured over the same substrate using the TFT. For example, in a display device, a driver IC or the like was previously mounted on a display portion as a drive circuit, but a display portion, a shift register circuit, and a level shifter circuit are formed on the same substrate by using a TFT of a crystalline semiconductor film. In addition, it is possible to arrange a drive circuit including a buffer circuit, a sampling circuit, and the like. The drive circuit is formed based on a CMOS circuit composed of an N-channel TFT and a P-channel TFT. In the drive circuit, it is necessary to secure a sufficient on-current value in order to increase the on-current drive capability.

  As a method for improving the on-characteristic, there is a method of reducing the parasitic resistance of the TFT. Specifically, metal silicide is provided in the source region and the drain region to reduce the parasitic resistance (see, for example, Patent Document 1).

  When the source region and the drain region are made into metal silicide, metal silicide is formed on the surface of the silicon (Si) impurity region, and a contact region between the metal silicide and Si is formed. At this time, when the resistance of the impurity region of Si is high, the contact portion between the metal silicide and Si becomes a Schottky junction. When a Schottky junction is formed, the contact resistance is high and the on-characteristics of the TFT are lowered. In order to improve the on-characteristic, it is necessary to reduce the resistance of Si and make the contact portion between the metal silicide and Si ohmic contact.

  In some cases, Si is used as a resistor in various circuits. However, if metal silicidation is performed, all the Si surfaces are metal silicidized and the resistance becomes too low. Therefore, there is a problem that the circuit area becomes large when metal silicided Si is used as a resistor.

Although there is a method of removing metal or metal silicide only on Si in a region where Si is used as a resistor, there is a problem that the number of steps increases.
Japanese Patent Laid-Open No. 10-98199

Currently, research on submicron TFTs is actively conducted. However, when the source and drain regions are metal silicided using a metal silicidation technique, it is difficult to measure the resistance of the Si impurity region.

Therefore, if the desired on-characteristics are not obtained when the TFT is manufactured, it is possible to investigate whether the Si resistance is high or whether the Si resistance is sufficiently low and there is another cause. It was difficult.

If it is possible to measure the resistance of Si after TFT fabrication, it can be estimated from the resistance value of Si whether the contact between the metal silicide and Si is an ohmic junction. If the TFT characteristics are abnormal, the Si resistance can be measured, and if it can be confirmed that the TFT is out of the standard value, feedback to the process can be promptly performed.

In view of the above, an object of the present invention is to measure the resistance of a Si impurity region in a substrate having a TFT in which a source region and a drain region are metal silicided. It is another object of the present invention to manufacture a Si region in which an impurity region is metal-silicided but a part of the impurity region is not metal-silicided without increasing the number of steps. An object is to improve the yield by measuring the resistance of Si after TFT fabrication to provide feedback to the process.

    The present inventor changes the structure of the TEG for measuring the Si resistance in the normal TFT forming process, and measures the Si resistance on the metal-silicided substrate by measuring under a specific measurement condition. I thought about TEG.

    One of the features of the present invention is that a semiconductor film having an impurity region, an insulating film formed on the semiconductor film, and a semiconductor formed on the insulating film are formed over the same substrate on which the TFT is formed. On the film, an electrode divided into a plurality at intervals a in the first direction (channel width direction), an insulator having a width b formed in contact with the side wall of the electrode, and a region between the divided electrodes And a silicide layer formed on a part of the surface of the impurity region, a wiring connected to the silicide layer, and a wiring connected to the electrode divided into a plurality of parts. The region between the electrodes is characterized by a semiconductor device that is covered with an insulator and has no silicide layer.

    In addition, according to the present invention, an Si region in which an impurity region is not metal-silicided while the impurity region is metal-silicided can be manufactured without increasing the number of steps. Since a resistance element using the Si impurity region that is not metal-silicided as a resistance can be manufactured, the circuit area can be reduced by using the resistance element as a circuit resistance as necessary. Can do.

  One feature of the present invention is that an island-shaped semiconductor film is formed, a first insulating film in contact with the semiconductor film is formed, and a conductive film is formed to cover the semiconductor film and the first insulating film. Is etched to form an electrode which is overlapped with the semiconductor film through the first insulating film and is divided into a plurality of portions with a distance a in the first direction on the semiconductor film, and the electrode is used as a mask to form the semiconductor film. A step of adding an impurity element, forming an impurity region, covering the electrode and the semiconductor film, forming a second insulating film, and anisotropically etching the second insulating film; In the anisotropic etching step, an insulator having a width b is formed on the side surface of the electrode, and an insulator is formed in a region between the divided electrodes. The width b of the insulator formed on the side surface satisfies the relationship of a <2b. That.

  One of the characteristics of the present invention is a method for manufacturing a semiconductor device including a semiconductor element and a thin film transistor, and the manufacturing process of the semiconductor element and the manufacturing process of the thin film transistor form an island-shaped semiconductor film, A first insulating film in contact with the semiconductor film is formed, a conductive film is formed so as to cover the semiconductor film and the first insulating film, the conductive film is etched, and an electrode overlapping with the semiconductor film through the first insulating film is formed An impurity element is added to the semiconductor film using the electrode as a mask, an impurity region is formed, a second insulating film is formed to cover the electrode and the semiconductor film, and the second insulating film is anisotropically etched. A step of exposing a part of the semiconductor film, forming a metal film in contact with the exposed part of the semiconductor film, and then performing a heat treatment to form a metal silicide layer on the exposed part of the semiconductor film. The semiconductor element has both In the step of etching the electrode film, the electrode is divided into a plurality on the semiconductor film with an interval a in the first direction, and in the step of anisotropically etching the second insulating film, An insulator having a width b is formed, and an insulator is formed in a region between the divided electrodes. The distance a between the electrodes and the width b of the insulator formed on the side surface of the electrode are a < It is characterized by satisfying the relationship 2b.

  One feature of the present invention is a semiconductor device evaluation method for evaluating characteristics of a thin film transistor based on characteristics of a semiconductor element. The semiconductor element manufacturing process and the thin film transistor manufacturing process include an island-shaped semiconductor film. A first insulating film in contact with the semiconductor film is formed, a conductive film is formed to cover the semiconductor film and the first insulating film, the conductive film is etched, and the semiconductor film is interposed through the first insulating film. And an impurity element is added to the semiconductor film using the electrode as a mask, an impurity region is formed, a second insulating film is formed to cover the electrode and the semiconductor film, and the second insulating film is formed differently. Isotropic etching is performed to expose a part of the semiconductor film, and after forming a metal film in contact with the exposed part of the semiconductor film, a heat treatment is performed to form a metal silicide layer on the exposed part of the semiconductor film. Have both processes to form In the step of etching the conductive film, the semiconductor element is divided into a plurality of electrodes in the first direction with an interval a in the step of etching the conductive film, and in the step of anisotropically etching the second insulating film, An insulator having a width b is formed on the side surface of the electrode, and an insulator is formed in a region between the divided electrodes. The distance a between the electrodes and the width of the insulator formed on the side surface of the electrode b satisfies the relationship of a <2b, a voltage at which the semiconductor film under the electrode of the semiconductor element becomes non-conductive is applied to the electrode, and the resistance of the semiconductor film of the semiconductor element is measured to reduce the resistance of the impurity region. The characteristics of the thin film transistor are evaluated based on the obtained resistance of the impurity region.

  One of the characteristics of the present invention is that a semiconductor film having an impurity region, an insulating film formed so as to be in contact with the semiconductor film and exposing a part of the impurity region, and the semiconductor film overlap with each other through the insulating film; On the semiconductor film, an electrode divided into a plurality at intervals a in the first direction, an insulator having a width b formed on a side surface of the electrode, and an insulator formed in a region between the divided electrodes And a metal silicide layer formed on the exposed portion of the impurity region, and the interval a between the electrodes and the width b of the insulator formed on the side surface of the electrodes satisfy the relationship of a <2b. It is characterized by being.

  One of the features of the present invention is a semiconductor device including a semiconductor element and a thin film transistor. The semiconductor element and the thin film transistor are in contact with the semiconductor film having the impurity region and part of the impurity region is exposed. An insulating film formed in such a manner, an electrode that overlaps the semiconductor film with the insulating film interposed therebetween, and a metal silicide layer formed in an exposed portion of the impurity region. The electrode is divided into a plurality of pieces with a distance a in the first direction, and has an insulator of width b formed on the side surface of the electrode and an insulator formed in a region between the divided electrodes. The distance a between the electrodes and the width b of the insulator formed on the side surfaces of the electrodes satisfy the relationship of a <2b.

According to the present invention, in a TFT manufacturing process in which an impurity region is metal-silicided, an evaluation semiconductor element having a Si region in which a part of the impurity region is not metal-silicided can be formed without increasing the number of steps. it can. By using this semiconductor element and measuring under certain specific measurement conditions, the resistance of the impurity region of Si can be measured, process defects can be easily found, and feedback to the process is facilitated.

The present invention can form a Si region in which the impurity region is not metal-silicided while the impurity region is metal-silicided without increasing the number of steps. By using the impurity region as a resistance element of the circuit, the circuit size can be easily reduced.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention should not be construed as being limited to the description of the embodiment modes.

Further, Embodiments 1 to 7 shown below can be freely combined within a practicable range.
(Embodiment 1)

A structure of a thin film transistor (TFT) and a semiconductor element used for an evaluation element (TEG) and a manufacturing method thereof will be described below with reference to FIGS. In each drawing, (a), (b), and (c) are cross-sectional views showing a manufacturing process of a TFT, (b) is a cross-sectional view showing a manufacturing process of a TEG, and (c) is a drawing of a TEG. It is a top view which shows a manufacturing process. (A) and (b) are different in how to cut the cross section, (a) shows a cross-sectional view in the channel length direction, whereas (b) shows the channel width direction (when TEG is regarded as a TFT) ). That is, (b) is a cross-sectional view taken along the line AA ′ in (c), whereas (a) is a cross-sectional view taken along the line AA ′ in (c).
The TEG used for the process evaluation of the semiconductor device of this embodiment includes a semiconductor film having an impurity region, an insulating film in contact with the semiconductor film, and overlaps with the semiconductor film through the insulating film. An electrode divided into a plurality at intervals a in the direction; an insulator having a width b formed on a side surface of the electrode; and an insulator formed in a region between the divided electrodes. And the width b of the insulator formed on the side surface of the electrode satisfy the relationship of a <2b.

First, as shown in FIGS. 1A, 1 </ b> B, and 1 </ b> C, a base insulating film 112 is formed to a thickness of 100 to 300 nm on a substrate 111. As the substrate 111, a glass substrate, a quartz substrate, a plastic substrate, an insulating substrate such as a ceramic substrate, a metal substrate, a semiconductor substrate, or the like can be used.

The base insulating film 112 includes silicon oxide (SiO _x ), silicon nitride (SiN _x ), silicon oxide containing nitrogen (SiO _x N _y ) (x> y) (also referred to as silicon oxynitride), silicon nitride containing oxygen ( A single-layer structure of an insulating film containing oxygen or nitrogen such as SiN _x O _y ) (x> y) (also referred to as silicon nitride oxide) or a stacked structure thereof can be used. In particular, when there is a concern about contamination from the substrate, it is preferable to form a base insulating film.

Alternatively, the surface of the glass substrate may be directly treated with high-density plasma excited by microwaves, having an electron temperature of 2 eV or less, an ion energy of 5 eV or less, and an electron density of about 10 ¹¹ to 10 ¹³ / cm ^3. . Plasma generation can be performed using a microwave-excited plasma processing apparatus using a radial slot antenna. At this time, when a nitride gas such as nitrogen (N ₂ ), ammonia (NH ₃ ), or nitrous oxide (N ₂ O) is introduced, the surface of the glass substrate can be nitrided. Since the nitride layer formed on the surface of the glass substrate contains silicon nitride as a main component, it can be used as a blocking layer for impurities diffused from the glass substrate side. A silicon oxide film or a silicon oxynitride film may be formed over the nitride layer by a plasma CVD method to form the base insulating film 112.

In addition, by performing similar plasma treatment on the surface of the base insulating film 112 using silicon oxide, silicon oxynitride, or the like, the surface and the depth of 1 to 10 nm can be nitrided from the surface. This very thin silicon nitride layer can be used as a blocking layer without affecting the semiconductor layer formed thereon.

The base insulating film 112 in contact with the semiconductor film is preferably a silicon nitride film or a silicon nitride oxide film with a thickness of 0.01 to 10 nm, preferably 1 to 5 nm. In a later crystallization process, when a method of adding a metal element to a semiconductor film to crystallize is used, it is necessary to getter the metal element. At this time, if the base insulating film is a silicon oxide film, a metal element in the silicon film and oxygen in the silicon oxide film react with each other at the interface between the silicon oxide film and the silicon film of the semiconductor film to form a metal oxide. Thus, the metal element may be difficult to getter. Therefore, the base insulating film portion in contact with the semiconductor film is preferably a layer that is not a silicon oxide film. As the base insulating film, a film with a small fixed charge is preferably used.

Subsequently, a semiconductor film is formed to 10 to 100 nm. The material of the semiconductor film can be selected according to the characteristics required for the TFT, and may be any of a silicon film, a silicon germanium film, and a silicon carbide film. As the semiconductor film, an amorphous semiconductor film or a microcrystalline semiconductor film is preferably used, and a crystalline semiconductor film crystallized by a laser crystallization method using an excimer laser or the like is preferably used. The microcrystalline semiconductor film can be obtained by glow discharge decomposition of a hydride of silicon such as SiH ₄ . By using silicon hydride diluted with hydrogen or a rare gas element of fluorine, a microcrystalline semiconductor film can be easily formed.

Further, as a crystallization technique, a rapid thermal annealing method (RTA method) using a halogen lamp or a technique for crystallization using a heating furnace can be applied. Further, a method may be used in which a metal element such as nickel is added to the amorphous semiconductor film and solid phase growth is performed using the added metal as a crystal nucleus.

Next, the semiconductor film is patterned to form an island-shaped semiconductor film 113. A first insulating film 114 is formed to have a thickness of 5 to 50 nm so as to cover the island-shaped semiconductor film 113. The first insulating film is in contact with the island-shaped semiconductor film and functions as a gate insulating film.

As the first insulating film 114, silicon oxide (SiO _x ), silicon nitride (SiN _x ), silicon oxide containing nitrogen (SiO _x N _y ) (x> y), or nitride containing oxygen is formed by CVD or sputtering. Any of silicon (SiN _x O _y ) (x> y) and the like may be appropriately combined to form a stacked structure. By radical a low electron temperature in the high density plasma, silicon oxide _(SiO x), silicon nitride _(SiN x), nitrogen oxide silicon containing _{(SiO x N y) (x} > y), silicon nitride containing oxygen (SiN _x Any of O _y ) (x> y) and the like may be appropriately combined to form a stacked structure. In the present embodiment, the first insulating film 114 has a stacked structure of a SiN _x O _y film and a SiO _x N _y film. In this case, the surface of the insulating film is excited by microwaves similarly to the above, and the electron temperature is 2 eV or less, the ion energy is 5 eV or less, and the electron density is about 10 ¹¹ to 10 ¹³ / cm ^3. It may be densified by oxidation or nitridation by plasma treatment. This treatment may be performed prior to the formation of the first insulating film 114. That is, plasma treatment is performed on the surface of the semiconductor film 113. At this time, the substrate temperature is set to 300 to 450 ° C., and the treatment is performed in an oxidizing atmosphere (O ₂ , N ₂ O, etc.) or a nitriding atmosphere (N ₂ , NH _3, etc.), so that an insulating film deposited thereon is excellent. An interface can be formed.

Subsequently, a conductive film 115 serving as an electrode is formed over the first insulating film 114. As the conductive film 115, an aluminum (Al) film, a copper (Cu) film, a film containing aluminum or copper as a main component, a chromium (Cr) film, a tantalum (Ta) film, a tantalum nitride (TaNx) film, titanium (Ti) ) Film, tungsten (W) film, tungsten nitride (WNx) film, molybdenum (Mo) film, laminated film in which the films are laminated, for example, laminated film of Al film and Ta film, laminated film of Al film and Ti film A stacked layer of a TaN film and a W film can be used. In this embodiment, the conductive film 115 is a stacked film of tantalum nitride (TaNx) 30 nm and tungsten (W) 370 nm on tantalum nitride.

Subsequently, a photomask is used over the conductive film 115, and a mask 116 is formed using a photolithography technique (FIGS. 1A, 1B, and 1C).
The mask 116 has different shapes for the TFT and the TEG. Although the TFT mask 116 is not divided in the first direction (direction connecting AA ′) on the semiconductor film, the TEG mask 116 connects the first direction (AA ′) on the semiconductor film. It is divided into a plurality at intervals in the direction).

Subsequently, the conductive film 115 is etched using the mask 116 to form the electrode 117. (FIG. 2 (a) (b) (c)).
In this step, the TFT electrode 117 and the TEG electrode 117 are formed in different shapes. The TEG electrode 117 is divided into a plurality on the semiconductor film at intervals a in the first direction (a direction connecting AA ′). On the other hand, the electrode 117 of the TFT is not divided in the first direction (direction connecting AA ′) on the semiconductor film.

In this embodiment mode, the mask 116 is used to etch tungsten (W) in the stacked film of the tantalum nitride (TaNx) 30 nm \ tungsten (W) 370 nm in the conductive film 115. In the first etching, it is preferable to perform etching under an etching condition having a high selectivity with respect to tantalum nitride (TaNx) 30 nm. In the first etching, a mixed gas of CF ₄ , Cl ₂ , and O ₂ is used as an etching gas, and the mixing ratio is CF ₄ / Cl ₂ / O ₂ = 60/50/45 sccm. Plasma is generated by supplying 2000 W of power to the coil-type electrode at a pressure of 0.67 Pa. A power of 150 W is applied to the substrate side (sample stage). The temperature of the sample stage is −10 ° C. Note that the mask 116 preferably has a vertical shape. When the first etching is performed, an etching reaction product adheres to the sidewall of the mask 116. The reaction product is infiltrated at 60 ° C. for 10 minutes using a chemical solution (trade name: SPR301) containing oxalic acid as a main component to remove the reaction product. Subsequently, the mask is removed by invading the stripping solution. Subsequently, tantalum nitride (TaNx) is etched using tungsten (W) as a mask. The electrode 117 is formed by the second etching. At this time, it is preferable to perform etching under an etching condition having a high selectivity with respect to the first insulating film 114 so that the first insulating film 114 is not etched. Further, it is preferable to perform etching under an etching condition having a high selectivity with respect to tungsten (W) so as not to etch tungsten (W). The second etching condition is that plasma is generated by supplying power of 1000 W to the coil-type electrode at a pressure of 2.00 Pa. A power of 50 W is applied to the substrate side (sample stage). Etching gas is Cl _2. The temperature of the sample stage is −10 ° C.

The vertical electrode shape is obtained by the above process. This electrode 117 functions as a gate electrode.

The etching in this embodiment mode can be performed by dry etching, and can be performed by using an ICP (Inductively Coupled Plasma) etching method.

Next, an impurity element is added to the island-shaped semiconductor film 113. In this embodiment mode, the island-shaped semiconductor film 113 is doped with high-concentration impurity ions 118 (FIGS. 3A, 3B, and 3C). FIG. 3B is a cross-sectional view taken along the line AA ′ of FIG. High-concentration impurity regions 119a, 119b, and 119c are formed by doping the island-shaped semiconductor film 113 with a high-concentration impurity element through the first insulating film. The element concentration of the high-concentration impurity regions 119a, 119b, and 119c is 1 × 10 ¹⁸ to 1 × 10 ²² atoms / cm ³ (preferably 1 × 10 ^{19 to} 5 × 10 ²⁰ atoms / cm ³ ). As a doping method, an ion doping method or an ion implantation method can be used. For example, boron (B), gallium (Ga), or the like is used as an impurity element when a P-type semiconductor is manufactured, and phosphorus (P), arsenic (As), or the like is used when an N-type semiconductor is manufactured. .

Next, a second insulating film is formed so as to cover the first insulating film 114 and the electrode 117. As the second insulating film, a silicon oxide film containing nitrogen (SiO _x N _y film) (x> y) is formed to 100 nm by a plasma CVD method, and then a silicon oxide film (SiO ₂ film) is formed to a thickness of 200 nm by a thermal CVD method. Form. As the second insulating film, a silicon oxide film (SiO _x N _y film) may be formed from a TEOS / O ₂ material by plasma CVD.

Next, the second insulating film is selectively etched by anisotropic etching mainly in the vertical direction, so that the insulator 120 in contact with the side surface of the electrode 117 and the region between the divided electrodes 120 are separated. (FIGS. 4A, 4B, and 4C). In this step, the upper surface of the electrode 117 is exposed. However, an insulating film used as a mask may be formed over the electrode 117, and in this case, the upper surface of the electrode 117 may not be exposed. The insulator formed on the side surface of the electrode can be formed with a width b of 10 nm to 300 nm. The width b is the width of the insulator formed on the side surface of the electrode other than the region between the divided electrodes.
The interval “a” between the plurality of divided electrodes 117 having the configuration shown in FIG. 2B may be smaller than twice the width “b” of the insulator formed on the side surface of the electrode. In other words, the distance a between the divided electrodes and the width b of the insulator formed on the side surface of the electrode need only satisfy the relationship of a <2b. If the relationship of a <2b is satisfied, the region between the electrodes divided into a plurality of portions is still covered with an insulator even after the anisotropic etching step. Therefore, the region between the plurality of divided electrodes is not converted into a metal silicide in a later process.
The insulator 120 formed on the side surface of the electrode serves as a sidewall and is used as a mask when forming silicide later. Further, part of the first insulating film is also removed by this etching step to form the insulating film 121, and a part of the semiconductor film is exposed. The step of removing the first insulating film and exposing the semiconductor film is performed using the electrode, the insulator in contact with the side surface of the electrode, and the insulator formed in a region between the divided electrodes as a mask. This exposed semiconductor film portion later becomes a source region and a drain region. The insulating film 121 functions as a gate insulating film. In the case where the etching selectivity between the insulating film and the semiconductor film is low, the exposed semiconductor film is slightly etched and thinned.

Note that the impurity region may be thermally activated before the insulator is formed or after the insulator is formed. Activation may be performed by a method such as laser light irradiation, RTA, or heat treatment using a furnace. In addition, since this structure is in contact with the wiring by silicide, the step of thermally activating the impurity region can be omitted.

    Next, after removing the natural oxide film formed on the exposed surface of the semiconductor film, a metal film 122 is formed (FIGS. 5A, 5B, and 5C). The metal film 122 is made of a material that forms silicide by reacting with the semiconductor film. Examples of the metal film include a nickel film, a titanium film, a cobalt film, a platinum film, or a film made of an alloy containing at least two of these elements. In this embodiment, a nickel film is used as the metal film 122, and a nickel film is formed by sputtering at a film formation power of 500 W to 1 kW at room temperature.

After the nickel film is formed, the silicide layer 123 is formed by heat treatment. The silicide layer 123 is nickel silicide here. As the heat treatment, RTA, furnace annealing, or the like can be used. Next, unreacted nickel is removed. Here, unreacted nickel is removed using an etching solution of HCl: HNO ₃ : H ₂ O = 3: 2: 1. When unreacted nickel is removed, the silicide layer 123 remains only in a region where the impurity region is exposed and exposed. (Fig. 6 (a) (b) (c))

Thereafter, an interlayer insulating film 124 is formed (FIGS. 7A, 7B, and 7C). The interlayer insulating film 124 is formed using an organic material or an inorganic material. The interlayer insulating film 124 may have a single layer structure or a stacked structure. A contact hole 125 for exposing the silicide layer 123 is formed in the interlayer insulating film 124 by etching. Next, a conductive layer is formed so as to fill the contact hole, and the wiring 126 is formed by etching. FIG. 7B is a cross-sectional view taken along the line A-A ′ of FIG. FIG. 7D is a B-B ′ cross section of FIG. 7C, and FIG. 7E is a C-C ′ cross section of FIG.

Note that the impurity region may be thermally activated before the interlayer insulating film is formed or after the first or second film is formed if the interlayer insulating film is a stacked layer. For thermal activation, methods such as laser light irradiation, RTA, and heat treatment using a furnace can be used. In addition, since this structure is in contact with the wiring by silicide, the step of thermally activating the impurity region can be omitted.

6A, 6B, and 6C, the high-concentration impurity regions 119a and 119b are silicided as shown in FIGS. 6A, 6B, and 6C, but 119c is a region between the divided electrodes. Is not silicided. In the structure of this embodiment mode, a region to be silicided and a region not to be silicided can be formed without increasing the number of steps.

    In addition, as shown in FIGS. 5A, 5B, and 5C, the metal film 122 is formed after forming the insulator in contact with the side surface of the electrode, but the present invention is not limited to this method. A mask may be used instead of the insulator in contact with the side surface of the electrode. The method will be described with reference to FIGS. After doping the impurity ions in FIG. 3, a mask 127 is formed so as to cover the electrode 117 and the region between the plurality of divided electrodes (FIGS. 8A, 8B, and 8C). As the mask 127, an insulating film such as a silicon oxide film, a resist mask, or the like can be used. After that, etching is performed to remove part of the first insulating film to expose part of the semiconductor film, so that the insulating film 121 is formed. The exposed portion of the semiconductor film later becomes a source region and a drain region. The insulating film 121 functions as a gate insulating film.

Next, as shown in FIGS. 9A, 9B, and 10C and FIGS. 10A, 10B, and 10C, a metal film 122 is formed, and the exposed semiconductor film portion is silicided by heat treatment. Layer 123 is formed. Thereafter, the unreacted metal film is removed. Thereafter, an interlayer insulating film 124 is formed, and a wiring 126 is formed, resulting in the configuration of FIGS. 11 (a), 11 (b), and 11 (c). Although the structure in which the mask 127 is left as it is is illustrated, the mask 127 may be removed after the silicide is formed. FIG. 11D is a B-B ′ cross section in FIG. 11C, and FIG. 11E is a C-C ′ cross section in FIG.

The method of using a mask instead of using an insulator formed on the side surfaces of electrodes and regions between divided electrodes by anisotropic etching is not limited to this embodiment, and also in Embodiments 2, 3, and 4 to be described later. Applicable.

As described above, in the semiconductor device including the TFT manufactured in this embodiment, the number of steps of a semiconductor element having a TFT in which the impurity region is metal silicided and a plurality of divided electrodes in which part of the impurity region is not metal silicided is increased. They can be formed on the same substrate without increasing.

A method for measuring a semiconductor element having a plurality of divided electrodes in which part of the impurity region manufactured in this embodiment is not metal-silicided will be described with reference to FIG. By using this semiconductor element, the resistance of the impurity region can be measured in a semiconductor device including a semiconductor element in which the impurity region is metal silicided. FIG. 12 shows the semiconductor element as an equivalent circuit of a TFT and a resistor.
In the top view of the semiconductor element in FIG. 7C, a region where the electrode 117 is formed on the semiconductor film (BB ′ section) corresponds to a TFT in the equivalent circuit of FIG. In the top view of the semiconductor element of FIG. 7C, a region (CC ′ cross section) in which an impurity region (119c) is formed between the plurality of divided electrodes 117 corresponds to a resistor in the equivalent circuit of FIG. To do.

    When an N-type high-concentration impurity region is formed using phosphorus (P), arsenic (As), or the like as the impurity ions 118 shown in FIG. 3, the TFT of the equivalent circuit shown in FIG. 12 becomes an N-type TFT. When the N-type TFT is formed, a negative voltage is applied to the terminal 2 so that the N-type TFT is in a non-conducting state (off state). When the N-type TFT is in an OFF state, no current flows through the TFT portion, so that the equivalent circuit can be approximated to only the original resistance. Under this condition, the resistance value of the equivalent circuit of FIG. 12 can be obtained from the current-voltage characteristics by setting the terminal 3 to the ground (GND) and changing the voltage of the terminal 1. The condition is that the terminal 3 is set to the ground, but the voltage relationship between the terminals 1, 2, and 3 is relative, and is not limited to this condition. It is sufficient that the voltage at the terminal 2 is smaller than the voltages at the terminals 1 and 3. Further, when the threshold value of the N-type TFT is low and normally on or depletion type, the voltage of the terminal 2 is set to a value about Vth + 0.3V to Vth + 2.0V lower than the voltages of the terminal 1 and the terminal 3. It is preferable to do.

When a P-type high-concentration impurity region is formed using boron (B), gallium (Ga), or the like for the impurity ions 118 shown in FIG. 3, the TFT of the equivalent circuit shown in FIG. 12 is a P-type TFT. When a P-type TFT is formed, a positive voltage is applied to the terminal 2 so that the P-type TFT is in a non-conducting state (off state). When the P-type TFT is in the off state, no current flows through the TFT portion, so that the equivalent circuit can be approximated to only the original resistance. Under this condition, the resistance value of the equivalent circuit of FIG. 12 can be obtained from the current-voltage characteristics by setting the terminal 3 to the ground (GND) and changing the voltage of the terminal 1. The condition is that the terminal 3 is set to the ground, but the voltage relationship between the terminals 1, 2, and 3 is relative, and is not limited to this condition. The voltage at terminal 2 only needs to be greater than the voltage at terminals 1 and 3. Further, when the threshold value of the P-type TFT is low and normally on or depletion type, the voltage of the terminal 2 is set to a value about Vth + 0.3V to Vth + 2.0V higher than the voltage of the terminal 1 and the terminal 3. It is preferable to do.

According to this embodiment, in a TFT manufacturing process in which an impurity region is metal-silicided, an evaluation semiconductor element having a Si region in which a part of the impurity region is not metal-silicided is formed without increasing the number of steps. be able to. By using this semiconductor element and measuring under specific measurement conditions, the resistance of the impurity region of Si can be measured, process defects can be easily found, and feedback to the process is facilitated.

In this embodiment mode, a semiconductor element in which three TFTs and two resistors are connected in parallel is shown; however, the number of TFTs and resistors is not limited to this. The number of TFTs and resistors can be increased or decreased as necessary.
(Embodiment 2)

In this embodiment mode, a semiconductor device having a low concentration impurity region is shown in FIG. In this embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
13A is a cross-sectional view of a TFT, FIGS. 13B, 13D, and 13E are cross-sectional views of a semiconductor element (TEG), and FIG. 13C is a top view of the semiconductor element. Yes. FIG. 13B is a cross-sectional view taken along the line AA ′ of FIG. FIG.13 (d) is a BB 'cross section of FIG.13 (c), FIG.13 (e) is CC' cross section of FIG.13 (c). 13A corresponds to a cross-sectional view in the direction of BB ′ intersecting with AA ′ in FIG. 13C.

In this embodiment mode, TFTs and semiconductor elements are formed through the same steps as in Embodiment Mode 1 up to FIG. Next, low concentration impurity ions are doped using the electrode 117 as a mask to form a low concentration impurity region. The element concentration in the low concentration impurity region is 1 × 10 ¹⁶ to 1 × 10 ²⁰ atoms / cm ³ (preferably 1 × 10 ^{17 to} 5 × 10 ¹⁹ atoms / cm ³ ). As a doping method, an ion doping method or an ion implantation method can be used. For example, boron (B), gallium (Ga), or the like is used as an impurity element when a P-type semiconductor is manufactured, and phosphorus (P), arsenic (As), or the like is used when an N-type semiconductor is manufactured. .

Next, the insulator 120 in contact with the side surface of the electrode and the insulator 120 are formed in a region between the plurality of divided electrodes, and the first insulating film is etched to form a new insulating film 121. At this time, when the etching selectivity between the insulating film and the semiconductor film is small, the semiconductor film that is not covered with the insulator 120 is slightly etched simultaneously with the formation of the insulating film 121, and the film thickness is reduced.

Next, a high concentration impurity region 404 is formed by doping high concentration impurity ions using the electrode 117 and the insulator 120 as a mask. A low concentration impurity region 405 is formed by doping with high concentration impurity ions. The element concentration of the high-concentration impurity region 404 is 1 × 10 ¹⁹ to 1 × 10 ²¹ atoms / cm ³ . As a doping method, an ion doping method or an ion implantation method can be used. For example, boron (B), gallium (Ga), or the like is used as an impurity element when a P-type semiconductor is manufactured, and phosphorus (P), arsenic (As), or the like is used when an N-type semiconductor is manufactured. .

Next, after forming the silicide layer 123, the interlayer insulating film 124 and the wiring 126 are formed to obtain the configuration of FIG.

Although not shown, the structure of the semiconductor element of this embodiment may be formed by forming the mask 127 without forming the insulator 120 as in the first embodiment.

Through the above steps, a TFT having a low-concentration impurity region 405 (a Loff region that is not disposed so as to overlap with an electrode through an insulating film) is completed. Since the TFT formed in this embodiment has a Loff region, a short channel effect that occurs when the gate length is shortened can be suppressed.

As described above, in the semiconductor device including the TFT manufactured in this embodiment, the TFT having the source region, the drain region, and the Loff region in which the high concentration impurity region is converted into metal silicide and the semiconductor element in which the low concentration impurity region is not converted into metal silicide. They can be formed on the same substrate without increasing the number of steps.

A method for measuring a semiconductor element in which the low-concentration impurity region manufactured in this embodiment is not metal-silicided is the same as that described in Embodiment 1, and thus description thereof is omitted here.

According to this embodiment, in a TFT manufacturing process in which an impurity region is metal-silicided, an evaluation semiconductor element having a Si region in which a part of the impurity region is not metal-silicided is formed without increasing the number of steps. be able to. By using this semiconductor element and measuring under specific measurement conditions, the resistance of the impurity region of Si can be measured, process defects can be easily found, and feedback to the process is facilitated.
(Embodiment 3)

In this embodiment mode, a semiconductor device including a TFT having a low-concentration impurity region (Lov region) which is disposed so as to overlap with an electrode with an insulating film interposed therebetween is shown in FIG. In the present embodiment, the same reference numerals are used for the same components as in the first and second embodiments, and detailed description thereof is omitted.
14A is a cross-sectional view of a TFT, FIGS. 14B, 14D, and 14E are cross-sectional views of a semiconductor element (TEG), and FIG. 14C is a top view of the semiconductor element (TEG). Is shown. FIG. 14B is an AA ′ cross section of FIG. 14D is a BB ′ cross section of FIG. 14C, and FIG. 14E is a CC ′ cross section of FIG. 14C. 14A corresponds to a cross-sectional view in the direction of BB ′ intersecting with AA ′ in FIG. 14C.

In this embodiment mode, TFTs and semiconductor elements are formed in the same process as in Embodiment Mode 1 until the first insulating film is formed so as to cover the island-shaped semiconductor film.
Next, a first conductive film to be an electrode and a second conductive film are formed over the first insulating film and the first conductive film. First, the first conductive film is formed to 5 to 50 nm. As the first conductive film, an aluminum (Al) film, a copper (Cu) film, a film containing aluminum or copper as a main component, a chromium (Cr) film, a tantalum (Ta) film, a tantalum nitride (TaN) film, titanium A (Ti) film, a tungsten (W) film, a molybdenum (Mo) film, or the like can be used. A second conductive film is formed thereon with a thickness of 150 to 500 nm. As the second conductive film, for example, a chromium (Cr) film, a tantalum (Ta) film, a film containing tantalum as a main component, or the like can be used. However, the first conductive film and the second conductive film must be combined so that a selectivity can be obtained in the mutual etching. For example, Al \ Ta, Al \ Ti, TaN \ W can be used as a combination of the first conductive film \ second conductive film capable of providing a selective ratio. In this embodiment mode, the first conductive film is TaN and the second conductive film is W.

Subsequently, a photomask is used over the second conductive film, and a mask made of resist is formed using a photolithography technique. This mask has different shapes for the TFT and the TEG. The TFT mask is not divided in the first direction (direction connecting AA ′) on the semiconductor film, but the TEG resist is in the first direction (direction connecting AA ′) on the semiconductor film. It is divided into a plurality at intervals.
Subsequently, the second conductive film and the first conductive film are etched into substantially the same first shape by using a resist mask.
In this step, the first and second conductive films of the TFT and the first and second conductive films of the semiconductor element (TEG) are formed in different shapes. The first and second conductive films of the TEG are divided into a plurality of parts in the first direction (direction connecting AA ′) on the semiconductor film. On the other hand, the first and second conductive films of the TFT are not divided in the first direction (direction connecting AA ′) on the semiconductor film.
For etching the second conductive film, a mixed gas of Cl ₂ , SF ₆ , and O ₂ is used as an etching gas, and the mixing ratio is Cl ₂ / SF ₆ / O ₂ = 33/33/10 sccm. Plasma is generated by supplying 2000 W of power to the coil-type electrode at a pressure of 0.67 Pa. A power of 50 W is applied to the substrate side (sample stage).
In the etching of the first conductive film, plasma is generated by supplying power of 2000 W to the coil-type electrode at a pressure of 0.67 Pa. A power of 50 W is applied to the substrate side (sample stage). Etching gas is Cl _2.

Next, 2000 W of electric power is supplied to the coil-type electrode at a pressure of 1.33 Pa to generate plasma. No power is supplied to the substrate side (sample stage). The etching gas is a mixed gas of Cl ₂ , SF ₆ and O ₂ , and the mixing ratio is Cl ₂ / SF ₆ / O ₂ = 22/22/30 sccm. In this etching, the resist mask is retracted to reduce the width of the mask. At the same time, using the resist that recedes as a mask, the gate length of the second conductive film is also receded and etched into the second shape. At this time, the first conductive film is not etched and remains substantially in the first shape.

Through the above steps, an electrode shape is obtained in which the lower gate length is longer than the upper gate length as shown in FIG. The electrode shape of this embodiment is formed by utilizing the resist recession width at the time of etching.
In this step, the TEG has an electrode made of a plurality of first and second conductive films divided into a plurality, and the electrode 117 is formed with an interval a with respect to the second conductive film.

In the manufacturing method of the electrode 117 in which the gate length of the lower layer in this embodiment is longer than the gate length of the upper layer, the electrode 117 includes the first conductive film 511 in the lower layer and the second conductive film 512 in the upper layer. The difference between the gate length of the first conductive film 511 and the gate length of the second conductive film 512 (Lov length) can be set to 20 to 200 nm, and a very fine electrode structure can be formed.

The etching in this embodiment mode can be performed by dry etching, and can be performed by using an ICP (Inductively Coupled Plasma) etching method.

Next, the island-shaped semiconductor film 113 is doped with low-concentration impurity ions. The island-shaped semiconductor film 113 is doped with a low-concentration impurity element through the first conductive film 511 and the first insulating film, and a low-concentration impurity region is formed in the island-shaped semiconductor film portion overlapping the first conductive film. 509 is formed. At the same time, only the first insulating film is allowed to pass through, and an impurity element is doped into both end portions of the island-shaped semiconductor film to form a low concentration impurity region. The element concentration of the low concentration impurity region is 1 × 10 ¹⁶ to 1 × 10 ²⁰ atoms / cm ³ (preferably 1 × 10 ^{16 to} 5 × 10 ¹⁹ atoms / cm ³ ). As the acceleration voltage, a voltage at which impurity ions can pass through the first conductive film and the first insulating film is used. For example, 50 kV to 90 kV (preferably 60 kV to 80 kV) is used. As a doping method, an ion doping method or an ion implantation method can be used. For example, boron (B), gallium (Ga), or the like is used as an impurity element when a P-type semiconductor is manufactured, and phosphorus (P), arsenic (As), or the like is used when an N-type semiconductor is manufactured. .

The doping to the low concentration impurity region 509 is performed not only through the first insulating film but also through the first conductive film 511. Therefore, the concentration of the impurity element in the low concentration impurity region 509 is lower than that of other low concentration impurity regions.

Next, high-concentration impurity regions 513 are formed by doping the island-shaped semiconductor film 113 with high-concentration impurity ions using the electrode 117 including the first conductive film 511 and the second conductive film 512 as a mask. The element concentration of the high-concentration impurity region 513 is 1 × 10 ¹⁸ to 1 × 10 ²² atoms / cm ³ (preferably 1 × 10 ^{19 to} 5 × 10 ²⁰ atoms / cm ³ ). As the acceleration voltage, the lower element concentration in the island-shaped semiconductor film 113 is set to 1 × 10 ¹⁷ to 1 × 10 ²⁰ atoms / cm ³ (preferably 1 × 10 ^{18 to} 5 × 10 ¹⁹ atoms / cm ³ ). Therefore, 10 kV to 20 kV is used. In this embodiment, 10 kV is used. As a doping method, an ion doping method or an ion implantation method can be used. For example, boron (B), gallium (Ga), or the like is used as an impurity element when a P-type semiconductor is manufactured, and phosphorus (P), arsenic (As), or the like is used when an N-type semiconductor is manufactured. .

Next, a second insulating film is formed so as to cover the first insulating film and the electrode 117. As the second insulating film, a silicon oxide film containing nitrogen (SiO _x N _y film) (x> y) is formed to 100 nm by plasma CVD, and then a silicon oxide film (SiO ₂ film) is formed to 200 nm by thermal CVD. To form. As the insulating film, a silicon oxide film (SiO _x N _y film) may be formed by plasma CVD using a TEOS / O ₂ system.

Next, the second insulating film is selectively etched by anisotropic etching mainly in the vertical direction, so that the insulator 120 in contact with the side surface of the electrode 117 and the region between the divided electrodes 120 are separated. Form. The insulator formed on the side surface of the electrode can be formed with a width b of 10 nm to 300 nm with reference to the second conductive film.
The interval a between the divided electrodes 117 may be smaller than twice the width b of the insulator formed on the side surface of the electrode. In other words, the distance a between the divided electrodes and the width b of the insulator formed on the side surface of the electrode need only satisfy the relationship of a <2b. Note that the distance a and the width b are values based on the second conductive film. If the relationship of a <2b is satisfied, the region between the electrodes divided into a plurality of portions is still covered with an insulator even after the anisotropic etching step. Therefore, the region between the plurality of divided electrodes is not converted into a metal silicide in a later process.
The insulator 120 formed on the side surface of the electrode serves as a sidewall and is used as a mask when forming silicide later. Further, part of the first insulating film is also removed by this etching step to form the insulating film 121, and a part of the semiconductor film is exposed. The step of removing the first insulating film and exposing the semiconductor film is performed using the electrode, the insulator in contact with the side surface of the electrode, and the insulator formed in a region between the divided electrodes as a mask. This exposed semiconductor film portion later becomes a source region and a drain region. The insulating film 121 functions as a gate insulating film. In the case where the etching selectivity between the insulating film and the semiconductor film is low, the exposed semiconductor film is slightly etched and thinned.

Next, after the silicide layer 123 is formed, the interlayer insulating film 124 and the wiring 126 are formed to obtain the configuration of FIG.

Although not shown, the structure of the TFT of this embodiment may be formed by forming the mask 127 without forming the insulator 120 as in the first embodiment.

Through the above steps, a TFT having a low-concentration impurity region 509 as a Lov region is completed. Since the TFT formed in this embodiment has a Lov region, a short channel effect that occurs when the gate length is shortened can be suppressed.

As described above, in the semiconductor device including the TFT manufactured in this embodiment, the TFT having the source region, the drain region, and the Lov region in which the high-concentration impurity region is converted into metal silicide and the semiconductor element in which the impurity region is not converted into metal silicide are processed. Can be formed on the same substrate without increasing.

Since the measurement method of the semiconductor element in which the impurity region manufactured in this embodiment is not metal-silicided is the same as that described in Embodiment 1, the description thereof is omitted here.

According to this embodiment, in a TFT manufacturing process in which an impurity region is metal-silicided, an evaluation semiconductor element having a Si region in which a part of the impurity region is not metal-silicided is formed without increasing the number of steps. be able to. By using this semiconductor element and measuring under specific measurement conditions, the resistance of the impurity region of Si can be measured, process defects can be easily found, and feedback to the process is facilitated.

(Embodiment 4)
In this embodiment mode, a low concentration impurity region (Lov region) arranged so as to overlap with the electrode through the insulating film and a low concentration impurity region (Loff region) not arranged so as to overlap with the electrode through the insulating film are formed. The structure having the above will be described with reference to FIG. In this embodiment, the same reference numerals are used for the same components as in the first to third embodiments, and detailed description thereof is omitted.
15A is a cross-sectional view of a TFT, FIGS. 15B, 15D, and 15E are cross-sectional views of a semiconductor element (TEG), and FIG. 15C is a top view of the semiconductor element (TEG). Is shown. FIG. 15B is an AA ′ cross section of FIG. 15D is a BB ′ cross section of FIG. 15C, and FIG. 15E is a CC ′ cross section of FIG. 15C. FIG. 15A corresponds to a cross-sectional view in the direction of BB ′ intersecting with AA ′ in FIG. 15C.

This embodiment is a process similar to that of Embodiment 3 until the electrode 117 having a shape in which the gate length of the lower first conductive film 511 is longer than the gate length of the upper second conductive film 512 is formed. A TFT and a semiconductor element are formed.
Next, low concentration impurity ions are doped into the island-shaped semiconductor film. The island-shaped semiconductor film is doped with a low-concentration impurity element through the first conductive film 511 and the first insulating film, and the island-shaped semiconductor film portion overlapping the first conductive film has a low-concentration impurity region 509. Form. At the same time, only the first insulating film is allowed to pass through, and an impurity element is doped into both end portions of the island-shaped semiconductor film to form a low concentration impurity region. The element concentration of the low concentration impurity region is 1 × 10 ¹⁶ to 1 × 10 ²⁰ atoms / cm ³ (preferably 1 × 10 ^{16 to} 5 × 10 ¹⁹ atoms / cm ³ ). As the acceleration voltage, a voltage at which impurity ions can pass through the first conductive film and the first insulating film is used. For example, 50 kV to 90 kV (preferably 60 kV to 80 kV) is used. As a doping method, an ion doping method or an ion implantation method can be used. For example, boron (B), gallium (Ga), or the like is used as an impurity element when a P-type semiconductor is manufactured, and phosphorus (P), arsenic (As), or the like is used when an N-type semiconductor is manufactured. .

The doping to the low concentration impurity region 509 is performed not only through the first insulating film but also through the first conductive film 511. Therefore, the concentration of the impurity element in the low concentration impurity region 509 is lower than that of other low concentration impurity regions.

Next, the insulator 120 that is in contact with the side surface of the electrode 117 including the first conductive film 511 and the second conductive film 512 and the region between the divided electrodes are formed, and the first conductor 120 is formed. An insulating film 121 is newly formed by etching the insulating film. At this time, when the etching selectivity between the insulating film and the semiconductor film is small, the semiconductor film that is not covered with the insulator 120 is slightly etched simultaneously with the formation of the insulating film 121, and the film thickness is reduced.
The insulator in contact with the side surface of the electrode can be formed with a width b of 10 nm to 300 nm with reference to the second conductive film. The interval a between the divided electrodes 117 may be smaller than twice the width b of the insulator formed on the side surface of the electrode. In other words, the distance a between the divided electrodes and the width b of the insulator formed on the side surface of the electrode need only satisfy the relationship of a <2b. Note that the distance a and the width b are values based on the second conductive film.

Next, a high concentration impurity region 404 is formed by doping high concentration impurity ions using the electrode 117 and the insulator 120 as a mask. A low concentration impurity region 405 is formed by doping with high concentration impurity ions. The element concentration of the high-concentration impurity region 404 is 1 × 10 ¹⁹ to 1 × 10 ²¹ atoms / cm ³ . As a doping method, an ion doping method or an ion implantation method can be used. For example, boron (B), gallium (Ga), or the like is used as an impurity element when a P-type semiconductor is manufactured, and phosphorus (P), arsenic (As), or the like is used when an N-type semiconductor is manufactured. .

Next, after forming the silicide layer 123, the interlayer insulating film 124 and the wiring 126 are formed to obtain the configuration of FIG.

Although not shown, the structure of the semiconductor element of this embodiment may be formed by forming the mask 127 without forming the insulator 120 as in the first embodiment.

Through the above steps, a TFT having a Lov region and a Loff region is completed. Since the TFT formed in this embodiment has a Lov region and a Loff region, the short channel effect that occurs when the gate length is shortened can be further suppressed.

As described above, in the semiconductor device including the TFT manufactured in this embodiment, the TFT having the source region, the drain region, the Lov region, and the Loff region in which the high concentration impurity region is converted into metal silicide and the low concentration impurity region are not converted into metal silicide. Semiconductor elements can be formed on the same substrate without increasing the number of steps.

A method for measuring a semiconductor element in which the low-concentration impurity region manufactured in this embodiment is not metal-silicided is the same as that described in Embodiment 1, and thus description thereof is omitted here.

According to this embodiment, in a TFT manufacturing process in which an impurity region is metal-silicided, an evaluation semiconductor element having a Si region in which a part of the impurity region is not metal-silicided is formed without increasing the number of steps. be able to. By using this semiconductor element and measuring under specific measurement conditions, the resistance of the impurity region of Si can be measured, process defects can be easily found, and feedback to the process is facilitated.

(Embodiment 5)
In the first, second, third, and fourth embodiments, the example in which the semiconductor element manufactured at the same time as the TFT is used as the evaluation element (TEG) is shown. However, in this embodiment, the semiconductor element is used as it is as the resistance element of the circuit. Indicates.
A circuit using a semiconductor element in which part of an impurity region of Si formed by using the first, second, third, or fourth embodiment is not metal-silicided will be described.

In this embodiment, an example in which a semiconductor element is used for a delay circuit will be described; however, the present invention is not limited to the above, and can be used as a resistance of various circuits.

A delay circuit using a resistance element formed by doping N-type impurity ions will be described with reference to FIG. A terminal 501 is an input terminal, a terminal 502 is an output terminal, and an element 503 is a semiconductor element formed by using the first, second, third, or fourth embodiment, and is represented by an equivalent circuit of a TFT and a resistor. Since the TFT in the element 503 is an N-type TFT, the gate electrode is connected to the ground (GND), and the TFT is turned off. When the TFT is in an OFF state, no current flows through the TFT portion, so that the equivalent circuit can be approximated to only the original resistance. Therefore, the element 503 can be used as a resistance element by turning off the TFT.
A signal input from the terminal 501 passes through the element 503 and the capacitor 505 in FIG.

The potential of the signal input from the terminal 501 is zero or more. If the TFT in the element 503 is an enhancement type TFT shown in FIG. 17A, the TFT is always turned off even if the input signal changes. In the configuration of the depletion type TFT shown in FIG. 17B, even when the potential of the input signal is almost zero, a current may flow through the TFT portion. In this case, there is no problem if the resistance in the element 503 is large. However, if the resistance in the element 503 is low, the magnitude of the current flowing through the TFT portion cannot be ignored, and the resistance of the entire element 503 changes depending on the input signal. It is necessary to determine whether the configuration of the depletion type TFT or the enhancement type is based on the resistance value in the element 503.

A delay element using a resistance element formed by doping P-type impurity ions will be described with reference to FIG. A terminal 501 is an input terminal, a terminal 502 is an output terminal, and an element 504 is a semiconductor element formed by using the first, second, third, or fourth embodiment, and is represented by an equivalent circuit of a TFT and a resistor. Since the TFT in the element 504 is a P-type TFT, the gate electrode is connected to the power supply line (Vdd), and the TFT is turned off. When the TFT is in an OFF state, no current flows through the TFT portion, so that the equivalent circuit can be approximated to only the original resistance. Therefore, the element 504 can be used as a resistance element by turning off the TFT.
A signal input from the terminal 501 passes through the element 504 and the capacitor 505 in FIG.

The potential of the signal input from the terminal 501 is zero or more. If the P-type TFT in the element 504 has the enhancement-type TFT structure shown in FIG. 18A, the TFT is always turned off even if the input signal changes. In the configuration of the depletion type TFT shown in FIG. 18D, even when the potential of the input signal is almost zero, a current may flow through the TFT portion. In this case, there is no problem if the resistance in the element 504 is large. However, if the resistance in the element 504 is low, the magnitude of the current flowing through the TFT portion cannot be ignored, and the resistance of the entire element 504 changes depending on the input signal. It is necessary to determine the configuration of the depletion type TFT or the enhancement type according to the resistance value in the element 504.

According to the present invention, an Si region in which the impurity region is metal-silicided while a part of the impurity region is not metal-silicided can be manufactured without increasing the number of steps. Since a resistance element using the Si impurity region that is not metal-silicided as a resistance can be manufactured, the circuit area can be reduced by using the resistance element as a circuit resistance.

If the width W in the channel width direction of the divided electrodes is formed as narrow as possible, the circuit area may be reduced.

In the element 503, a resistance element in which three TFTs and two resistors are connected in parallel is shown; however, the number of TFTs and resistors is not limited thereto. The number of TFTs and resistors can be increased or decreased depending on the required resistance value.

(Embodiment 6)
Another example will be described in which a semiconductor element in which part of an impurity region of Si formed by using the first, second, third, or fourth embodiment is not metal-silicided is used as a resistance element of a circuit.
In the present embodiment, a low-pass filter circuit will be described. However, the present invention is not limited to the above, and the present embodiment can be used as a variable resistor of various circuits such as a high-pass filter circuit.

A low-pass filter circuit using a resistance element formed by doping N-type impurity ions will be described with reference to FIG. A terminal 801 is an input terminal, a terminal 802 is an output terminal, and an element 803 is a variable resistance element. A terminal 804 is a control terminal that controls the resistance value of the element 803. Although description is omitted, it is also possible to form a low-pass filter of FIG. 19B having a terminal 806 which is a control terminal for controlling the resistance value of the element 805 by doping P-type impurity ions in the same manner. is there.

A signal input from the terminal 801 passes through the variable resistance element 803 and the capacitor 807 in FIG. 19A and is output from the terminal 802. At that time, a low-frequency signal having a certain value or less determined from the resistance value and the capacitance value of the variable resistance element 803 is output to the terminal 802. As the TFT in the variable resistance element 803, an enhancement type TFT structure shown in FIG. 19B or a depletion type TFT can be used.

A terminal 804 is a control terminal of the variable resistance element 803, and can change the voltage from the ground (GND) to the power supply voltage (Vdd).

The variable resistance element 803 is composed of a low-concentration impurity region or a high-concentration impurity region as a resistor and a TFT. By doing so, it becomes possible to change the resistance value in an arbitrary range. It is also possible to change the resistance value within a very narrow range with respect to the resistance value of the resistor composed of the low concentration impurity region or the high concentration impurity region. It is possible to control the threshold frequency of the pass filter circuit using this resistance value change.

    In this embodiment, the threshold frequency control of the pass filter circuit using the variable resistance element has been described. However, the variable resistance element shown in this embodiment can be used for various circuits such as the delay time control of the delay circuit. it can.

According to the present invention, an Si region in which the impurity region is metal-silicided while a part of the impurity region is not metal-silicided can be manufactured without increasing the number of steps. Since a resistance element using the Si impurity region that is not metal-silicided as a resistance can be manufactured, the circuit area can be reduced by using the resistance element as a circuit resistance.

If the width W in the channel width direction of the divided electrodes is formed as narrow as possible, the circuit area may be reduced.

In the element 803, a resistance element in which three TFTs and two resistors are connected in parallel is shown; however, the number of TFTs and resistors is not limited to this. The number of TFTs and resistors can be increased or decreased depending on the required resistance value.

(Embodiment 7)
The semiconductor device described in any of Embodiments 1, 2, 3, 4, 5, and 6 can be used for manufacturing various electronic devices. Examples of such electronic devices include television devices, cameras such as video cameras and digital cameras, navigation systems, sound playback devices (car audio, audio components, etc.), personal computers, game devices, portable information terminals (mobile computers, A mobile phone, a portable game machine, an electronic book, etc.), and an image playback apparatus (specifically, a digital versatile disc (DVD)) provided with a recording medium, and a display capable of displaying the image Apparatus).

  By using the present invention, the degree of circuit integration can be improved. Further, the quality of the manufactured semiconductor device is in a good state. A specific example will be described with reference to FIG.

  FIG. 20A illustrates a display device, which includes a housing 1901, a support base 1902, a display portion 1903, speaker portions 1904, a video input terminal 1905, and the like. This display device is manufactured by using a thin film transistor, a semiconductor element, or a circuit formed by the manufacturing method described in Embodiment Modes 1 to 6 for the display portion 1903 and a driver circuit. The display device includes a liquid crystal display device, a light emitting device, and the like, and specifically includes all information display devices such as a computer, a television receiver, and an advertisement display.

  FIG. 20B illustrates a computer, which includes a housing 1911, a display portion 1912, a keyboard 1913, an external connection port 1914, a pointing mouse 1915, and the like. By using the manufacturing method described in Embodiment Modes 1 to 6, the present invention can be applied to the display portion 1912 and other circuits. Furthermore, the present invention can also be applied to semiconductor devices such as a CPU and a memory inside the main body.

FIG. 20C illustrates a mobile phone, which is a typical example of a portable information terminal. This mobile phone includes a housing 1921, a display portion 1922, a sensor portion 1924, operation keys 1923, and the like. The sensor unit 1924 includes an optical sensor element, and controls the luminance of the display unit 1922 according to the illuminance obtained by the sensor unit 1924 or controls illumination of the operation key 1923 according to the illuminance obtained by the sensor unit 1924. By doing so, the current consumption of the mobile phone can be suppressed. In the case of a mobile phone having an imaging function such as a CCD, it is detected whether or not the photographer has looked into the optical viewfinder by changing the amount of light received by the sensor unit 1924 provided near the optical viewfinder. When the photographer is looking into the optical viewfinder, power consumption can be suppressed by turning off the display portion 1922.

  Since electronic devices such as PDAs (Personal Digital Assistants, information portable terminals), digital cameras, and small game machines are portable information terminals, the display screen is small. Therefore, by forming functional circuits such as a CPU, a memory, and a sensor using the fine transistors and semiconductor elements described in the above embodiments, the size and weight can be reduced.

In addition, the TFT and the semiconductor element of the present invention can be used as a thin film integrated circuit or a non-contact type thin film integrated circuit device (also referred to as a wireless IC tag or RFID (radio frequency identification)). In addition, by attaching the IC tag to various electronic devices, the distribution route of the electronic devices can be clarified.

FIG. 20D illustrates a state where the wireless IC tag 1942 is attached to the passport 1941. A wireless IC tag may be embedded in the passport 1941. Similarly, you can attach or embed a wireless IC tag to a driver's license, credit card, banknote, coin, securities, gift certificate, ticket, traveler's check (T / C), health insurance card, resident card, family register copy, etc. it can. In this case, only information indicating authenticity is input to the wireless IC tag, and an access right is set so that information cannot be read or written illegally. This can be realized by using a memory for the TFT or the semiconductor element described in the first to sixth embodiments. By using it as a tag in this way, it becomes possible to distinguish it from a forged one.

In addition, a wireless IC tag can be used as a memory. FIG. 20E illustrates an example in which the wireless IC tag 1951 is used as a label attached to a vegetable package. Further, a wireless IC tag may be attached or embedded in the package itself. The wireless IC tag 1951 includes a production stage process such as production place, producer, date of manufacture, processing method, product distribution process, price, quantity, usage, shape, weight, expiration date, various authentication information, etc. Can be recorded. Information from the wireless IC tag 1951 is received and read by the antenna unit 1953 of the wireless reader 1952 and displayed on the display unit 1954 of the reader 1952 so that the wholesaler, retailer, and consumer can easily grasp the information. become. In addition, by setting access rights for producers, traders, and consumers, it is possible to read, write, rewrite, or erase without access rights.

The wireless IC tag can be used as follows. At the time of accounting, the fact that accounting has been completed is entered in the wireless IC tag, and a check means is provided at the exit to check whether accounting has been written on the wireless IC tag. If you try to leave the store without checking out, an alarm will sound. This method can prevent forgetting to pay and shoplifting.

Further, in consideration of customer privacy protection, the following method can be used. At the stage of accounting at the cash register, (1) lock the data input to the wireless IC tag with a password, (2) encrypt the data itself input to the wireless IC tag, (3) wireless Either the data input to the IC tag is deleted, or (4) the data input to the wireless IC tag is destroyed. These can be realized by using the memory described in the other embodiments. Then, by providing a check means at the exit, it is checked whether any of the processes (1) to (4) has been performed, or whether the wireless IC tag data has not been processed. Check for accounting. In this way, it is possible to check whether or not there is a transaction in the store, and it is possible to prevent information on the wireless IC tag from being read outside the store against the will of the owner.

Since the wireless IC tag mentioned above has a higher manufacturing cost than a conventionally used barcode, it is necessary to reduce the cost. By using the present invention, process defects can be easily found and feedback to the process is facilitated, which is effective in reducing costs. In addition, any wireless IC tag can be manufactured with high quality and no variation in performance.

  As described above, the applicable range of the semiconductor device manufactured according to the present invention is so wide that the semiconductor device manufactured according to the present invention can be used for electronic devices in various fields.

1 is a diagram showing Embodiment 1 of the present invention. 1 is a diagram showing Embodiment 1 of the present invention. 1 is a diagram showing Embodiment 1 of the present invention. 1 is a diagram showing Embodiment 1 of the present invention. 1 is a diagram showing Embodiment 1 of the present invention. 1 is a diagram showing Embodiment 1 of the present invention. 1 is a diagram showing Embodiment 1 of the present invention. 1 is a diagram showing Embodiment 1 of the present invention. 1 is a diagram showing Embodiment 1 of the present invention. 1 is a diagram showing Embodiment 1 of the present invention. 1 is a diagram showing Embodiment 1 of the present invention. 1 is a diagram showing Embodiment 1 of the present invention. The figure which shows Embodiment 2 of this invention. The figure which shows Embodiment 3 of this invention. The figure which shows Embodiment 4 of this invention. The figure which shows Embodiment 5 of this invention. The figure which shows Embodiment 5 of this invention. The figure which shows Embodiment 5 of this invention. The figure which shows Embodiment 6 of this invention. The figure which shows Embodiment 7 of this invention.

Explanation of symbols

111 Substrate 112 Underlying insulating film 113 Island-shaped semiconductor film 114 First insulating film 115 Conductive film 116 Mask 117 Electrode 118 Impurity ion 119a High-concentration impurity region 119b High-concentration impurity region 119c High-concentration impurity region 120 Insulator 121 Insulating film 122 Metal film 123 Silicide layer 124 Interlayer insulating film 125 Contact hole 126 Wiring 127 Mask 404 High concentration impurity region 405 Low concentration impurity region 501 Terminal 502 Terminal 503 Element 504 Element 505 Capacitance 509 Low concentration impurity region 511 First conductive film 512 Second Conductive film 513 High-concentration impurity region 801 Terminal 802 Terminal 803 Element 804 Terminal 805 Element 806 Terminal 807 Capacity 1901 Housing 1902 Support base 1903 Display portion 1904 Speaker portion 1905 Video input terminal 1911 Housing Body 1912 Display unit 1913 Keyboard 1914 External connection port 1915 Pointing mouse 1921 Case 1922 Display unit 1923 Operation key 1924 Sensor unit 1941 Passport 1942 Wireless IC tag 1951 Wireless IC tag 1952 Wireless reader 1953 Antenna unit 1954 Display unit

Claims (1)

A semiconductor device having a semiconductor element and a thin film transistor,
The semiconductor element is
A first semiconductor film having a first impurity region;
A first insulating film on the first semiconductor film;
A plurality of divided electrodes on the first insulating film;
A sidewall formed between the plurality of electrodes;
A metal silicide layer formed in a part of the first impurity region,
The first impurity region is formed between the plurality of electrodes,
The metal silicide layer is formed at both ends in the first direction of the first semiconductor film,
The plurality of electrodes are not divided in the first direction, but are divided in a second direction intersecting the first direction,
The thin film transistor
A second semiconductor film having a second impurity region formed in the same step as the first impurity region;
A second insulating film on the second semiconductor film;
A gate electrode on the second insulating film;
A sidewall formed on a sidewall of the gate electrode;
And a metal silicide layer formed in a part of the second impurity region.

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