JP2000114526A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture a thin-film transistor excellent in characteristic and make a semiconductor to have high performance by annealing a semiconductor film containing crystal by laser and oxidizing the semiconductor film by furnace annealing so as to reduce the thickness thereof. SOLUTION: First, an amorphous silicon film 102 and a nickel containing layer 103 are formed on a quartz substrate 101, It is heated at 550-650 deg.C for 4 to 24 hours to form a polysilicon film 104, and it is annealed by excimer laser light and further annealed at 1000 deg.C for 30 minutes in an oxidizing atmosphere in the furnace so as to form a polysilicon film 106 with a small film thickness. Next, a polysilicon film 107 with high crystallinity which is formed by furnace annealing at 1000 deg.C for two hours is patterned to form an active layer 108. Therefore, a circuit can be fabricated by such a TFT that has a semiconductor film as an active layer that has a crystallinity substantially equivalent to that of a single crystal, so that a high-performance semiconductor device can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique relating to a semiconductor device including a thin film transistor (hereinafter, referred to as a TFT) using a semiconductor thin film as a circuit and a method for manufacturing the same. Note that in this specification, a semiconductor device generally refers to a device that functions using a semiconductor.

Therefore, the term semiconductor device used in the claims includes not only a single semiconductor element such as a TFT but also a semiconductor device.
It also includes an electro-optical device having a TFT, a semiconductor circuit, and an electronic device equipped with the same.

[0003]

2. Description of the Related Art In recent years, TFTs used for electro-optical devices such as active matrix type liquid crystal display devices have been actively developed. An active matrix liquid crystal display device is a monolithic display device in which a pixel matrix circuit and a driver circuit are provided on the same substrate.

[0004] Recently, attempts have been made to form a semiconductor circuit having a function equivalent to that of a conventional IC using TFTs provided on a substrate. For example, development of a system-on-panel incorporating a logic circuit such as a gamma correction circuit, a memory circuit, and a clock generation circuit has been studied.

Since such driver circuits and logic circuits need to operate at high speed, it is inappropriate to use an amorphous semiconductor film (typically, an amorphous silicon film) as an active layer. Therefore, at present, a crystalline semiconductor film (typically, a polysilicon film) is being studied.

[0006]

SUMMARY OF THE INVENTION However, TFT
When circuit performance comparable to that of a conventional IC is required for a circuit assembled in the above, a crystalline semiconductor film formed by the conventional technology has sufficient performance to satisfy the specifications of the circuit. It has become difficult to manufacture TFTs.

Therefore, an object of the present invention is to realize a high-performance semiconductor device by fabricating a TFT having better electric characteristics than a TFT using a conventional polysilicon film and assembling a circuit with the TFT. .

[0008]

The gist of the present invention disclosed in this specification is a first step of forming a semiconductor film containing a crystal,
250 to 5000 mJ / c for the semiconductor film containing the crystal
^2nd laser annealing process with m ² energy density
A third step of performing a furnace annealing process on the semiconductor film containing the crystal after the second step, and a fourth step of oxidizing the semiconductor film containing the crystal after the third step to reduce the film thickness.
And a step.

In the third step, the furnace annealing treatment is not particularly limited to a treatment atmosphere, but is preferably performed in a reducing atmosphere. The reducing atmosphere is a hydrogen atmosphere, an ammonia atmosphere, an inert atmosphere containing hydrogen or ammonia (such as a mixed atmosphere of hydrogen and nitrogen, or a mixed atmosphere of hydrogen and argon).
Pointing to. The processing temperature is 900-1200 ° C.
(Preferably 1000 to 1100 ° C.).

This third step has the effect of further planarizing the surface of the semiconductor film containing crystals. This is the result of enhanced surface diffusion of semiconductor atoms in an attempt to minimize surface energy. At the same time, this step also has an effect of remarkably reducing crystal grain boundaries and defects existing in crystal grains. This is due to the effect of terminating dangling bonds by hydrogen, the effect of removing impurities by hydrogen, and the resulting recombination of semiconductor atoms. To obtain these effects, heat treatment at 900 to 1200 ° C. in a reducing atmosphere is required.

The step of reducing the film thickness by oxidizing in the fourth step may be performed by a plurality of thermal oxidation steps. As a means for reducing the film thickness by oxidation, thermal oxidation, plasma oxidation, or the like can be used. In particular, in the present invention,
Oxidation by thermal oxidation is preferred. In the case of plasma oxidation, it is preferable to add He to an oxygen atmosphere because oxygen radicals are easily generated. In the fourth step, an effect of flattening unevenness on the surface of the semiconductor film can be obtained.

Another aspect of the invention is a first step of forming a semiconductor film including a crystal and a second step of performing a laser annealing process on the semiconductor film including the crystal at an energy density of 250 to 5000 mJ / cm ² . Two steps, and 90 degrees in a reducing atmosphere with respect to the semiconductor film including the crystal after the second step.
It is characterized by including a third step of performing a furnace annealing treatment at 0 to 1200 ° C. and a fourth step of oxidizing a semiconductor film containing crystals after the third step to reduce the film thickness.

Further, the gist of another invention is that a first step of forming a semiconductor film containing crystals and a second step of performing laser annealing on the semiconductor film containing crystals at an energy density of 250 to 5000 mJ / cm ² . Two steps, a third step of oxidizing the semiconductor film including the crystal after the second step to reduce the film thickness, and a fourth step of performing a furnace annealing process on the semiconductor film including the crystal after the third step And is characterized by including.

Another aspect of the invention is a first step of forming a semiconductor film including a crystal, and a second step of performing a laser annealing process on the semiconductor film including the crystal at an energy density of 250 to 5000 mJ / cm ² . Two steps; a third step of oxidizing the semiconductor film containing the crystal after the second step to reduce the film thickness; and 900 to 1200 ° C. in a reducing atmosphere with respect to the semiconductor film containing the crystal after the third step. And a fourth step of performing a furnace annealing process.

In the third step, the step of oxidizing to reduce the film thickness may be performed by a plurality of thermal oxidation steps. As a means for reducing the film thickness by oxidation, thermal oxidation, plasma oxidation, or the like can be used. In particular, in the present invention,
Oxidation by thermal oxidation is preferred. In the case of performing plasma oxidation, it is preferable to add He to an oxygen atmosphere because oxygen radicals are easily generated. In the third step, an effect of flattening unevenness on the surface of the semiconductor film can be obtained.

In the fourth step, the furnace annealing treatment is not particularly limited to a treatment atmosphere, but is preferably performed in a reducing atmosphere. The reducing atmosphere refers to a hydrogen atmosphere, an ammonia atmosphere, or an inert atmosphere containing hydrogen or ammonia (such as a mixed atmosphere of hydrogen and nitrogen or a mixed atmosphere of hydrogen and argon). The processing temperature is 900 to 12
The temperature is preferably set to 00 ° C (preferably 1000 to 1100 ° C).

This fourth step has the effect of further planarizing the surface of the semiconductor film containing crystals. This is the result of enhanced surface diffusion of semiconductor atoms in an attempt to minimize surface energy. At the same time, this step also has an effect of remarkably reducing crystal grain boundaries and defects existing in crystal grains. This is due to the effect of terminating dangling bonds by hydrogen, the effect of removing impurities by hydrogen, and the resulting recombination of semiconductor atoms. To obtain these effects, heat treatment at 900 to 1200 ° C. in a reducing atmosphere is required.

Note that the surface of the semiconductor film including crystals can be planarized even in an inert atmosphere (nitrogen atmosphere, helium atmosphere, or argon atmosphere). However, it is preferable to reduce the natural oxide film by using a reducing action, since many silicon atoms having high energy are generated, and as a result, the flattening effect is enhanced.

In the first step in each of the above aspects, the semiconductor film containing a crystal includes all semiconductor films containing a crystal component, and specifically, a single crystal semiconductor film, a polycrystalline semiconductor film, a microcrystalline semiconductor film, A semiconductor film in which only part of an amorphous semiconductor film is crystallized, or a semiconductor film that can be regarded as substantially single crystal.

Note that a semiconductor film that can be substantially regarded as a single crystal is a semiconductor film formed by assembling a plurality of crystal grains but having crystallinity such that the plane orientation of each crystal grain is uniform. Has a specific orientation on the entire film surface.

The semiconductor film containing amorphous includes all semiconductor films containing an amorphous component, and only a part of the microcrystalline semiconductor film, the amorphous semiconductor film, and the amorphous semiconductor film is crystallized. Semiconductor film.

In this specification, a silicon film is taken as a typical example of a semiconductor film. However, a germanium film or a silicon germanium film (Si1-xGex (0 <X <1)
It is needless to say that a semiconductor film (e.g., represented by) can also be used in the present invention.

In the second step in each of the above aspects, in the step of performing the laser annealing treatment, KrF (wavelength 2
48 nm), XeCl (wavelength 308 nm), ArF (wavelength 1
Excimer laser light with an excitation gas of 93 nm) or the like is preferably used. The beam shape of the laser light may be linear or planar.

The light energy that can be used in the present invention is not limited to excimer laser light.
Ultraviolet light or infrared light may be used. In that case, strong light having the same light intensity as the laser light may be irradiated from an ultraviolet lamp or an infrared lamp.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention having the above configuration will be described in detail with reference to the following examples.

[0026]

[Embodiment 1] In this embodiment, a process of manufacturing a TFT on a substrate by implementing the present invention will be described.
FIG. 1 is used for the description.

First, a quartz substrate 101 was prepared. A material having high heat resistance must be selected for the substrate. Instead of a quartz substrate, a highly heat-resistant material such as a silicon substrate, a ceramic substrate, a crystallized glass substrate, or a metal substrate can be used.

However, when a quartz substrate is used, a base film may or may not be provided. However, when another material is used, it is preferable to provide an insulating film as the base film. As the insulating film, a silicon oxide film (SiOx), a silicon nitride film (Six N
y), a silicon oxynitride film (SiOxNy), an aluminum nitride film (AlxNy), or a laminated film thereof.

It is effective to use a base film in which a heat-resistant metal layer and a silicon oxide film are laminated because the heat radiation effect is greatly increased. The heat dissipation effect is sufficient even with the above-described laminated structure of the aluminum nitride film and the silicon oxide film.

After the quartz substrate 101 is prepared in this way,
A 90 nm thick semiconductor film (amorphous silicon film in this embodiment) 102 is formed, and a nickel-containing layer 10 is formed on the surface thereof.
3 was formed. Regarding the method of forming the nickel-containing layer 103, it is preferable to refer to the technique described in Japanese Patent Application Laid-Open No. 7-130652. (Fig. 1 (A))

In this embodiment, Japanese Patent Application Laid-Open No.
Examples of adding nickel by using the technology described in Japanese Patent Publication No. 2 are disclosed. A nickel film is formed and thermally diffused, an ion implantation method (ion implantation method (with mass separation), a plasma doping method ( (No mass separation)
Alternatively, a laser doping method or the like may be used.

In this embodiment, the amorphous silicon film 10
Disilane (Si2H6) was used as a film forming gas for 2 and 4
The film was formed by a low pressure thermal CVD method at 50 ° C. At this time, it is important to thoroughly control the concentration of impurities such as C (carbon), N (nitrogen) and O (oxygen) mixed in the film. This is because the presence of many of these impurities hinders the progress of crystallization.

The applicant has determined that the concentration of carbon and nitrogen is 5 × 10
¹⁸ atoms / cm ³ or less (preferably 5 × 10 ¹⁷ atoms / cm ³ or less) and oxygen concentration of 1 × 10 ¹⁹ atoms / cm ³ or less (preferably 5 × 10 ¹⁸ atoms / cm ³ or less). The impurity concentration was controlled. The metal element was controlled to be 1 × 10 ¹⁷ atoms / cm ³ or less. If such concentration control is performed at the film formation stage, the impurity concentration will not increase during the TFT manufacturing process as long as external contamination is prevented.

The nickel-containing layer 103 is coated with a nickel acetate solution containing 10 ppm by weight of nickel by spin coating on the entire surface (entire region) of the amorphous silicon film 102, and dehydrated at 450 ° C. for about 1 hour. Was done.

After that, a heat treatment is performed at a temperature of 500 to 700 ° C. (typically 550 to 650 ° C.) for 4 to 24 hours in an inert atmosphere, a hydrogen atmosphere or an oxygen atmosphere to obtain a polysilicon film 104. . This polysilicon film 104 contains nickel at 1 × 10 ^{18 to} 1 × 10 ¹⁹ at.
It remains at a concentration of oms / cm ³ . (FIG. 1 (B))

Strictly speaking, at the time of spin coating, nickel has not been added to the amorphous silicon film. However, nickel can be easily diffused into the amorphous silicon film in the subsequent hydrogen removal step, so it can be considered as a substantial addition step.

Note that a plasma CVD method may be used as long as film quality equivalent to that of an amorphous silicon film formed by a low pressure thermal CVD method can be obtained. Further, the semiconductor does not need to be completely amorphous, and a microcrystalline silicon film or the like may be formed.

Further, instead of the silicon film, silicon germanium (Si) containing germanium in the silicon film is used.
A semiconductor film such as x Ge 1-x (represented by 0 <X <1) may be used. In that case, it is desirable that the germanium contained in the silicon germanium be 5 atomic% or less.

In addition to nickel, cobalt (C
o), iron (Fe), palladium (Pd), platinum (P
t), a lattice intrusion type catalyst element such as copper (Cu) or gold (Au) or a lattice substitution type (or fusion type) catalyst element such as germanium (Ge), lead (Pb) or tin (Sn). One or more types can be used.

FIG. 11 shows the result of examining the temperature at which the amorphous silicon film changes to a polysilicon film by differential thermal analysis (more precisely, differential thermal analysis). Differential thermal analysis (also referred to as DTA method) is a method in which a reference material and a sample are simultaneously heated at a constant rate and a temperature difference between the two is measured to analyze the thermal characteristics of the sample material. .

As a result of analyzing the phase change from the amorphous silicon film (thickness: 500 nm) to the polysilicon film by the differential thermal analysis method, as shown by the arrow in FIG. It was confirmed that a phase change occurred at ℃. Note that the results in FIG. 11A are data obtained when crystallization was performed without using a catalyst or the like.

On the other hand, FIG. 11B shows a state of a phase change when nickel is used as a catalyst element for promoting crystallization of the amorphous silicon film as in this embodiment. At this time,
The addition amount of nickel is 1-2 × 10 ¹⁹ atoms / cm ³ .
In that case, the temperature for phase change (crystallization) decreases, and
It was confirmed that the temperature was 5.0 ° C.

When the same experiment was conducted using other catalyst elements, it was confirmed that all of them were around 600 ° C. (550 to 550 ° C.).
(650 ° C.), it was confirmed that a phase change occurred and crystallization occurred. The reason why the applicant performs the crystallization step in the above-mentioned temperature range is supported by such data.

When the state shown in FIG. 1B is obtained,
Next, the polysilicon film 104 was irradiated with excimer laser light. In this embodiment, laser annealing was performed by pulse oscillation type excimer laser light using XeCl (wavelength 308 nm) as an excitation gas. The beam shape of the excimer laser may be a linear beam, but a planar beam may be used to enhance the uniformity of processing. (Figure 1
(C))

Note that an excimer laser beam using KrF, KrCl, ArF or the like as an excitation gas or another ultraviolet laser may be used. When infrared light is used, the polysilicon film 104 may be irradiated with strong light emitted from an infrared lamp.

In this embodiment, a linear laser beam having an oscillation frequency of 30 Hz and a beam shape of 145 × 0.41 mm was used. Also,
The laser beam is scanned from one end to the other end of the substrate at 1.2 mm / sec, and the overlap between adjacent linear laser beams is
%.

In this embodiment, the laser energy density is 250 to 5000 mJ / cm ² (preferably 450 to 500 mJ / cm ² ).
It is preferably performed under the condition of 1000 mJ / cm ² ). In this embodiment, the laser energy density was set to 550 mJ / cm ² .
Here, a method for measuring the laser energy density in this specification will be described.

First, the light intensity (E ₀ ) of the laser light oscillated from the laser oscillator is measured by a power meter. However, the laser light after passing through the power meter is dimmed according to the transmittance (a) of the attenuator, and further dimmed according to the transmittance (b) of the optical system. The value obtained by dividing the light intensity of the laser light thus reduced by the laser irradiation area (A) is the laser energy density (E). This can be expressed as E = (E ₀ × a × b) / A.

When the state shown in FIG. 1C is obtained,
A furnace annealing treatment (heat treatment using an electric furnace) was performed at 1000 ° C. for 30 minutes in an oxidizing atmosphere. At this time, the thickness of the polysilicon film 105 was reduced by a thermal oxidation process (thinning process), and a polysilicon film 106 thinner than the polysilicon film 105 was formed. (Fig. 1 (D))

Although not shown in FIG. 1D,
A thermal oxide film is formed on the polysilicon film 105. This thermal oxide film may be removed or may be used as a protective film in the next laser annealing step.

In this thermal oxidation step, defects and the like in the polysilicon film were repaired by excess silicon atoms generated when the oxidation reaction progressed, and a polysilicon film with very few defects could be obtained. Further, by reducing the thickness of the polysilicon film, the thickness was initially 90 nm, but was increased to 60 nm.

Further, the oxidation reaction proceeds while shaving the surface layer of the polysilicon film, so that the formed polysilicon film 106 becomes a semiconductor film having a very flat surface. This will work effectively in reducing the level at the interface between the active layer and the gate insulating film of the TFT in the future.

When the thinning step is performed a plurality of times, the flatness of the polysilicon film is further improved. In that case, the thermal oxidation step and the step of removing the thermal oxide film are alternately repeated.

In this embodiment, a thinning process is employed because an amorphous silicon film having a thickness of 90 nm is used as the initial film. However, if it is not necessary to reduce the thickness of the initial film to about 50 nm or more, the thinning process is performed. It is also possible to omit the step.

Next, the polysilicon film 106 obtained by performing the thinning step was subjected to furnace annealing at 1000 ° C. for 2 hours. In this embodiment, the processing atmosphere is a hydrogen atmosphere, but there is no problem as long as the atmosphere is a reducing atmosphere.
Further, the object of improving the crystallinity even in an inert atmosphere such as a nitrogen atmosphere is achieved. (FIG. 1 (E))

It is preferable that the surface of the polysilicon film 106 be cleaned with a hydrofluoric acid-based etchant before performing the furnace annealing step. That is, it is effective to remove the natural oxide film and terminate the silicon atoms on the surface with hydrogen to prevent the natural oxide film from being formed before the actual processing.

It should be noted that the concentration of oxygen or an oxygen compound (for example, OH group) contained in the atmosphere is set to 10 ppm or less (preferably 1 ppm or less). Otherwise, the flattening effect by heat treatment in a reducing atmosphere will be weakened.

Thus, a polysilicon film 107 was obtained. Further, the polysilicon film 107 had a very flat surface by hydrogen annealing at a high temperature of 1000 ° C. Further, since annealing was performed at a high temperature, almost no stacking faults or the like were present in the crystal grains.

As a result of observation of the polysilicon film obtained in the process of this embodiment by the Raman measurement method, the Raman peak value was 517 to 520 cm ^-1 (typically 518 to 51 cm ^-1 ).
9 cm ^-1 ). The half width at half maximum is 2.2 to 3.0 cm.
^-1 (typically 2.4 to 2.6 cm ^-1 ).

The Raman peak value of 518 to 519 cm ^-1 is on the very high wavenumber side, and it is understood that the polysilicon film obtained in this embodiment has a crystal very close to a single crystal. In addition, the value of 2.4 to 2.6 cm ^-1 is very small (a single crystal silicon film measured as a reference has a value of 2.
It was 1 cm ^-1 . ), That is, high crystallinity.

In this specification, the Raman peak value refers to an Ar laser having a wavelength of 514.5 cm ^{-1 at} a wavelength of 1.0 × 1.
A Lorentz distribution fitting is performed on a Raman spectrum obtained when the semiconductor film including the crystal (polysilicon film in this embodiment) is irradiated with a light intensity of 0 ^{5 to} 1.3 × 10 ⁵ W / cm ^2. This is the peak value obtained when In addition, a Raman measuring device called “Ramascope microscope Raman device system 2000” of Renishaw was used for the actual measurement.

The half-width at half maximum means that an Ar laser having a wavelength of 514.5 cm ^-1 is irradiated with a laser beam of 1.0 × 10 ^{5 to} 1.3 × 10 ⁵ W / cm ²
This is a half of the half-width obtained when the fitting by Lorentz distribution is performed on the Raman spectrum obtained when the semiconductor film including the crystal is irradiated with the light intensity. This was also measured with the above-mentioned Raman measuring device.

Although the Raman peak value and the half width at half maximum defined by the above definitions, the ratio of the Raman peak value to the half width at half maximum (Raman peak value / half width at half maximum) of the polysilicon film 107 of this embodiment is 170 to 240 (representative). Specifically 190 to 220).

When the polysilicon film 107 having remarkably high crystallinity was thus obtained, the polysilicon film 107 was patterned to form an active layer 108. In this embodiment, the heat treatment is performed in a hydrogen atmosphere before forming the active layer. However, the heat treatment may be performed after forming the active layer. In that case, it is preferable that the patterning reduces the stress generated in the polysilicon film.

Then, a silicon oxide film 109 having a thickness of 10 nm was formed on the surface of the active layer 108 by performing a thermal oxidation step. This silicon oxide film 109 functions as a gate insulating film. The thickness of the active layer 108 was reduced to 45 nm because the thickness of the active layer 108 was reduced by 5 nm due to this oxidation. Finally 10
The thickness of the initial semiconductor film (semiconductor film formed first) must be determined in consideration of film reduction due to thermal oxidation so that an active layer (especially a channel formation region) having a thickness of about 50 nm remains. is necessary.

After the gate insulating film 109 was formed, a conductive polysilicon film was formed thereon, and a gate wiring 110 was formed by patterning. (Fig. 2 (A))

In this embodiment, polysilicon having N-type conductivity is used as the gate wiring, but the material is not limited to this. In particular, it is effective to use tantalum, a tantalum alloy, or a stacked film of tantalum and tantalum nitride to reduce the resistance of the gate wiring. If a low-resistance gate wiring is aimed at, it is effective to use copper or a copper alloy.

When the state shown in FIG. 2A was obtained, an impurity for imparting N-type conductivity or P-type conductivity was added to form an impurity region 111. At this time, the impurity concentration is
It was determined in consideration of the impurity concentration in the region. In this embodiment, 1 ×
Although arsenic was added at a concentration of 10 ¹⁸ atoms / cm ³ , neither the impurity nor the concentration need be limited to this embodiment.

Next, 5 to 10
A thin silicon oxide film 112 of about nm was formed. This may be formed using a thermal oxidation method or a plasma oxidation method. This silicon oxide film 112 functions as an etching stopper in the next sidewall forming step.

After the silicon oxide film 112 serving as an etching stopper was formed, a silicon nitride film was formed and etched back to form side walls 113. Thus, the state shown in FIG. 2B was obtained.

Although the silicon nitride film is used as the sidewall in this embodiment, a polysilicon film or an amorphous silicon film may be used. Needless to say, if the material of the gate wiring changes, the material that can be used as the sidewall changes accordingly.

Next, impurities of the same conductivity type as above were added again. The concentration of the impurity added at this time was higher than that in the previous step. In the present embodiment, arsenic is used as an impurity and the concentration is 1 × 10 ²¹ atoms / cm ³ , but it is not necessary to limit to this. The source region 114, the drain region 115, the LDD region 116, and the channel formation region 117 were defined by the impurity doping process. (Fig. 2 (C))

After the formation of each impurity region, the impurities were activated by a heat treatment such as furnace annealing, laser annealing or lamp annealing.

Next, the gate wiring 110 and the source region 11
4 and the silicon oxide film formed on the surface of the drain region 115 were removed, and their surfaces were exposed. And
A heat treatment process was performed by forming a cobalt film (not shown) of about 5 nm. This heat treatment causes a reaction between cobalt and silicon to form a silicide layer (cobalt silicide layer).
118 were formed. (FIG. 2 (D))

This technique is a known salicide technique.
Therefore, titanium or tungsten may be used instead of cobalt, and annealing conditions and the like may be referred to a known technique. In this embodiment, the lamp annealing process is performed by irradiating infrared light.

After the formation of the silicide layer 118, the cobalt film was removed. Thereafter, an interlayer insulating film 119 having a thickness of 1 μm was formed. As the interlayer insulating film 119, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a resin film (polyimide, acrylic, polyamide, polyimide amide, benzocyclobutene (BCB), or the like) may be used. Further, these insulating films may be stacked in any combination.

Next, a contact hole was formed in the interlayer insulating film 119 to form a source wiring 120 and a drain wiring 121 made of a material containing aluminum as a main component. Finally, the entire device was subjected to furnace annealing at 300 ° C. for 2 hours in a hydrogen atmosphere to complete hydrogenation.

Thus, a TFT as shown in FIG. 2D was obtained. The structure described in this embodiment is an example, and the TFT structure to which the present invention can be applied is not limited to this. Therefore, the present invention can be applied to any known TFT. Also, the numerical conditions in the steps after the formation of the polysilicon film 107 need not be limited to the present embodiment. Furthermore, there is no problem if a known channel doping step (an impurity adding step for controlling a threshold voltage) is introduced somewhere in this embodiment.

In this embodiment, the concentration of impurities such as C, N and O is thoroughly controlled at the stage of forming the amorphous silicon film as the initial film.
The concentration of each impurity contained in the T active layer is such that the concentration of carbon and nitrogen is 5 × 10 ¹⁸ atoms / cm ³ or less (preferably 5 × 1
0 ¹⁸ atoms / cm ³ or less), and the oxygen concentration is 5 × 10 ¹⁸ atoms / c
m ³ or less (preferably 5 × 10 ¹⁸ atoms / cm ³ or less). The metal element except nickel is 1 × 10 ¹⁷
atoms / cm ³ or less.

It is needless to say that the present invention can be easily applied not only to a top gate structure but also to a bottom gate structure represented by an inverted staggered TFT.

In this embodiment, an N-channel TFT has been described as an example. However, a P-channel TFT can be easily manufactured by combining with a known technique. Furthermore, if known techniques are combined, an N-channel TF
It is also possible to form a CMOS circuit by forming and combining T and P-channel TFTs complementarily.

Further, a pixel electrode (not shown) electrically connected to the drain wiring 121 in the structure of FIG.
Is formed by known means, it is easy to form a pixel switching element of an active matrix display device. That is, the present invention can be implemented when an active matrix type electro-optical device such as a liquid crystal display device or an EL (electroluminescence) display device is manufactured.

(Embodiment 2) In this embodiment, an example in which a polysilicon film is obtained by a method different from that in Embodiment 1 will be described with reference to FIG.
This will be described with reference to FIG. The basic configuration is almost the same as that of the first embodiment. Therefore, only the differences will be described.

This embodiment is the same as the first embodiment up to the step of obtaining the state shown in FIG. First, the quartz substrate 201
A 90 nm-thick semiconductor film (amorphous silicon film in this embodiment) 202 was formed thereon, and a nickel-containing layer 203 was formed on the surface thereof. (FIG. 3 (A)) and 500 to 70 in an inert atmosphere, a hydrogen atmosphere or an oxygen atmosphere.
4-24 at a temperature of 0 ° C. (typically 550-650 ° C.)
A heat treatment for a long time was applied to obtain a polysilicon film 204.
(FIG. 3B) Thereafter, the polysilicon film 204 was irradiated with excimer laser light to obtain a polysilicon film 205. (FIG. 3 (C))

Next, the polysilicon film 205 obtained by performing the laser annealing step was subjected to furnace annealing at 1000 ° C. for 2 hours. In this embodiment, the processing atmosphere is a hydrogen atmosphere, but there is no problem as long as the atmosphere is a reducing atmosphere. Further, the object of improving the crystallinity even in an inert atmosphere such as a nitrogen atmosphere is achieved. Also,
By this step, the polysilicon film 2 having a flat surface is formed.
06 was obtained. (FIG. 3 (D))

When the state shown in FIG. 3D is obtained,
A furnace annealing treatment (heat treatment using an electric furnace) was performed at 1000 ° C. for 30 minutes in an oxidizing atmosphere. At this time, the thickness of the polysilicon film 206 was reduced by a thermal oxidation process (thinning process), and a polysilicon film 207 thinner than the polysilicon film 206 was formed. (Figure

In this thermal oxidation step, defects and the like in the polysilicon film were repaired by excess silicon atoms generated when the oxidation reaction progressed, and a polysilicon film with very few defects could be obtained. Further, by reducing the thickness of the polysilicon film, the thickness was initially 90 nm, but was increased to 60 nm.

Since the oxidation reaction proceeds while shaving the surface layer of the polysilicon film planarized by the furnace annealing treatment in the reducing atmosphere, the formed polysilicon film 207 is formed.
Became a semiconductor film having a flatter surface. This will work effectively in reducing the level at the interface between the active layer and the gate insulating film of the TFT in the future. In addition, the resulting oxide film is
Since it has a very flat surface, it can be used as a gate insulating film or a part thereof.

When the thinning step is performed a plurality of times, the flatness of the polysilicon film is further improved. In this case, the thermal oxidation step and the thermal oxide film removing step are alternately repeated.

The subsequent steps are the same as in the first embodiment, and will not be described. That is, a combination with the first embodiment is possible.

(Embodiment 3) In this embodiment, an example in which a polysilicon film is obtained by a method different from that in Embodiment 1 will be described with reference to FIG.
This will be described with reference to FIG. Since the basic configuration is almost the same as that of the first embodiment, only the differences will be described.

This embodiment is the same as the first embodiment up to the step of obtaining the state shown in FIG. First, the quartz substrate 211
A 90-nm-thick semiconductor film (amorphous silicon film in this embodiment) 212 is formed thereon, and a nickel-containing layer 213 is formed on the surface thereof. (FIG. 4 (A)) and 500 to 70 in an inert atmosphere, a hydrogen atmosphere or an oxygen atmosphere.
4-24 at a temperature of 0 ° C. (typically 550-650 ° C.)
A heat treatment was performed for a long time to obtain a polysilicon film 214.
(FIG. 4B) After that, the polysilicon film 214 was irradiated with an excimer laser beam to obtain a polysilicon film 215. (FIG. 4 (C))

Next, the polysilicon film 215 obtained by performing the laser annealing step was subjected to a furnace annealing treatment (a heat treatment using an electric furnace) in an oxidizing atmosphere. At this time, the polysilicon film 2 is thermally oxidized.
15 thinning process (thinning process), polysilicon film 2
A polysilicon film 216 thinner than 15 was formed. (FIG. 4 (D))

Note that, when this thinning step is performed a plurality of times, the flatness of the polysilicon film is further improved. In that case, the thermal oxidation step and the step of removing the thermal oxide film are alternately repeated.

The subsequent steps are the same as in the first embodiment, and will not be described. That is, this embodiment can be combined with the first embodiment. The feature of this embodiment is that the furnace annealing step described in the second embodiment is also used as a thermal oxidation step.

(Embodiment 4) In this embodiment, an example in which an initial film formed first on a substrate is a polysilicon film will be described with reference to FIG.

First, base films 302 and 7 made of a silicon oxide film are formed on a metal substrate (a tantalum substrate in this embodiment) 301.
The 5 nm-thickness polysilicon film 303 and the protection film 304 are continuously laminated without opening to the atmosphere. In this embodiment, the film is formed by a multi-chamber reduced-pressure thermal CVD apparatus having a vacuum load lock and a common chamber. (FIG. 5 (A))

Next, a laser annealing step is performed with KrF excimer laser light while leaving the protective film 304.
The laser irradiation conditions in this example used a linear laser beam having an oscillation frequency of 30 Hz and a beam shape of 145 × 0.41 mm. In addition, the laser beam travels from one end to the other end of the substrate at 1.2 mm / sec.
And the overlap between adjacent linear laser beams was set to 92%.

In this embodiment, the laser energy density is 250 to 5000 mJ / cm ² (preferably 500 to 500 mJ / cm ² ).
It is performed under the condition of 1000 mJ / cm ² ). 600 mJ in this embodiment
/ cm ² . The method for measuring the laser energy density is the same as that in the first embodiment. Thus, the polysilicon film 30
5 are formed. (FIG. 5 (B))

Next, a thermal oxidation step is performed at 1050 ° C. for 30 minutes. In this embodiment, in order to perform the heat treatment while relaxing the stress, a wet oxidation method containing water vapor is used. The thickness of the polysilicon film 307 that has undergone this step is reduced by oxidation to a thickness of 50 nm. Also, the protective film 30
No. 6 increases in film thickness by the formed thermal oxide film. (FIG. 5
(C))

Of course, this thermal oxidation step is performed as a thinning step for further reducing the thickness of the polysilicon film. When the thinning step is performed a plurality of times, the flatness of the polysilicon film is further improved. In that case, the thermal oxidation step and the thermal oxide film removal step may be alternately repeated.

After the thermal oxidation process is completed, a furnace annealing process is performed at 1100 ° C. for 2 hours in a nitrogen atmosphere to improve the crystallinity of the polysilicon film 307. Through this step, a polysilicon film 308 is obtained. (FIG. 5
(D) The polysilicon film 308 thus obtained exhibits a specific orientation over the entire film surface, and becomes a semiconductor film which can be regarded substantially as a single crystal.

The polysilicon film 308 formed as described above is processed in all the steps from FIG. 5A to FIG. 5D without contacting the outside air, so that an extremely clean interface is formed. Have. This is the case in the present embodiment.
This is an effect of two constitutions: the step (1) is performed by continuous film formation without opening to the atmosphere; and all the processing is performed through a protective film.

The Raman peak value and the half width at half maximum also fall within the ranges described in the first embodiment.

In this embodiment, a polysilicon film is used as an initial film (a semiconductor film to be formed first), but a microcrystalline silicon film or an amorphous silicon film is used.
Laser crystallization can be performed via a protective film. Of course, a semiconductor material other than silicon may be used.

After the polysilicon film 308 is obtained, a TFT may be manufactured in the same procedure as in the first embodiment. Needless to say, not only in the first embodiment, but also
Can also be prepared.

(Embodiment 5) In this embodiment, the crystallization of an amorphous silicon film as an initial film is described in Japanese Patent Application Laid-Open No. 8-7832.
An example in the case of performing the processing using the technique described in Japanese Patent Application Publication No. 9 will be described with reference to FIG.

First, a quartz substrate 40 provided with an insulating film on its surface
1 is prepared, and an amorphous silicon film (not shown) and a silicon oxide film (not shown) are continuously formed thereon without opening to the atmosphere. Next, a mask 402 having an opening is formed by patterning the silicon oxide film.

Next, a solution containing 100 ppm by weight of nickel is applied by spin coating to obtain a state in which the amorphous silicon film and nickel are in contact with each other at the bottom of the opening. Thereafter, a furnace annealing step at 570 ° C. for 14 hours is performed to obtain a lateral growth region 403.

Since the bar-shaped crystal grows in a direction substantially parallel to the substrate, the lateral growth region 403 becomes a semiconductor film having fewer defects and trap levels than a polysilicon film in which nuclei are randomly generated.

In the state shown in FIG. 6A, a semiconductor film in which a region which remains as an amorphous component and a laterally grown region (a region having a crystalline component) is obtained. In this specification, such a film is also referred to as a semiconductor film (or a semiconductor film including crystals).

When the state shown in FIG. 6A is obtained,
Using the mask 402 as a mask, phosphorus is added by a plasma doping method or an ion implantation method. When the concentration of phosphorus in the silicon film is 1 × 10 ¹⁹ to SIMS,
Adjust so as to be 1 × 10 ²¹ atoms / cm ³ . (FIG. 6
(B))

The region to which phosphorus is added at a high concentration in this manner is referred to as a gettering region 404 in this specification.

When the gettering region 404 is formed, 6
A furnace annealing step of 12 hours at 00 ° C. is performed to getter the nickel present in the lateral growth region 403 to the gettering region 404. Thus, the lateral growth region 405 is obtained in which the nickel concentration in the film is reduced to 1 × 10 17 atoms / cm 3 or less by m. (FIG. 6 (C))

Next, patterning is performed to form a lateral growth region 4.
Thus, an island-shaped semiconductor film 406 formed only of the semiconductor film 05 is obtained. At this time, since the gettering region contains phosphorus and nickel at a high concentration, it is desirable to completely remove the gettering region.

Thus, the state shown in FIG. 6D is obtained. next,
Laser annealing is performed using XeCl excimer laser light. The laser irradiation conditions in this embodiment are the same as those in the first embodiment. Thus, an island-shaped semiconductor film 407 is obtained. (FIG. 6E)

Next, furnace annealing is performed in an oxygen atmosphere at 1000 ° C. for 30 minutes to perform a thermal oxidation step (thinning).
Step) is performed. Thermal oxide film (not shown) formed at this time
May be removed here, or may be left until the next furnace annealing process is performed. (FIG. 6 (F))

After the island-shaped semiconductor film 408 whose thickness has been reduced by the thinning step is obtained, a furnace annealing process is further performed at 1100 ° C. for 2 hours in an atmosphere in which hydrogen and nitrogen are mixed. Thus, an island-shaped semiconductor film 409 is obtained. (FIG. 6 (G))

The island-shaped semiconductor film 4 formed as described above
09 has the same crystallinity as the polysilicon film described in the first and second embodiments. In other words, the entire film surface shows a specific orientation, and is a semiconductor film which can be substantially regarded as a single crystal.

The Raman peak value and half width at half maximum obtained by Raman measurement are the same as those described in the first embodiment.

The structure of this embodiment can be combined with any of the structures of the first to third embodiments.

(Embodiment 6) In the first to third embodiments, a catalyst element (specifically, nickel) which promotes crystallization at the time of crystallization of the initial film is used, but polysilicon which is crystallized by natural nucleation is used. Film (also a semiconductor film containing crystals)
However, a sufficient effect can be obtained even if the steps of the present invention are performed.

In this case, the base film, the amorphous silicon film, and the protective film are continuously laminated without being opened to the atmosphere.
By crystallizing the amorphous silicon film into a polysilicon film by furnace annealing at 00 ° C. for 24 hours, a polysilicon film having a clean interface can be obtained.

However, when the semiconductor film is crystallized by natural nucleation as in this embodiment, it is desirable that the film has a thickness of 80 to 120 nm (typically 90 to 100 nm). That is, it is empirically known that the crystallization efficiency is reduced when the initial film is thin from the beginning.

In such a case, it is important to thin the semiconductor film including the crystal by performing an oxidation step after crystallization is completed. By doing so, crystallization is performed efficiently, and thereafter, a polysilicon film having a desired film thickness can be obtained.

The configuration of the present embodiment is similar to Embodiments 1 to 3,
5 can be combined.

Embodiment 7 In this embodiment, an example of a reflective liquid crystal display device manufactured according to the present invention is shown in FIG.
A well-known means may be used for a method of manufacturing a pixel TFT (pixel switching element) and a cell assembling step, and a detailed description thereof will be omitted.

In FIG. 7A, reference numeral 11 denotes a substrate having an insulating surface (ceramic substrate provided with a silicon oxide film);
Is a pixel matrix circuit, 13 is a source driver circuit,
14 is a gate driver circuit, 15 is a counter substrate, 16 is an FPC (flexible printed circuit), and 17 is a signal processing circuit. As the signal processing circuit 17, D / A
Conventional ICs such as converters, gamma correction circuits, and signal division circuits
Thus, a circuit for performing the processing similar to the above can be formed. Of course, it is also possible to provide an IC chip on a substrate and perform signal processing on the IC chip.

Further, in this embodiment, a liquid crystal display device is described as an example. However, if the display device is an active matrix type display device, the present invention is applied to an EL (electroluminescence) display device and an EC (electrochromics) display device. It goes without saying that the invention can be applied.

Here, the driver circuit 13 shown in FIG.
FIG. 7B illustrates an example of a circuit included in 14. In addition,
Since the TFT portion has already been described in the first embodiment, only necessary portions will be described here.

In FIG. 7B, 501 and 502 indicate N
A channel TFT 503 is a P-channel TFT, and a TFT 501 and a TFT 503 constitute a CMOS circuit. Reference numeral 504 denotes an insulating layer formed of a laminated film of a silicon nitride film / silicon oxide film / resin film, on which a titanium wiring 505 is provided, and the above-described CMOS circuit and the TFT 502 are electrically connected. The titanium wiring is further covered with an insulating layer 506 made of a resin film. The two insulating layers 504 and 506 also have a function as a planarization film.

The pixel matrix circuit 1 shown in FIG.
Part (C) of FIG. FIG.
In (C), reference numeral 507 denotes a pixel TFT formed of an N-channel TFT having a double gate structure, and a drain wiring 508 is formed so as to greatly expand in a pixel region. Note that a single gate structure, a triple gate structure, or the like may be employed in addition to the double gate structure.

An insulating layer 504 is provided thereon, and a titanium wiring 405 is provided thereon. At this time, a recess is formed in a part of the insulating layer 504, and only the lowermost silicon nitride and silicon oxide are left.
Thus, an auxiliary capacitance is formed between the drain wiring 508 and the titanium wiring 505.

Further, the titanium wiring 505 provided in the pixel matrix circuit provides an electric field shielding effect between the source / drain wiring and the subsequent pixel electrode. Further, in a gap between a plurality of provided pixel electrodes, it also functions as a black mask.

An insulating layer 506 is provided so as to cover the titanium wiring 505, and a pixel electrode 509 made of a reflective conductive film is formed thereon. Of course, the surface of the pixel electrode 509 may be devised to increase the reflectance.

Although an alignment film and a liquid crystal layer are actually provided on the pixel electrode 509, the description is omitted here.

The reflection type liquid crystal display device having the above-mentioned structure can be manufactured by using the present invention. Of course, a transmission type liquid crystal display device can be easily manufactured by combining with a known technique.

Although not distinguished in the drawings, the thickness of the gate insulating film can be made different between the pixel TFT forming the pixel matrix circuit and the CMOS circuit forming the driver circuit or the signal processing circuit.

In the pixel matrix circuit, since the driving voltage applied to the TFT is high, a gate insulating film having a thickness of about 50 to 200 nm is required. On the other hand, in a driver circuit or a signal processing circuit, a driving voltage applied to a TFT is low, and a high-speed operation is required.
It is effective to make it as thin as about nm and smaller than the pixel TFT.

(Embodiment 8) The present invention can be applied to all conventional IC technologies. That is, the present invention can be applied to all semiconductor circuits currently on the market. For example, RISC processor integrated on one chip, ASIC
It may be applied to a microprocessor such as a processor, a signal processing circuit typified by a liquid crystal driver circuit (D / A converter, γ correction circuit, signal division circuit, etc.), and a portable device (cellular phone, PHS, mobile computer) ) May be applied to the high frequency circuit.

FIG. 8 shows an example of a microprocessor. The microprocessor typically includes a CPU core 21, a RAM 22, a clock controller 23, a cache memory 24, a cache controller 25, a serial interface 26, an I / O port 27, and the like.

Of course, the microprocessor shown in FIG. 8 is a simplified example, and an actual microprocessor is designed for various circuits depending on the application.

However, a microprocessor having any function can function as a center only by an IC (Integer).
grated circuit) 28. The IC 28 is a functional circuit in which an integrated circuit formed on the semiconductor chip 29 is protected by ceramic or the like.

The integrated circuit formed on the semiconductor chip 29 is composed of the N-channel TFT 30 and the P-channel TFT 31 having the structure of the present invention. Note that power consumption can be suppressed by configuring a basic circuit with a CMOS circuit as a minimum unit.

The microprocessor shown in this embodiment is mounted on various electronic devices and functions as a central circuit. Representative electronic devices include personal computers, portable information terminal devices, and all other home appliances. Further, a computer for controlling a vehicle (an automobile, a train, or the like) is also included.

Needless to say, the structure of this embodiment can be combined with any of the structures of the first to seventh embodiments.

(Embodiment 9) The electro-optical device according to the present invention is constructed as follows.
It is used as a display for various electronic devices. Such electronic devices include a video camera, a digital camera, a front projector, a rear projector (projection TV), a goggle display, a car navigation, a personal computer, and a personal digital assistant (mobile computer, mobile phone, electronic book, etc.).
And the like. One example is shown in FIG.

FIG. 9A shows a mobile phone, and a main body 200.
1, audio output unit 2002, audio input unit 2003, display device 2004, operation switch 2005, antenna 2006
It consists of. The present invention can be applied to the audio output unit 2002, the audio input unit 2003, the display device 2004, and other signal control circuits.

FIG. 9B shows a video camera,
101, display device 2102, audio input unit 2103, operation switch 2104, battery 2105, image receiving unit 210
6. The present invention can be applied to the display device 2102, the audio input unit 2103, and other signal control circuits.

FIG. 9C shows a mobile computer (mobile computer), which includes a main body 2201 and a camera section 2.
202, an image receiving unit 2203, operation switches 2204, and a display device 2205. The present invention relates to a display device 220.
5 and other signal control circuits.

FIG. 9D shows a goggle type display, which includes a main body 2301, a display device 2302, and an arm 230.
3 The present invention can be applied to the display device 2302 and other signal control circuits.

FIG. 9E shows a rear type projector, in which a main body 2401, a light source 2402, a display device 2403,
Polarizing beam splitter 2404, reflector 240
5, 2406 and a screen 2407. The present invention can be applied to the display device 2403 and other signal control circuits.

FIG. 9F shows an electronic book, which has a main body 250.
1, display devices 2502, 2503, storage medium 2504,
It is composed of an operation switch 2505 and an antenna 2506. The present invention can be applied to the display devices 2502 and 2503 and other signal control circuits.

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in all fields.

(Embodiment 10) A semiconductor film containing crystals obtained by the steps shown in Embodiments 1 to 5 exhibits a specific orientation over the entire film surface. That is, even if the crystal grains have a form such as a polycrystalline semiconductor film formed by assembling individual crystal grains, 80% or more (typically 90% or more) of the entire crystal grains have the same crystal plane (orientation). Surface). Such a crystal plane occupying 80% or more of the whole is referred to as a main orientation plane.

The main crystal planes that can be taken by the semiconductor film (semiconductor film containing crystals) formed by the process of the present invention are as follows:
{110} plane, {100} plane, {111} plane, {31}
1｝, {511}, or {110} and {100}
It is one of the crystal faces where the face and the face are mixed. At present, it is not known which crystal plane is the main orientation plane.

That is, in the semiconductor film (semiconductor film containing crystals) formed by the process of the present invention, any one of the above six types of crystal planes accounts for 80% or more of the total crystal planes that may exist on the film plane (typically 90% or more).

As is well known using single crystal silicon as an example, the interface properties vary depending on the crystal plane. The plane orientation at which the interface state density (Qss) becomes the smallest is the {100} plane, followed by the {511} plane, the {311} plane, and the {111} plane.
Plane, a mixed crystal plane of {110} plane and {100} plane,
It becomes larger in the order of the {110} plane. It is known that the {511} plane has an interface state density comparable to the {100} plane.

Therefore, when the main orientation plane of the semiconductor film formed by the process of the present invention is the {100} plane, the interface state density between the active layer and the gate insulating film is extremely low. In that case, a semiconductor device having performance comparable to a conventional IC can be realized. As will be described later, the TFT actually manufactured using the present invention can form a circuit having electrical characteristics comparable to those of a conventional IC.

In the process of the present invention, the furnace annealing in a reducing atmosphere or an inert atmosphere performed after the laser annealing is very effective in flattening the interface between the active layer and the gate insulating film. . In particular, when the treatment is performed in a reducing atmosphere, an extremely flat surface can be obtained by accelerated surface diffusion of semiconductor atoms on the surface of the semiconductor film.

The applicant measured surface irregularities using an AFM (molecular force microscope). As a result, the PV value of the irregularities within the range of 1 μm ² (the height between the top of the projections and the bottom of the depressions) was measured. Is 10 nm or less (typically 5 nm or less), and the PV value of unevenness is 20 nm or less (typically 10 nm or less) within a range of 10 μm ^2.
nm or less).

(Example 11) Representative electrical characteristics of a TFT manufactured by carrying out the present invention were as follows. (1) When the drain voltage is 1 V, the sub-threshold coefficient as an index of the switching performance (the agility of switching on / off operation) is 60 to 150 mV / decade for both the N-channel TFT and the P-channel TFT (typically, 80-10
0mV / decade). (2) The field effect mobility (μ _FE ) which is an index of the operation speed of the TFT is N-channel type T
200 to 500 cm ² / Vs by FT (typically 300 to 400 cm ² / Vs
), The 100 ~300cm ² / Vs (typically a P-channel type TFT as large as 150~200cm ² / Vs). (3) The threshold voltage (V
th) is an N-channel type T when the drain voltage is 14V.
-1.0 to 2.5 V (typically -0.5 to 1.5 V) for FT, -2.5 to 1.0 V (typically -1.5 to 0.5 V) for P-channel TFT
V) and small.

Further, a normal probability graph was created based on data obtained by measuring 500 TFTs of the present invention, and characteristic variations were estimated using the graph. As a result, it was found that 90 out of 100 pieces (typically 95 pieces) fall within the range of the electric characteristics.

As described above, it has been confirmed that extremely excellent switching characteristics and high-speed operation characteristics can be realized.

Embodiment 12 In this embodiment, a shift register, which is a liquid crystal driver circuit, was manufactured, and the operating frequency was confirmed. As a result, in a shift register circuit having a power supply voltage of 5 V and 50 stages, the operating frequency is 80 to 200 MHz.
An output pulse of (typically 100-150 MHz) was obtained.

(Embodiment 13) Embodiment 1 shows an example in which nickel is used as a catalyst element for promoting crystallization in crystallization of an amorphous silicon film. In this embodiment, an example in which germanium is used as a catalyst element is shown. It is shown in FIG.

First, the quartz substrate 8 was made according to the process of the first embodiment.
An amorphous silicon film 802 having a thickness of 80 nm is formed on the substrate 01. Then, germanium is added to the amorphous silicon film 802. (FIG. 10A)

It is preferable to use an ion implantation method, a plasma doping method or a laser doping method for adding germanium.

A method in which a germanium film is formed and then thermally diffused may be employed. Alternatively, as in the first embodiment, a germanium salt solution is spin-coated and germanium is adsorbed on amorphous silicon. A method of thermally diffusing may be employed. Further, a method of adding in advance when forming the amorphous silicon film may be used.

In this embodiment, germane (Ge
Using H4), germanium is added by an ion implantation method at an acceleration voltage of 30 keV, an RF power of 5 W, and a dose of 1 × 10 ¹⁴ atoms / cm ² . Of course, it is not necessary to limit to this condition, and 1 × 10 ^{14 to} 5 × 10 ¹⁹ atoms / cm ³ (typically 1 × 10 ¹⁹ atoms / cm ³ )
It may be adjusted so that germanium is added at a concentration of 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ ).

[0171] It should be noted that the additive
Germanium is 1 × 10¹⁴atoms / cm^ThreeAbove (typically
Is 1 × 10¹⁶atoms / cm^ThreeOtherwise, crystals as catalyst
Cannot make use of the promoting effect of Also, the addition
5 × 10¹⁹atoms / cm^ThreeBeyond amorphous silicon
The melting point of the film is too low.
It is not preferable because there is a risk that the Therefore,
The limit is 1 × 10 for safety ¹⁸atoms / cm^ThreeLeave it as a degree
Is desirable.

Next, a heat treatment (furnace annealing) at 550 ° C. for one hour is performed to form an amorphous silicon film 802.
Is changed to a polysilicon film 803. Of course, it is not necessary to limit to this condition, and a heat treatment in the temperature range as shown in Embodiment 1 may be performed. (FIG. 10B)

In the case of this embodiment, it is desirable that the processing atmosphere is an inert atmosphere or a reducing atmosphere. The reason will be described later.

After the crystallization step of the amorphous silicon film is completed, an irradiation step of excimer laser light is performed according to the first embodiment. In this embodiment, KrF is used as the excitation gas.
Irradiation with linear excimer laser light (wavelength 248 nm) using a laser beam. Thus, a polysilicon film 804 with improved crystallinity is obtained. (FIG. 10 (C))

Next, a thermal oxidation step (thinning step) of the polysilicon film 804 is performed. Although a thermal oxide film is actually formed, it is not shown here. Thus, a polysilicon film 805 having undergone the thinning step is obtained. (FIG. 10
(D))

At this time, there is a remarkable feature when germanium is used as a catalyst element. Germanium is 70
Heat treatment at 0 ° C. or higher causes germanium oxide to be sublimated. That is, when performing the thinning step of the polysilicon film 804, germanium inevitably sublimes and separates from the polysilicon film 804.

That is, as described above, the reason why the crystallization step is desirably performed in an inert atmosphere or a reducing atmosphere is that the catalyst action of germanium can be used most efficiently when no germanium oxide is formed as much as possible. Nothing else.

It has been confirmed that the temperature at which an amorphous silicon film is crystallized is around 600 ° C. when a catalytic element is used as described in Example 1. Actually, it varies slightly depending on the processing temperature, and therefore 550 to 650
C may be considered as the temperature required for crystallization. That is, if the temperature at the time of crystallization is raised only to 650 ° C., it is almost impossible for germanium to sublime at the time of crystallization.

As described above, in the fifth embodiment, since nickel is used as a catalytic element for promoting crystallization, gettering is performed using phosphorus, but in this embodiment, only gettering is performed by heat treatment. An effect equivalent to the gettering step of the catalytic element is obtained.

This heat treatment can be performed not only by furnace annealing but also by any one of laser annealing and lamp annealing.

Therefore, germanium oxide can be sublimated in the laser annealing step shown in FIG. In that case, it is necessary to set the irradiation time of the laser beam (including the number of laser pulse irradiations) longer.

A halogen element may be added to the heat treatment atmosphere. Since the halogen element combines with germanium to form a volatile germanium halide, the gettering effect can be promoted.

As described above, at the same time as performing the thinning step, the catalyst element (germanium) used for crystallization of the amorphous silicon film can be removed or reduced from the polysilicon film without increasing the number of steps. .

Thereafter, a TFT as shown in FIG. 2D may be formed according to the same steps as in the first embodiment. Of course, it is possible to combine with any of the configurations of the second to fifth embodiments, and this embodiment may be used in manufacturing the semiconductor devices shown in the seventh to ninth embodiments.

In this embodiment, an example is shown in which only germanium is used as a catalyst element for promoting crystallization of an amorphous silicon film.
Cobalt, iron, palladium, platinum, copper, gold, lead, tin, etc.) and germanium may be used at the same time. In this case, it may be necessary to combine gettering means as shown in the fifth embodiment with this embodiment.

(Embodiment 14) In Embodiment 13, the case where an ion implantation method or the like is used as a means for adding germanium to an amorphous silicon film has been described. In this embodiment, thermal diffusion is performed after forming a germanium film. The example of adding is shown.

In the case of this embodiment, after the amorphous silicon film is formed, 1 to 50 nm (typically, 10 to 50 nm) is formed thereon.
A 20 nm) germanium film is formed. As a film formation method, a gas phase method such as a plasma CVD method, a low pressure thermal CVD method, or a sputtering method can be used.

Note that the germanium film may be formed so as to directly touch the amorphous silicon film, or may be provided via an insulating film. In the case where an insulating film is formed, if the insulating film is too thick, thermal diffusion of germanium into the silicon film is hindered. Therefore, the thickness is preferably set to 10 to 30 nm.

When the crystallization step is performed with the germanium film provided, the germanium is thermally diffused into the amorphous silicon film by being heated, and acts as a catalytic element for promoting crystallization.

The germanium film after the crystallization step may be oxidized and removed, or a sulfuric acid peroxide solution (H ₂ SO ₄ : H ₂ O ₂ =
1: 1). Thereafter, by performing a heat treatment at 700 ° C. or more, germanium in the formed polysilicon film is removed or reduced.

The configuration of this embodiment can be combined with any of the first to twelfth embodiments and can be applied to any of the embodiments.

(Embodiment 15) In this embodiment, a case where a spin coating method by a solution coating method and a thermal diffusion method are used as means for adding germanium to an amorphous silicon film will be described.

In the case of this embodiment, after the amorphous silicon film is formed, a solution containing germanium is applied thereon. Such solutions include germanium oxide (GeOx,
Typically, GeO ₂ ), germanium chloride (GeCl ₄ ), germanium bromide (GeBr ₄ ), germanium sulfide (GeS ₂ )
There is an aqueous solution of a germanium salt such as germanium acetate (Ge (CH ₃ CO ₂ )).

Further, an alcoholic solvent such as ethanol and isopropyl alcohol may be used as the solvent.

In this embodiment, a germanium-containing layer is formed by preparing a 10 to 100 ppm aqueous solution of germanium oxide, applying the solution on an amorphous silicon film (an insulating film may be interposed), and spin-coating.

Since the amorphous silicon film exhibits hydrophobicity, it is effective to form an insulating film on the surface of the silicon film before spin coating to enhance wettability. In this case, if the insulating film is too thick, thermal diffusion of germanium into the silicon film will be hindered.
Preferably, it is set to 30 nm.

When the crystallization step is performed in the state where the germanium-containing layer is provided, germanium is thermally diffused into the amorphous silicon film by being heated, and functions as a catalytic element for promoting crystallization.

The configuration of this embodiment can be combined with any of the first to twelfth embodiments, and can be applied to any of the embodiments.

[0199]

According to the present invention, a semiconductor film having crystallinity that can be regarded as a single crystal can be obtained. And a TFT using such a semiconductor film as an active layer.
And a high-performance semiconductor device can be realized.

[Brief description of the drawings]

FIG. 1 illustrates a manufacturing process of a thin film transistor.
(Example 1)

FIG. 2 illustrates a manufacturing process of a thin film transistor.
(Example 1)

FIG. 3 illustrates a manufacturing process of a thin film transistor.
(Example 2)

FIG. 4 illustrates a manufacturing process of a thin film transistor.
(Example 3)

FIG. 5 illustrates a manufacturing process of a thin film transistor.
(Example 4)

FIG. 6 illustrates a manufacturing process of a thin film transistor.
(Example 5)

FIG. 7 illustrates a structure of a semiconductor device (electro-optical device). (Example 7)

FIG. 8 illustrates a structure of a semiconductor device (semiconductor circuit). (Example 8)

FIG. 9 illustrates a structure of a semiconductor device (electronic device).
(Example 9)

FIG. 10 illustrates a manufacturing process of a thin film transistor.
(Example 13)

FIG. 11 is a view showing a result of differential thermal analysis. (Example 1)

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F052 AA02 AA17 BA07 BB07 CA02 CA08 DA01 DA02 DB02 DB03 EA15 EA16 FA24 HA01 HA06 JA01

Claims (18)

[Claims] 1. A TFT having a semiconductor film containing a crystal as an active layer.
Wherein the semiconductor film containing the crystal has a Raman peak value of 517 to 5
Is 20 cm ^-1, and wherein a half width at half maximum is 2.2~3.0cm ^-1. 2. A TFT having a semiconductor film containing crystals as an active layer.
Wherein the ratio of the Raman peak value to the half width at half maximum (Raman peak value / half width at half maximum) of the semiconductor film including the crystal is 170 to 240. . 3. The Raman peak value according to claim 1, wherein the Raman peak value is a light intensity of 1.0 × 10 ^{5 to} 1.3 × 10 ⁵ W / cm ^{2 using} an Ar laser having a wavelength of 514.5 cm ^−1. A peak value obtained when a fitting by Lorentz distribution is performed on a Raman spectrum obtained when irradiating a semiconductor film containing the crystal. 4. An apparatus according to claim 1, wherein said half width at half maximum is 1.0 ×× an Ar laser having a wavelength of 514.5 cm ^−1.
A Raman spectrum obtained when the semiconductor film containing the crystal is irradiated with a light intensity of 10 ^{5 to} 1.3 × 10 ⁵ W / cm ^{2 has} a half-value width obtained when fitting by Lorentz distribution is performed. A semiconductor device having a half value. 5. The semiconductor device according to claim 1, wherein the semiconductor device is a liquid crystal display device, an EL display device, or an EC display device. 6. The semiconductor device according to claim 1, wherein the semiconductor device is a microprocessor, a signal processing circuit, or a high-frequency circuit. 7. The semiconductor device according to claim 1, wherein the semiconductor device is a video camera, a digital camera, a projector, a goggle display, a car navigation, a personal computer, or a personal digital assistant. 8. A first step of forming a semiconductor film including a crystal, wherein the semiconductor film including the crystal is formed in a thickness of 250 to 5000 mJ / c.
^2nd laser annealing process with m ² energy density
A third step of performing a furnace annealing process on the semiconductor film containing the crystal after the second step, and a fourth step of oxidizing the semiconductor film containing the crystal after the third step to reduce the film thickness. A method for manufacturing a semiconductor device, comprising: 9. A first step of forming a semiconductor film including a crystal, wherein the semiconductor film including the crystal is formed in a thickness of 250 to 5000 mJ / c.
^2nd laser annealing process with m ² energy density
A third step of performing a furnace annealing process at 900 to 1200 ° C. on the semiconductor film including the crystal after the second step in a reducing atmosphere in a reducing atmosphere; and oxidizing the semiconductor film including the crystal after the third step. A method of manufacturing a semiconductor device, comprising: 10. The method for manufacturing a semiconductor device according to claim 8, wherein the fourth step is performed by a plurality of thermal oxidation steps. 11. A first step of forming a semiconductor film including a crystal, wherein the semiconductor film including the crystal is formed in a thickness of 250 to 5000 mJ / c.
^2nd laser annealing process with m ² energy density
A third step of oxidizing the semiconductor film including the crystal after the second step to reduce the film thickness, and a fourth step of performing a furnace annealing process on the semiconductor film including the crystal after the third step. A method for manufacturing a semiconductor device, comprising: 12. A first step of forming a semiconductor film containing a crystal, wherein the semiconductor film containing the crystal is formed in a thickness of 250 to 5000 mJ / c.
^2nd laser annealing process with m ² energy density
A third step of oxidizing the semiconductor film including the crystal after the second step to reduce the film thickness, and reducing the semiconductor film including the crystal after the third step to 900 to 1200 ° C. in a reducing atmosphere. A fourth step of performing a furnace annealing process. 13. The method according to claim 11, wherein the third step is performed by a plurality of thermal oxidation steps. 14. A method for manufacturing a semiconductor device according to claim 8, wherein said first step is a step of crystallizing a semiconductor film containing amorphous by thermal annealing. 15. The semiconductor film according to claim 14, wherein nickel, cobalt, iron, palladium, platinum, copper, gold, germanium, lead, and tin are added to the amorphous semiconductor film before performing the thermal annealing treatment. A method for manufacturing a semiconductor device. 16. The semiconductor film according to claim 14, wherein germanium is added to the amorphous-containing semiconductor film by an ion implantation method, a plasma doping method, or a laser doping method before performing the thermal annealing treatment. Of manufacturing a semiconductor device. 17. The method according to claim 8, wherein the energy density (E) is a light intensity (E ₀ ) of a laser beam oscillated from a laser oscillator, a transmittance (a) of an attenuator, and an optical system. A method for manufacturing a semiconductor device, wherein E = (E ₀ × a × b) / A using a transmittance (b) and a laser irradiation area (A). 18. A method for manufacturing a semiconductor device according to claim 9, wherein the reducing atmosphere is a hydrogen atmosphere, an ammonia atmosphere, a mixed atmosphere of hydrogen and nitrogen, or a mixed atmosphere of hydrogen and argon. .