JP2000269513A - Semiconductor device and its forming method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a semiconductor device using TFT(thin film transistor) structure of high reliability. SOLUTION: As an insulating film to be used in a TFT, such as a gate insulating film, a protective film, an underlying film and an interlayer insulating film, a silicon oxinitride film containing boron (SiNxByOz) is formed by a sputtering method. As a result, the internal stress of the film becomes representatively -5×1010 dyn/cm2 to 5×1010 dyn/cm2, preferably -1010 dyn/cm2 to 1010 dyn/cm2, and high thermal conductivity is obtained. Thereby deterioration, due to heat generated when the TFT turns on, can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device using a crystalline semiconductor film formed by crystallizing an amorphous semiconductor thin film, and more particularly to a method for improving the reliability of a semiconductor device. About. The semiconductor device of the present invention includes a thin film transistor (TF).
This includes not only elements such as T) and MOS transistors, but also electro-optical devices such as display devices and image sensors having a semiconductor circuit composed of these insulated gate transistors. In addition, the semiconductor device of the present invention includes an electronic device equipped with the display device and the electro-optical device.

[0002]

2. Description of the Related Art In recent years, a technique for forming a TFT on a glass substrate or the like to form a semiconductor circuit has been rapidly advanced. As such a semiconductor circuit, an electro-optical device such as an active matrix type liquid crystal display device is typical.

An active matrix type liquid crystal display device is a monolithic type display device in which a pixel matrix circuit and a driver circuit are provided on the same substrate. Further, development of a system-on-panel having a built-in logic circuit such as a memory circuit and a clock generation circuit is also in progress.

Since a driver circuit and a logic circuit of an active matrix type liquid crystal display device need to operate at a high speed, it is inappropriate to use an amorphous silicon film (amorphous silicon film) as an active layer. for that reason,
At present, TFTs using a crystalline silicon film (polysilicon film) as an active layer are becoming mainstream.

[0005]

Since the TFT can be formed on a transparent glass substrate, its application to an active matrix type display device has been actively developed.
Since a TFT using a polysilicon film has high mobility, it is possible to realize a high-definition image display by integrating functional circuits on the same substrate.

In an active matrix display device, as the resolution of a screen becomes higher and higher, 1 million TFTs are required even for pixels alone. If a functional circuit is further added, a larger number of TFTs are required, and in order to operate the liquid crystal display device stably, it is necessary to secure the reliability of each TFT and to operate it stably.

In such an active matrix type display device, particularly when TFTs are provided on a substrate (eg, a glass substrate) having poor heat conductivity and good heat insulation, large voltages and currents are applied to the TFTs of the peripheral driving circuit. Since the voltage is applied, the semiconductor layer generates heat and significantly reduces the reliability of the TFT.

The present invention has been made in view of the above problems, and quickly diffuses the heat generated when driving a TFT provided on an insulating surface, so as to make the entire semiconductor device uniform. The task is to provide technology.

In the case of forming a TFT by laminating thin films formed by a CVD method, a sputtering method or the like,
When films having different internal stresses are stacked to some extent, the films are peeled off due to the interaction between the internal stresses of the respective films. An object of the present invention is to provide a technique for solving the problem of the internal stress.

[0010]

In order to solve the above-mentioned problems, the present invention provides an insulating film (SiN _{x) having} excellent thermal conductivity by using a sputtering method capable of forming a film at a low temperature and excellent in productivity. B
_Y O _Z : Here, X, Y, and Z are values representing the composition ratio, and X> 0, Y> 0, and Z> 0. ) Is used as an insulating film of a semiconductor element or a semiconductor device. Insulating film of the present invention (SiN _X B _Y O _Z) is, 0.1~50atoms% or 1~50atoms the boron element
%, Preferably 0.1 to 10 atoms%, has high thermal conductivity, and has an effect of preventing deterioration of characteristics of the semiconductor device due to heat. Further, since the insulating film of the present invention (SiN _X B _Y O _Z) has a blocking effect against mobile ions such as sodium, that these ions from the substrate or the like in a semiconductor device, penetrates especially the channel formation region It also has the effect of preventing. In addition, the insulating film of the present invention _{(SiN X B Y O Z)} , oxygen 30
atoms%, the internal stress of the film is typically -5 × 10 ¹⁰ dyn / cm ^{2 to} 5 × 10 ¹⁰ dyn / c.
m ² , preferably −10 ¹⁰ dyn / cm ² to 10 ¹⁰ dy
n / cm ² , the stress between the films is reduced, and film peeling or the like can be suppressed.

[0011] The structure of the present invention disclosed in this specification includes a gate electrode formed on an insulating surface, a gate insulating film on the gate electrode, a source region in contact with the gate insulating film, and a drain region. In a semiconductor device having a region and a channel formation region formed between the source region and the drain region, the gate insulating film further includes a silicon nitride oxide film containing a boron element. It is.

Another structure of the present invention includes a source region, a drain region, a channel forming region formed between the source region and the drain region, and A gate insulating film, and a gate electrode in contact with the gate insulating film, wherein the gate insulating film further includes a silicon nitride oxide film containing a boron element. .

According to another aspect of the present invention, in a semiconductor device having an insulating film formed on an insulating surface and a semiconductor element formed on the insulating film, the insulating film contains a boron element. A semiconductor device is a silicon nitride oxide film.

According to another aspect of the present invention, there is provided a semiconductor device having a semiconductor element formed on an insulating surface and an insulating film for protecting the semiconductor element, wherein the insulating film is a silicon nitride oxide containing a boron element. A semiconductor device, which is a film.

Further, the structure of the present invention relating to a manufacturing method for carrying out the present invention is that a silicon nitride oxide film is formed by performing sputtering using a semiconductor target to which boron element is added in an atmosphere containing a nitrogen oxide gas. Forming a semiconductor device.

In the above structure, the nitrogen oxide gas may be one or more of nitrogen monoxide gas, nitrous oxide gas, nitrogen dioxide gas, and nitrogen trioxide gas, or a mixture of these gases. It is characterized by being a gas diluted with an active gas or an oxygen gas.

Another structure of the present invention relating to the manufacturing method is that a silicon nitride oxide film containing a boron element is formed by performing sputtering using a semiconductor target in an atmosphere containing a gas containing a boron element and a nitrogen oxide gas. A method for manufacturing a semiconductor device, including a step of forming the semiconductor device.

In the above structure, the nitrogen oxide gas may be one or more of nitrogen monoxide gas, nitrous oxide gas, nitrogen dioxide gas, and nitrogen trioxide gas, or an inert gas. It is characterized by being a gas diluted with oxygen gas.

The above structure is characterized in that sputtering is performed while changing the content ratio of the boron element in the atmosphere continuously or stepwise.

Another structure of the present invention relating to a manufacturing method includes a step of forming a gate electrode on an insulating surface and a step of forming a gate insulating film made of a silicon nitride oxide film containing a boron element on the gate electrode. And a step of forming a semiconductor thin film on the gate insulating film.

In another aspect of the present invention relating to a manufacturing method, a step of forming a semiconductor thin film on an insulating surface and a step of forming a gate insulating film made of a silicon nitride oxide film containing a boron element on the semiconductor thin film And a step of forming a gate electrode on the gate insulating film.

[0022]

Embodiments of the present invention will be described with reference to FIG. Here, an insulating film (SiN _x
A bottom gate type TFT having a gate insulating film made of (B _Y O _Z ) and a manufacturing method thereof will be described.

First, a substrate 101 is prepared. Substrate 101
For example, a glass substrate, a quartz substrate, an insulating substrate such as crystalline glass, a ceramic substrate, a semiconductor substrate, a plastic substrate (polyethylene terephthalate substrate), or the like can be used.

Next, a conductive film made of a conductive material formed on the substrate 101 by a sputtering method is patterned to form a gate wiring (including a gate electrode) 102. As a material of the gate wiring 102, a material mainly composed of a conductive material or a semiconductor material, for example, Ta (tantalum),
Metal materials such as Mo (molybdenum), Ti (titanium), W (tungsten), and chromium (Cr); silicide which is a compound of these metal materials and silicon; polysilicon having N-type or P-type conductivity; Any structure can be used without particular limitation as long as the structure has at least one material layer mainly composed of a material, a low-resistance metal material Cu (copper), Al (aluminum), or the like.

Next, the substrate 101 and the gate electrode 102
Silicon nitride oxide film on _{(SiN X B Y O Z)} 103a
Is formed by a sputtering method.

The sputtering apparatus used in the embodiment of the present invention basically includes a chamber, an exhaust system for evacuating the chamber, a gas introduction system for introducing a gas for sputtering into the chamber, a target and an RF electrode. It comprises an electrode system and a sputtering power supply connected to the electrode system. Note that a nitrogen oxide gas is used as a sputtering gas. This nitric oxide gas refers to nitric oxide gas,
One or more of nitrous oxide gas, nitrogen dioxide gas, and nitric oxide gas, or these gases with an inert gas (Ar, He, Ne, N ₂ ), oxygen gas, or ammonia (NH ₃ ) It is a diluted gas. The sputtering conditions (gas for sputtering, gas flow rate, film forming pressure, substrate temperature, film forming power, etc.) are as follows: target size, substrate size, silicon nitride oxide film (SiN _X B _Y O _Z ) of thickness, a practitioner in consideration of the film quality of the silicon nitride oxide film (SiN _X B _Y O _Z) may be determined as appropriate. It is also possible to use DC power instead of RF power.

According to the present invention, the silicon nitride oxide film (Si
One of the features is a method of forming the (N _X B _Y O _Z ) 103a, and there are two methods as described below.

The first forming method of the present invention is a sputtering method using a target obtained by adding a boron element to single crystal silicon in an atmosphere containing the above-mentioned nitrogen oxide gas. Note that in the present invention, a single crystal or polycrystalline semiconductor target to which boron element is preferably added at 1 × 10 ¹⁷ cm ⁻³ or more is used. By changing the boron element content of the target, it is possible to change the composition ratio of the boron element in a silicon nitride oxide film _{(SiN X B Y O Z)} . Further, a plurality of targets, for example, a target to which a boron element is added at the same time, and another impurity (for example, gallium (Ga)) which imparts one conductivity type
By using a target to which is added, an insulating film having a more complicated composition ratio can be obtained.

The second formation method of the present invention is a method of forming a gas containing a nitrogen oxide gas and a boron element (for example, diborane:
B ₂ H ₆ ) and a sputtering method using a target made of single crystal silicon. In addition, by changing the amount of gas containing boron element, an insulating film (SiN _x
The composition ratio of B _Y O _Z) can be varied. Further, the boron element content ratio in the atmosphere may be changed continuously or stepwise so as to have a boron element concentration gradient in the film.

The above-mentioned first forming method or second forming method
Is used so that the boron element is contained in the film by 0.1 to 5
0 atoms% or 1 to 50 atoms%, preferably 0.1 to
Increasing thermal conductivity by containing 10 atoms%, oxygen in the film
Nitriding oxidation with improved adhesion by containing 1-30 atoms%
Silicon film (SiN_XB_YO_Z) Forming 103a
Can be. This silicon nitride oxide film (SiN_XB_YO
_Z) 103a contains the elemental boron, so that
Higher thermal conductivity than silicon nitride film (SiN)
Have. The silicon nitride oxide film (SiN_X
B_YO_Z) 103a contains 1-30 atoms% of oxygen
Therefore, compared with the conventional silicon nitride film (SiN)
It has high adhesion, and film peeling hardly occurs. this
Silicon nitride oxide film (SiN_XB_YO_Z) Of 103a
Partial stress is typically −5 × 10 ^Tendyn / cm^Two~ 5
× 10^Tendyn / cm^Two, Preferably -10^Tendyn /
cm^Two-10^Tendyn / cm^Two(Mo from Ionic System
is the value obtained by measuring the stress with del-30114).
No. Of course, this silicon nitride oxide film (SiN_XB
_YO_Z) Needless to say that it has enough insulation
Nor. In particular, a silicon nitride oxide film (SiN_XB
_YO_Z) Is formed in contact with the gate electrode.
The heat generated when moving is easily diffused quickly,
Efficiently soaking the entire conductor device
it can.

Next, the insulating film 103b and the amorphous semiconductor film 104 were sequentially formed without being exposed to the atmosphere. (Figure 1
(B) By doing so, the contamination of the interface can be prevented. Here, a two-layer insulating film of the insulating film 103a and the insulating film 103b is used as the gate insulating film.
It may have a single-layer structure or a stacked structure of three or more layers.

As the amorphous semiconductor film 104, an amorphous semiconductor film containing silicon, for example, an amorphous silicon film, an amorphous semiconductor film having microcrystals, a microcrystalline silicon film, an amorphous germanium film, Six An amorphous silicon germanium film represented by Ge ₁ -x (0 <X <1) or a stacked film thereof can be used in a thickness range of 10 to 80 nm, more preferably 15 to 60 nm. As a method for forming the insulating film 103b and the amorphous semiconductor film 104, a formation method such as a thermal CVD method, a plasma CVD method, a low-pressure thermal CVD method, an evaporation method, or a sputtering method can be used.

Next, the amorphous semiconductor film 104 is crystallized to form a crystalline semiconductor film 105. (Figure 1
(C) The crystallization treatment includes any known means such as thermal crystallization treatment, crystallization treatment by irradiation with infrared light or ultraviolet light (hereinafter referred to as laser crystallization), and thermal crystallization using a catalytic element. A treatment or the like or a combination of these crystallization treatments can be used.

Using the crystalline semiconductor film 105 thus obtained as an active layer, a bottom gate type TFT is manufactured. Although the crystalline semiconductor film 105 is used here as an active layer, a bottom gate type TFT may be manufactured using an amorphous semiconductor film as an active layer without performing crystallization. Further, since the subsequent steps may be manufactured according to a known manufacturing method, detailed description will be omitted.

Here, the film contains boron element in an amount of 0.1 to 5%.
0 atoms% or 1 to 50 atoms%, preferably 0.1 to
Containing 10atoms%, but oxygen the example of using an insulating film containing 1～30Atoms% of (SiN _X B _Y O _Z) as one layer of the gate insulating film of the bottom gate type TFT, and particularly limited as long as it is an insulating film Instead, for example, it can be used for a base film, an interlayer insulating film, a mask insulating film, a channel protective film, a protective film, and the like. In addition, it can be used for an insulating film used for a top gate type TFT, for example, a base film, a gate insulating film, a mask insulating film, an interlayer insulating film, a protective film, and the like. Further, the present invention can be applied to an insulating film used for a forward stagger type TFT. Thus, the present invention provides a TFT
It can be applied regardless of the structure.

Thus, the elemental boron is contained in the film in an amount of 0.1 to 5%.
0 atoms% or 1 to 50 atoms%, preferably 0.1
Containing ～10Atoms%, the semiconductor device of oxygen 1～30Atoms% containing the silicon nitride oxide film (SiN _X B _Y O _Z) was used as the insulating film, and rapidly diffuse the heat generated when driving the TFT As a result, the entire semiconductor device can be soaked, so that higher reliability can be provided as compared with the related art.

Of course, a silicon oxynitride film (SiN ₁ −) containing 1-30 atoms% of oxygen in the film to improve the adhesion.
x Ox (0 <X <1): where X is a value representing a composition ratio. Can be used for an insulating film used for a TFT.

[0038]

Embodiments of the present invention will be described below, but it is needless to say that the present invention is not limited to these embodiments.

Example 1 Hereinafter, referring to FIGS.
Embodiments of the present invention will be described in detail.

First, a glass substrate (Corning 1737; strain point 667 ° C.) was prepared as the substrate 101. Then
A gate wiring (including a gate electrode) 102 having a laminated structure (not shown for simplicity) was formed on a substrate 101. In this embodiment, a tantalum nitride film (thickness: 50 nm) and a tantalum film (thickness: 250 nm) are stacked by sputtering, and a gate wiring having a stacked structure is formed by photolithography, which is a known patterning technique. 102 (including a gate electrode).

Next, the film thickness range is set to 1 to 3 by the sputtering method.
1000 nm, preferably silicon nitride oxide film containing boron element is _{10~100nm (SiN X B Y O Z} ) 10
3a is formed. (FIG. 1A) In this embodiment, sputtering is performed using a single crystal silicon target to which boron element is added in an atmosphere containing a nitrogen oxide gas (here, to form a 50nm silicon nitride oxide film _{(SiN X B Y O Z)} . Further, in an atmosphere using nitrogen oxide gas and diborane (B ₂ H ₆ ), a silicon nitride oxide film (SiN _X B _Y O _Z ) is formed by a sputtering method using a target made of single crystal silicon. Is also good. Thus obtained silicon nitride oxide film (SiN _X B _Y O _Z) has a high thermal conductivity because they boron element contained 0.1～50Atoms%, characteristic deterioration due to heat of the semiconductor device It has the effect of preventing. Further, since the silicon nitride oxide film has a blocking effect on mobile ions such as sodium, the silicon nitride oxide film also has an effect of preventing these ions from entering a semiconductor device, particularly, a channel formation region from a substrate or the like. .

Next, the insulating film 103b and the amorphous semiconductor film 104 were sequentially formed without opening to the atmosphere. (Figure 1
(B)) In this embodiment, the silicon oxide film 103b (film thickness 1)
(25 nm) by plasma CVD to form a gate insulating film having a laminated structure. In this embodiment, a two-layer insulating film is used as the gate insulating film, but a single layer or a stacked structure of three or more layers may be used. In this embodiment, the amorphous semiconductor film 104 is formed on the gate insulating film to a thickness of 54 n.
m amorphous silicon film (amorphous silicon film) was formed by a plasma CVD method. Note that, in order to prevent contaminants from the atmosphere from adhering to the interfaces of any of the layers, the layers were sequentially formed without opening to the atmosphere. After that, heat treatment (at 500 ° C. for one hour) was performed to reduce the concentration of hydrogen in the amorphous silicon film which prevented crystallization of the semiconductor film.

When the state shown in FIG. 1B is obtained,
The amorphous semiconductor film 104 was crystallized by irradiation with infrared light or ultraviolet light (laser crystallization) to form a crystalline semiconductor film (semiconductor film containing crystals) 105. (Figure 1
(C) When ultraviolet light is used as a crystallization technique, excimer laser light or strong light generated from an ultraviolet lamp may be used. When infrared light is used, strong light generated from an infrared laser light or an infrared lamp may be used. It may be used. In this embodiment, a KrF excimer laser beam is formed into a linear beam for irradiation. As the irradiation condition, the pulse frequency is 30 Hz, an overlap ratio is 96%, the laser energy density in this example be 100 to 500 mJ / cm ² was 360 mJ / cm ^2. Note that conditions for laser crystallization (wavelength of laser light, overlap ratio, irradiation intensity, pulse width, repetition frequency, irradiation time, etc.) are determined in consideration of the thickness of the amorphous semiconductor film 104, the substrate temperature, and the like. May be determined as appropriate. Depending on the laser crystallization conditions, the initial semiconductor film may be crystallized after passing through a molten state, or the initial semiconductor film may be crystallized in a solid state without melting or in an intermediate state between a solid phase and a liquid phase. May be. In this step, the amorphous semiconductor film 104 is crystallized and changes to a crystalline semiconductor film 105. In this embodiment, the crystalline semiconductor film is a polycrystalline silicon film (polysilicon film).

Next, the thus-formed crystalline semiconductor 1
An insulating film (which will later become a channel protective film) 106 for protecting a channel formation region is formed on the substrate 05. In this embodiment, a silicon oxide film (200 nm thick) was formed. Then
A resist mask 107 was formed in contact with the insulating film 106 by patterning using a backside exposure (film formation, exposure, and development of a resist film). (FIG. 1D) The formation of a resist mask by exposure from the back does not require a mask, so that the number of manufacturing masks can be reduced. As shown in the figure, the size of the resist mask became slightly smaller than the width of the gate wiring due to light wraparound.

Next, the insulating film 106 was etched using the resist mask 107 as a mask to form a channel protective film 108, and then the resist mask 107 was removed. (FIG. 1E) By this step, the channel protective film 1 is formed.
The surface of the crystalline silicon film other than the region in contact with 08 was exposed. The channel protective film 108 serves to prevent a dopant from being added to a region to be a channel formation region in a later doping step. In this embodiment, a silicon oxide film is used as the channel protective film 108,
It may be configured to prevent the characteristic degradation due to heat of the semiconductor device using a silicon nitride oxide film containing boron element of the present invention in place of the silicon oxide film _{(SiN X B Y O Z)} .

Next, a resist mask 109 covering a part of the n-channel TFT or the p-channel TFT is formed by patterning using a photomask, and an impurity element for imparting n-type to the crystalline semiconductor film whose surface is exposed is provided. Was performed to form a first impurity region (n ⁺ region) 110a. (FIG. 2A) In this example, phosphorus element was used as an impurity for imparting n-type conductivity. Phosphine (PH ₃ ) diluted to 1 to 10% (5% in this embodiment) with hydrogen is used as the doping gas, the dose is 5 × 10 ¹⁴ atoms / cm ² , and the acceleration voltage is 1
0 kV. In addition, the width of the n ⁺ -type region is determined by the practitioner appropriately setting the pattern of the resist mask 109, and it is relatively easy to obtain the n ⁻ -type region and the channel formation region having the desired width. .

Next, after removing the resist mask 109, an insulating film 111 for forming an LDD region was formed. (FIG. 2B) In this embodiment, a silicon oxide film (50 nm thick) is used as the insulating film 111 by plasma CVD.
It was formed by a method. In this embodiment, a silicon oxide film is used as the insulating film 111. However, instead of the silicon oxide film, a silicon nitride oxide (SiN
_X B _Y O _Z) may be configured to prevent the characteristic degradation due to heat of the semiconductor device used.

Next, an insulating film 111 was provided on the surface.
Adding an impurity element imparting n-type to the crystalline semiconductor film
The process is performed, and the second impurity region (n^-Region) 112
Formed. (FIG. 2 (C)) However, through the insulating film 111,
In order to add impurities to the crystalline semiconductor film below
Considering the thickness of the insulating film 111, doping conditions as appropriate
It is important to set. In this embodiment, doping is performed.
Dilute to 1 to 10% (5% in this example) with hydrogen as gas
Using phosphine, which has been released, with a dose of 3 × 10 ¹³atoms
/ Cm^TwoAnd the acceleration voltage was 60 kV. This insulating film 11
1 by adding an impurity element through
(1 × 10 by SIMS analysis)¹⁸~ 1 × 10 ¹⁹atoms / cm
^Three) Could be formed. Also,
The second impurity region 112 formed by
Function. At this time, impurities are further added.
To form first impurity region 110b, thereby protecting the channel.
An intrinsic crystalline semiconductor region remained immediately below the film. However
Although not shown in the figure, actually, it is slightly inside the channel protective film.
The impurity element is added around.

[0049] Next, a resist mask 114 covering the n-channel type TFT using a photomask, subjected to the step of adding an impurity element imparting p-type crystalline semiconductor film, a third impurity region (p ⁺ (Region) 113 was formed. (FIG. 2D) In this example, B (boron element) was used as an impurity element imparting p-type. The doping gas is diborane (B) diluted to 1 to 10% with hydrogen.
₂ H ₆ ) at a dose of 4 × 10 ¹⁵ atoms / cm ² ,
The acceleration voltage was 30 kV.

Next, after removing the resist mask 114 and performing an impurity activation treatment by laser annealing or thermal annealing, a heat treatment (350
C., 1 hour), and the whole was hydrogenated. (FIG. 3
(A)) Thereafter, an active layer having a desired shape was formed by a known patterning technique, and the channel protective film 108 and the insulating film 111 covering the active layer were removed. (FIG. 3
(B))

Through the above steps, the source region 115, drain region 116, low concentration impurity regions 117 and 118, and channel formation region 119 of the n-channel TFT are formed, and the source region 121 and drain region 122 of the p-channel TFT are formed. Thus, a channel forming region 120 was formed.

Next, the n-channel TFT and the p-channel TFT are covered with a film thickness of 10 by plasma CVD.
An interlayer insulating film 123 having a stacked structure of a 0-nm-thick silicon oxide film and a 940-nm-thick silicon oxide film using TEOS and oxygen (O ₂ ) as a source gas was formed. (FIG. 3
(C)) In this embodiment, a silicon oxide film is used as the interlayer insulating film 123. However, instead of the silicon oxide film, silicon nitride oxide containing a boron element of the present invention (SiN _{X BY)}
O _Z ) may be used to prevent the characteristic deterioration of the semiconductor device due to heat.

Then, contact holes were formed to form source wirings 124 and 126 and drain wirings 125 and 127, and the state shown in FIG. 3D was obtained. Finally, heat treatment was performed in a hydrogen atmosphere, and the whole was hydrogenated to complete an n-channel TFT and a p-channel TFT.

In this embodiment, the crystallization process may be performed after patterning the amorphous semiconductor film by changing the process order. In addition, the order of the impurity adding step in this embodiment is not limited, and the practitioner may appropriately change the order of the impurity adding step to form the impurity region.

Second Embodiment In the first embodiment, the amorphous silicon film is crystallized by the laser beam. In the second embodiment, the amorphous semiconductor film is crystallized by a method different from that in the first embodiment. Here is an example. Hereinafter, this embodiment will be described with reference to FIGS.

First, as in the first embodiment,
A gate electrode 102 and gate insulating films 103a and 103b were formed. (FIG. 4A) Since the steps up to this point are the same as those in Example 1, the same reference numerals are used as in FIG. Note that the gate insulating film 103a is a silicon nitride oxide film containing boron element _{(SiN X B Y O Z)} .

Next, an amorphous silicon film 104a was formed according to the first embodiment. Next, in an oxygen atmosphere, UV
By irradiating light, an extremely thin oxide film (not shown) is formed on the surface of the amorphous silicon film 104a. This oxide film has a function of improving the wettability of a solution containing nickel to be applied later.

Next, a solution containing nickel is applied to the surface of the amorphous silicon film 104a. Nickel content (weight conversion) is 0.1 to 50 ppm, more preferably 1 ppm
What is necessary is just to 30 ppm. This is because the nickel concentration in the amorphous silicon film 104a is 10 ¹⁵ to 10 ¹⁹ atoms / cm ^3.
This is for order. If it is less than 10 ¹⁵ atoms / cm ³ , the catalytic action of nickel cannot be obtained. 10 ¹⁹
With a concentration of about atoms / cm ^3, a TFT that can operate even without performing gettering can be manufactured, and this is also for efficiently performing the gettering process. Note that the nickel concentration is defined by the maximum value measured by SIMS.

In this embodiment, a nickel acetate solution containing 10 ppm of nickel was applied. Then, the substrate 101 is rotated by a spin coater, and excess nickel acetate solution is blown off to remove the amorphous nickel film 10.
An extremely thin nickel-containing layer 205 is formed on the surface of 4a.
(FIG. 4 (B))

When the state shown in FIG. 4B was obtained, the amorphous silicon film 104a was crystallized by heating at 550 ° C. for 4 hours in a nitrogen atmosphere. Through this crystallization step, a crystalline silicon film 204b was obtained. This crystal growth is performed from the surface of the amorphous silicon film 104a to which nickel is added.
01 (vertical direction), this is referred to as vertical growth in this specification (FIG. 4C). In this embodiment, the nickel-containing layer is formed on the entire surface. However, the nickel-containing layer is selectively formed using a resist or the like, and the crystallization proceeds in a direction (lateral direction) parallel to the substrate surface. It may be.

Although a polycrystalline silicon film including grain boundaries is formed according to this crystallization step, a microcrystalline silicon film can be formed under different conditions.

The above heat treatment is carried out in an electric furnace for 50 hours.
It can be performed at a temperature of 0 to 700 ° C, more preferably 550 to 650 ° C. At this time, the upper limit of the heating temperature needs to be lower than the glass strain point of the glass substrate 101 used in consideration of heat resistance. If the glass strain point is exceeded, warpage and shrinkage of the glass substrate become apparent. The heating time may be about 1 to 12 hours. This heat treatment is performed by furnace annealing (heat treatment in an electric furnace). Note that it is also possible to use heating means such as lamp annealing.

Next, the obtained crystalline silicon film 204b
Is irradiated with laser light to obtain a crystalline silicon film 204c with improved crystallinity. In this embodiment, a pulse oscillation type KrF excimer laser (wavelength: 248 nm)
Was used (FIG. 4 (D)). Note that an ultrathin oxide film formed to improve the wettability of the solution may be removed before laser light irradiation.

As a pulse oscillation type laser, a short wavelength (ultraviolet region) XeCl excimer laser or a long wavelength Y
An AG laser or the like is used. Since the excimer laser used in this embodiment oscillates ultraviolet light, melting and solidification are repeated instantaneously in the irradiated area. Therefore, by irradiating the excimer laser beam, a kind of non-equilibrium state is formed, and nickel becomes very mobile.

In the crystalline silicon film 204b obtained in the crystallization step shown in FIG. 4C, amorphous components remain irregularly. However, since such an amorphous component can be completely crystallized by irradiation with a laser beam shown in FIG. 4D, the crystallinity of the crystalline silicon film 204c is greatly improved.

Although the laser irradiation step can be omitted, the laser irradiation has the effect of improving the efficiency of the later gettering step in addition to improving the crystallinity. After the laser irradiation, the SIM of the residual nickel concentration in the crystalline silicon film 204c
The maximum value of S is about 1 × 10 ¹⁹ to 2 × 10 ¹⁹ atoms / cm ³ .

After the crystallization step, a gettering technique (Japanese Patent Laid-Open No. 10-270363) for removing or reducing the catalytic element remaining in the crystalline silicon film may be used. This publication describes a technique of performing a heat treatment (300 to 700 ° C., 1 to 12 hours) after the entire or selective addition of the phosphorus element. Further, a method using a liquid phase using high-temperature sulfuric acid, a method using a gas phase containing a halogen element, or a method using a method in which a boron element is added and heated may be used.

Next, in the same manner as in the step shown in FIG. 1D of the first embodiment, an insulating film (to be a channel protective film later) 206 for protecting a channel formation region having a thickness of 200 nm is formed on the crystalline semiconductor 204c. did. In this embodiment, a silicon oxide film is used as the insulating film 206. However, instead of the silicon oxide film, silicon nitride oxide containing a boron element (SiN _X B _Y O _Z ) of the present invention is used and heat generated by a semiconductor device is used. A configuration for preventing characteristic deterioration may be adopted. Next, the insulating film 206 is patterned by patterning using exposure from the back side.
Then, a resist mask 207 was formed. (FIG. 4
(E))

Next, the insulating film 206 was etched using the resist mask 207 as a mask to form a channel protective film 208, and then the resist mask 207 was removed. (FIG. 4 (F))

Next, a resist mask 209 covering a part of the n-channel TFT or the p-channel TFT is formed by patterning using a photomask, and an impurity element for imparting n-type to the crystalline semiconductor film whose surface is exposed is provided. A step of adding (phosphorus) was performed to form a first impurity region (n ⁺ region) 210a. (FIG. 5A) In this embodiment, phosphine (PH ₃ ) diluted to 1% to 10% (5% in this embodiment) with hydrogen is used as a doping gas, and the dose amount is 5 × 10 ¹⁴ atoms / cm ^2. The accelerating voltage was 10 kV.

Next, the resist mask 209 was removed.
Then, a control insulating film for forming an LDD region (this embodiment)
Now, a 50 nm-thick silicon oxide film) 211 is formed.
Was. (FIG. 5B) In this embodiment, the control insulating film 211 is used.
Used a silicon oxide film, but instead of a silicon oxide film
The silicon nitride oxide (SiN) containing boron element of the present invention _X
B_YO_Z) To prevent deterioration of characteristics of semiconductor devices due to heat
It may be configured to stop.

Next, a step of adding an impurity element imparting n-type to the crystalline semiconductor film provided with the control insulating film 211 on the surface is performed, and the second impurity region (n ⁻ region) 21 is formed.
2 was formed. (FIG. 5C) In this embodiment, a phosphine diluted to 1 to 10% (5% in this embodiment) with hydrogen is used as a doping gas, and a dose amount is 3 × 10 ¹³ atoms.
/ Cm ² , and the acceleration voltage was 60 kV. A desired concentration (1 × 10 ¹⁸ to 1 × 10 ¹⁹ atoms / SIMS by SIMS analysis) can be obtained by adding an impurity element through the control insulating film 211.
cm ³ ) of the impurity region could be formed. Also,
The second impurity region 212 thus formed functions as an LDD region. At this time, the first impurity region 210b was further formed by adding an impurity, and an intrinsic crystalline semiconductor region remained immediately below the channel protective film.

[0073] Next, a resist mask 214 covering the n-channel type TFT using a photomask, subjected to the step of adding an impurity element imparting p-type crystalline semiconductor film, a third impurity region (p ⁺ Region 213 was formed. (FIG. 5 (D)) In this embodiment, diborane (B ₂ H ₆ ) diluted to 1 to 10% with hydrogen is used as the doping gas, the dose amount is 4 × 10 ¹⁵ atoms / cm ² , and the acceleration voltage is 3
0 kV.

Then, the resist mask 214 is removed, and a heat treatment at 300 to 700 ° C. for 1 to 12 hours is performed to reduce the nickel concentration (JP-A-8-330602). . In the present embodiment, 600 ° C., 8
Heat treatment is performed for a long time to move nickel remaining inside the LDD region and the channel formation region toward the high-concentration impurity regions (source region and drain region).
(FIG. 6A) The channel formation region in which the nickel concentration is reduced (1 × 10 ¹⁸ atoms / cm by SIMS analysis)
³ or less, preferably 1 × 10 ¹⁶ atoms / cm ³ or less). At the same time as the reduction of the catalytic element by this heat treatment, recovery of crystallinity damage during doping and activation treatment of impurities by thermal annealing are performed. In addition, furnace annealing, laser annealing or lamp annealing may be performed. Then, heat treatment (350
C., 1 hour), and the whole was hydrogenated.

Thereafter, an active layer having a desired shape was formed by a known patterning technique, and the insulating film 211 and the channel protective film 208 were removed. (FIG. 6 (B))

Through the above steps, a source region 215, a drain region 216, low-concentration impurity regions 217 and 218, and a channel formation region 219 of the n-channel TFT are formed, and a source region 221 and a drain region 222 of the p-channel TFT are formed. Thus, a channel forming region 220 was formed.

Next, the n-channel TFT and the p-channel TFT are covered with a film thickness of 10 by plasma CVD.
An interlayer insulating film 223 having a stacked structure of a 0-nm-thick silicon oxide film and a 940-nm-thick silicon oxide film using TEOS and oxygen (O ₂ ) as a source gas was formed. (FIG. 6
(C) In this embodiment, a silicon oxide film is used as the interlayer insulating film 223. However, instead of the silicon oxide film, a silicon nitride oxide film containing a boron element of the present invention (SiN _x B)
_(Y O _Z ) may be used to prevent deterioration of characteristics of the semiconductor device due to heat.

Then, contact holes were formed to form source wirings 224 and 226 and drain wirings 225 and 227, and the state shown in FIG. 6D was obtained. Finally, heat treatment was performed in a hydrogen atmosphere, and the whole was hydrogenated to complete an n-channel TFT and a p-channel TFT.

[Embodiment 3] FIGS. 7A to 7C show a semiconductor device provided with an n-channel TFT and a p-channel TFT using the manufacturing process of Embodiment 1 or 2.
An example of the structure will be described with reference to FIG. 8C and FIGS.

The semiconductor device according to the present invention includes a peripheral drive circuit section and a pixel matrix circuit section on the same substrate. In this embodiment, for the sake of simplicity of illustration, FIG. 7 shows a CMOS circuit constituting a part of the peripheral drive circuit section.
A pixel TFT (N
FIG. 8 shows a channel type TFT). Example 1
2 and 2, a passivation film (protective film) 319 having a thickness of 0.2 to 0.4 μm was formed. As the passivation film 319, it is preferable to use a nitrogen silicon film, for example, a silicon nitride oxide film containing a boron element (SiN _X B _Y O _Z ), so as to prevent deterioration of characteristics of the semiconductor device due to heat.

The CMOS circuit shown in FIG. 7 is also called an inverter circuit and is a basic circuit constituting a semiconductor circuit. By combining such inverter circuits, N
A basic logic circuit such as an AND circuit or a NOR circuit can be formed, or a more complicated logic circuit can be formed.

FIG. 7A is a diagram corresponding to the top view of FIG. 7B. In FIG. 7A, a portion cut along a dotted line AA ′ is a CMOS circuit of FIG. 7B. Corresponding to the cross-sectional structure. Further, FIG. 7 (C) shows FIGS. 7 (A) and 7
It is a circuit diagram of an inverter circuit corresponding to (B).

In FIG. 7B, all TFTs (thin film transistors) are formed on a substrate 301. C
In the case of a P-channel type TFT of the MOS circuit, the gate electrode 302 is formed, the first insulating film 303 made of a silicon nitride oxide film (SiN _X B _Y O _Z) containing the boron element thereon, composed of silicon oxide A second insulating film 304 is provided. On the second insulating film, ap ⁺ region 31 is formed as an active layer.
2 (drain region), 315 (source region) and a channel formation region 314 are formed. In the first and second embodiments, in order to reduce the number of steps, a low-concentration impurity region (LDD region) is not provided between the high-concentration impurity region and the channel formation region in the P-channel TFT. Good. A contact hole is formed in first interlayer insulating film 317 covering the active layer, wirings 318 and 320 are connected to p ⁺ regions 312 and 315, and a passivation film 319 is formed thereon. Although not shown for the sake of simplicity, a second interlayer insulating film is further formed thereon, a lead wiring is connected to the wiring 320, and a third interlayer insulating film is formed so as to cover the second interlayer insulating film.

On the other hand, in an N-channel type TFT, an n ⁺ region (source region) 305 and an n ⁺ region 311 are used as active layers.
(Drain region), a channel forming region 309, and an n ⁻ type region 30 between the n ⁺ type region and the channel forming region.
6, 310 are formed. Note that the n ⁻ -type region 310 in contact with the drain region is formed wider than the n ⁻ -type region 306 to improve reliability. A contact hole is formed in first interlayer insulating film 317 covering the active layer, wirings 316 and 318 are formed in n ⁺ -type regions 305 and 311, and a passivation film 319 is formed thereon. Although not shown for the sake of simplicity, a second interlayer insulating film is further formed thereon, a lead wiring is connected to the wiring 320, and a third interlayer insulating film is formed so as to cover the second interlayer insulating film. The portion other than the active layer is the same as the P-channel type TF.
The structure is substantially the same as T, and the description is omitted for simplification.

FIG. 8A is a diagram corresponding to the top view of FIG. 8B, and in FIG. 8A, a dotted line AA ′ is shown.
The portion cut by corresponds to the cross-sectional structure of the pixel matrix circuit in FIG. FIG. 8C is a view similar to FIG.
FIG. 9 is a circuit diagram corresponding to FIG.

N channels formed in the pixel matrix circuit
Basically, the CMOS type N-channel TFT
It has the same structure as the channel type TFT. Game on the substrate 401
Electrode 403 is formed thereon, and a nitride electrode containing boron element is formed thereon.
Silicon oxide (SiN)_XB _YO_ZThe first insulation consisting of
A film 402 and a second insulating film 404 made of silicon oxide are provided.
Have been. On the second insulating film, n is formed as an active layer.⁺Area 4
05, 409 and 414, and channel formation regions 407 and 4
11 and n⁺N between the mold region and the channel formation region^-
Mold regions 406 and 413 are formed. Over the active layer
A contact hole is formed in first interlayer insulating film 419.
And n⁺A wiring 416 is connected to the region 405, and n⁺region
A wiring 417 is connected to 414, and a passivation
The activation film 418 is formed. And on top of it
Two interlayer insulating films 420 are formed. And on top of that
A third interlayer insulating film 422 is formed, and ITO, SnO_Two
The pixel electrode 423 made of a transparent conductive film is connected.
Reference numeral 421 denotes a pixel electrode adjacent to the pixel electrode 423.
You.

The capacitance portion of the pixel matrix circuit is formed by using the first insulating film and the second insulating film as dielectrics,
5 and an n ⁺ region 414.

In this embodiment, a transmissive LCD is manufactured as an example, but there is no particular limitation. For example, a reflective LCD can be manufactured by using a reflective metal material as the material of the pixel electrode and changing the patterning of the pixel electrode or adding / deleting some steps as appropriate.

In this embodiment, the gate wiring of the pixel TFT of the pixel matrix circuit has a double gate structure. However, a multi-gate structure such as a triple gate structure may be used in order to reduce variation in off current. Further, a single gate structure may be used to improve the aperture ratio.

The TFT manufactured according to this embodiment is
It shows electrical characteristics with less variation. This embodiment can be combined with the first and second embodiments.

[Embodiment 4] This embodiment will be described with reference to FIGS. In Examples 1 and 2, to further the gate insulating film of the bottom gate type TFT, and an example is shown of using a silicon nitride oxide containing a boron element _{(SiN X B Y O Z)} , in this embodiment, the top and further the base film gate type TFT, and an example of using a silicon nitride oxide containing a boron element _{(SiN X B Y O Z)} .

Here, an example in which an n-channel TFT and a p-channel TFT are formed over the same substrate to form an inverter circuit which is a basic configuration of a CMOS circuit will be described.

As the substrate 501, a glass substrate, a plastic substrate, a ceramic substrate, or the like can be used. Alternatively, a silicon substrate having a surface over which an insulating film such as a silicon oxide film or a silicon nitride oxide film is formed, or a metal substrate represented by stainless steel may be used. Of course, a quartz substrate can be used.

Then, on the main surface of the substrate 501 where the TFT is to be formed, silicon nitride oxide (Si
And N _X B _Y O _Z) base film 502 made of a base film 503 made of a silicon nitride oxide film is formed. In this embodiment, in an atmosphere containing argon (Ar) and diborane (B ₂ H ₆ ), silicon nitride oxide (SiN) is formed by sputtering using a target made of single crystal silicon.
To form _X B _Y O _Z) 502. Further, in an atmosphere containing nitrogen (N ₂ ) or ammonia (NH ₃ ), a silicon nitride oxide (SiN _X B _Y O _Z ) is formed by a sputtering method using a target of single crystal silicon to which a boron element is added. May be formed. Silicon nitride oxide thus obtained _{(SiN X B Y O Z)} 502 is
Since it contains 1 to 50 atoms% of boron element, it has high thermal conductivity and has an effect of preventing deterioration of characteristics of the semiconductor device due to heat. The base film 503 is made of plasma C
It may be formed by a VD method or a sputtering method, and is provided to prevent impurities harmful to the TFT from the substrate 501 from diffusing into the semiconductor layer. Therefore, the base film 5 consisting of a silicon nitride oxide containing a boron element (SiN _X B _Y O _Z)
02 is formed to a thickness of 20 to 100 nm, typically 50 nm, and a base film 50 made of a silicon nitride oxide film is further formed.
3, 50 to 500 nm, typically 150 to 200 nm
It should have laminated | stacked to thickness of.

[0095] Of course, the base film 502 made a base film from a silicon nitride oxide containing a boron element _{(SiN X B Y O Z)} ,
Alternatively, it may be formed using only one of the base films 503 made of a silicon nitride oxide film. However, in consideration of the reliability of the TFT, a two-layer structure is most desirable.

The semiconductor layer formed in contact with the base film 503 is formed by converting an amorphous semiconductor formed by a film forming method such as a plasma CVD method, a low pressure CVD method, or a sputtering method to a solid phase formed by a laser crystallization method or heat treatment. It is desirable to use a crystalline semiconductor crystallized by a growth method. Further, a microcrystalline semiconductor formed by the above film formation method can be used. The semiconductor material applicable here includes silicon (Si), germanium (Ge), a silicon germanium alloy, and silicon carbide. In addition, a compound semiconductor material such as gallium arsenide can be used.

The semiconductor layer is formed to have a thickness of 10 to 100 nm, typically 50 nm. 10 to 40 at for an amorphous semiconductor film formed by a plasma CVD method.
Although hydrogen is contained in the film at a ratio of om%, a heat treatment process at 400 to 500 ° C. is performed prior to the crystallization process to desorb hydrogen from the film to reduce the hydrogen content to 5 atom% or less. It is desirable to keep. Although an amorphous silicon film may be formed by another manufacturing method such as a sputtering method or an evaporation method, it is preferable that impurity elements such as oxygen and nitrogen contained in the film be sufficiently reduced.

Since the base film and the amorphous semiconductor film can be formed by the same film formation method, the base film 503 and the semiconductor layer are preferably formed continuously. After each film is formed,
Since the surface does not come into contact with the atmosphere, contamination of the surface can be prevented. As a result, it was possible to eliminate one of the factors that cause variations in TFT characteristics.

For the step of crystallizing the amorphous semiconductor film, a known laser crystallization technique or thermal crystallization technique may be used. Further, when a crystalline semiconductor film is formed by a thermal crystallization technique using a catalytic element, excellent TFT characteristics can be obtained.

Using the first photomask, a resist mask was formed on the thus formed crystalline semiconductor film by a known patterning method, and island-like semiconductor layers 504 and 505 were formed by dry etching.

Next, a gate insulating film 506 containing silicon oxide or silicon nitride as a main component is formed on the surfaces of the island-shaped semiconductor layers 504 and 505. Also, the gate insulating film 5
06, silicon nitride oxide containing boron element (SiN
_X B _Y O _Z) may be configured to prevent the characteristic degradation due to heat of the semiconductor device used. The gate insulating film 506 is formed by a plasma CVD method or a sputtering method, and has a thickness of 10
The thickness may be set to 200 nm, preferably 50 to 150 nm.

Then, the first surface of the gate insulating film 506 is
Of the conductive layer 507 and the third conductive layer 508 were formed.
For the first conductive layer 507, a conductive material mainly containing an element selected from Ta, Ti, Mo, and W is used. And
The thickness of the first conductive layer 507 may be 5 to 50 nm, preferably 10 to 25 nm.

The gate insulating film 506 and the first conductive layer 507
The thickness was important. This is because an impurity imparting n-type is passed through the gate insulating film 506 and the first conductive layer 507 in a first impurity doping step performed later,
This is for adding to the semiconductor layers 504 and 505. Actually, the conditions of the first impurity doping step were determined in consideration of the thicknesses of the gate insulating film 506 and the first conductive layer 507. Here, the gate insulating film 506 and the first conductive layer 507
This is because if the thickness of the layer fluctuates by 10% or more from a predetermined value, the concentration of the added impurity decreases.

For the third conductive layer 508, a conductive material containing Al or Cu as a main component is used. For example, when Al is used, the element selected from Ti, Si, and Sc is 0.1%.
An Al alloy to which about 5 atom% is added may be used. The third conductive layer has a thickness of 100 to 1000 nm, preferably 200 to 4 nm.
It may be formed with a thickness of 00 nm. This is formed as a wiring material for reducing the wiring resistance of the gate wiring or the gate bus line. (FIG. 9A)

In the present invention, the gate wiring is a wiring formed on the gate insulating film 506 from the same material as the gate electrode and connected to the gate electrode. Is considered part of.

Next, a resist mask was formed using a second photomask, and an unnecessary portion of the third conductive layer was removed to form a part of a gate bus line (FIG. 9B). 509). When the third conductive layer was Al, it could be removed with good selectivity from the underlying first conductive layer by a wet etching method using a phosphoric acid solution.

Then, resist masks 510 and 511 which cover the semiconductor layer 504 and a channel formation region of the semiconductor layer 505 were formed using a third photomask. At this time, a resist mask 512 may be formed in a region where a wiring is to be formed.

Then, a step of adding a first impurity element imparting n-type was performed. N for crystalline semiconductor material
As an impurity element for imparting a mold, phosphorus (P), arsenic (As), antimony (Sb) and the like are known.
Here, ion doping was performed using phosphorus and phosphine (PH ₃ ). In this step, the acceleration voltage was set to be as high as 80 keV in order to add phosphorus to the underlying semiconductor layer through the gate insulating film 506 and the first conductive film 507. The concentration of phosphorus added to the semiconductor layer is 1
It is preferable to set the range of × 10 ¹⁶ to 1 × 10 ¹⁹ atoms / cm ³ , and here, it is set to 1 × 10 ¹⁸ atoms / cm ³ . And
Regions 513 and 514 in which phosphorus was added to the semiconductor layer were formed. A part of the region to which phosphorus is formed is a second impurity region which functions as an LDD region. (Fig. 9 (B))

Thereafter, the resist masks 510, 511,
512 was removed to form a second conductive layer 515 on the front surface. The second conductive layer 515 may be formed using the same material as the first conductive layer 507, and uses a conductive material mainly containing an element selected from Ta, Ti, Mo, and W. And
The thickness of the second conductive layer 515 may be 100 to 1000 nm, preferably 200 to 500 nm.
(FIG. 9 (C))

Next, resist masks 516, 517, 518, and 519 were formed using a fourth photomask. The fourth photomask was for forming a gate electrode of a p-channel TFT, a gate wiring, and a gate bus line. Since a gate electrode of the n-channel TFT was formed in a later step, a resist mask 517 was formed so that the first conductive layer 522 and the second conductive layer 523 remained on the semiconductor layer 505.

Unnecessary portions of the first conductive layer and the second conductive layer were removed by dry etching. Then, the gate electrodes 520 and 521, the gate wirings 524 and 525,
Gate bus lines 526 and 527 were formed.

The gate bus line is connected to the third conductive layer 509
Was formed as a clad-type structure covered with the first conductive layer 526 and the second conductive layer 527. The third conductive layer was a low-resistance material containing Al or Cu as a main component, and was able to reduce wiring resistance.

Then, the resist masks 516, 517,
518, 519, p-channel TFT
Was added to a part of the semiconductor layer 504 in which is formed a third impurity element imparting p-type. As the impurity element imparting the p-type, boron (B), gallium (Ga), or the like is known, but here, the boron element is used as an impurity element, and diborane (B ₂ H ₆ ) is used for the ion doping method. Was added. Again, the acceleration voltage is 80 ke
As V, a boron element was added at a concentration of 2 × 10 ²⁰ atoms / cm ³ . Then, as shown in FIG. 9D, the third impurity regions 552 and 553 to which the boron element is added at a high concentration.
Was formed.

After removing the resist mask provided in FIG. 9D, resist masks 528, 529, and 530 were newly formed using a fifth photomask. The fifth photomask is for forming a gate electrode of an n-channel TFT, and the gate electrodes 531 and 532 are formed by a dry etching method. At this time, the gate electrode 53
1 and 532 are formed so as to overlap a part of the second impurity regions 513 and 514. (FIG. 9E)

Then, resist masks 528, 529,
After completely removing 530, the resist masks 533, 5
34, 535 were formed. The resist mask 534 was formed so as to cover the gate electrodes 531 and 532 of the n-channel TFT and part of the second impurity region.
The resist mask 534 determines the offset amount of the LDD region.

Then, a step of adding a second impurity element imparting n-type was performed. Then, a first impurity region 537 serving as a source region and a first impurity region 536 serving as a drain region were formed. Here, the ion doping method using phosphine was performed. Also in this step, the acceleration voltage was set as high as 80 keV in order to add phosphorus to the underlying semiconductor layer through the gate insulating film 506. The concentration of phosphorus in this region is higher than that in the step of adding the first impurity element imparting n-type, and is 1 × 10 ¹⁹ to
It is preferably 1 × 10 ²¹ atoms / cm ^3.
× 10 ²⁰ atoms / cm ³ . (FIG. 10A)

Then, the gate insulating film 506, the gate electrodes 520, 521, 531, 532, the gate wiring 524,
525, the first on the surfaces of the gate bus lines 526 and 527.
Are formed. The first interlayer insulating film 550 is made of silicon nitride oxide and has a thickness of 50 nm. The first interlayer insulating film 538 is a silicon oxide film and has a thickness of 950 nm. Also,
It may be configured to prevent the characteristic degradation due to heat of the semiconductor device using a silicon nitride oxide containing a boron element (SiN _X B _Y O _Z) as the first interlayer insulating film 550.

The first interlayer insulating film 550 made of silicon nitride oxide formed here was necessary for performing the next heat treatment step. These are the gate electrodes 520, 5
21, 531, 532, the gate wirings 524, 525, and the gate bus lines 526, 527 are effective for preventing the surface from being oxidized.

The heat treatment step had to be performed in order to activate the n-type or p-type imparting impurity element added at each concentration. This step may be performed by a thermal annealing method using an electric heating furnace, a laser annealing method using the above-described excimer laser, or a rapid thermal annealing method (RTA method) using a halogen lamp. However, although the laser annealing method can be activated at a low substrate heating temperature, it has been difficult to activate a region under the gate electrode. Therefore, the activation step was performed here by the thermal annealing method. The heat treatment is performed in a nitrogen atmosphere at 300 to 700 ° C., preferably at 350
The treatment was performed at ℃ 550 ° C., here 450 ° C., for 2 hours.

After the first interlayer insulating films 538 and 550 are formed using a seventh photomask, a predetermined resist mask is formed, and the respective TFTs are etched by etching.
A contact hole reaching the source region and the drain region was formed. Then, source electrodes 539 and 540 and a drain electrode 541 were formed. Although not shown, in this embodiment, this electrode was used as an electrode having a three-layer structure in which a 100 nm thick Ti film, a 300 nm thick Al film containing Ti, and a 150 nm thick Ti film were continuously formed by sputtering.

Through the above steps, a channel formation region 545, first impurity regions 548 and 549, and second impurity regions 546 and 547 were formed in the n-channel TFT of the CMOS circuit. Here, the second impurity region includes regions (GOLD region) 536a and 547a overlapping with the gate electrode,
A region (LDD region) 546b not overlapping with the gate electrode,
547b were each formed. Then, the first impurity region 548 serves as a source region,
9 became the drain region.

On the other hand, in the p-channel TFT, a channel formation region 542 and third impurity regions 543 and 544 were formed. Then, the third impurity region 543 became a source region, and the third impurity region 544 became a drain region. (FIG. 10B)

FIG. 10C is a top view of the inverter circuit, which shows a cross-sectional structure taken along line AA ′ of the TFT portion, a cross-sectional structure taken along line BB ′ of the gate wiring portion, and a cross-sectional view taken along line CC ′ of the gate bus line portion. The structure corresponds to FIG.
In the present invention, a gate electrode and a gate wiring are formed of a first conductive layer and a second conductive layer, and a gate bus line is formed of a first conductive layer, a second conductive layer, and a third conductive layer. It has a clad structure formed from.

FIGS. 9 and 10 show a CMO comprising a complementary combination of an n-channel TFT and a p-channel TFT.
Although the S circuit has been described as an example, the present invention can also be applied to an NMOS circuit using an n-channel TFT or a pixel matrix circuit of a liquid crystal display device.

[Embodiment 5] In this embodiment, an example will be described in which the crystalline semiconductor films used as the semiconductor layers 504 and 505 in Embodiment 4 are formed by a thermal crystallization method using a catalytic element. When a catalyst element is used, see JP-A-7-13065.
It is desirable to use the technology disclosed in Japanese Patent Application Laid-Open No. 2-78329 and Japanese Patent Application Laid-Open No. 8-78329.

FIG. 11 shows an example in which the technique disclosed in Japanese Patent Application Laid-Open No. Hei 7-130652 is applied to the present invention. First, a base film 602 was provided over a substrate 601, and an amorphous silicon film (also referred to as amorphous silicon) 603 was formed thereon. In this embodiment, a silicon oxide film is used as an upper layer of the base film 602, and silicon nitride oxide containing a boron element (SiN _X B _Y O _Z ) is used as a lower layer to prevent deterioration of characteristics of the semiconductor device due to heat. In addition,
If film peeling does not occur, silicon nitride oxide (SiN _X B
_Y O _Z) in contact with the amorphous silicon film may be formed.
Further, a nickel acetate solution containing 10 ppm by weight of nickel was applied to form a nickel-containing layer 604. (FIG. 11A)

Next, after the dehydrogenation step at 500 ° C. for 1 hour, the temperature is set at 500 to 650 ° C. for 4 to 24 hours (in this embodiment, 5 to 24 hours)
Heat treatment (50 ° C., 14 hours) was performed to form a crystalline silicon film 605. The crystalline silicon film (also referred to as polysilicon) 605 thus obtained had extremely excellent crystallinity. (FIG. 11B)

Further, the technique disclosed in Japanese Patent Application Laid-Open No. 8-78329 allows selective crystallization of an amorphous semiconductor film by selectively adding a catalytic element. FIG. 12 illustrates a case where the same technology is applied to the present invention.

First, a base film 702 is formed on a glass substrate 701.
And an amorphous silicon film 703 and a silicon oxide
The film 704 was formed continuously. As the upper layer of the base film 702
Using a silicon oxide film and containing boron element as a lower layer.
Silicon nitride oxide (SiN _XB_YO_Z) Using semi-conduct
The characteristic deterioration of the body device due to heat was prevented. In addition, film peeling
If silicon nitride oxide (SiN_XB_YO_Z)
, An amorphous silicon film may be formed.

Next, the silicon oxide film 704 was patterned to selectively form openings 705, and then a nickel acetate solution containing 10 ppm by weight of nickel was applied. As a result, a nickel-containing layer 706 was formed, and the nickel-containing layer 706 was in contact with the amorphous silicon film 702 only at the bottom of the opening 705. (FIG. 12 (A))

Next, heat treatment is performed at 500 to 650 ° C. for 4 to 24 hours (in this embodiment, 580 ° C., 14 hours).
A crystalline silicon film 707 was formed. In this crystallization process, the portion of the amorphous silicon film in contact with nickel is first crystallized, and the crystallization proceeds laterally from there. The crystalline silicon film 707 thus formed is made up of a collection of rod-shaped or needle-shaped crystals, each of which is macroscopically grown in a specific direction, and therefore has a uniform crystallinity. There are advantages.

The catalyst elements that can be used in the above two technologies are not only nickel (Ni) but also germanium (Ge), iron (Fe), palladium (Pd), tin (S
n), lead (Pb), cobalt (Co), platinum (Pt),
Elements such as copper (Cu) and gold (Au) may be used.

A semiconductor layer of a TFT can be formed by forming a crystalline semiconductor film (including a crystalline silicon film, a crystalline silicon germanium film, and the like) using the above-described techniques and performing patterning. The TFT manufactured from the crystalline semiconductor film by using the technique of this embodiment can obtain excellent characteristics, but is required to have high reliability. However, by adopting the insulating film and the TFT structure of the present invention, it is possible to manufacture a TFT that makes the most of the technology of the present embodiment.

[Embodiment 6] In this embodiment, as a method of forming the semiconductor layers 504 and 505 used in the embodiment 4, the catalyst element is used as an initial film using an amorphous semiconductor film as in the embodiment 5. An example in which a step of removing the catalytic element from the crystalline semiconductor film after forming the crystalline semiconductor film by the method will be described. In this embodiment, the method is described in
The technique described in JP-A-135468 or JP-A-10-135469 was used.

The technique described in the publication is a technique for removing the catalytic element used for crystallization of the amorphous semiconductor film by using the gettering action of phosphorus after crystallization. By using this technique, the concentration of the catalytic element in the crystalline semiconductor film can be reduced to 1 × 1
0 ¹⁷ atoms / cm ³ or less, preferably 1 × 10 ¹⁶ atoms / cm ³
Can be reduced to

The structure of this embodiment will be described with reference to FIG. Here, an alkali-free glass substrate typified by a Corning 1737 substrate was used. In FIG. 13A, the underlying film 8 is formed using the crystallization technique described in the second embodiment.
02 shows a state where the crystalline silicon film 803 is formed. In this embodiment, using a silicon nitride oxide film as the upper layer of the base film 802, as the lower layer, to prevent characteristic degradation due to heat of the semiconductor device using a silicon nitride oxide containing a boron element _{(SiN X B Y O Z)} . Incidentally, the amorphous silicon film may be formed in contact with the silicon nitride oxide if film peeling does not occur _{(SiN X B Y O Z)} . Then, a silicon oxide film 804 for a mask is formed on the surface of the crystalline silicon film 803 to a thickness of 150 nm, an opening is provided by patterning, and a region where the crystalline silicon film is exposed is provided. Then, a step of adding phosphorus is performed, and the region 80 where phosphorus is added to the crystalline silicon film is formed.
5 were provided.

In this state, 550 to 80
When heat treatment is performed at 0 ° C. for 5 to 24 hours (600 ° C. for 12 hours in this embodiment), the region 805 in which phosphorus is added to the crystalline silicon film functions as a gettering site and remains in the crystalline silicon film 803. The catalyst element was able to move to the region 805 to which phosphorus was added.

Then, a silicon oxide film 804 for a mask is used.
And the region 805 to which phosphorus is added by etching to remove the crystalline silicon film in which the concentration of the catalytic element used in the crystallization step is reduced to 1 × 10 ¹⁷ atoms / cm ³ or less. I got it. This crystalline silicon film could be used as it is as the semiconductor layer of the TFT of the present invention shown in Example 4.

[Embodiment 7] In this embodiment, another embodiment in which the semiconductor layers 504 and 505 and the gate insulating film 506 are formed in the step of manufacturing the TFT of the present invention shown in Embodiment 4 will be described.

Here, at least 700 to 1100 ° C.
A substrate having a high degree of heat resistance is required.
0 was used. The silicon oxide film used as the upper layer of the base film 901, as the lower layer, to prevent characteristic degradation due to heat of the semiconductor device using a silicon nitride oxide containing a boron element _{(SiN X B Y O Z)} . Incidentally, the amorphous silicon film may be formed in contact with the silicon nitride oxide if film peeling does not occur _{(SiN X B Y O Z)} . Then, a crystalline semiconductor film is formed using the technique described in the fifth embodiment.
In order to form a T active layer, semiconductor layers 902 and 903 were formed by patterning in an island shape. Then, the semiconductor layer 90
2, 903, a gate insulating film 904 was formed with a film containing silicon oxide as a main component. In this embodiment, a silicon nitride oxide film is formed with a thickness of 70 nm by a plasma CVD method. (FIG. 14A)

Then, heat treatment was performed in an atmosphere containing halogen (typically chlorine) and oxygen. In this embodiment, 9
50 ° C., 30 minutes. The processing temperature is 700 to 110.
The temperature may be selected within the range of 0 ° C.
I wish I had to choose between the hours. (FIG. 14 (B))

As a result, under the conditions of this embodiment, a thermal oxide film was formed at the interface between the semiconductor layers 902 and 903 and the gate insulating film 904, and a gate insulating film 907 was formed.

The gate insulating film 90 manufactured by the above steps
In No. 7, the withstand voltage was high and the interface between the semiconductor layers 905 and 906 and the gate insulating film 907 was very good. In the subsequent steps, a TFT can be manufactured according to the fourth embodiment.

Of course, the combination of the fifth embodiment and the sixth embodiment with this embodiment may be determined by the practitioner as appropriate.

[Embodiment 8] In this embodiment, an example will be described in which a crystalline silicon film is formed by a process different from that of the embodiment 4. Specifically, a gettering step different from the phosphorus gettering step described in the fifth embodiment will be described. In addition,
Since the basic steps follow those shown in FIG. 9 or FIG. 10, only the differences will be described.

First, FIG.
The state of (A) was obtained. However, the thermal crystallization technique described in the fifth embodiment is used to form the crystalline silicon film 1005 which becomes the active layer of the TFT.

Next, the substrate 1001 is immersed in a liquid phase heated at 300 ° C. (in this embodiment, in a sulfuric acid solution) to remove or reduce nickel used for crystallization. In this embodiment, gettering is performed before patterning the active layer.
It may be performed after patterning the active layer. Further, as another means for contacting with sulfuric acid, a method of uniformly dropping a heated sulfuric acid solution on a substrate may be used.

In this step, nickel is dissolved and dissolved in the heated sulfuric acid, and is easily removed from the vicinity of the surface. Then, the nickel inside diffuses into the vicinity of the low concentration surface, and more nickel is melted. By repeating this phenomenon, nickel used for crystallization is removed or reduced from the crystalline silicon film. In this manner, by performing the treatment for reducing the catalytic element by the liquid phase, the concentration of the catalytic element in the crystalline silicon film 1106 is 1 × 10 ¹⁷ atoms / cm ³ or less, preferably 1 × 10 ¹⁶ atoms / cm ³ Can be reduced to (FIG. 15 (B))

In order to increase the contact between the sulfuric acid solution and the crystalline semiconductor film, it is desirable to remove and clean the natural oxide film and the like on the surface of the crystalline semiconductor film in advance using an etchant containing hydrofluoric acid. . By doing so, gettering efficiency can be increased.

In this embodiment, nickel is described as an example, but gettering is also performed by the same phenomenon with other catalyst elements described above.

By using the crystalline silicon film 1006 obtained through the above steps and using the process described in the fifth embodiment, the TFT shown in FIG. 10 can be obtained.

The structure of this embodiment can be freely combined with any of the structures of Embodiments 4 to 7.

[0153] In Example 9 Example 1, the boron element contained 0.1～50Atoms% in the film, a high dielectric film having thermal conductivity (SiN _X B _Y O _Z) a bottom gate type T
An example in which the FT is used as a single layer of a gate insulating film has been described.
In this embodiment, an example of applying the insulating film to use silicon nitride oxide containing a boron element a (SiN _X B _Y O _Z) in staggered TFT of the present invention shown in FIG. 16.

FIG. 16 shows a typical forward stagger type TFT. First, a source layer and a drain layer are formed over a substrate provided with a base film 1100. Next, an amorphous silicon film which covers the source layer and the drain layer is formed and crystallized with a laser beam, so that the semiconductor layer 1101 is formed. Thereafter, an insulating film was formed, a gate electrode and a wiring electrode were formed, and a staggered TFT was formed. In this embodiment,
Applying the silicon nitride oxide containing a boron element (SiN _X B _Y O _Z) on the base film 1100 or the insulating film 1102.

As described above, the present invention can be applied regardless of the TFT structure.

Embodiment 10 In this embodiment, FIG. 17 shows an example of a liquid crystal display device manufactured according to the present invention.
A well-known means may be used for a method of manufacturing a pixel TFT (pixel switching element) and a cell assembling step, and a detailed description thereof will be omitted.

FIG. 17 is a schematic view of the active matrix type liquid crystal panel of this embodiment. As shown in FIG. 17, an active matrix substrate and a counter substrate face each other, and a liquid crystal is sandwiched between these substrates. The active matrix substrate includes a pixel matrix circuit 1201, a scan line driver circuit 1202, and a signal line driver circuit 1203 formed over a glass substrate 1200.

The scanning line driving circuit 1202 and the signal line driving circuit 1203 are connected to the pixel matrix circuit 1201 by the scanning line 1230 and the signal line 1240, respectively.
These drive circuits 1202 and 1203 are mainly constituted by CMOS circuits.

A scanning line 1230 is formed for each row of the pixel matrix circuit 1201, and a signal line 1240 is formed for each column. A pixel TFT 1210 is formed near the intersection of the scanning line 1230 and the signal line 1240. The gate electrode of the pixel TFT 1210 is connected to the scanning line 1230, and the source is connected to the signal line 1240. Furthermore, the drain has a pixel electrode 1260 and a storage capacitor 1270.
Is connected.

The opposing substrate 1280 has an IT
A transparent conductive film such as an O film is formed. The transparent conductive film is a counter electrode for the pixel electrode 1260 of the pixel matrix circuit 1201, and the liquid crystal material is driven by an electric field formed between the pixel electrode and the counter electrode. If necessary, an alignment film, a black matrix, and a color filter are formed on the counter substrate 1280.

IC chips 1232 and 1233 are mounted on the glass substrate on the active matrix substrate side by using the surface on which the FPC 1231 is mounted. These IC chips 1232 and 1233 are configured by forming circuits such as a video signal processing circuit, a timing pulse generating circuit, a gamma correction circuit, a memory circuit, and an arithmetic circuit on a silicon substrate.

Further, in this embodiment, a liquid crystal display device is described as an example, but an active matrix type display device may be applied to an EL (electroluminescence) display device or an EC (electrochromics) display device. It goes without saying that the invention can be applied.

The liquid crystal display device which can be manufactured by using the present invention is not limited to a transmission type or a reflection type. It is up to the implementer to choose either. As described above, the present invention can be applied to any active matrix type electro-optical device (semiconductor device).

In manufacturing the semiconductor device shown in this embodiment, any one of the first to ninth embodiments may be employed, or each embodiment may be freely combined and used. .

[Embodiment 11] The present invention can be applied to all conventional IC technologies. That is, the present invention can be applied to all semiconductor circuits currently on the market. For example,
AS integrated RISC processor on one chip
The present invention may be applied to a microprocessor such as an IC processor, a signal processing circuit represented by a liquid crystal driver circuit (D / A converter, a gamma correction circuit, a signal dividing circuit, and the like), and a portable device (mobile phone, PHS, mobile). Computer)
May be applied to a high-frequency circuit for use.

Furthermore, it is also possible to realize a semiconductor device having a three-dimensional structure in which an interlayer insulating film is formed on a conventional MOSFET and a semiconductor circuit is formed thereon using the present invention. As described above, the present invention can be applied to all semiconductor devices using LSIs at present. That is, a SOI structure (such as SIMOX, Smart-Cut (registered trademark of SOITEC), and ELTRAN (registered trademark of Canon Inc.)) (T
The present invention may be applied to an FT structure.

A semiconductor circuit such as a microprocessor is mounted on various electronic devices and functions as a central circuit. Representative electronic devices include personal computers, portable information terminal devices, and all other home appliances. Further, a computer for controlling a vehicle (an automobile, a train, or the like) is also included. The present invention is also applicable to such a semiconductor device.

In manufacturing the semiconductor device shown in this embodiment, any of the structures of the first to ninth embodiments may be adopted, and the embodiments can be freely combined and used. .

[Embodiment 12] In Embodiment 1, an example in which a crystalline silicon film is used as an active layer of a TFT has been described. In this embodiment, an example in which an amorphous silicon film is used as an active layer is shown. .

The boron-containing insulating film of the present invention is suitable for an amorphous silicon TFT using an amorphous silicon film as an active layer, rather than a polysilicon TFT using a crystalline silicon film as an active layer.

According to Example 1, a gate electrode was formed on a substrate.

Next, a gate insulating film covering the gate electrode is formed.
And an amorphous silicon film are continuously formed. Amorphous silicon
In the case of a con-TFT, the gate insulation is performed in the same manner as in the first embodiment.
The film may be multi-layered,
Even if boron is mixed in the active layer, it is not activated and affects the conductivity type
Therefore, in this embodiment, silicon nitride oxide
A silicon film and an amorphous silicon film are continuously formed in the same chamber.
Was. Oxygen-containing oxynitride with boron added
The internal stress of the silicon film is typically -5 × 10^Tendyn /
cm^Two~ 5 × 10^Tendyn / cm^Two, Preferably -10
^Tendyn / cm ^Two-10^Tendyn / cm^TwoBecomes amorphous
This is a preferable stress range in the adhesiveness with the porous silicon film.

Next, an insulating film (which will later become a channel protective film) for protecting the channel formation region was formed on the amorphous semiconductor film in the same manner as in Example 1. Note that this insulating film may also be formed continuously with the amorphous silicon film.

In the subsequent steps, a bottom gate type TFT was completed according to the first embodiment.

In this embodiment, an example is shown in which a silicon nitride oxide film containing boron is used as one layer of a gate insulating film of a bottom gate type TFT.
For example, it can be used for a base film, an interlayer insulating film, a mask insulating film, a channel protective film, a protective film, and the like.

For example, when a silicon nitride oxide film containing boron is used as a gate insulating film, a silicon nitride oxide film containing boron is used as a channel protective film, and a channel formation region is sandwiched between silicon nitride films containing boron. The heat radiation effect can be obtained effectively. Alternatively, a silicon nitride film containing boron may be used as a gate insulating film, and a silicon nitride oxide film containing boron may be used as a channel protective film. Alternatively, a silicon nitride film may be used as a gate insulating film and a silicon nitride oxide film containing boron may be used as a channel protective film.

In manufacturing the semiconductor device shown in this embodiment, any of the structures of Embodiments 1 to 3 may be employed, or the semiconductor device may be used in any combination with Embodiments 10 and 11. It is possible.

[Embodiment 13] In this embodiment, an example in which an EL (electroluminescence) display device is manufactured by using the present invention will be described.

FIG. 21A is a top view of an EL display device using the present invention. In FIG. 21A, 10 is a substrate, 11 is a pixel portion, 12 is a source side drive circuit, 13 is a gate side drive circuit, and each drive circuit is a wiring 14.
〜16 to the FPC 17 and connected to an external device.

At this time, a sealing material (also referred to as a housing material) 18 is provided so as to surround at least the pixel portion, preferably the driving circuit and the pixel portion. Note that the sealing material 18 may be a metal plate or a glass plate having a concave portion surrounding the element portion, or may be an ultraviolet curable resin.
When a metal plate having a concave portion surrounding the element portion is used as the sealing material 18, the sealing member 18 is fixed to the substrate 10 with an adhesive 19 to form a sealed space with the substrate 10. At this time, the EL element is completely sealed in the closed space, and is completely shut off from the outside air.

Further, it is desirable to fill the gap 20 between the sealing material 18 and the substrate 10 with an inert gas (argon, helium, nitrogen, etc.) or to provide a desiccant such as barium oxide. . This makes it possible to suppress the deterioration of the EL element due to moisture or the like.

FIG. 21B shows a cross-sectional structure of the EL display device of this embodiment, in which a TFT for a driving circuit (here, an n-channel TFT and a p-channel TFT) is formed on the substrate 10 and the base film 21. A CMOS circuit combining TFTs is shown) 22 and a TFT 23 for a pixel portion (however, only a TFT for controlling current to an EL element is shown here).

The present invention can be used when forming the insulating layers of the driving circuit TFT 22 and the pixel portion TFT 23. In addition, a known technique may be used for processes other than the formation of the insulating layer. The NTFT and PTFT shown in FIG. 7 may be used as the driving TFT 22. Further, the NTF shown in FIG.
T or PTFT may be used.

A TFT 22 for a driving circuit and a TFT for a pixel portion are formed by using the present invention to form an insulating layer and use it as a gate insulating film.
When the FT 23 is completed, a pixel electrode 27 made of a transparent conductive film electrically connected to the drain of the pixel portion TFT 23 is formed on an interlayer insulating film (flattening film) 26 made of a resin material. As the transparent conductive film, a compound of indium oxide and tin oxide (called ITO) or a compound of indium oxide and zinc oxide can be used. After the pixel electrode 27 is formed, an insulating film 28 is formed, and an opening is formed on the pixel electrode 27.

Next, the EL layer 29 is formed. EL layer 29
Are known EL materials (a hole injection layer, a hole transport layer, a light emitting layer,
An electron transport layer or an electron injection layer) may be freely combined to form a stacked structure or a single-layer structure. A known technique may be used to determine the structure. EL materials include low molecular weight materials and high molecular weight (polymer) materials.
When a low molecular material is used, an evaporation method is used. When a high molecular material is used, a simple method such as a spin coating method, a printing method, or an ink jet method can be used.

[0186] In this embodiment, an EL layer is formed by an evaporation method using a shadow mask. By forming a light-emitting layer (a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer) capable of emitting light having different wavelengths for each pixel using a shadow mask, color display becomes possible. In addition, the color conversion layer (CC
M) and a color filter are combined, and a white light-emitting layer and a color filter are combined. Either method may be used. Needless to say, a monochromatic EL display device can be used.

After forming the EL layer 29, the cathode 3
0 is formed. It is desirable to remove moisture and oxygen existing at the interface between the cathode 30 and the EL layer 29 as much as possible. Therefore, the EL layer 29 and the cathode 30 are continuously formed in a vacuum,
It is necessary to devise that the EL layer 29 is formed in an inert atmosphere and the cathode 30 is formed without opening to the atmosphere. In this embodiment, a multi-chamber method (cluster tool method)
By using the film forming apparatus described above, the film forming as described above can be performed.

In this embodiment, the cathode 30 is made of Li
A laminated structure of an F (lithium fluoride) film and an Al (aluminum) film is used. Specifically, one layer is formed on the EL layer 29 by vapor deposition.
A LiF (lithium fluoride) film having a thickness of 300 nm is formed, and an aluminum film having a thickness of 300 nm is formed thereon. Of course, a MgAg electrode which is a known cathode material may be used. The cathode 30 is connected to the wiring 16 in a region indicated by 31. The wiring 16 is a power supply line for applying a predetermined voltage to the cathode 30, and is connected to the FPC 17 via a conductive paste material 32.

In order to electrically connect the cathode 30 and the wiring 16 in the region indicated by 31, it is necessary to form contact holes in the interlayer insulating film 26 and the insulating film 28. These may be formed at the time of etching the interlayer insulating film 26 (at the time of forming a contact hole for a pixel electrode) or at the time of etching the insulating film 28 (at the time of forming an opening before forming an EL layer). Further, when etching the insulating film 28, the etching may be performed all at once up to the interlayer insulating film 26. In this case, if the interlayer insulating film 26 and the insulating film 28 are the same resin material, the shape of the contact hole can be made good.

The wiring 16 has a gap between the sealing material 18 and the substrate 10 (however, the wiring 16 is closed with the adhesive 19).
And is electrically connected to the FPC 17. Although the wiring 16 has been described here, the other wirings 14, 15
In the same manner, pass under the sealing material 18 and pass through the FPC 17
Is electrically connected to

The present invention can be used in the EL display device having the above-described structure. By using the present invention, the electrical characteristics of the TFT can be improved. Therefore, the displayed image quality can be improved.

[Embodiment 14] A CMOS circuit and a pixel portion formed by carrying out the present invention are used for various electro-optical devices (active matrix liquid crystal display, active matrix EL display, active matrix EC display). Can be. That is, the invention of the present application can be applied to all electronic devices in which these electro-optical devices are incorporated in a display unit.

Examples of such electronic devices include a video camera, a digital camera, a projector (rear or front type), a head mounted display (goggle type display), a car navigation, a car stereo,
Examples include a personal computer and a portable information terminal (a mobile computer, a mobile phone, an electronic book, or the like). Examples of these are shown in FIGS. 18, 19 and 20.

FIG. 18A shows a personal computer, which includes a main body 2001, an image input section 2002, and a display section 20.
03, a keyboard 2004 and the like. The present invention can be applied to the image input unit 2002, the display unit 2003, and other signal control circuits.

FIG. 18B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 210.
6 and so on. The present invention can be applied to the display portion 2102 and other signal control circuits.

FIG. 18C shows a mobile computer (mobile computer), which includes a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, a display section 2205, and the like. The present invention can be applied to the display portion 2205 and other signal control circuits.

FIG. 18D shows a goggle type display, which includes a main body 2301, a display portion 2302, and an arm portion 230.
3 and so on. The present invention can be applied to the display portion 2302 and other signal control circuits.

FIG. 18E shows a player that uses a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display section 2402, and a speaker section 240.
3, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (D
digital Versatile Disc), CD
And the like, it is possible to perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 2402 and other signal control circuits.

FIG. 18F shows a digital camera, which includes a main body 2501, a display section 2502, an eyepiece section 2503, operation switches 2504, an image receiving section (not shown), and the like. The present invention can be applied to the display portion 2502 and other signal control circuits.

FIG. 19A shows a front type projector, which includes a projection device 2601, a screen 2602, and the like. The present invention can be applied to the liquid crystal display device 2808 forming a part of the projection device 2601 and other signal control circuits.

FIG. 19B shows a rear type projector, which includes a main body 2701, a projection device 2702, and a mirror 270.
3, including a screen 2704 and the like. The present invention relates to a projection device 2
The present invention can be applied to the liquid crystal display device 2808 forming a part of the signal control circuit 702 and other signal control circuits.

FIG. 19C is a diagram showing an example of the structure of the projection devices 2601 and 2702 in FIGS. 19A and 19B. Projection devices 2601, 27
02 denotes a light source optical system 2801, mirrors 2802, 280
4 to 2806, dichroic mirror 2803, prism 2807, liquid crystal display device 2808, retardation plate 280
9. The projection optical system 2810. Projection optical system 28
Reference numeral 10 denotes an optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in an optical path indicated by an arrow in FIG. Good.

FIG. 19D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. 19C. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, a lens array 2813,
814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system shown in FIG. 19D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

However, in the projector shown in FIG. 19, a case where a transmissive electro-optical device is used is shown, and examples of application to a reflective electro-optical device and an EL display device are not shown.

FIG. 20A shows a mobile phone,
01, audio output unit 2902, audio input unit 2903, display unit 2904, operation switch 2905, antenna 2906
And so on. The present invention can be applied to the audio output unit 2902, the audio input unit 2903, the display unit 2904, and other signal control circuits.

FIG. 20B shows a portable book (electronic book), which includes a main body 3001, a display portion 3002, a 3003 storage medium 3004, operation switches 3005, an antenna 3006, and the like. The present invention can be applied to the display units 3002 and 3003 and other signal circuits.

FIG. 20C shows a display, which includes a main body 3101, a support 3102, a display portion 3103, and the like.
The present invention can be applied to the display portion 3103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for a display having a diagonal of 10 inches or more (particularly 30 inches or more).

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in various fields.

In manufacturing the semiconductor device shown in this embodiment, any of the structures of Embodiments 1 to 9 may be employed, or the embodiments may be freely combined and used. . Further, the electro-optical devices and the semiconductor circuits described in the tenth and eleventh embodiments may be used in such a combination.

[0210]

As it is evident from the foregoing description, a film of silicon nitride of the present invention as a main component (SiN _X B _Y O _Z) is a boron element 0.
Since it contains 1 to 50 atoms% or 1 to 50 atoms%, and preferably 0.1 to 10 atoms%, it has high thermal conductivity and has an effect of preventing deterioration of characteristics of the semiconductor device due to heat. Further, since the film of the present invention containing silicon nitride as a main component has a blocking effect on mobile ions such as sodium, it is possible to prevent these ions from entering a semiconductor device, particularly a channel formation region, from a substrate or the like. It also has an effect. In addition, films of silicon nitride of the present invention as a main component (SiN _X B _Y O _Z) is oxygen 1-3
Since it contains 0 atoms%, the internal stress is typically-
5 × 10 ¹⁰ dyn / cm ^{2 to} 5 × 10 ¹⁰ dyn / c
m ² , preferably −10 ¹⁰ dyn / cm ² to 10 ¹⁰ dy
n / cm ² , which is higher in adhesion than a conventional silicon nitride film (SiN) (a crystalline semiconductor film and SiN _X B _Y O).
Adhesion with _Z film or amorphous semiconductor film with SiN _{X BY}
O _Z film has adhesion) between, film peeling is unlikely to occur.

[0211] By using the present invention, the reliability of a semiconductor device including a CMOS circuit made of a TFT, specifically, a pixel matrix circuit of a liquid crystal display device and a drive circuit provided therearound can be improved. Was completed. As a result, the reliability of a semiconductor circuit including a TFT in a circuit and an electronic device in which the liquid crystal display device is incorporated as a component have been improved.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a manufacturing process of a TFT of Example 1.

FIG. 2 is an explanatory diagram of a manufacturing process of the TFT of Example 1.

FIG. 3 is an explanatory diagram of a manufacturing process of the TFT of Example 1.

FIG. 4 is an explanatory diagram of a manufacturing process of a TFT of Example 2.

FIG. 5 is an explanatory diagram of a manufacturing process of a TFT of Example 2.

FIG. 6 is an explanatory diagram of a manufacturing process of the TFT of Example 2.

FIG. 7 is an explanatory diagram of a top view and a cross-sectional view of a CMOS circuit according to a third embodiment.

FIG. 8 is an explanatory diagram of a top view and a cross-sectional view of a pixel matrix circuit according to a third embodiment.

FIG. 9 is an explanatory diagram of a manufacturing process of a TFT of Example 4.

FIGS. 10A and 10B are an explanatory diagram and a top view of a manufacturing process of a TFT of Example 4. FIGS.

FIG. 11 is an explanatory view of a crystallization step of Example 5, which is a cross-sectional view of the substrate.

FIG. 12 is an explanatory view of a crystallization step of Example 5, which is a cross-sectional view of the substrate.

FIG. 13 is an explanatory diagram of a gettering step in Example 6, which is a cross-sectional view of the substrate.

FIG. 14 is an explanatory diagram of a gettering step in Example 7, which is a cross-sectional view of the substrate.

FIG. 15 is an explanatory diagram of a gettering step in Example 8, which is a cross-sectional view of the substrate.

FIG. 16 is an explanatory view of Example 9 and is a cross-sectional view of the substrate.

FIG. 17 is a diagram illustrating a configuration of an active matrix substrate.

FIG. 18 is an explanatory diagram of an electronic device.

FIG. 19 is an explanatory diagram of an electronic device.

FIG. 20 is an explanatory diagram of an electronic device.

FIG. 21 is an explanatory diagram of an EL display device.

FIG. 22 is a diagram showing a structure of a bottom gate type TFT using amorphous silicon.

Claims (16)

[Claims] A gate electrode formed on an insulating surface; a gate insulating film on the gate electrode; and a source region, a drain region, and a source region and a drain region in contact with the gate insulating film. A semiconductor device having a channel formation region formed therebetween, wherein the gate insulating film further includes a silicon nitride oxide film containing a boron element. 2. A source region, a drain region, a channel forming region formed between the source region and the drain region in contact with an insulating surface, a gate insulating film on the channel forming region, A semiconductor device having a gate electrode in contact with an insulating film, wherein the gate insulating film further includes a silicon nitride oxide film containing a boron element. 3. A semiconductor device comprising an insulating film formed on an insulating surface and a semiconductor element formed on the insulating film, wherein the insulating film is a silicon nitride oxide film containing a boron element. Characteristic semiconductor device. 4. A semiconductor device formed on an insulating surface,
A semiconductor device including an insulating film for protecting a semiconductor element, wherein the insulating film is a silicon nitride oxide film containing a boron element. 5. The method according to claim 1, wherein:
A semiconductor device, wherein a composition ratio of a boron element in the silicon oxynitride film is 0.1 to 50 atoms%. 6. The method according to claim 1, wherein
The composition ratio of oxygen in the silicon nitride oxide film is 1 to 30.
A semiconductor device characterized in that the content is atoms%. 7. The method according to claim 1, wherein
The semiconductor device is an electro-optical device or an electronic device. 8. The semiconductor device according to claim 7, wherein the electro-optical device is a liquid crystal display, an EL display, an EC display, or an image sensor. 9. The electronic device according to claim 7, wherein:
A semiconductor device, which is a video camera, a digital camera, a projector, a goggle display, a car navigation, a personal computer, or a personal digital assistant. 10. A method for manufacturing a semiconductor device, comprising a step of forming a silicon nitride oxide film by performing sputtering using a semiconductor target to which a boron element is added in an atmosphere containing a nitrogen oxide gas. 11. The method according to claim 10, wherein the nitrogen oxide gas is one or more of nitrogen monoxide gas, nitrous oxide gas, nitrogen dioxide gas, and nitrogen trioxide gas, or these gases. A method for manufacturing a semiconductor device, which is a gas diluted with an inert gas or an oxygen gas. 12. A semiconductor, which includes a step of forming a silicon nitride oxide film containing a boron element by performing sputtering using a semiconductor target in an atmosphere containing a gas containing a boron element and a nitrogen oxide gas. Method for manufacturing the device. 13. The method according to claim 12, wherein the nitrogen oxide gas is one or more of nitrogen monoxide gas, nitrous oxide gas, nitrogen dioxide gas, and nitrogen trioxide gas, or a mixture thereof. A method for manufacturing a semiconductor device, which is a gas diluted with an inert gas or an oxygen gas. 14. The method for manufacturing a semiconductor device according to claim 12, wherein sputtering is performed by changing the content ratio of the boron element in the atmosphere continuously or stepwise. 15. A step of forming a gate electrode on an insulating surface, a step of forming a gate insulating film made of a silicon nitride oxide film containing a boron element on the gate electrode, and forming a semiconductor thin film on the gate insulating film. Forming a semiconductor device. 16. A step of forming a semiconductor thin film on an insulating surface, a step of forming a gate insulating film made of a silicon nitride oxide film containing a boron element on the semiconductor thin film, and forming a gate electrode on the gate insulating film. Forming a semiconductor device.