JP2003188098A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the additive concentration of catalytic metal element at the time of growing a CG silicon film laterally. <P>SOLUTION: An a-Si film 12 is formed on a quartz substrate 11, a plurality of holes 14 are made by making thin the a-Si film 12, each hole 14 is added with a catalytic element of Ni for accelerating crystallization, the a-Si film 12 is grown epitaxially by performing first heat treatment, a CG silicon film 15 is formed, a hole 14a located between adjacent holes 14 is added with a gettering element of P (phosphorus) exhibiting an effect for attracting Ni of the catalytic element selectively, Ni of the catalytic element in the CG silicon film 15b is moved to a region added with P (phosphorus) of the gettering element by performing second heat treatment, and the active region of a semiconductor device is formed using a region of the CG silicon film 15 other than the region added with P (phosphorus) of the gettering element. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a thin film transistor for driving liquid crystal in an active matrix liquid crystal display device and a method for manufacturing the same.

[0002]

2. Description of the Related Art In a thin liquid crystal display device driven with low power consumption, a thin film transistor (T
A liquid crystal display device using a (Hin Film Transistor: hereinafter referred to as a TFT) has high performance such as good image contrast and fast image signal response speed. It is used in the display section of portable TVs, etc., and its market size is growing significantly.

In such a TFT, a CG (Continuous Grain) is formed in an electrically active area of the TFT.
A silicon film may be used in some cases. The CG silicon film is an amorphous Si film (amorphous silicon film: a in the following a) as disclosed in JP-A-6-244105.
-Si film) is a silicon film with excellent crystallinity obtained by depositing a small amount of a metal element such as Ni on the surface of (Si film) and then performing a high temperature treatment such as an annealing treatment.

The CG silicon film has a higher carrier mobility than the conventional a-Si film and polycrystalline silicon film (polysilicon film: hereinafter referred to as p-Si film).
Therefore, the CG silicon film is capable of driving with low power consumption and high-speed response of signals. In addition, since the CG silicon film has a high carrier mobility, it has a possibility of manufacturing a sheet computer using it in the future, and is a material for manufacturing a next-generation driver monolithic liquid crystal display device. Is seen as promising.

There are mainly the following two types of methods for producing a CG silicon film.

The first method is a method in which a catalyst metal such as Ni is added to the entire surface of an a-Si film formed on a predetermined substrate, and the CG silicon film is grown using the catalyst metal as crystal nuclei. is there. Hereinafter, this first method will be referred to as vertical growth.

The second method is to add a catalytic metal such as Ni to a partial region of an a-Si film formed on a predetermined substrate and subject it to a high temperature treatment such as an annealing treatment to obtain N.
This is a method in which a CG silicon film generated in a region to which a catalyst metal such as i is added is subjected to crystal growth in a region to which a catalyst metal such as Ni is not added with the passage of time. Less than,
This second method is designated as lateral growth.

2A to 2D are schematic plan views showing a state in which a CG silicon film is vertically grown.

First, as shown in FIG. 2A, a catalytic metal element such as Ni is added to the entire surface of the a-Si film 51 formed on the quartz substrate. Then, a temperature of about 600 ° C. is applied to the a-Si film 51 to which a catalytic metal element such as Ni is added.
Heat treatment is performed for about an hour to promote solid phase growth.

At the initial stage of solid phase growth, as shown in FIG. 2B, a plurality of CG silicon crystals 52 serving as crystal nuclei at the center of the domain are formed in arbitrary regions of the a-Si film 51 on the quartz substrate.
Is formed. The generation density of crystal nuclei of the formed CG silicon crystal 52 depends on the film quality of the a-Si film 51 and the amount of N added.
It is affected by the concentration of metal elements such as i.

After that, when the heat treatment is continued and solid phase growth proceeds, as shown in FIG. 2C, the CG silicon crystal 52 is centered on the crystal nuclei of the minute CG silicon crystal 52 generated first. It grows radially. The region of the CG silicon crystal 52 grown around such one crystal nucleus is called a domain (hereinafter, the CG silicon crystal is referred to as a domain). Although the inside of the domain 52 is in a polycrystalline state, the plane orientations of adjacent crystals in the domain 52 are continuous (ContinuousGrai).
n). Therefore, the inside of the domain 52 is in a polycrystal state and a quasi-single crystal state.

Further, when the heat treatment is continued and solid phase growth is performed for a long time, finally, as shown in FIG. 2 (d), the grown domains 52 collide with each other to form a- on the quartz substrate. The entire surface of the Si film 51 becomes a CG silicon film and the growth is completed. Domain 5 where domains 52 collide
The interface of 2 is called the domain boundary 53.

FIGS. 3A to 3D are schematic plan views showing a state in which a CG silicon film is laterally grown.

First, as shown in FIG. 3A, a silicon oxide film 55 is formed on the entire surface of an a-Si film 54 formed on a quartz substrate, and then a silicon oxide film 55 is formed on the silicon oxide film 55. In order to expose a part of the region 54a of the Si film 54, a plurality of rectangular holes 56 are formed in a predetermined region. Then, a catalytic metal element such as Ni is added to the surface of a part of the region 54a of the a-Si film 54 exposed from the holes 56. In this case, the catalytic metal element such as Ni is not added to the a-Si film 54 covered with the silicon oxide film 55. After that, the catalytic metal element such as Ni is partially contained in the region 54a.
To the a-Si film 54 added to
Heat treatment is performed for about an hour to promote solid phase growth.

At the initial stage of solid phase growth, as shown in FIG. 3B, an a-Si film 5 to which a catalytic metal element such as Ni has been added.
A large number of minute CG silicon crystals (hereinafter referred to as domains) 57 are formed in a partial region 54 a of No. 4. The size of the domain 57 should be small.

After that, when the heat treatment is continued and the solid phase growth proceeds, as shown in FIG.
A domain 58, which is a CG silicon crystal, grows in the region of the a-Si film 54 covered with the silicon oxide film 55 with the crystal nucleus of No. 7 as a starting point.

Further, when the heat treatment is continued and solid phase growth is carried out for a long time, finally, as shown in FIG. 3 (d), the grown domains 58 collide with each other to form a- on the quartz substrate. The entire surface of the Si film 54 becomes a CG silicon film and the growth is completed. Domain 5 where domains 58 collide
The interface of 8 is called the domain boundary 59.

When the CG silicon film grows laterally, as shown in FIGS. 3A to 3D, a catalytic metal element such as Ni is added, and the side edge portion of the hole 56 where the domain 57 is grown is formed. From the region, it is important that the domain 58 grows perpendicular to the region of its lateral edges. Lateral growth CG
The characteristic of the silicon film is that the region of the domain boundary 59 can be specified in advance because the generation region of the domain 58 and the growth direction of the domain 58 are determined.

The domain boundary 59 is a region where a large amount of catalytic metal such as Ni gathers and the crystal continuity of the CG silicon film is interrupted. Therefore, the domain boundary 59
Is not suitable for the channel region, which is the active region of the TFT, in view of the crystal uniformity of the CG silicon film.

In the laterally grown CG silicon film, the position of the domain boundary 59 can be assumed in advance depending on the position of the hole 56 to which the catalytic metal such as Ni is added. Therefore, the TFT
At the time of designing, the channel region of the TFT may be arranged in a region other than the region supposed to be the domain boundary 59 on the CG silicon film.

In such a laterally grown CG silicon film, the size of the domain 57 shown in FIG. 3B must be as small as possible. When the size of the domain 57 is large, for example, the domain 57a as shown in FIG. 4 grows. When such a domain 57a grows, the growth direction of the domain 57a and the domain 57a
The positions of the boundaries between them are not constant, and the region where the domain boundary 59 shown in FIG. 3D is formed cannot be assumed. Therefore, in the laterally grown CG silicon film grown from the large size domain 57a, there is a possibility that the channel region of the TFT cannot be arranged in a region without domain boundaries in advance.

On the other hand, if the size of the domain 57 is very small, as shown in FIG. 5 in which the boundary area between the domain 57 and the domain 58 is enlarged, the domains 57 have a gap between the domains 57 in the hole 56. It is formed without it.
When the domain 58 that grows with the domain 57 as a crystal nucleus grows from the hole 56 toward the region of the a-Si film 54 covered with the silicon oxide film 55,
It grows in a direction perpendicular to the side edge region of the hole 56.

Therefore, it can be assumed that the domain boundary 59 formed by the growth of the domain 58 is formed at a position approximately in the middle of the adjacent holes 56, and the domain boundary 59 is grown from the domain 57 having a minute size. With the laterally grown CG silicon film, it becomes possible to form a TFT in a region that does not include the domain boundary 59.

As a method of forming the minute domains 57, a method of increasing the addition concentration of the catalytic metal element such as Ni is usually considered. By increasing the addition concentration of the catalytic metal element such as Ni, CG which becomes the crystal nucleus of the domain 57
The generation density of silicon crystals becomes high, and inevitably the size of each domain 57 becomes small. Normally lateral growth CG
In the case of forming a silicon film, 5 is added with respect to the addition concentration of the catalytic metal element in the case of forming a vertically grown CG silicon film.
Double the concentration of the catalytic metal element added.

However, when the catalytic metal element such as Ni added in the CG silicon film is left as it is, when a TFT is formed on the CG silicon film, the OFF current increases in the OFF state of the TFT, and the TFT is increased. Adversely affect the electrical characteristics of. Therefore, it is necessary to remove the catalytic metal element such as Ni from the inside of the CG silicon film after crystallization of the CG silicon film.

A method for removing the catalytic metal element such as Ni added in the Si crystal is disclosed in Japanese Patent Laid-Open No. 10-22353.
No. 3 publication. The method for removing catalytic metal elements such as Ni disclosed in this publication is based on the formed CG
After a portion of the silicon film is doped with P (phosphorus), which is a group V element, at a high concentration, heat treatment is performed to move a catalytic metal element such as Ni to the P (phosphorus) -doped region of the CG silicon film. By (gettering), C
Drain region, channel region of TFT of G silicon film,
A catalytic metal element such as Ni is removed from a region forming an active region such as a source region.

[0027]

However, when the concentration of the catalytic metal element added increases, the concentration of the catalytic metal element remaining in the CG silicon also increases. If the removal ability of the catalytic metal element by gettering is the same, the higher the added concentration of the catalytic metal element in the CG silicon film, the higher the concentration of the catalytic metal element remaining in the CG silicon film after gettering.

Therefore, in order to reduce the concentration of the catalytic metal element remaining in the CG silicon film, it is necessary to reduce the added concentration of the catalytic metal element to be added first. There is a possibility that a good lateral growth CG silicon film cannot be formed.

The present invention is intended to solve such a problem, and an object thereof is to reduce the addition concentration of a catalytic metal element when a laterally grown CG silicon film is grown, and
It is an object of the present invention to provide a semiconductor device capable of forming a TFT having good electric characteristics in a laterally grown CG silicon film and a method for manufacturing the semiconductor device.

[0030]

According to a method of manufacturing a semiconductor device of the present invention, an amorphous silicon film having a predetermined thickness is formed on a substrate having an insulating surface, and a plurality of regions in the amorphous silicon film are formed. Forming a plurality of first regions by reducing the thickness of the film, adding a first element that promotes crystallization to each of the first regions, and then performing a first heating. A step of performing a crystal growth on the amorphous silicon film to form a crystalline silicon film, and each of the first regions,
A second portion disposed between each of the adjacent first regions
Of the first element in the crystalline silicon film and a step of adding a second element having an effect of selectively attracting the first element to the region of And a step of forming at least an active region of the semiconductor device by using the region of the crystalline silicon film other than the region to which the second element is added. It is characterized by

The first element is Fe, Co, Ni, C.
It is one or more kinds of elements selected from u, Ru, Rh, Pd, Os, Ir, Pt, and Au.

The second element is P (phosphorus).

The semiconductor device of the present invention has a crystalline silicon film which is crystallized by adding the first element that promotes crystallization to the amorphous silicon film formed on the substrate having an insulating surface. A semiconductor device, wherein the content of the first element in the crystalline silicon film is 1.0 × 10 ¹⁵ atoms
It is characterized by being less than / cm ³ .

The first element is Ni (nickel).

[0035]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

1A to 1I are cross-sectional views for explaining each step in the method for manufacturing a semiconductor device according to the embodiment of the present invention.

First, as shown in FIG. 1A, an LPCVD (Low Pressure CV) is formed on a quartz substrate 11.
By the method D), the a-Si film 12 having a film thickness of 65 nm is formed. To form the a-Si film 12, disilane gas (Si ₂ H ₅ ) is used as a source gas, the temperature is 450 ° C., and the pressure is 5
It was performed under the condition of 0 Pa. After that, a protective film 13 made of silicon oxide is formed on the entire surface of the a-Si film 12, and a hole for adding a catalytic metal to a predetermined region on the protective film 13 is formed by general photolithography and dry etching. 14 is formed to expose a part of the a-Si film 12.

Next, as shown in FIG. 1B, the surface portion of the a-Si film 12 exposed in the region inside the hole 14 is removed by dry etching to reduce the film thickness. In this case, a exposed in the area inside the hole 14
The film thickness of the -Si film 12 is 20 nm. Then, in order to add Ni as a catalyst metal for promoting crystallization to the surface of the a-Si film 12, an aqueous solution containing 10 ppm of nickel acetate (Ni) dissolved therein is spin-coated on the quartz substrate 11. In this case, the Ni concentration on the surface of the a-Si film 12 is
It is set to be about 5 × 10 ¹² atoms / cm ² . Further, as a method of adding the catalytic metal, a sputtering method,
Any of a CVD method, a plasma treatment method, or an evaporation method may be used. The catalytic metals that promote crystallization of the a-Si film 12 include Fe, Co, Ni, Cu, Ru, Rh, and P.
One or more elements may be selected from the elements d, Os, Ir, Pt, and Au.

Next, as shown in FIG. 1C, a-Si
The quartz substrate 11 on which the film 12 is formed is subjected to heat treatment at a temperature of 570 ° C. for 18 hours in a nitrogen atmosphere to perform a-Si.
Crystallize the film 12. In the region of the hole 14, a CG silicon film 15a, which is a collection of minute domains, grows,
On the lower side of the protective film 13, the CG silicon film 15b grown from the CG silicon film 15a grows. Further, a domain boundary 16 is formed at an intermediate position between the adjacent holes 14.

Next, as shown in FIG. 1D, the protective film 1
3 is again subjected to general photolithography and etching to remove the protective film 13 on the periphery of the hole 14 and in the vicinity of the domain boundary 16, and a hole 14a is formed above the domain boundary 16. As a result, the CG silicon film 15c which is a part of the CG silicon film 15b is exposed. After that, P (phosphorus) which is a group V element is formed on the entire surface of the quartz substrate 11 by an ion implantation method.
Are implanted to form P (phosphorus) implantation regions 17 in the holes 14 and 14a. P (phosphorus) dose is 2 × 1
It is about 0 ¹⁵ atoms / cm ² . P (phosphorus) acts as a gettering element that moves Ni, which is a catalytic metal, to the P (phosphorus) implantation region 17. In this case, the protective film 13 functions as a mask for P (phosphorus) implantation,
P (phosphorus) is not implanted into the CG silicon film 15b below the protective film 13. Further, the CG silicons 15a and 15c in the hole 14 which are considered to contain the largest amount of Ni as the catalyst metal, the CG silicon 15c in the region near the domain boundary 16 in the hole 14a, etc. are P (phosphorus).
It is better to be included in the implantation region 17.

Next, as shown in FIG. 1E, the temperature of 60 is applied to the quartz substrate 11 on which the CG silicon film 15b is grown.
The heat treatment is performed under the heating conditions of 0 ° C. to 700 ° C. for 24 hours to move (getter) Ni of the catalytic metal contained in the CG silicon film 15b to the P (phosphorus) implantation region 17. By such a gettering process, the CG silicon film 15b on the lower side of the protective film 13 is changed to N of the catalytic metal.
The CG silicon film 15 contains almost no i.

Next, as shown in FIG. 1F, the protective film 1
After removing 3 by etching, the CG silicon film 15 on the quartz substrate 11 is patterned into a predetermined shape by general photolithography and etching.
At this time, the P (phosphorus) implantation region 17 is entirely removed by etching. After that, the CG silicon film 15 is heated in an O ₂ atmosphere. By heating in the O ₂ atmosphere, the first silicon oxide film is formed on the surface of the CG silicon film 15. At this time, Ni of the catalytic metal remaining in the CG silicon film 15 is taken into the first silicon oxide film. This step is called a second gettering process and has an effect of further removing the catalytic metal element (Ni) in the CG silicon film 15 which has been reduced by the gettering process described above. This second gettering process is performed with HCl, HF,
The gettering effect becomes more remarkable when the heat treatment is performed in an oxidizing atmosphere containing at least one kind of halogen element such as HBr, Cl ₂ , F ₂ , Br ₂ or the like.

In this case, the temperature range of the heat treatment is 900
C. to 1150.degree. C. is desirable, and the higher the heating temperature, the greater the gettering effect on the catalytic metal element. In addition, the CG silicon film 15 is subjected to high temperature oxidation
The defect density inside is also reduced, and the characteristics of the CG silicon film 15 are improved. After that, the first silicon oxide film is removed using buffered hydrofluoric acid, and then patterning is performed using general photolithography and dry etching to form the CG silicon film 15 in a predetermined shape. At this time, the formed CG silicon film 15 does not include the domain boundary 16.

Next, as shown in FIG. 1G, a second silicon oxide film 19 as a gate insulating film is formed on the CG silicon film 15 by the CVD method. The thickness of the second silicon oxide film 19 is 80 nm. After that, a p-Si film having a film thickness of 300 nm is further formed on the second silicon oxide film 19 by the CVD method, and the p-Si film is patterned by using general photolithography and dry etching. , The gate electrode 20 is formed on the CG silicon film 15 near the central portion.

Next, as shown in FIG. 1H, the second silicon oxide film 1 is formed by using the gate electrode 20 as a mask.
From above on the CG silicon film 15 by ion implantation,
P (phosphorus) ions are implanted to form the source region 21a, the drain region 21b and the channel 22 of the TFT.
The dose amount of P (phosphorus) ions is 2 × 10 ¹⁵ atoms
It is about / cm ² . The channel region 22 of the TFT is formed in the CG silicon film 15 below the gate electrode 20, and the source region 21a and the drain region 21b are formed on both sides of the channel region 22 of the TFT, respectively.
Then, a third silicon oxide film 23 having a film thickness of 600 nm, which functions as an interlayer insulating film, is formed on the entire surfaces of the second silicon oxide film 19 and the gate electrode 20 by the CVD method, and the source regions 21a and Drain region 2
For activation of P (phosphorus) ions injected into 1b,
Heat treatment is performed at a temperature of 950 ° C. for 30 minutes in a nitrogen atmosphere.

After that, the second silicon oxide film 19 and the third silicon oxide film 23 on the source region 21a and the drain region 21b in the CG silicon film 15 are removed by general photolithography and dry etching. A source contact hole 24 and a drain contact hole 25 are formed, respectively.

Next, as shown in FIG. 1H, a film thickness of 400 nm is formed on the third silicon oxide film 23, the source contact hole 24 and the drain contact hole 25.
The AlSi film is formed and patterned by using photolithography and dry etching to form the source wiring 26 and the drain electrode 27 made of the AlSi film in the source contact hole 24 and the drain contact hole 25, respectively. The source wiring 26 and the drain electrode 27 are connected to the source region 21a and the drain region 21b, respectively. After that, an interlayer insulating film 28 made of a nitride film and having a thickness of 400 nm is formed on the third silicon oxide film 23, the source wiring 26, and the drain electrode 27, and the drain electrode 27 is formed on the drain electrode 27 by photolithography and dry etching. A pixel contact hole 29 is formed in the interlayer insulating film 28. After that, a transparent conductive film (ITO) having a film thickness of 80 nm is formed on the interlayer insulating film 28 and the pixel contact hole 29, and patterned by using photolithography and dry etching to form a pixel electrode 30 made of the transparent conductive film (ITO). To form. The pixel electrode 30 formed in the pixel contact hole 29 is connected to the drain electrode 27.

As described above, the liquid crystal driving TFT can be manufactured by the steps shown in FIGS.

Further, Ni of the catalytic metal element remaining in the CG silicon film formed by the method of manufacturing a semiconductor device of the present invention is removed by ICP-MS (Inductive C).
open Plasma-Mass Spectro
The following results were obtained by measurement by the method of measurement: inductively coupled plasma mass spectrometry. For the measurement, a CG silicon film having a film thickness of 70 nm was formed on the entire surface of the quartz substrate and the gettering treatment was completed was used as a sample.

As a result, first, the Ni residue on the entire surface of the quartz substrate was left.
The average value of the distillate is 4 × 10⁹atoms / cm²Is below
It was At this time, on the quartz substrate after the gettering process is completed
The area ratio of the CG silicon film in the
When converted from the thickness of the recon film being 70 nm, C
The residual amount of Ni in the G silicon film is 8.79 × 10. ¹⁴a
toms / cm³It becomes the following.

The present embodiment is an example of a TFT manufactured by the method for manufacturing a semiconductor device of the present invention, and the materials, film thicknesses, forming methods, etc. of parts other than those described in the present embodiment are as described above. Not as long as the.

[0052]

According to the method of manufacturing a semiconductor device of the present invention, a plurality of first regions, each having a reduced thickness of the amorphous silicon film, are formed on the amorphous silicon film having a predetermined thickness. A catalytic element, which is the first element, is added to the first region of 1 to form a crystalline silicon film. After that, a gettering element which is a second element is added to the first region and the second region which is arranged between the first regions which are adjacent to each other, and the first region in the crystalline silicon film is added. The element is moved to the region to which the second element is added, and the active region of the semiconductor device is formed using the region of the crystalline silicon film other than the region to which the second element is added. As a result, the concentration of the catalytic metal element added when the laterally grown CG silicon film is grown can be reduced.

In the semiconductor device of the present invention, the first element for promoting crystallization is 1.0 × 10 ¹⁵ atoms / cm ^{3 in the} amorphous silicon film formed on the substrate having an insulating surface.
Since it has a crystalline silicon film that is crystallized by adding less than that, a TFT having good electric characteristics can be formed in the laterally grown CG silicon film.

[Brief description of drawings]

1A to 1I are cross-sectional views for explaining respective steps in a method for manufacturing a semiconductor device according to an embodiment of the present invention.

2A to 2D are schematic plan views showing states in which a CG silicon film is vertically grown.

3A to 3D are schematic plan views showing states in which a CG silicon film is laterally grown.

FIG. 4 is a schematic plan view showing a lateral growth state of a CG silicon film when the size of a domain 57 is large.

FIG. 5 is a schematic plan view showing a lateral growth state of a CG silicon film when the size of a domain 57 is small.

[Explanation of symbols]

11 Quartz substrate 12 Amorphous silicon film 13 Protective film 14 holes 14a hole 15 CG silicon film 15aCG silicon film 15bCG silicon film 16 domain boundaries 17 P (phosphorus) implantation area 19 Second silicon oxide film 20 gate electrode 21a source area 21b drain region 22 channel area 23 Third Silicon Oxide Film 24 Source contact hole 25 Drain contact hole 26 Source wiring 27 drain electrode 28 Interlayer insulation film 29 pixel contact hole 30 pixel electrodes

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 2H092 JA25 JA34 JA37 JA41 JA46                       JB57 KA04 KA05 KA10 MA04                       MA05 MA08 MA15 MA18 MA27                       MA41 NA21 NA24 NA29                 5F052 AA11 AA17 DA01 DA02 DB02                       EA16 FA06 HA06 JA01                 5F110 AA30 BB01 CC02 DD03 EE09                       EE45 FF02 FF29 FF35 GG02                       GG13 GG47 HJ01 HJ04 HJ13                       HJ23 HL05 NN03 NN23 NN24                       NN72 PP10 PP13 PP23 PP34                       QQ11 QQ28

Claims (5)

[Claims] 1. An amorphous silicon film having a predetermined thickness is formed on a substrate having an insulating surface, and a plurality of regions of the amorphous silicon film are thinned to form a plurality of first regions. And a step of adding a first element that promotes crystallization to each of the first regions, and then a first heat treatment is performed to grow the amorphous silicon film to crystallize Of forming a conductive silicon film, and an effect of selectively attracting the first element to the first regions and the second regions arranged between the first regions adjacent to each other And a step of performing a second heat treatment to move the first element in the crystalline silicon film to a region to which the second element has been added, By using the region of the crystalline silicon film other than the region in which the element of Method of manufacturing a semiconductor device characterized in that it comprises forming an active region of a semiconductor device. 2. The first element is Fe, Co, Ni,
The element is one or more elements selected from Cu, Ru, Rh, Pd, Os, Ir, Pt, and Au.
A method of manufacturing a semiconductor device according to item 1. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the second element is P (phosphorus). 4. A semiconductor device having a crystalline silicon film which is crystallized by adding a first element for promoting crystallization to an amorphous silicon film formed on a substrate having an insulating surface. , The content of the first element in the crystalline silicon film is 1.0
A semiconductor device having a density of less than × 10 ¹⁵ atoms / cm ³ . 5. The semiconductor device according to claim 4, wherein the first element is Ni (nickel).