JP2629601B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a p-type thin film transistor.

[0002]

2. Description of the Related Art A p-type thin film transistor (hereinafter, referred to as TFT)
Is mainly used in a complementary circuit together with an n-type transistor. Specifically, it is used in a CMOS circuit composed of a TFT or a complete CMOS type SRAM. Therefore, as its characteristics, it is required that the ON current is large and the OFF current is low. Furthermore, TF
In the T CMOS circuit, it is required that the absolute value of the threshold value is not largely different from that of the n-type TFT. If this condition is not satisfied, an inverter having desirable characteristics cannot be obtained.

[0003] FIG. 7 shows a conventional C-type TFT composed of TFTs.
FIG. 3 is a sectional view of a MOS circuit. As shown in FIG. 1, an n-type TFT 20a and a p-type TFT
20b are formed. The n-type TFT 20a includes an n ⁺ -type polycrystalline silicon thin film 6a and a channel region 7a formed on the quartz glass substrate 1, a gate oxide film 4 formed on the channel region, and a gate electrode 5 formed thereon. And the p-type TFT 20b is
It is composed of a p ⁺ -type polycrystalline silicon thin film 6b and a channel region 7b formed on a quartz glass substrate 1, a gate oxide film 4 formed on the channel region, and a gate electrode 5 formed thereon. I have. TFT 20a, 2
Ob is covered with an interlayer insulating film 8, and the n ⁺ -type polycrystalline silicon thin film 6 a and the p ⁺ -type polycrystalline silicon thin film 6 b serving as source / drain regions are formed through contact holes formed in the interlayer insulating film 8. The metal wiring 9 is drawn out onto the interlayer insulating film.

In the semiconductor device shown in FIG. 7, the characteristics when both channel regions 7a and 7b of both transistors are formed of non-doped polycrystalline silicon are shown in FIG.
Shown in As shown in the figure, the n-type TFT shows almost ideal characteristics, while the p-type TFT shows depletion characteristics, and a large drain current flows at a gate voltage: Vg = 0V. That is, a non-doped polycrystalline silicon formed on a quartz glass substrate is used as a channel region.
In the type TFT, a back channel is easily formed, and deterioration of the off characteristics cannot be avoided. Such a tendency is observed not only when a TFT is formed directly on a quartz glass substrate but also when a TFT is formed on a silicon oxide film. Therefore, conventionally, an n-type impurity such as P (phosphorus) or As (arsenic) has been doped into the channel region to lower the off-state current by moving the threshold voltage to the negative side.

[0005] As this kind of prior art, in addition to the above-mentioned ones, contrary to the above-described case, p-channel TFTs are formed in the channel region of the n-type TFT.
Japanese Unexamined Patent Publication No. Hei 4 (1994) -104605 discloses that the n-type TFT and the p-type TFT have the same absolute value of the threshold voltage by doping with n-type impurities.
Japanese Patent Application Laid-Open No. 290467/1990.
It is proposed to form a polycrystalline silicon film containing boron (B) at a concentration of 1E15 to 1E19 cm ^-3 , thereby forming a p-type TFT and an n-type TFT, and making the absolute values of the threshold voltages of both transistors uniform. Have been.

[0006]

In each of the prior arts described above, the threshold voltage is adjusted by doping the channel region with an impurity. That is, since the channel region is doped with impurities of different conductivity types from the source / drain region, the on-current decreases as the injection amount increases, and at the same time, the junction leakage between the channel region and the source / drain region increases. As a result, the on / off characteristics deteriorate. In addition, in a p-type TFT used for a load transistor of an SRAM, when the threshold is controlled by channel doping, the drain region is usually formed at an offset, so that the conditions for optimizing the amount of ion implantation are strict. There is a drawback that the leakage current tends to increase. Furthermore, there has been another inconvenience that it is difficult to secure an on-current due to a recent reduction in drive voltage.

The present invention has been made in view of such a point, and an object thereof is to shift the threshold voltage of a p-type TFT to a negative side without performing channel doping. Is to do so. As a result, the on / off current ratio of the p-type TFT is improved, and the absolute values of the threshold values of the p-type and n-type TFTs are made closer to maintain the characteristics of the CMOS circuit including the CMOS inverter in a good condition. Is to try to be able to.

[0008]

[MEANS FOR SOLVING THE PROBLEMS] To achieve the above object
According to the present invention,p-channel type thin film transistor
an n-channel type thin film transistor;
-Type thin film transistor and the n-channel type thin film transistor
StarEachButVia the gate electrode and the gate insulating film
A channel region and a channel region formed facing the gate electrode;
Polysilicon film forming the source and drain regions
AndAndSemiconductor devices, The p-channel
The channel region of the thin film transistor is the gate electrode
On the opposite side of the silicon nitride filming,
The channel region of the n-channel thin film transistor is
Except for the silicon nitride film on the surface opposite to the gate electrode
In contact with the insulationIs,That the two conditions are met
That these two conditions are metBy both tran
Threshold voltage of transistor is almost equal in absolute value
A semiconductor device, characterized in that
You.

[0009]

[Function] An n-type TFT and a p-type TF formed on a quartz substrate
FIG. 1 shows the gate voltage Vg-drain current Id characteristic of T.
(A). Similar data can be obtained when these transistors are formed on a silicon oxide film. Also,
FIG. 1B shows a gate voltage V of both transistors when an n-type TFT and a p-type TFT are formed on a silicon nitride film.
It is a graph which shows g-drain current Id characteristic.

As shown in FIGS. 1A and 1B, among the TFTs on the quartz substrate, the n-type TFT shows good characteristics, but the threshold value of the p-type TFT shifts to the depletion side. The off-state current has increased. Therefore, this p
A circuit using a single type TFT and a CMOS circuit using this transistor hinder circuit operation. On the other hand, for a TFT on a silicon nitride film,
Contrary to the characteristics of T, in the p-type TFT, the threshold value shifts to the enhancement side, and relatively good characteristics are obtained. However, in the n-type TFT, the threshold value shifts greatly to the depletion side, and the leakage occurs. The current increases and the transistor does not turn off.

The reason why such a phenomenon occurs is that a p-type back channel is easily formed on a quartz substrate and an n-type back channel is easily formed on a silicon nitride film due to the characteristics of the underlying material. It is thought to be. Therefore, in the present invention, the p-type TFT is formed on the silicon nitride film, and only the n-type TFT is formed directly on the quartz substrate (or silicon oxide film). By doing so, the threshold values of both transistors can be equalized, and the off-state current of each transistor can be reduced and the on-state current can be maintained large.

[0012]

Next, embodiments of the present invention will be described with reference to the drawings. [First Embodiment] FIG. 2 is a cross-sectional view of a CMOS circuit comprising TFTs according to a first embodiment of the present invention. As shown in the figure, in the present embodiment, the n-type TFT 20a
Are formed directly on the quartz glass substrate 1 and the p-type TFT 20
b is formed on the quartz glass substrate 1 via the silicon nitride film 2. Since the structure and features of the present embodiment become more apparent by knowing the manufacturing method, the manufacturing method of the present embodiment will be described below with reference to FIG.

FIGS. 3A to 3D are process cross-sectional views sequentially showing the manufacturing steps of the first embodiment of the present invention. First,
A low pressure vapor phase epitaxy (hereinafter referred to as LPCV)
D), a silicon nitride film 2 is deposited to a thickness of 10 to 50 nm, and a photolithography method and a dry etching method are applied to selectively form the silicon nitride film 2 in a region where the p-type TFT is arranged [FIG. (A)].

Next, amorphous silicon is deposited in the same temperature range of 450 to 550 ° C. using silane or disilane as a raw material gas in an LPCVD apparatus, and is thermally annealed at about 600 ° C. to cause solid phase growth. Is formed (FIG. 3B). Next, this is patterned by a photolithography method and a dry etching method, and is formed on an n-type TFT forming region on the quartz glass substrate 1.
Then, the polycrystalline silicon thin film 3 is left on the p-type TFT formation region on the silicon nitride film 2 [FIG. 3 (c)].

Next, a gate oxide film 4 made of a silicon oxide film having a thickness of about 100 nm is formed by the LPCVD method or the thermal oxidation method. Subsequently, a polycrystalline silicon film is deposited by the LPCVD method. The gate electrode 5 of the transistor is formed. Then, p
Type TFT side is masked by a photoresist, the gate electrode 5 as a mask polycrystalline silicon thin film of n-type TFT side by doping P ions or As ions at a high concentration, forming an n ⁺ -type polycrystalline silicon film 6a I do. Then, n-type TFT
The side is masked with a photoresist, and using the gate electrode 5 as a mask, the polycrystalline silicon thin film on the p-type TFT side is heavily doped with B ions or BF ₂ ions to form a p ⁺ -type polycrystalline silicon thin film 6b. . At this time, portions of the polycrystalline silicon thin film which are not doped with impurities become channel regions 7a and 7b (FIG. 3D). Here, the order of forming the n ⁺ -type polycrystalline silicon thin film 6a and the p ⁺ -type polycrystalline silicon thin film 6b can be reversed. Also, the first photoresist mask can be omitted. In this case, it is necessary to increase the later ion implantation concentration.

Next, an interlayer insulating film 8 is formed, and after a contact hole is formed, a metal wiring 9 is formed by depositing aluminum and patterning the same. Thereafter, the channel regions 7a and 7b are stabilized by a treatment in plasma hydrogen. Thus, the semiconductor device of the present embodiment shown in FIG. 1 can be obtained.

In the CMOS semiconductor device formed as described above, the n-type TFT has the characteristics shown in FIG.
Since the p-type TFT has the characteristics shown in FIG. 1B, the gate voltage Vg−
The drain current Id characteristic is as shown in FIG. As shown in the figure, both transistors are of the enhancement type, and the absolute values of the threshold values are almost equal. Further, the current at Vg = 0, that is, the off current, is also kept low. Therefore, a CMOS circuit having excellent characteristics can be obtained according to this embodiment.

Reference Example FIG. 5 is a cross-sectional view showing a reference example of the present invention. This reference example relates to an example of applying the present invention to a load transistor of the full CMOS type SRAM. A bulk type n-channel MOS transistor as a driving transistor includes a gate electrode 5 formed on a p-type silicon substrate 10 via a first gate oxide film 4a, and a source formed in a surface region of the silicon substrate.・ N ⁺ type diffusion layer 1 constituting drain region
And 1.

On the other hand, the p-type TFT serving as a load has the gate electrode 5 in common with the drive transistor, and is formed with a p ^{+ serving} as a source / drain region formed thereon via a second gate oxide film 4b. It has a type polycrystalline silicon thin film 6b and a channel region 7b. The drain region is formed at an offset to improve characteristics. The p-type TFT is covered with a silicon nitride film 2a, on which an interlayer insulating film 8 is formed. The drain of the n-channel MOS transistor and the drain of the p-type TFT are connected by a metal wiring 9.

In the p-type load transistor formed as described above, a large on-state current can be realized and an off-state current can be suppressed low, so that the operation speed can be improved and the standby state can be improved. Current consumption can be reduced. Further, according to the present reference example, an effect of improving passivation characteristics such as improvement of moisture resistance can be expected.

Second Embodiment FIG. 6 is a sectional view showing a second embodiment of the present invention. In order to manufacture the semiconductor device of this embodiment, first, a silicon oxide film 12 is formed on a quartz glass substrate 1 at a high temperature by an LPCVD method.
Is deposited on the entire surface. This is a film formed for the purpose of equalizing the surface state of a substrate when a TFT is manufactured on a glass substrate, thereby preventing a change in characteristics. The subsequent steps are the same as in the first embodiment. In FIG. 6, the same parts as those in FIG. 2 are denoted by the same reference numerals, and the description thereof will not be repeated.

Also in this embodiment, since the n-type TFT 20a is formed on silicon oxide and the p-type TFT is formed on silicon nitride, almost the same characteristics as those of the first embodiment shown in FIG. 4 are obtained. be able to. The present embodiment can provide the same effects as the first embodiment, and can reduce the variation in characteristics as compared with the case of the first embodiment.

While the preferred embodiment has been described above,
The present invention is not limited to the above embodiments, and various changes can be made without departing from the spirit of the present invention. For example, although polycrystalline silicon is used for the gate electrode in the embodiment, silicide or polycide can be used instead. Also, an SOI (silicon on insulator) substrate can be used instead of the insulating substrate of the embodiment. Although the non-doped polycrystalline silicon is basically used for the channel region of the TFT of the present invention, a slight impurity can be doped to more accurately control the threshold voltage. Even in this case, channel doping can be suppressed as compared with the conventional example in which the entire threshold voltage shift is compensated by impurity doping.

[0024]

As described above, the semiconductor device according to the present invention has a structure in which the surface of the channel region of the p-type TFT opposite to the gate electrode is in contact with the silicon nitride film. As a result, the off-state current can be reduced. Further, since the threshold value is not moved by channel doping, the problem of a decrease in on-current due to ion implantation can be avoided.
Therefore, using this p-type TFT, a TFT-type CMOS
, The absolute values of the threshold voltages of the p-type and n-type TFTs can be made substantially equal without performing channel doping, and an inverter having excellent characteristics can be formed. become. Therefore, according to the present invention, T
In the case where the FT-CMOS is used for a drive circuit for a liquid crystal display device, for example, the performance of the liquid crystal display device can be improved.

[Brief description of the drawings]

FIG. 1 is a graph showing a gate voltage-drain current characteristic curve for explaining the operation of the present invention.

FIG. 2 is a sectional view of the first embodiment of the present invention.

FIG. 3 is a process sectional view for describing the manufacturing method according to the first embodiment of the present invention.

FIG. 4 is a gate voltage-drain current characteristic curve diagram for explaining the effect of the first embodiment of the present invention.

FIG. 5 is a sectional view of a reference example of the present invention.

FIG. 6 is a sectional view of a second embodiment of the present invention.

FIG. 7 is a sectional view of a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Quartz glass substrate 2, 2a Silicon nitride film 3 Polycrystalline silicon thin film 4 Gate oxide film 4a First gate oxide film 4b Second gate oxide film 5 Gate electrode 6an n ⁺ type polycrystalline silicon thin film 6b p ⁺ type polycrystalline Silicon thin film 7a, 7b Channel region 8 Interlayer insulating film 9 Metal wiring 10 p-type silicon substrate 11 n ⁺ type diffusion layer 12 silicon oxide film 20a n-type TFT (n-type thin film transistor) 20b p-type TFT (p-type thin film transistor)

Claims (5)

(57) [Claims] (1)P channel type thin film transistor and n channel
And a p-channel thin film transistor.
Film transistor and the n-channel thin film transistor
EachButA gate electrode and a gate insulating film,
A channel region and a source formed opposite the gate electrode.
And a polycrystalline silicon film forming a source / drain region.
PreparationAndSemiconductor devices,  The channel region of the p-channel thin film transistor is
A silicon nitride film is formed on the surface opposite to the gate electrode.
contacting,  The channel region of the n-channel thin film transistor is
On the surface opposite to the gate electrode, a silicon nitride film
In contact with outside insulationIs,Are satisfied, and these two conditions are satisfied.
Being done Threshold voltage of both transistors
Characterized in that they are formed almost equally in log values
Semiconductor device. 2. The semiconductor device according to claim 1, wherein the channel region of the p-channel thin film transistor is a region to which an impurity is not intentionally added. 3. The n-channel thin film transistor.
The channel region is a region where impurities are not intentionally added.
The semiconductor device according to claim 1, wherein 4. The p-channel thin film transistor and the n-channel thin film transistor are formed on an insulating film or an insulating substrate, and between the insulating film or the insulating substrate and the p-channel thin film transistor. 2. The semiconductor device according to claim 1 , wherein a silicon nitride film is formed. 5. An n-channel thin film transistor.
Insulation in contact with the surface of the channel region opposite to the gate electrode
2. The method according to claim 1, wherein the material is silicon oxide.
Semiconductor device.