KR100542989B1 - Cmos thin film transistor and display device using the same - Google Patents

Abstract

The present invention relates to a CMOS thin film transistor and a display device using the same, wherein the polycrystalline silicon crystal grains formed in the active channel of the P-type thin film transistor have an anisotropic crystal grain structure, and are formed in the active channel of the N-type thin film transistor. By providing a CMOS thin film transistor and a display device using the same, the grain has a grain structure of the isotropic crystal form to provide a CMOS thin film transistor and a display device having improved electrical characteristics such as the absolute value of the threshold voltage and current mobility. Can be.

CMOS thin film transistor, organic EL device, isotropic grain structure, anisotropic grain structure

Description

CMOS Thin Film Transistor and Display Device Using the Same {CMOS THIN FILM TRANSISTOR AND DISPLAY DEVICE USING THE SAME}

1A to 1G are flowcharts sequentially illustrating a process for manufacturing a CMOS thin film transistor according to an exemplary embodiment of the present invention.

2A to 2D are graphs showing grain shapes of polycrystalline silicon thin films included in active channel regions of the P-type thin film transistor having the LDD structure of FIG. 1G and the N-type thin film transistor, and FIGS. 2A to 2C are anisotropic shapes. Particle form, and FIG. 2D shows the particle form of the isotropic form.

3A and 3B are graphs showing threshold voltage values Vth of a P-type thin film transistor (FIG. 3A) and an N-type thin film transistor (FIG. 3B) employing polycrystalline silicon having the crystal form of FIGS. 2A to 2D.

[Industrial use]

The present invention relates to a CMOS thin film transistor and a display device using the same, and more particularly, a CMOS thin film transistor having a high current mobility and little difference in absolute values of threshold voltages of a P-type thin film transistor and an N-type thin film transistor; It relates to a display device using the same.

[Prior art]

In general, circuits using a CMOS metal thin film transistor (CMOS TFT) are used to drive an active matrix LCD, an organic EL device, an image sensor, and the like. However, in general, the absolute value of the threshold voltage of the TFT is larger than the absolute value of the threshold voltage of the MOS transistor using a single crystal semiconductor. Moreover, the absolute value of the threshold voltage of the N-type thin film transistor is very different from the absolute value of the P-type thin film transistor. For example, when the threshold voltage of the N-type thin film transistor is 2V, it is -4V in the P-type thin film transistor.

Therefore, it is not desirable to operate the circuit that the absolute value of the threshold voltage of the P-type thin film transistor and the N-type thin film transistor is very different, and in particular, it serves as a large barrier to reducing the driving voltage. For example, a P-type thin film transistor having a large absolute value of a threshold voltage generally does not operate properly at a low driving voltage.

That is, the P-type thin film transistor merely functions as a passive element such as a resistor and does not operate fast enough. To operate the P-type thin film transistor like a passive device, the driving voltage needs to be high enough.

In particular, when the gate electrode is made of a material having a work function of 5 eV or less, such as aluminum, the difference in work function between the gate electrode and the intrinsic silicon semiconductor is reduced by -0.6 eV. As a result, the threshold voltage of the P-type thin film transistor is shifted to a negative value, and the threshold voltage of the N-type thin film transistor is close to 0V. Therefore, the N-type thin film transistor is generally made to be on-state.

In the above state, it is preferable that the absolute values of the threshold voltages of the N-type thin film transistor and the P-type thin film transistor are almost the same. In conventional single crystal semiconductor integrated circuit technology, the threshold voltage has been controlled using N or P type impurity doping at very small concentrations of up to 10 ¹⁸ atoms / cm 3. That is, the threshold voltage has been controlled with an accuracy of 0.1 V or less by impurity doping at a concentration of 10 ¹⁵ to 10 ¹⁸ atoms / cm 3.

However, when using a semiconductor other than a single crystal semiconductor, no shift in threshold voltage is observed even when impurities are added at a concentration of 10 ¹⁸ atoms / cm 3 or less. Moreover, when the concentration of the impurity is 10 ¹⁸ atoms / cm 3 or more, the threshold voltage changes rapidly, and the conductivity becomes p-type or n-type. This is because polycrystalline silicon has many defects. Since the defect concentration is 10 ¹⁸ atoms / cm 3, the added impurities cannot be trapped and activated by this defect. Moreover, the concentration of impurities is greater than the concentration of defects and excess impurities are activated and the conductivity type is changed to n or p type.

In order to solve this problem, in US Patent Nos. 6,492,268, 6,124,603 and 5,615,935, the channel length of the P-type thin film transistor is made smaller than the channel length of the N-type thin film transistor by varying the channel length. However, this patent also has a problem in that the manufacturing process is complicated because the channel length must be manufactured differently.

The present invention has been made to solve the problems described above, an object of the present invention is to adjust the shape of the crystal grains included in the active channel, the difference between the absolute value of the threshold voltage of the P-type thin film transistor and the N-type thin film transistor The present invention provides a CMOS thin film transistor having almost no current mobility and a display device using the same.

The present invention to achieve the above object,

The polycrystalline silicon crystal grains formed in the active channel of the P-type thin film transistor have an anisotropic crystal grain structure, and the polycrystalline silicon crystal grains formed in the active channel of the N-type thin film transistor have an isotropic crystal grain structure. To provide.

In addition, the present invention

A liquid crystal display device or an organic EL device using the CMOS thin film transistor is provided.

Hereinafter, with reference to the accompanying drawings of the present invention will be described in more detail.

1A to 1G are flowcharts sequentially illustrating a process for manufacturing a CMOS thin film transistor according to an exemplary embodiment of the present invention.

As shown in FIG. 1A, after depositing a polysilicon film on a substrate 10 having an N-type thin film transistor region 10a and a P-type thin film transistor region 10b, a first mask (not shown) is applied to the substrate (not shown). 10, the polysilicon film is etched to form polysilicon patterns 11a and 11b in the N-type thin film transistor region 10a and the P-type thin film transistor region 10b, respectively. The channel region of the N-type thin film transistor and the channel region of the P-type thin film transistor are formed to have the same width.

At this time, in the case of forming the polysilicon patterns 11a and 11b, the shape of the polysilicon particles formed in the active channel of the region 10b in which the P-type thin film transistor is formed and the region in which the N-type thin film transistor 10a is formed is defined. Form differently. That is, polysilicon having isotropic particles is formed in the active channel of the N-type thin film transistor region, and polysilicon having anisotropic grains is formed in the active channel of the P-type thin film transistor region.

In the present invention, the polysilicon pattern is used to crystallize the amorphous silicon to form a polysilicon film.

Preferably, the active channel region of the P-type thin film transistor is formed by a sequential laser solidification (SLS) method, and the active channel region of the N-type thin film transistor uses the ELA (Exmire Laser Annealing) method.

In addition, when using the same laser crystallization method, the energy of the laser irradiated to the active channel region of the P-type thin film transistor should be greater than the energy of the laser irradiated to the active channel region of the N-type thin film transistor.

In addition, the average size of the grains formed should be larger than that of the N-type thin film transistor, preferably 2 μm or more in the active channel region of the P-type thin film transistor, and 1 in the active channel region of the N-type thin film transistor. It should be less than or equal to μm.

After forming the polysilicon pattern, as shown in FIG. 1B, the polysilicon pattern 11a of the channel region 10a of the N-type thin film transistor is exposed to provide conductivity to the N-type thin film transistor, and then the patterned photoresist is exposed. Channel doping is performed with an N-type dopant using (12) as a mask.

In the present invention, it may have a structure of a conventional N-type thin film transistor, may have a lightly doped drain (LDD) structure or an off-set structure, but is not limited to a specific structure. However, in the present embodiment, for convenience of description, the following steps will be described with respect to the CMOS thin film transistor having the LDD structure.

Subsequently, as shown in FIG. 1C, the photoresist 12 is removed, a gate insulating layer 13 is formed on the substrate 10, and a gate electrode material is deposited thereon. Subsequently, a gate electrode material is formed on the substrate 10 by using a mask to form etched N-type thin film transistors and gate electrodes 14a and 14b of P-type thin film transistors in the corresponding regions. Next, in order to form an LDD structure, an N-type low concentration impurity is ion-implanted into the polysilicon pattern 11a of the N-type thin film transistor region 10a so as to form a low concentration source / drain region on both sides of the gate electrode 14a. (15) is formed.

Subsequently, as shown in FIG. 1D, after the photoresist is applied to the entire surface of the substrate 10 on which the low concentration source / drain regions 15 are formed, impurities to the N-type thin film transistor region 10a are performed by performing a photolithography process. While preventing ion implantation, a mask for forming a source / drain region of a P-type thin film transistor is formed, and the mask is used to form a high concentration of P-type impurities into the polysilicon pattern 11b of the P-type thin film transistor region 10b. Ion implantation forms a high concentration source / drain region 17 of the P-type thin film transistor.

Subsequently, as shown in FIG. 1E, after removing the mask and applying photoresist on the substrate 10 again, a photolithography process is performed to perform the gate electrode and the P-type thin film transistor region of the N-type thin film transistor ( A mask 18 is formed to prevent impurity ion implantation into 10a). Next, the N-type high concentration impurity is ion-implanted into the polysilicon pattern 11a of the N-type thin film transistor region 10a using the mask 18 to form a high concentration source / drain region 19.

Next, as shown in FIG. 1F, after removing the mask 18, an interlayer insulating film 20 is formed on the entire surface of the substrate 10. Subsequently, by placing a mask on the substrate 10, the interlayer insulating layer 20 is etched so that the source / drain regions 17 and 19 of the N-type thin film transistor and the P-type thin film transistor are exposed, thereby etching the N-type thin film transistor region 10a. ) And the contact holes 21a and 21b are formed in the P-type thin film transistor region 10b, respectively.

Finally, as shown in FIG. 1G, after depositing a conductive metal material for forming a source / drain electrode on the entire surface of the substrate 10, the conductive metal material is etched using a mask to form an N-type thin film transistor and a P-type. Source / drain electrodes 22a and 22b of the thin film transistor are formed, respectively.

Thus, a CMOS thin film transistor including an N-type thin film transistor having an LDD structure and a P-type thin film transistor having a conventional structure was produced.

2A to 2D are graphs showing grain shapes of polycrystalline silicon thin films included in active channel regions of the P-type thin film transistor having the LDD structure of FIG. 1G and the N-type thin film transistor, and FIGS. 2A to 2C are anisotropic shapes. Particle form, and FIG. 2D shows the particle form of the isotropic form.

3A and 3B are graphs showing threshold voltage values Vth of a P-type thin film transistor (FIG. 3A) and an N-type thin film transistor (FIG. 3B) employing polycrystalline silicon having the crystal form of FIGS. 2A to 2D. The threshold voltage values are shown in Table 1 below.

Table 1

                                                           (Unit: V)

Form of Grain Vth of P-type Thin Film Transistor Vth of N-type Thin Film Transistor Figure 2a (anisotropic) -4.82 1.41 2b (anisotropy) -4.01 2.34 Figure 2c (anisotropy) -5.84 0.92 2d (isotropic) -11.60 7.90

Referring to Table 1, FIGS. 3A and 3B, in the case of FIGS. 2A to 2C having the anisotropic crystal form, the absolute values of the threshold voltages Vth of the P-type thin film transistor and the N-type thin film transistor have the isotropic crystal form of FIG. 2D. It can be seen that it is smaller than the absolute value of the threshold voltage in the case of having. Therefore, when the thin film transistor is adopted so that the difference in the absolute value of the threshold voltage value between the P-type thin film transistor and the N-type thin film transistor is small, the P-type thin film transistor has an anisotropic crystal form and the N-type thin film transistor has an isotropic crystal form. It can be seen that.

The anisotropic crystal form of FIG. 2A is a pseudo hexagonal shape, the crystal form of FIG. 2B is an anisotropic cylinder shape, the crystal form of FIG. 2C is a pseudo square shape, and FIG. 2D is an isotropic crystal form is an equiaxed crystal shape. have.

As in the present invention, when a CMOS thin film transistor having a different crystal form of polycrystalline silicon contained in an active channel region of an N-type thin film transistor and a crystal form of polysilicon contained in an active channel region of a P-type thin film transistor is used in a display device, It is preferably used in an active element type LCD or an organic electroluminescent element.

As described above, the absolute value of the threshold voltage and the current mobility are changed by varying the number of "primary" grain boundaries in the active channel region of the N-type thin film transistor and the P-type thin film transistor included in the CMOS thin film transistor. The controllability can provide a CMOS thin film transistor with improved electrical characteristics.

Claims (9)

The polycrystalline silicon crystal grains formed in the active channel of the P-type thin film transistor have an anisotropic crystal grain structure, and the polycrystalline silicon crystal grains formed in the active channel of the N-type thin film transistor have an isotropic crystal grain structure. . The method of claim 1, Wherein the grain structure of the anisotropic form is larger in particle size than the grain structure of the isotropic form. delete The method of claim 1, The polycrystalline silicon crystal grains formed in the active channel of the P-type thin film transistor are formed by a sequential lateral solidification (SLS) method, and the polycrystalline silicon crystal grains formed in the active channel of the N-type thin film transistor are subjected to an Eximer Laser Annealing (ELA) method. CMOS thin film transistor that is formed by. The method of claim 1, When polycrystalline silicon crystal grains formed in the active channel of the P-type thin film transistor and polycrystalline silicon crystal grains formed in the active channel of the N-type thin film transistor are formed by the same laser crystallization method, the active channel of the P-type thin film transistor is irradiated. And the energy is greater than the energy radiated to the active channel of the N-type thin film transistor. The method of claim 1, The crystal structure of the anisotropic shape is one of a pseudo hexagonal shape, an anisotropic cylinder shape, or a pseudo square shape, and the crystal structure of the isotropic shape is an equiaxed form (CMOS thin film transistor). The method of claim 1, Wherein said CMOS thin film transistor comprises an LDD structure or an off-set structure. A display device comprising the CMOS thin film transistor according to claim 1. The method of claim 8, And the display device is a liquid crystal display element or an organic electroluminescent display device.

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