KR100308852B1 - Method of fabricating a thin film transistor - Google Patents
Method of fabricating a thin film transistor Download PDFInfo
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- KR100308852B1 KR100308852B1 KR1019980054620A KR19980054620A KR100308852B1 KR 100308852 B1 KR100308852 B1 KR 100308852B1 KR 1019980054620 A KR1019980054620 A KR 1019980054620A KR 19980054620 A KR19980054620 A KR 19980054620A KR 100308852 B1 KR100308852 B1 KR 100308852B1
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000010409 thin film Substances 0.000 title description 13
- 238000000034 method Methods 0.000 claims abstract description 39
- 239000012535 impurity Substances 0.000 claims abstract description 32
- 150000002500 ions Chemical class 0.000 claims abstract description 22
- 239000004973 liquid crystal related substance Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000000137 annealing Methods 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 230000003213 activating effect Effects 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 abstract description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 230000000903 blocking effect Effects 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 5
- 239000010408 film Substances 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000005224 laser annealing Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000001994 activation Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005499 laser crystallization Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- G—PHYSICS
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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Abstract
본 발명은 공정이 단순화된 오버랩 엘디디를 형성함으로써 핫캐리어 스트레스를 저감시킬 수 있는 액정표시장치의 트랜지스터 제조방법에 관한 것으로, 절연기판 상에 활성층을 형성하는 공정과, 상기 활성층 상에 게이트절연막을 개재시키어 게이트전극을 형성하는 공정과, 상기 게이트전극을 마스크로 이용하여 상기 활성층의 노출된 부분에 제 1도전형 불순물이온을 저농도로 도핑하여 저농도영역을 형성하는 공정과, 상기 게이트전극 측면에 상기 저농도영역의 일부분과 중첩되는 제 1도전측벽과 제 2절연측벽을 순차적으로 형성하는 공정과, 상기 활성층의 노출된 부분에 상기 제 1도전형의 불순물이온을 고농도로 도핑하여 고농도영역을 형성하면서 엘디디영역을 한정하는 공정과, 상기 활성층의 고농도영역 및 엘디디영역에 도핑된 불순물 이온을 어닐링하여 활성화시키는 공정을 구비한다.The present invention relates to a method of manufacturing a transistor of a liquid crystal display device capable of reducing hot carrier stress by forming an overlap LED in which the process is simplified, and a method of forming an active layer on an insulating substrate, and forming a gate insulating film on the active layer. Forming a low concentration region by interposing a gate electrode through the interposed portion of the active layer using a gate electrode as a mask, and a low concentration of a first conductive impurity ion in the exposed portion of the active layer; Sequentially forming a first conductive side wall and a second insulating side wall overlapping a portion of the low concentration region; and forming a high concentration region by doping the exposed portion of the active layer with a high concentration of impurity ions of the first conductivity type. A process for defining a region of the CD, and the impurities doped in the high concentration region and the LED region of the active layer A comprises a step of annealing to activate.
따라서, 별도의 엘디디 형성용 포토공정없이 게이트전극 및 그측벽들을 이용함으로써 엘디디를 형성할 수 있어 포토공정이 불필요함에 따라 포토마스크 사용에 따른 미스어라인을 방지하며 전체 제조공정이 단순화되고, 게이트전극 측면의 측벽이 드레인에서 소오스, 소오스에서 드레인 쪽으로 확산이 진행되지 않도록 차단함에 따라 채널길이를 용이하게 제어할 수 있으며, 또한, 핫캐리어 스트레스에 강하며 오프전류를 제어할 수 있다.Therefore, it is possible to form the LEDs by using the gate electrode and the side walls thereof without a separate LED forming process, thereby preventing the misalignment caused by the use of the photomask and simplifying the entire manufacturing process. As the sidewalls of the gate electrode sidewalls prevent the diffusion from proceeding from the drain to the source and the drain from the source, the channel length can be easily controlled, and the channel length is also resistant to hot carrier stress and the off current can be controlled.
Description
본 발명은 액정표시장치의 트랜지스터 제조방법에 관한 것으로, 특히, 공정이 단순화된 엘디디(Lightly Doped Drain) 구조를 형성함으로써 핫캐리어 스트레스(hot carrier stress)를 저감시킬 수 있는 액정표시장치의 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a transistor of a liquid crystal display device, and more particularly, to manufacturing a transistor of a liquid crystal display device capable of reducing hot carrier stress by forming a lightly doped drain structure. It is about a method.
박막 트랜지스터 어레이(TFT-Array)는 스위칭소자로서 박막 트랜지스터를 형성한다.The thin film transistor array (TFT-Array) forms a thin film transistor as a switching element.
이 박막 트랜지스터는 다결정실리콘 또는 단결정실리콘 등을 이용하여 제조할 수 있으며, 다결정실리콘을 이용한 박막 트랜지스터는 비정질실리콘을 이용한 박막 트랜지스터에 비하여 전자나 정공의 이동도가 높고 CMOS 트랜지스터 구현이 가능하다.The thin film transistor may be manufactured using polycrystalline silicon or single crystal silicon, and the thin film transistor using polysilicon may have a higher mobility of electrons or holes and a CMOS transistor than the thin film transistor using amorphous silicon.
다결정실리콘 박막 트랜지스터를 사용하고 있는 액정표시장치는 유리 등의 절연기판 상에 구동회로부와 화소부가 함께 내장된 구조를 취하고 있다. 상기의 다결정실리콘 박막 트랜지스터를 구동회로부에 제작하는 경우에는 다결정실리콘의 특성상 빠른 주파수에서 스위칭이 가능하여 문제가 없지만, 다결정실리콘 박막 트랜지스터를 화소부에 제작하는 경우에는 다결정실리콘의 특성상 오프상태의 드레인 전류값이 크기 때문에 화소전극의 전위 폭을 크게 함으로써 화면특성을 저하시킨다. 따라서, 최근에는 이러한 화소부에서의 오프전류값를 적절한 수준으로 낮추기 위하여 엘디디 구조 혹은 오프셋 구조 등의 박막 트랜지스터를 적용하고 있다.A liquid crystal display device using a polysilicon thin film transistor has a structure in which a driving circuit portion and a pixel portion are incorporated together on an insulating substrate such as glass. In the case where the polysilicon thin film transistor is fabricated in the driving circuit portion, switching is possible at a high frequency due to the nature of the polysilicon, and there is no problem. Since the value is large, the screen characteristic is lowered by increasing the potential width of the pixel electrode. Therefore, in recent years, thin film transistors such as an LED structure or an offset structure have been applied to lower the off current value in the pixel portion to an appropriate level.
도 1a 내지 도 1c는 종래기술에 따른 제 1실시예로, 액정표시장치의 트랜지스터 제조에 있어서, 엘디디 형성을 보이기 위한 공정단면도이다.1A to 1C are cross-sectional views of a first embodiment according to the prior art, in which transistor formation of a liquid crystal display device is shown.
도 1a와 같이, 유리 등의 절연기판(100)상에 다결정실리콘(polysilicon) 박막을 형성한 후, 패턴식각하여 활성층(102)을 형성한다.As shown in FIG. 1A, after forming a polysilicon thin film on an insulating substrate 100 such as glass, the active layer 102 is formed by pattern etching.
활성층(102) 형성은 상기의 방법 외에도 절연기판(100) 상에 비정질 실리콘 상태로 박막을 증착한 후에 레이저 등을 이용하여 다결정 상태로 결정화시키는 방법도 있다.In addition to the above method, the active layer 102 may be formed by depositing a thin film in an amorphous silicon state on the insulating substrate 100 and crystallizing the polycrystalline state using a laser or the like.
전자의 경우에는 다결정 상태로 증착하기 위하여 절연기판 위에서의 Si원자들의 빠른 이동을 위한 고온의 증착온도가 필요하며, 후자의 경우에는 저온에서 비정질실리콘 박막을 형성한 후 고온에서 엑시머 레이저를 이용한 재결정화 방법이 이용된다.In the former case, a high temperature deposition temperature is required for the rapid movement of Si atoms on an insulating substrate in order to deposit in a polycrystalline state. In the latter case, an amorphous silicon thin film is formed at a low temperature and then recrystallized using an excimer laser at a high temperature. Method is used.
도 1b와 같이, 활성층(102)상에 게이트절연막(104)을 개재시키어 게이트전극(106)을 형성한다. 이 후, 활성층(102)상에 게이트전극(106)을 이온블로킹 마스크(ion blocking mask)로 이용하여 저농도의 제 1도전형 또는 제 2도전형의 불순물이온(108)을 도핑한다. 이 과정에서,As shown in FIG. 1B, the gate electrode 106 is formed on the active layer 102 with the gate insulating film 104 interposed therebetween. Thereafter, the first electrode of the first conductivity type or the second conductivity type dopant ion 108 is doped on the active layer 102 using the gate electrode 106 as an ion blocking mask. In this process,
게이트전극(106) 양측의 활성층(106)에는 저농도 불순물영역(a1)이 형성된다.Low concentration impurity regions a1 are formed in the active layers 106 on both sides of the gate electrode 106.
도 1c와 같이, 활성층(102)상에 포토레지스트를 도포한 후, 게이트전극(106)을 덮도록 패턴식각함으로써 마스크패턴(mask pattern)(110)을 형성한다.As shown in FIG. 1C, after the photoresist is applied on the active layer 102, a mask pattern 110 is formed by pattern etching to cover the gate electrode 106.
활성층(102)상에 마스크패턴(110)을 이온 블로킹 마스크로 이용하여 고농도의 제 1도전형 또는 제 2도전형 불순물이온(112)을 도핑한다. 이 과정에서, 마스크패턴(110) 양측의 활성층에는 고농도 불순물영역(b1)이 형성되며, 마스크패턴(110) 하부의 활성층에는 잔류된 저농도 불순물영역인 엘디디(c1)가 형성된다.The first conductive type or the second conductive type impurity ion 112 of high concentration is doped using the mask pattern 110 as an ion blocking mask on the active layer 102. In this process, a high concentration impurity region b1 is formed in the active layers on both sides of the mask pattern 110, and an LED c1, which is a low concentration impurity region remaining, is formed in the active layer under the mask pattern 110.
고농도 불순물영역(b1)은 이 후의 과정을 통해, 소오스/드레인전극(미도시)과 연결된다.The high concentration impurity region b1 is connected to a source / drain electrode (not shown) through the following process.
도 1d와 같이, 마스크패턴(110)을 제거한다.As shown in FIG. 1D, the mask pattern 110 is removed.
이 후, 상기 구조에 레이저(laser)등을 이용하여 어닐링 공정(120)을 진행시킴으로써 엘디디(c1) 및 고농도 불순물영역(b1)을 활성화시킨다.Thereafter, the annealing process 120 is performed using a laser or the like to activate the LEDs c1 and the high concentration impurity region b1.
상기와 같은 방법에 의해, 게이트전극(106) 양측의 활성층에는 엘디디(c1) 및 이 후 공정을 통해 소오스/드레인전극에 연결되는 고농도 불순물영역(b1)가 형성된다.By the above method, the high concentration impurity region b1 is formed in the active layers on both sides of the gate electrode 106 and connected to the source / drain electrodes through a subsequent process.
즉, 종래기술에 따른 제 1실시예에서는 상기에서 처럼, 1회의 포토 공정을 통해 게이트전극 양측의 활성층에 엘디디를 형성하였다.That is, in the first embodiment according to the prior art, the LEDs are formed in the active layers on both sides of the gate electrode through one photo process.
도 2a 내지 도 2e는 종래기술에 따른 제 2실시예로, 액정표시장치의 트랜지스터 제조에 있어서, 엘디디 형성을 보이기 위한 공정단면도이다.2A to 2E are cross-sectional views of a second embodiment according to the prior art, in which the formation of the LEDs is shown in transistor manufacturing of a liquid crystal display device.
도 2a와 같이, 유리 등의 절연기판(200)상에 다결정실리콘 박막을 형성한 후에 식각패턴함으로써 활성층(202)을 형성한다.As shown in FIG. 2A, an active layer 202 is formed by etching patterns after forming a polysilicon thin film on an insulating substrate 200 such as glass.
도 2b와 같이, 활성층(202)상에 포토레지스트(photoresist)를 도포한 후 소정영역을 덮도록 패턴식각하여 제 1마스크패턴(210)을 형성한다.As shown in FIG. 2B, the first mask pattern 210 is formed by applying a photoresist on the active layer 202 and pattern etching to cover a predetermined region.
활성층(202) 상에 제 1마스크패턴(210)을 이온블로킹 마스크로 이용하여 저농도의 제 1도전형 또는 제 2도전형의 불순물이온(208)을 도핑한다.The first mask pattern 210 is used as an ion blocking mask on the active layer 202 to dope a low concentration of the first conductive type or the second conductive type impurity ions 208.
이 과정에서, 제 1마스크패턴(210) 양측 활성층에는 저농도의 불순물영역(a2)이 형성된다.In this process, low concentration impurity regions a2 are formed in the active layers on both sides of the first mask pattern 210.
도 2c와 같이, 활성층(202) 상에 제 1마스크패턴(210)을 덮도록 제 2마스크패턴(214)을 형성한다. 제 1마스크패턴(210)과 제 2마스크패턴(214)간의 간격이 이 후 형성될 엘디디 치수가 된다.As illustrated in FIG. 2C, a second mask pattern 214 is formed on the active layer 202 to cover the first mask pattern 210. An interval between the first mask pattern 210 and the second mask pattern 214 becomes an LED dimension to be formed later.
활성층(202)상에 제 2마스크패턴(214)을 이온블로킹 마스크로 이용하여 고농도의 제 1도전형 또는 제 2도전형의 불순물이온(212)을 도핑한다. 이 과정에서, 제 2마스크패턴(214) 양측의 활성층에는 고농도의 불순물영역(b2)이 형성된다.The second mask pattern 214 is used as an ion blocking mask on the active layer 202 to dope the impurity ions 212 having a high concentration of the first conductive type or the second conductive type. In this process, a high concentration of impurity regions b2 are formed in the active layers on both sides of the second mask pattern 214.
도 2d와 같이, 제 2마스크패턴(214)을 제거한다.As shown in FIG. 2D, the second mask pattern 214 is removed.
이 후, 활성층(202)에 레이저 어닐링 공정을 진행시킴으로써 엘디디(c2) 및 고농도의 불순물영역(b2)을 활성화시킨다.Thereafter, the active layer 202 is subjected to a laser annealing process to activate the LEDs c2 and the high concentration impurity regions b2.
도 2e 와 같이, 활성층(202) 상에 게이트절연막(204)을 개재시키어 제 1마스크패턴과 동일 크기인 게이트전극(206)을 형성한다.As shown in FIG. 2E, the gate electrode 206 having the same size as the first mask pattern is formed on the active layer 202 with the gate insulating film 204 interposed therebetween.
즉, 종래기술에 따른 제 2실시예에서는 2회에 걸친 포토 공정을 이용하여 활성층에 엘디디를 형성하였다.That is, in the second embodiment according to the prior art, the LED was formed in the active layer using two photo processes.
그러나, 상기에서 언급하였던 종래의 제 1, 2실시예에서는 엘디디 형성을 위해 1회 또는 2회의 포토공정이 진행됨에 따라, 포토공정 시의 오정렬을 고려해야 하므로, 엘디디 치수를 조절하기 어렵고, 또한 전체공정이 복잡해졌다.However, in the first and second exemplary embodiments mentioned above, as one or two photo processes are performed to form the LEDs, misalignment during the photo process is to be taken into consideration. The whole process is complicated.
그리고, 레이저를 이용한 활성화 공정시 확산이 진행됨에 따라, 채널길이(channel length)가 변하므로, 소오스에서 드레인, 드레인에서 소오스 쪽으로의 트랜지스터 특성이 달라진다. 또한, 종래의 제 1실시예에서는 자기정렬(self align)TFT 이므로 핫캐리어 스트레스에 매우 취약한 문제점이 있었다.In addition, as diffusion progresses during an activation process using a laser, a channel length changes, and thus transistor characteristics from a source to a drain and a drain to a source are changed. In addition, in the first embodiment of the related art, since the self alignment TFT is very vulnerable to hot carrier stress.
상기의 문제점을 해결하고자, 본 발명의 목적은 엘디디 형성 공정을 단순화시킬 수 있는 액정표시장치의 트랜지스터 제조방법을 제공하려는 것이다.In order to solve the above problems, an object of the present invention is to provide a method of manufacturing a transistor of a liquid crystal display device that can simplify the process of forming the LED.
본 발명의 다른 목적은 핫캐리어 스트레스에 강한 액정표시장치의 트랜지스터 제조방법을 제공하려는 것이다.Another object of the present invention is to provide a transistor manufacturing method of a liquid crystal display device resistant to hot carrier stress.
상기 목적들을 달성하기 위한 본 발명에 따른 액정표시장치의 트랜지스터 형성방법은 절연기판 상에 활성층을 형성하는 공정과, 상기 활성층 상에 게이트절연막을 개재시키어 게이트전극을 형성하는 공정과, 상기 게이트전극을 마스크로 이용하여 상기 활성층의 노출된 부분에 제 1도전형 불순물이온을 저농도로 도핑하여 저농도영역을 형성하는 공정과, 상기 게이트전극 측면에 상기 저농도영역의 일부분과 중첩되는 제 1도전측벽과 제 2절연측벽을 순차적으로 형성하는 공정과, 상기 활성층의 노출된 부분에 상기 제 1도전형의 불순물이온을 고농도로 도핑하여 고농도영역을 형성하면서 엘디디영역을 한정하는 공정과, 상기 활성층의 고농도영역 및 엘디디영역에 도핑된 불순물 이온을 어닐링하여 활성화시키는 공정을 구비한다.A transistor forming method of a liquid crystal display device according to the present invention for achieving the above objects is a step of forming an active layer on an insulating substrate, a step of forming a gate electrode by interposing a gate insulating film on the active layer, and the gate electrode Forming a low concentration region by doping a first conductive type impurity ion to a low concentration in the exposed portion of the active layer using a mask; and a first conductive side wall and a second overlapping portion of the low concentration region on the side of the gate electrode. A step of sequentially forming an insulating side wall, a step of doping the exposed portion of the active layer with a high concentration of doping impurity ions of the first conductivity type to form a high concentration region, and a high concentration region of the active layer and And annealing and activating the impurity ions doped in the LED region.
도 1a 내지 도 1d는 종래기술에 따른 제 1실시예로, 액정표시장치의 트랜지스터 제조에 있어서, 엘디디 형성을 보이기 위한 공정단면도이다.1A to 1D are cross-sectional views of a first embodiment according to the prior art, in which transistor formation of a liquid crystal display device is shown.
도 2a 내지 도 2e는 종래기술에 따른 제 2실시예로, 액정표시장치의 트랜지스터 제조에 있어서, 엘디디 형성을 보이기 위한 공정단면도이다.2A to 2E are cross-sectional views of a second embodiment according to the prior art, in which the formation of the LEDs is shown in transistor manufacturing of a liquid crystal display device.
도 3a 내지 도 3e는 본 발명에 따른 액정표시장치의 트랜지스터 제조에 있어서, 오버랩 엘디디 형성을 보이기 위한 공정단면도이다.3A to 3E are cross-sectional views illustrating a process of forming overlap LEDs in transistor manufacturing of a liquid crystal display according to the present invention.
도 4는 본 발명에 따른 일실시예로, 오버랩(overlap) 엘디디 및 비오버랩(non overlap)된 엘디디 형성을 보이기 위한 공정단면도이다.4 is a cross-sectional view of an embodiment according to the present invention for showing overlapped LEDs and non-overlapped LEDs.
*도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
100, 200, 300, 400. 반도체기판 102, 202, 302, 402. 활성층100, 200, 300, 400. Semiconductor substrate 102, 202, 302, 402. Active layer
104, 204, 304, 404. 게이트절연층 106, 206, 306, 406. 게이트전극104, 204, 304, 404. Gate insulating layers 106, 206, 306, 406. Gate electrodes
108, 208, 308. 저농도 불순물이온주입108, 208, 308. Low concentration impurity ion implantation
110. 마스크패턴110. Mask Pattern
112, 212, 312. 고농도 불순물이온 주입112, 212, 312. High concentration impurity ion implantation
a1, a2, a3 . 저농도 불순물영역a1, a2, a3. Low concentration impurity area
b1, b2, b3, b4. 고농도 불순물영역b1, b2, b3, b4. High concentration impurity area
c1, c2, c3, l, m. 엘디디c1, c2, c3, l, m. Eldi
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하겠다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 3a 내지 도 3e는 본 발명에 따른 액정표시장치의 트랜지스터 제조에 있어서, 엘디디 형성을 보이기 위한 공정단면도이다.3A to 3E are cross-sectional views of a process for showing LED formation in transistors of a liquid crystal display according to the present invention.
도 3a와 같이, 유리 등의 절연기판(300)상에 다결정실리콘을 CVD(Chemical Vapor Deposition)방법으로 증착한 후, 패턴식각함으로써 활성층(302)을 형성한다. 상기 방법 외에도, 비정질실리콘을 증착한 후, 레이저 결정화를 통하여 활성층을 형성할 수도 있다.As illustrated in FIG. 3A, polysilicon is deposited on an insulating substrate 300 such as glass by CVD (Chemical Vapor Deposition), followed by pattern etching to form an active layer 302. In addition to the above method, after depositing amorphous silicon, the active layer may be formed through laser crystallization.
도 3b와 같이, 반도체기판(300)상에 활성층(302)을 덮도록 산화실리콘 등을 증착하여 게이트절연막(304)을 형성한다. 그리고, 게이트절연막(304)상에 활성층의 소정영역과 대응된 부분을 덮도록 부게이트전극(306)을 형성한다.As illustrated in FIG. 3B, a gate insulating layer 304 is formed by depositing silicon oxide or the like on the semiconductor substrate 300 to cover the active layer 302. The sub-gate electrode 306 is formed on the gate insulating film 304 so as to cover a portion corresponding to the predetermined region of the active layer.
이 후, 활성층(302)상에 부게이트전극(306)을 이온블로킹 마스크로 이용하여 저농도의 제 1도전형 또는 제 2도전형의 불순물이온(308)을 도핑한다. 이 과정에서, 부게이트전극(306) 앵측의 활성층에는 저농도의 불순물영역(a3)이 형성된다. 도면에서는 활성층 상에 n형의 불순물이온이 도핑처리된 것이 도시되었다.Thereafter, on the active layer 302, a low concentration of the first conductive type or the second conductive type impurity ions 308 is doped using the sub-gate electrode 306 as an ion blocking mask. In this process, a low concentration impurity region a3 is formed in the active layer on the side of the subgate electrode 306. In the figure, n-type impurity ions are doped on the active layer.
도 3c와 같이, 게이트절연막(304)상에 부게이트전극(306)을 덮도록 금속층(320) 및 절연층(322)을 순차적으로 형성한다. 금속층은 모든 금속이 가능하며, 부게이트전극(306) 형성을 위한 금속과 동일해도 상관없다.As illustrated in FIG. 3C, the metal layer 320 and the insulating layer 322 are sequentially formed on the gate insulating film 304 to cover the subgate electrode 306. The metal layer may be any metal, and may be the same as the metal for forming the subgate electrode 306.
도 3d와 같이, 금속층(320)이 노출되는 시점까지 절연층(322)을 건식식각 방법으로 에치백하여 제 2측벽(322a)을 형성한다. 이 후, 제 2측벽(322a)을 마스크로 하여 금속층을 습식식각 방법으로 제거하여 부게이트전극(306) 측면에 제 1측벽(320a)을 형성한다.As illustrated in FIG. 3D, the second side wall 322a is formed by etching back the insulating layer 322 by a dry etching method until the metal layer 320 is exposed. Thereafter, the metal layer is removed by a wet etching method using the second side wall 322a as a mask to form the first side wall 320a on the side of the sub-gate electrode 306.
따라서, 도면에 도시되어 있듯이, 부게이트전극(306)측면에는 차례로 제 1측벽(320a)과 제 2측벽(322a)이 형성된다. 본 발명에서는 실제적으로 부게이트전극(306)과 제 1측벽(320a)이 게이트전극이 된다. 따라서, 이하에서 부게이트전극(306)과 제 1측벽(320a)을 주게이트전극라 칭하기로 한다.Therefore, as shown in the drawing, the first side wall 320a and the second side wall 322a are sequentially formed on the side surface of the subgate electrode 306. In the present invention, the sub-gate electrode 306 and the first side wall 320a become the gate electrode. Therefore, the subgate electrode 306 and the first side wall 320a will be referred to as a main gate electrode hereinafter.
그리고, 제 1, 제 2측벽(320a)(322a)을 포함한 부게이트전극(306)을 이온블로킹 마스크로 이용하여 활성층(302) 상에 고농도의 제 1도전형 또는 제 2도전형의 불순물이온(312)을 도핑한다. 상기 도핑 과정을 통해, 활성층(302)에는 엘디디(c3)와 고농도의 불순물영역(b3)이 형성된다. 본 발명에서는 도면에서와 같이, 엘디디(c3)가 주게이트전극(320a)(306) 하부에 오버랩된 구조를 갖는다.Then, using the sub-gate electrode 306 including the first and second sidewalls 320a and 322a as an ion blocking mask, the impurity ions having a high concentration of the first conductive type or the second conductive type are formed on the active layer 302. 312). Through the doping process, the LEDs c3 and the impurity regions b3 of high concentration are formed in the active layer 302. In the present invention, as shown in the figure, the LED (c3) has a structure overlapping the lower portion of the main gate electrode (320a) (306).
도 3e와 같이, 상기 구조에 레이저 어닐링공정을 진행시키어 엘디디(c3)와 고농도의 불순물영역(b3)을 활성화시킨다.As shown in FIG. 3E, the laser annealing process is performed on the structure to activate the LEDs c3 and the high concentration impurity regions b3.
도 4는 본 발명에 따른 일실시예로, 오버랩(overlap) 엘디디 및 비오버랩(non overlap)된 엘디디 형성을 보이기 위한 공정단면도이다.4 is a cross-sectional view of an embodiment according to the present invention for showing overlapped LEDs and non-overlapped LEDs.
도 3d에서와 같은 공정을 통해 형성된 제 1및 제 2측벽(320a)(322a)에 추가로 습식식각 공정을 진행시키면, 도 4와 같은 구조가 형성된다. 즉, 도 4와 같이, 활성층(402)에는 고농도영역(b4)와 저농도영역(c4)인 엘디디가 형성되며, 엘디디는 주게이트전극(406, 420a)과 오버랩된 엘디디인 제 1영역(l)과, 주게이트전극(406, 420a)과 비오버랩(non overlap)된 엘디디인 제 2영역(m)으로 구분된다. 여기에서, 제 2영역(m)은 주게이트전극(406, 420a)이 덮여 있지 않으므로 옵셋(off-set)영역이 된다.When the wet etching process is further performed on the first and second side walls 320a and 322a formed through the process as shown in FIG. 3D, the structure as shown in FIG. 4 is formed. That is, as shown in FIG. 4, the LEDs having the high concentration region b4 and the low concentration region c4 are formed in the active layer 402, and the LEDs are the first regions (LEDs) overlapping the main gate electrodes 406 and 420a. l) and the second region m, which is a non-overlapping LED, with the main gate electrodes 406 and 420a. The second region m is an offset region because the main gate electrodes 406 and 420a are not covered.
따라서, 본 발명의 오버랩 엘디디 구조 또는 오버랩 엘디디 및 비오버랩 엘디디를 동시에 갖는 구조는 실제적으로 단채널효과를 가지므로 오프전류를 줄일 수 있다.Therefore, the overlap LED structure of the present invention or the structure having the overlap LED and non-overlap LED at the same time can have a short channel effect, thereby reducing the off current.
상술한 바와 같이, 본 발명에서는 별도의 엘디디 형성용 포토공정없이 게이트전극 및 그측벽들을 이용함으로써 엘디디를 형성할 수 있다. 따라서, 포토공정이 불필요함에 따라 포토마스크 사용에 따른 미스이라인을 방지할 수 있고, 또한 전체 제조공정이 단순화된다.As described above, in the present invention, the LEDs may be formed by using the gate electrode and the side walls thereof without a separate LED forming process. Therefore, the miss line can be prevented due to the use of the photomask because the photo process is unnecessary, and the entire manufacturing process is simplified.
그리고 본 발명에서는 게이트전극 측면의 측벽이 드레인에서 소오스, 소오스에서 드레인 쪽으로 확산이 진행되지 않도록 차단함에 따라, 채널길이를 용이하게 제어할 수 있다.In the present invention, the channel length can be easily controlled by blocking the sidewalls of the gate electrode side from being diffused from the drain to the source and from the source to the drain.
또한, 본 발명의 오버랩 엘디디 구조 또는 오버랩 엘디디 및 비오버랩 엘디디를 동시에 갖는 구조는 핫캐리어 스트레스에 강하며 오프전류 제어효과가 큰 이점이 있다.In addition, the overlap LED structure of the present invention or the structure having an overlap LED and non-overlap LED at the same time is strong against the hot carrier stress and has the advantage of a large off-current control effect.
Claims (3)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980054620A KR100308852B1 (en) | 1998-12-12 | 1998-12-12 | Method of fabricating a thin film transistor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980054620A KR100308852B1 (en) | 1998-12-12 | 1998-12-12 | Method of fabricating a thin film transistor |
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| Publication Number | Publication Date |
|---|---|
| KR20000039312A KR20000039312A (en) | 2000-07-05 |
| KR100308852B1 true KR100308852B1 (en) | 2002-10-25 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980054620A KR100308852B1 (en) | 1998-12-12 | 1998-12-12 | Method of fabricating a thin film transistor |
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| KR (1) | KR100308852B1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR101026808B1 (en) | 2004-04-30 | 2011-04-04 | 삼성전자주식회사 | Manufacturing method for thin film transistor array panel |
| US9318506B2 (en) * | 2011-07-08 | 2016-04-19 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| KR20230073403A (en) * | 2021-11-18 | 2023-05-26 | 삼성디스플레이 주식회사 | Display device and method for fabricating the saem |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0621098A (en) * | 1992-07-03 | 1994-01-28 | Seiko Epson Corp | Semiconductor device and manufacture thereof |
| JPH0832080A (en) * | 1994-07-14 | 1996-02-02 | Semiconductor Energy Lab Co Ltd | Semiconductor device and manufacture thereof |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0621098A (en) * | 1992-07-03 | 1994-01-28 | Seiko Epson Corp | Semiconductor device and manufacture thereof |
| JPH0832080A (en) * | 1994-07-14 | 1996-02-02 | Semiconductor Energy Lab Co Ltd | Semiconductor device and manufacture thereof |
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| Publication number | Publication date |
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| KR20000039312A (en) | 2000-07-05 |
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