KR100274887B1 - Thin film transistor and method for manufacturing the same - Google Patents

Abstract

PURPOSE: A thin film transistor is provided to be capable of reducing an off current, by diffusing an impurity doped into drain and source regions with a high concentration onto a channel layer upon a laser annealing to form a lightly doped drain region. CONSTITUTION: The thin film transistor includes a channel layer(103) on a buffer layer(102) formed on a substrate(101). The channel layer(103) has a step at its both directions. A source region(105b) and a drain region(105a) are formed at the both sides of the channel layer. A portion of the source and drain regions is overlapped with the channel layer. A gate insulating film(107) is deposited on the source and drain regions. A gate electrode(108) is positioned at a given portion of the gate insulating film so that the gate electrode can be located between the source region and the drain region.

Description

Thin film transistor and its manufacturing method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and a method of fabricating the same. In particular, a thin film transistor and a method of manufacturing the same may be formed by diffusing impurities heavily doped in drain and source regions into a channel layer during laser annealing to form an LDD region. It is about.

The thin film transistor is a switching device for switching the image data signal of each pixel region in the liquid crystal display device. The thin film transistor shown in FIGS. 3 and 4 has a top gate structure, and FIG. 3 is an offset set. Or a cross-sectional structure diagram of a conventional thin film transistor having no LDD (Lightly doped drain) region, and FIG. 4 is a cross-sectional structure diagram of a conventional thin film transistor having an offset or LDD region.

The conventional thin film transistor of FIG. 3 includes a substrate 1 and a buffer layer 2 formed by depositing an oxide film on the substrate 1 using thin film equipment, and a drain region 3a heavily doped on the buffer layer 2. And a channel layer 3 on which the source region 3b and the channel regions I are formed, a gate insulating film 4 formed on the channel layer 3, and a gate electrode 5 formed on the gate insulating film 4. The length of the channel region I of the channel layer 3 and the length of the gate electrode 5 are the same.

The conventional thin film transistor having the offset or LDD region of FIG. 4 is the same as the thin film transistor of FIG. 3 except that the leakage current flowing between the drain and the source of the thin film transistor when the thin film transistor is off, that is, the off current ( Channel region longer than the length of channel region I of FIG. 3 to form an offset or LDD region II lightly doped at both edges of channel region I of FIG. 3 to reduce off-current. Has (I). That is, the length of the channel region I of the conventional thin film transistor of FIG. 4 is longer than the length of the gate electrode 5.

The manufacturing method of the conventional thin film transistor of FIG. 3 is as follows.

An oxide film is deposited on the upper portion of the substrate 1 to form a buffer layer 2, and a channel layer 3 made of amorphous silicon undoped at low temperature is formed on the entire upper surface of the buffer layer 2. It is formed using a thin film deposition apparatus, and the channel layer 3 is patterned, and then laser annealed the patterned channel layer 3 to recrystallize the channel layer 3 into polycrystalline silicon. . The gate insulating film 4 is formed on the patterned channel layer 3 and the buffer layer 2, and the gate electrode 5 is formed at a predetermined position on the gate insulating film 4. After the gate electrode 5 is formed, a high concentration of impurities are ion implanted using the gate electrode 5 as a mask and heat-treated to a predetermined temperature to form a channel region 3 under the gate electrode 5. ) Is formed, and the drain region 3a and the source region 3b are formed on the left and right sides of the channel region I by the implanted high concentration of impurities.

After the gate electrode 5 is formed, the gate electrode 5 is used as a mask, and thus the drain region 3a and the source region 3b are automatically self-aligned by the gate electrode 5 during ion implantation. After ion implantation, the channel layer 3 is heat-treated to a predetermined temperature to recrystallize between the channel region 3 of the drain region 3a and the source region 3b and the high concentration of impurities implanted, and in this process Impurities doped in the region 3a and the source region 3b are electrically activated.

The manufacturing method of the conventional thin film transistor having the offset region of FIG. 4 is the same as the manufacturing method of the conventional thin film transistor of FIG. 3 except that ion implantation of impurities of high concentration is performed by a separate photolithography process after forming the gate electrode 5. By forming the drain region 3a and the source region 3b or by forming the gate electrode 5 as a mask, ion implantation of low concentration of impurities is carried out and ion implantation of high concentration of impurities is performed by a separate photolithography process. It is implanted to form the drain region 3a and the source region 3b. Accordingly, the channel region I between the drain region 3a and the source region 3b has an offset or LDD region II doped with a low concentration of impurities and is formed longer than the length of the gate electrode 5.

Since the drain region 3a and the source region 3b are spaced apart from the gate electrode 5 by the offset or LDD region II, the influence of the electric field on the gate electrode 5 from the drain or source having a constant potential is reduced. Therefore, the leakage current between the drain and the source is reduced when the thin film transistor is turned off. That is, it is possible to reduce the off current of the thin film transistor.

In manufacturing a thin film transistor having an offset or LDD region for reducing the conventional off current, after setting the offset or LDD region through a separate photographic process to form the offset or LDD region to a low concentration in the set region Due to the ion implantation, there is a problem in that the production step is increased and productivity is lowered and manufacturing cost is increased.

In addition, in the process of forming the offset or LDD region, since the diffusion length of the impurities in the horizontal direction cannot be accurately adjusted, the off current of the thin film transistor cannot be effectively reduced, thereby reducing the reliability of the device.

According to the present invention, a thin film transistor capable of reducing off current by forming an LDD region by diffusing impurities doped at a high concentration in a drain region and a source region during a laser annealing to a channel layer during laser annealing, and a manufacturing method thereof In providing.

The thin film transistor of the present invention for achieving the above object is formed of a substrate coated with a buffer layer, a channel layer formed in a predetermined region of the buffer layer to form a step on both sides to set the channel region and LDD region, the channel layer A structure including a drain region and a source region formed by overlapping portions of the steps formed at both sides, a gate insulating layer stacked to include exposed surfaces of the source region, the drain region, and the channel layer, and a gate electrode formed at a predetermined position of the gate insulating layer Becomes

In order to achieve the above object, a method of manufacturing a thin film transistor according to the present invention may include forming a buffer layer on a substrate, forming a channel layer on a predetermined portion of the buffer layer, and forming a drain region and a source region so as to overlap the channel layer. Forming a step by etching the channel layer exposed by the drain region and the source region to a predetermined depth; forming a gate insulating film on the entire surface including the drain region and the source region; Recrystallizing the channel layer, the drain region, and the source region; and forming a gate electrode between the drain region and the source region on the upper surface of the gate insulating film.

1 is a cross-sectional structure diagram of a thin film transistor according to the present invention;

2a to 2e is a process chart for explaining a manufacturing method of a thin film transistor according to the present invention,

3 is a cross-sectional structure diagram of a conventional thin film transistor;

4 is a cross-sectional view of a thin film transistor for reducing off-state current in the related art.

* Description of the symbols for the main parts of the drawings *

101: substrate 102: insulating layer

103: channel layer 104: first mask pattern

105: doped amorphous silicon layer 105a: source region

105b: drain region 106: mask pattern

107: gate insulating film 108: gate electrode

Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

1 is a side cross-sectional view of a thin film transistor according to an embodiment of the present invention, in which a channel layer 103 having steps formed on both sides is disposed on an upper surface of a buffer layer 102 formed on an upper surface of a substrate 101, and source regions are disposed on both sides thereof. 105b and the drain region 105a are formed to partially overlap the channel layer 103, and the gate insulating film 107 is formed on the top surface of the source region 105b and the drain region 105a. Deposition is formed and the gate electrode 108 is disposed at a predetermined position of the gate insulating layer 107 so as to be positioned between the source region 105b and the drain region 105a.

In such a configuration, a portion of the source region 105b and the drain region 105a overlapping the channel layer 103 becomes an LDD region II, and a channel region I is formed between the LDD regions II. Is formed.

The thin film transistor having the above-described configuration is obtained through the process shown in Figs. 2A to 2E.

First, as shown in FIG. 2A, the buffer layer 102 is formed on the substrate 101, and then the channel layer 103 for forming the channel region and the LDD region is formed by completely depositing amorphous silicon (a-Si) thereon. . In this case, the buffer layer 102 is deposited on the substrate 101 using thin film deposition equipment, and the channel layer 103 is formed by depositing the entire surface on the buffer layer 102 with undoped amorphous silicon and then patterning the same. .

In order to form the channel layer 103, first, amorphous silicon is entirely deposited on the buffer layer 102 using chemical vapor deposition (CVD), and then a first mask pattern 104 is formed on the amorphous silicon using a photolithography process. do. When the first mask pattern 104 is formed, the first mask pattern 104 is patterned into a channel layer 103 having a predetermined standard using the first mask pattern 104 as an etch mask, and then the first mask pattern 104 is removed.

On the upper surface of the channel layer 103 having a predetermined standard, a doped amorphous silicon layer 105 is formed using CVD as shown in FIG. 2B. The doped amorphous silicon layer 105 is formed by simultaneously doping impurities at a high concentration during deposition of amorphous silicon. At this time, the doping concentration may be adjusted by controlling the amount of the impurity injected into the CVD.

When the doped amorphous silicon layer 105 is formed, the doped amorphous silicon layer 105 is patterned to form the drain region 105a and the source region 105b as shown in FIG. 2C. That is, after the second mask pattern 106 is formed on the doped amorphous silicon layer 105 by using a photolithography process, the doped amorphous silicon layer 105 is formed using the second mask pattern 106 as an etching mask. It is etched to penetrate to form the drain region 105a and the source region 105b.

In this case, when the doped amorphous silicon layer 105 is overetched, the channel layer 103 is exposed by penetrating through the doped amorphous silicon layer 105 to expose the channel layer 103 by a predetermined thickness. Steps 103a are formed on both sides of the 103. When the upper surface of the channel layer 103 is etched to a predetermined thickness under the excessive etching conditions of the doped amorphous silicon layer 105, the step 103a is formed on both sides, and the second mask pattern 106 is removed.

That is, as the doped amorphous silicon layer 105 is removed by etching the region selected by the second mask pattern 106, the doped amorphous silicon layer 105 is separated into the drain region 105a and the source region 105b. The channel layer 103 is etched by a predetermined thickness due to an excessive etching condition of the amorphous silicon layer 105 doped with the exposed region except for the portion overlapping the drain region 105a and the source region 105b.

Subsequently, a gate insulating film 107 is formed on the channel layer 103, the drain region 105a and the source region 105b, and then laser annealing is performed as shown in FIG. 2D.

Laser annealing is performed by irradiating a laser beam to the surfaces of the channel layer 103, the drain region 105a and the source region 105b after the gate insulating film 107 is formed and then passes through the gate insulating film 107. In this case, the gate insulating layer 107 is used as a capping layer that absorbs and transmits the laser beam so that the irradiated laser beam is not reflected from the surfaces of the channel layer 103, the drain region 105a, and the source region 105b. do.

The laser beam energy absorbed and transmitted by the gate insulating layer 107 is irradiated to the channel layer 103, the drain region 105a and the source region 105b, and the channel layer 103 is irradiated by the irradiated laser beam energy. The drain region 105a and the source region 105b are recrystallized from amorphous silicon to polycrystalline silicon. That is, after forming amorphous silicon at low temperature using CVD and recrystallization by laser annealing, it is possible to form polycrystalline silicon at low temperature.

Impurities diffused in the drain region 105a and the source region 105b during the recrystallization process are electrically activated, and grain sizes of the channel layer 103, the drain region 105a, and the source region 105b increase. Thus, carrier mobility is improved.

The grain size is grown laterally because the thickness of the channel layer 103 and the drain region 105a or the source region 105b overlap with the region of the non-overlapping channel layer 103. This is due to the active movement of the surface of the silicon atoms to the thin non-overlapping channel layer 103 in the region where the thick channel layer 103, the drain region 105a and the source region 105b overlap. Grain size grows laterally.

In this way, in the process of recrystallizing the channel layer 103, the drain region 105a and the source region 105b by laser annealing, in the portion where the impurities doped at high concentration in the drain region 105a and the source region 105b overlap. Diffusion is made to the channel layer 103.

That is, impurities doped in the drain region 105a and the source region 105b are activated by the laser beam energy to diffuse into the channel layer 103, and are formed by the step 103a formed on both sides of the channel layer 103. It can be adjusted by stopping the diffusion in the horizontal direction.

The step 103a for preventing the diffusion of impurities in the horizontal direction is formed by etching a predetermined thickness on the upper surface of the channel layer 103 by excessive etching during the etching of the doped amorphous silicon layer 105. As a result, impurities can be prevented from being diffused into the channel region I as shown in FIG. 2E. That is, the length of the channel region (I) and the LDD region (II) can be accurately adjusted by the step 103a of the channel layer 103.

After the laser annealing process is completed, the gate electrode is deposited to have a top gate structure as shown in FIG. 108).

In the thin film transistor obtained through such a process, the channel region I is formed in the channel layer 103 between the drain region 105a and the source region 105b, and the drain region 105a and the source region 105b and the channel are formed. Diffusion is formed in the portion where the layer 103 overlaps to form the LDD region (II).

The LDD region (II) prevents a high electric field applied from the drain to the gate insulating film 107 in the turn off state of the thin film transistor having the top gate structure, thereby preventing the source region 105b from the drain region 105a. It is possible to reduce the leakage current flowing to).

The present invention described above can form a desired LDD region by the step formed on both sides of the channel layer during laser annealing during the manufacturing process of the thin film transistor, thereby improving the reliability of the device.

In addition, by simultaneously performing recrystallization of amorphous silicon, activation of doped impurities, and laser annealing to form LDD regions, the number of processes can be reduced to improve productivity, thereby reducing manufacturing costs.

Claims (7)

A substrate coated with a buffer layer; A channel layer formed in a predetermined region of the buffer layer and having steps formed on both sides to set the channel region and the LDD region; A drain region and a source region formed by overlapping a part of a step formed on both sides of the channel layer; A gate insulating layer stacked to include the exposed surfaces of the channel layer, the drain region, and the source region; And A thin film transistor comprising a gate electrode formed at a predetermined position of the gate insulating film. The method of claim 1, The channel layer is a thin film transistor, characterized in that formed of undoped amorphous silicon. The method of claim 1, And the drain region and the source region are formed of doped amorphous silicon. Forming a buffer layer on the substrate; Forming a channel layer on a predetermined portion of the buffer layer; Forming a drain region and a source region to overlap the channel layer; Etching the channel layer exposed by the drain region and the source region to a predetermined depth to form a step; Forming a gate insulating film on an entire surface including the drain region and the source region; Recrystallizing the channel layer, the drain region, and the source region by a laser heat treatment process; And And forming a gate electrode between the drain region and the source region on the upper surface of the gate insulating film. The method of claim 4, wherein The channel layer is a method of manufacturing a thin film transistor, characterized in that formed of undoped amorphous silicon. The method of claim 4, wherein And the drain region and the source region are formed of doped amorphous silicon. The method of claim 4, wherein And a LDD region is formed at both sides of the channel layer overlapping the drain region and the source region by the laser annealing process.