KR100612987B1 - Manufacturing Method of Thin Film Transistor Liquid Crystal Display - Google Patents

Abstract

A double metal film for the gate electrode is deposited and patterned so that the lower metal pattern has a wider width than the upper gate electrode. A high concentration of n-type ions is implanted into the semiconductor layer using the lower metal pattern as a mask to form a high concentration of source and drain regions outside from a portion corresponding to the edge of the lower metal pattern. Next, the lower metal pattern is patterned using the upper gate electrode as a mask to form the lower gate electrode.

Description

Manufacturing Method Of Liquid Crystal Display

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a liquid crystal display device, and more particularly, to a method for manufacturing a thin film transistor liquid crystal display device having an off-set or lightly doped drain (LDD) structure in a polysilicon layer.

The thin film transistor liquid crystal display is a display device in which a liquid crystal material is injected between a thin film transistor substrate on which a thin film transistor, a data line, a gate line, and the like are formed, and a substrate on which a color filter and a transparent common electrode are formed. Thin film transistors are used as elements for displacing materials.

The semiconductor layer of this thin film transistor is mainly formed using amorphous or polycrystalline silicon.

Amorphous silicon can be deposited at low temperatures and has excellent off current characteristics, but its mobility is less than 1 cm3 / Vsec, and is mainly used to form switching elements in liquid crystal displays. In addition, the driving circuit forms a separate IC (IC) and is mounted around. As the module process increases, the process cost increases.

In contrast, since polycrystalline silicon has a greater mobility of 50 cm3 / Vsec or more than amorphous silicon, the driving circuit can be integrated in the substrate at the same time as the pixel portion is formed, thereby reducing the cost of driving IC materials and related process equipment. Can be. In addition, power consumption can be lowered by five times or more than when using amorphous silicon.

On the other hand, when the thin film transistor is closed, there is a problem such as excessive leakage of current.

As a method for controlling the off current, a lightly doped drain (LDD) region or an undoped offset region may be provided inside the source and drain regions of the thin film transistor.

An object of the present invention is to reduce offset or misalignment of LDD structures.

Another object of the present invention is to stably form an offset or LDD structure under high energy and high concentration doping.

In order to solve this problem, in the method of manufacturing the liquid crystal display according to the exemplary embodiment of the present invention, the first and second metal films for the gate electrode are sequentially stacked, and the first and second metal films are selectively etched to lower the metal pattern and the lower metal pattern. An upper gate electrode having a width narrower than that of the metal pattern is formed. That is, the upper gate electrode and the lower metal pattern are etched to have a hat shape. Thereafter, ions are implanted using the lower metal pattern as a mask to form source and drain regions in the semiconductor layer. Next, the lower metal pattern is etched using the upper gate electrode as a mask to form the lower gate electrode.

Here, lightly doped LDD regions may be formed inside the source and drain regions by implanting low concentration ions into the semiconductor layer using the upper and lower gate electrodes as masks.

The upper gate electrode is formed by wet etching the second metal layer with an etchant having a selectivity with the first metal layer, and forming the lower metal pattern by dry etching is effective for forming the upper and lower patterns in the shape of a hat.

A photoresist film covering the lower metal pattern and the upper gate electrode is coated, and the lower metal pattern is used as a mask for back exposure and development to form a photoresist pattern, which can be used as a mask for forming source and drain regions.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

First, the wiring and the structure of the thin film transistor liquid crystal display device will be described with reference to FIGS. 1 and 2.

FIG. 1 is a wiring diagram of a thin film transistor liquid crystal display, and FIG. 2 is a cross-sectional view of a portion taken along the line II-II ′ of FIG. 1, that is, a thin film transistor.

As shown in FIG. 1 and FIG. 2, the polysilicon pattern 210 is formed on the transparent insulating substrate 1, and the first insulating film 300 is covered thereon. The gate line 400 is formed in the horizontal direction on the first insulating layer 300, and the gate electrode 410 extending from the gate line 400 overlaps a portion of the polycrystalline silicon pattern 210.

In this case, the polycrystalline silicon pattern 210 does not overlap the undoped channel region 211 disposed below the gate electrode 410, and the undoped or lightly doped offset formed outside the channel region 211. Or into heavily doped source and drain regions 212 and 213 located outside the LDD region 214, offset or LDD region 214. In addition, the gate electrode 410 may be formed of two metal layers 421 and 412 or more layers.

The second insulating film 500 covers the gate electrode 410 and the gate line 400, and the data line 600 is formed in the vertical direction on the second insulating film 500. The data line 600 is connected to the source region 212 through the first contact hole C1 formed in the first and second insulating layers 300 and 500.

The third insulating film 700 covers the data line 400, and a transparent pixel electrode 800 is formed on the third insulating film 700. The pixel electrode 800 is connected to the drain region 213 through the second contact hole C2 formed in the first, second, and third insulating layers 300, 500, and 700.

When the open signal is applied to the gate electrode 410, an image signal applied to the data line 600 is transmitted to the source region 212, and the channel region 211 is turned on so that the signal is a pixel. It flows into the drain region 213 connected to the electrode 800. As such, the gate electrode 410, the source and drain regions 212 and 213 and the channel region 211 of the polysilicon pattern 210 become thin film transistors that switch signals.

As mentioned above, the LDD region 214 is offset or lightly doped between the channel region 211 and the source and drain regions 212 and 213 to prevent excessive leakage of current when the thin film transistor is closed. Puts.

Next, a method of forming the offset or LDD region 214 of the thin film transistor will be described below.

3A to 3F are cross-sectional views illustrating a method of forming an offset or LDD region 214 according to a first embodiment of the present invention in a process sequence, in which a gate electrode film is formed in double and a lower electrode pattern is formed than an upper electrode pattern. A wide pattern is used to show the method used for LDD formation.

As shown in FIG. 3A, first, a polysilicon pattern 210 is formed on a substrate 1, and an insulating film 300 is formed thereon.

Next, a lower metal film 410 is deposited using molybdenum-tungsten-nitride (MoWN _x ) or molybdenum tungsten (MoW), and then an upper metal film is deposited by aluminum (Al) and aluminum neodymium (AlNd). A metal film may be further formed between the lower metal film 410 and the upper metal film by molybdenum (Mo) or molybdenum tungsten (MoW).

Next, a photoresist film is coated and patterned on the upper metal film to form a photoresist pattern 2 for forming a gate electrode, and then the upper metal film is wet-etched using an aluminum etchant. In this case, the upper gate electrode 421 is formed to undercut into the photoresist pattern 2, and the lower metal layer 410 having a high selectivity with respect to the aluminum etchant is not etched.

When one or more intermediate metal films (not shown) are formed between molybdenum, molybdenum tungsten, or the like between the upper and lower metal films 410, the upper metal film and the intermediate metal film are etched using an etchant capable of etching simultaneously.

Next, as illustrated in FIG. 3B, the lower metal layer 410 is etched by dry etching to form the lower metal pattern 411. Since the edge of the lower metal pattern 411 is etched in a manner substantially coincident with the edge of the photoresist pattern 2, the lower metal pattern 411 is formed to have a wider width than the upper gate electrode 421.

As in FIG. 3C, the photoresist pattern 2 is removed.

Next, as shown in FIG. 3D, a high concentration of n-type ions are implanted into the polycrystalline silicon layer 210 using the lower metal pattern 411 as a mask. In this step, high concentration source and drain regions 212 and 213 are formed in the polysilicon layer 210 positioned outside the lower metal pattern 411.

As shown in FIG. 3E, the lower metal pattern 411 is etched using the upper gate electrode 421 as a mask to form the lower gate electrode 412 having the same pattern as the upper gate electrode 421.

As a result, the polysilicon pattern 210 has an inner region of the offset region and the offset region, that is, the gate electrode, which is an undoped portion from the point corresponding to the edges of the gate electrodes 412 and 421 to the source and drain regions 212 and 213. An undoped channel region 211 underlying 412 and 421 is formed.

If necessary, as shown in FIG. 3F, low concentration n-type ions may be implanted using the upper and lower gate electrodes 421 and 412 as a mask to lightly dop the offset region to form the LDD region 214.

As such, the source is formed in a self-aligned manner by first forming a hatched double-layer gate electrode pattern having a lower width than the upper layer, and using the lower layer as an ion mask for forming source and drain regions. And a drain region can be formed. In addition, the boundary of the LDD region is formed by a self-aligning method using the lower layer etched with respect to the upper layer and the upper layer as a mask.

Therefore, the problem of misalignment which arises when using a photoresist film as an ion implantation mask can be solved.

However, when ions of high energy and high concentration are implanted, there is a fear that the ions pass through the thickness of the lower metal film and are implanted into an unintended region.

4A to 4J are cross-sectional views illustrating a method of manufacturing an offset or LDD region according to a second embodiment of the present invention according to a process sequence, and ion implantation is performed after covering a gate electrode pattern with a protective film or a photoresist film. It shows how to do it.

The polycrystalline silicon pattern 210 and the first insulating film 300, the lower metal pattern 411 and the upper gate electrode 421 in the same material, shape, and method as in the first embodiment shown in FIGS. 3A to 3C. To form.

Next, as shown in FIG. 4A, a photoresist film 3 covering the lower metal pattern 411 and the upper gate electrode 421 is coated on the entire surface of the first insulating film 300.

As shown in FIG. 4B, the back side of the substrate 1, that is, the polycrystalline silicon pattern 210, the first insulating layer 300, the lower metal pattern 411, the upper gate electrode 421, and the like are not formed. The back exposure is performed from the side.

Next, as shown in FIG. 4C, the photoresist film 3 is patterned to form the mask photoresist pattern 4 in the same pattern as the lower metal pattern 411. Source and drain regions 212 and 213 are formed by implanting a high concentration of n-type ions into the polycrystalline silicon pattern 210 using the pattern 4, the upper gate electrode 421, and the lower gate metal pattern 411 as a mask. .

As shown in FIG. 4E, after the mask pattern 4 is removed, the lower gate metal pattern 411 is etched using the upper gate electrode 421 as a mask to form the lower gate electrode (the same pattern as the upper gate electrode 421). 412 is formed. In this step, the polycrystalline silicon pattern 210 has an undoped offset region and a gate electrode 412, 421, which are portions extending from the point corresponding to the edges of the gate electrodes 412, 421 to the source and drain regions 212, 213. An undoped channel region 211 lying below is formed.

Next, as shown in FIG. 4F, a low concentration of n-type ions is implanted to dope the offset region into the low concentration LDD region 214.

As described above, in the method of forming the LDD region according to the second embodiment, by forming a mask photoresist pattern having the same pattern as the lower metal pattern on the lower metal pattern and the upper gate electrode serving as an ion implantation mask, high energy and high concentration Even when ions in a state are implanted, the ions can be sufficiently masked.

As described above, in the method of manufacturing the thin film transistor liquid crystal display according to the present invention, misalignment of the LDD region can be reduced, and ion implantation in a high energy and high concentration state is possible.

1 is a wiring diagram of a thin film transistor liquid crystal display device;

FIG. 2 is a cross-sectional view taken along line II-II 'of FIG. 1;

3A to 3F are cross-sectional views illustrating a method of forming an off-set or lightly doped drain according to a first embodiment of the present invention in a process sequence;

4A through 4F are cross-sectional views illustrating a method of forming an offset or LDD structure according to a second embodiment of the present invention in a process sequence.

Claims (11)

Forming a semiconductor pattern on the substrate, Forming an insulating film covering the semiconductor pattern; Depositing first and second metal films on the insulating film in order; Applying a first photoresist film on the second metal film; Exposing and developing the first photoresist film to form a first photoresist pattern; Wet etching the second metal layer using the first photoresist pattern as a mask to form an upper gate electrode undercut with respect to the first photoresist pattern; Dry etching the first metal layer using the first photoresist pattern as a mask to form a lower metal pattern; Removing the first photoresist pattern; Forming a source and a drain region by doping a high concentration of ions into the semiconductor pattern using the lower metal pattern as an ion doping mask; Etching the lower metal pattern using the upper gate electrode as a mask to form a lower gate electrode Method of manufacturing a liquid crystal display comprising a. In claim 1, And implanting low concentration ions into the mask using the upper and lower gate electrodes to form an LDD region inside the source and drain regions. The method of claim 1 or 2, Prior to forming the source and drain regions, applying a second photoresist film, performing a back exposure using the lower metal pattern as an exposure mask, and developing the second photoresist film to form a second photoresist pattern. A method of manufacturing a liquid crystal display device further comprising the step. The method of claim 1 or 2, And the first and second metal films are formed of molybdenum alloy and aluminum alloy, respectively. In claim 4, And forming the upper gate electrode by etching the second metal layer using an etchant having an etching selectivity with respect to the first metal layer. In claim 4, The second metal film is selectively etched using an aluminum etchant. Forming a polycrystalline silicon pattern on the insulating substrate, Forming a gate insulating film on the polycrystalline silicon pattern, Sequentially stacking first and second metal films on the gate insulating film; Selectively etching the first and second metal layers to form a lower metal pattern and an upper gate electrode having a narrower width than the lower metal pattern; Implanting ions using the lower metal pattern as a mask to form source and drain regions; Etching the lower metal pattern using the upper gate electrode as a mask to form a lower gate electrode Method of manufacturing a liquid crystal display comprising a. In claim 7, And forming a LDD region inside the source and drain regions by implanting low concentrations of ions using the upper and lower gate electrodes as masks after the forming of the lower gate electrodes. In claim 7 or 8, The upper gate electrode may be formed by wet or dry etching the second metal layer with an etchant having a selectivity with the first metal layer. In claim 9, The lower metal pattern may be formed by wet or dry etching. In claim 8, After forming the lower metal pattern and the upper gate electrode, applying a photoresist film covering the lower metal pattern and the upper gate electrode, back exposing the lower metal pattern as a mask, and developing the photoresist film. A method of manufacturing a liquid crystal display further comprising the step of forming a photoresist pattern.