WO2017206215A1 - Manufacturing method for low-temperature polycrystalline silicon thin-film transistor - Google Patents

Manufacturing method for low-temperature polycrystalline silicon thin-film transistor Download PDF

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WO2017206215A1
WO2017206215A1 PCT/CN2016/086723 CN2016086723W WO2017206215A1 WO 2017206215 A1 WO2017206215 A1 WO 2017206215A1 CN 2016086723 W CN2016086723 W CN 2016086723W WO 2017206215 A1 WO2017206215 A1 WO 2017206215A1
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layer
silicon nitride
temperature polysilicon
film transistor
silicon
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French (fr)
Chinese (zh)
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吴元均
连水池
周星宇
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深圳市华星光电技术有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating a low temperature polysilicon thin film transistor.
  • the flat display device has many advantages such as thin body, power saving, no radiation, and has been widely used.
  • the existing flat display devices mainly include a liquid crystal display (LCD) and an organic light emitting display (OLED).
  • a Thin Film Transistor In a flat display device, a Thin Film Transistor (TFT) is generally used as a switching element to control a pixel or as a driving element to drive a pixel. Thin film transistors are generally classified into amorphous silicon (a-Si) and polycrystalline silicon (poly-Si) depending on their silicon film properties.
  • a-Si amorphous silicon
  • poly-Si polycrystalline silicon
  • LTPS Low Temperature Poly-Silicon
  • Low-temperature polysilicon film has a high carrier mobility (10 to 300 cm 2 /Vs) due to its atomic arrangement and can be applied to electronic components such as thin film transistors, so that the thin film transistor has a higher driving current, and thus the thin film transistor
  • the LTPS film is widely used as the material of the active layer of one of the core structures of the thin film transistor in the fabrication process.
  • a conventional low temperature polysilicon thin film transistor generally includes: an active layer, a gate insulating layer disposed on the active layer, a gate electrode disposed on a gate insulating layer above the active layer, and a drain and a source contacted at both ends of the active layer; wherein the gate insulating layer generally includes a silicon oxide layer disposed on the active layer, and a silicon nitride layer disposed on the silicon oxide layer, Contacting the gate with a silicon nitride layer to resist ion diffusion in the gate, however, the silicon nitride layer is not a good insulator for long-term electrical operation, during operation, Whether it is an N-type thin film transistor or a P-type thin film transistor, the gate insulating layer is prone to carrier trapping, which reduces the reliability of the gate insulating layer and affects the stability of the low-temperature polysilicon thin film transistor. .
  • An object of the present invention is to provide a method for fabricating a low temperature polysilicon thin film transistor capable of The gate insulating layer capable of simultaneously resisting ion diffusion and suppressing carrier injection is formed without increasing the number of process masks, thereby improving the reliability of the gate insulating layer and the stability of the low-temperature polysilicon thin film transistor.
  • the present invention provides a method for fabricating a low temperature polysilicon thin film transistor, comprising the following steps:
  • Step 1 Providing a substrate, depositing a low temperature polysilicon layer on the substrate, and performing ion doping and patterning on the low temperature polysilicon layer to form an active layer;
  • Step 2 depositing a silicon oxide layer on the active layer and the substrate;
  • Step 3 depositing a silicon nitride layer on the silicon oxide layer and oxidizing the silicon nitride layer with an oxygen-containing gas to oxidize the entire silicon nitride layer or a portion of the upper silicon nitride layer a silicon oxynitride layer, such that the silicon oxynitride layer and the silicon oxide layer or the silicon oxynitride layer, the silicon oxide layer and the remaining silicon nitride layer together form a gate insulating layer;
  • Step 4 forming a gate on the silicon oxynitride layer above the active layer;
  • Step 5 Deposit an interlayer insulating layer on the gate electrode and the silicon oxynitride layer, and form a source and a drain on the interlayer insulating layer in contact with both ends of the active layer.
  • the silicon nitride layer is subjected to rapid thermal annealing while introducing an oxygen-containing gas to completely oxidize the silicon nitride layer into a silicon oxynitride layer.
  • a silicon nitride layer deposition is performed for a while, and then an oxygen-containing gas is introduced to continue deposition, and a part of the silicon nitride layer of the upper layer is oxidized to a silicon oxynitride layer.
  • the oxygen-containing gas in the step 3 is oxygen, moisture, or nitrous oxide.
  • the gate material is molybdenum.
  • the material of the source and the drain is two layers of titanium sandwiched with aluminum.
  • the material of the interlayer insulating layer is silicon nitride.
  • the ions doped in the low temperature polysilicon layer in the step 1 are P-type ions or N-type ions.
  • the source and the drain are in contact with both ends of the active layer through two via holes penetrating the interlayer insulating layer and the gate insulating layer.
  • the invention also provides a method for fabricating a low temperature polysilicon thin film transistor, comprising the following steps:
  • Step 1 Providing a substrate, depositing a low temperature polysilicon layer on the substrate, and performing ion doping and patterning on the low temperature polysilicon layer to form an active layer;
  • Step 2 depositing a silicon oxide layer on the active layer and the substrate;
  • Step 3 depositing a silicon nitride layer on the silicon oxide layer and oxidizing the silicon nitride layer with an oxygen-containing gas to oxidize the entire silicon nitride layer or a portion of the upper silicon nitride layer a silicon oxynitride layer, such that the silicon oxynitride layer and the silicon oxide layer or the silicon oxynitride layer, the silicon oxide layer and the remaining silicon nitride layer together form a gate insulating layer;
  • Step 4 forming a gate on the silicon oxynitride layer above the active layer;
  • Step 5 depositing an interlayer insulating layer on the gate electrode and the silicon oxynitride layer, and forming a source and a drain on the interlayer insulating layer in contact with both ends of the active layer;
  • the gate material is molybdenum
  • the material of the source and the drain is two layers of titanium sandwiched with aluminum;
  • the material of the interlayer insulating layer is a combination of one or more of silicon nitride and silicon oxide.
  • the present invention provides a method for fabricating a low temperature polysilicon thin film transistor by oxidizing a silicon nitride layer in contact with a gate electrode to a silicon oxynitride layer, and contacting the gate electrode with silicon oxynitride, the nitrogen oxide
  • the silicon layer not only resists ion diffusion, but also has high electrical stability, can effectively suppress carrier injection of the gate insulating layer, improve the reliability of the gate insulating layer, and low-temperature polysilicon thin film transistor.
  • the stability, the production method is simple, and there is no need to increase the number of process masks.
  • step 1 is a schematic diagram of step 1 of a method for fabricating a low temperature polysilicon thin film transistor of the present invention
  • step 2 is a schematic diagram of step 2 of a method for fabricating a low temperature polysilicon thin film transistor of the present invention
  • step 3 is a schematic diagram of step 3 of the first embodiment of the method for fabricating a low temperature polysilicon thin film transistor of the present invention
  • step 3 is a schematic diagram of step 3 of a second embodiment of a method for fabricating a low temperature polysilicon thin film transistor of the present invention
  • step 4 is a schematic diagram of step 4 of the first embodiment of the method for fabricating a low temperature polysilicon thin film transistor of the present invention
  • step 4 is a schematic diagram of step 4 of a second embodiment of a method for fabricating a low temperature polysilicon thin film transistor of the present invention
  • step 5 is a schematic diagram of step 5 of the first embodiment of the method for fabricating a low temperature polysilicon thin film transistor of the present invention.
  • FIG. 9 is a flow chart of a method of fabricating a low temperature polysilicon thin film transistor of the present invention.
  • the present invention provides a method for fabricating a low temperature polysilicon thin film transistor, comprising the following steps:
  • Step 1 Referring to FIG. 1, a substrate 1 is provided. A low temperature polysilicon layer is deposited on the substrate 1, and the low temperature polysilicon layer is ion doped and patterned to form an active layer 2.
  • the substrate 1 is a transparent substrate, preferably a glass substrate.
  • the step 1 includes first depositing an amorphous silicon layer on the substrate 1 and performing crystallization by excimer laser crystallization or solid phase crystallization. A low temperature polysilicon layer is formed, and then ion doping and patterning are performed to form the active layer 2.
  • the thickness of the active layer 2 is
  • the ion-doped ions are P-type ions (such as boron ions) or N-type ions (such as phosphorus ions).
  • Step 2 see Figure 2, a deposition of silicon oxide (SiO X) on the layer 31 2, the active layer and the substrate 1.
  • the thickness of the silicon oxide layer 31 is the thickness of the silicon oxide layer 31 .
  • Step 3 depositing a silicon nitride (SiN x ) layer 32 on the silicon oxide layer 31 and oxidizing the silicon nitride layer 32 by using an oxygen-containing gas, and the entire silicon nitride layer 32 or the upper layer A portion of the silicon nitride layer 32 is oxidized to form a silicon oxynitride (SiON) layer 33 such that the silicon oxynitride layer 33 and the silicon oxide layer 31 or the silicon oxynitride layer 33, the silicon oxide layer 31 and the remaining nitrogen
  • the silicon layer 32 collectively forms a gate insulating layer 3;
  • the oxygen-containing gas in the step 3 is oxygen (O 2 ), moisture (H 2 O), or nitrous oxide (N 2 O).
  • the silicon nitride layer 32 is rapidly thermally annealed (Rapid Thermal Annealing).
  • RTA Rapid Thermal Annealing
  • the silicon nitride layer 32 is rapidly thermally annealed (Rapid Thermal Annealing).
  • RTA simultaneously oxidizing the silicon nitride layer 32 to the silicon oxynitride layer 33 by introducing an oxygen-containing gas, that is, the gate insulating layer 3 is formed including the silicon oxide layer 31 and the nitrogen layer stacked from the bottom to the top.
  • the thickness of the silicon oxynitride layer 33 is
  • the silicon nitride layer 32 is deposited for a period of time in the step 3, and then an oxygen-containing gas is introduced to continue deposition, and a part of the upper layer is nitrogen.
  • the silicon layer 32 is oxidized to the silicon oxynitride layer 33, that is, the gate insulating layer 3 is formed including a silicon oxide layer 31 stacked from the bottom up, a remaining unoxidized silicon nitride layer 32, and oxynitride. Silicon layer 33.
  • the total thickness of the remaining unoxidized silicon nitride layer 32 and silicon oxynitride layer 33 is
  • the silicon oxynitride layer 33 has both the silicon nitride layer 32 resisting ion diffusion and the high electrical stability of the silicon oxide layer 31, and the silicon oxynitride layer 33 is used instead of the silicon nitride layer 32 in contact with the gate. It can not only resist ion diffusion, but also effectively suppress carrier injection of the gate insulating layer and improve the reliability of the gate insulating layer 3. The entire process does not need to change the process of the existing low-temperature polysilicon thin film transistor, and no additional need is added.
  • the mask or process can be realized only by introducing an oxygen-containing gas during the deposition of the silicon nitride layer 31 or by rapid thermal annealing in an oxygen-containing atmosphere after the deposition of the silicon nitride layer 31.
  • Step 4 Referring to FIG. 5 or FIG. 6, a gate electrode 4 is formed on the silicon oxynitride layer 33 above the active layer 2.
  • the material of the gate 4 is molybdenum (Mo), and the thickness is Specifically, the step 4 first deposits a metal layer on the silicon oxynitride layer 33, and then patterns the metal layer to form the gate electrode 4.
  • Mo molybdenum
  • Step 5 referring to FIG. 7 or FIG. 8, an interlayer insulating layer 5 is deposited on the gate electrode 4 and the silicon oxynitride layer 33, and the active layer is formed on the interlayer insulating layer 5.
  • the source 61 and the drain 62 are in contact with both ends of 2.
  • the material of the interlayer insulating layer 5 is a combination of one or more of silicon nitride and silicon oxide.
  • the interlayer insulating layer 5 includes a layer stacked from bottom to top. Silicon oxide, and a layer of silicon nitride, wherein the thickness of the silicon oxide is The thickness of silicon nitride is The material of the source 61 and the drain 62 is two layers of titanium sandwiched with aluminum, and the thickness of the first layer of titanium is The thickness of the second layer of titanium is The thickness of aluminum is Specifically, the step 5 includes first depositing an interlayer insulating layer 5 on the gate electrode 4 and the silicon oxynitride layer 33, and then patterning the interlayer insulating layer 5 to form through the interlayer insulating layer.
  • Two via holes of the gate insulating layer 3 the two via holes respectively exposing both ends of the active layer 2, and then depositing a metal layer on the interlayer insulating layer 5 and patterning, forming through The two vias are respectively connected to the source 61 and the drain 62 of both ends of the active layer 2.
  • the present invention provides a method for fabricating a low temperature polysilicon thin film transistor by oxidizing a silicon nitride layer in contact with a gate electrode to a silicon oxynitride layer, and contacting silicon oxide with a gate electrode, the silicon oxynitride.
  • the layer not only resists ion diffusion, but also has high electrical stability, can effectively suppress carrier injection of the gate insulating layer, improve the reliability of the gate insulating layer, and improve the reliability of the low-temperature polysilicon thin film transistor. Stability, simple production method, no need to increase the number of process masks.

Abstract

The present invention provides a manufacturing method for a low-temperature polycrystalline silicon thin-film transistor. In the method, a silicon nitride layer in contact with a gate electrode is oxidized into a silicon oxynitride layer to use the silicon oxynitride to be in contact with the gate electrode. Compared with the silicon nitride layer, the silicon oxynitride layer not only can resist ion diffusion, but also has high electrical stability and can effectively suppress carrier injection at a gate insulating layer, so that the reliability of the gate insulating layer and the stability of the low-temperature polycrystalline silicon thin-film transistor can be enhanced. The manufacturing method is simple, and the number of photomasks in the manufacturing process does not need to be increased.

Description

低温多晶硅薄膜晶体管的制作方法Low-temperature polysilicon thin film transistor manufacturing method 技术领域Technical field
本发明涉及显示技术领域，尤其涉及一种低温多晶硅薄膜晶体管的制作方法。The present invention relates to the field of display technologies, and in particular, to a method for fabricating a low temperature polysilicon thin film transistor.
背景技术Background technique
平面显示器件具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有的平面显示器件主要包括液晶显示器件(Liquid Crystal Display，LCD)及有机发光二极管显示器件(Organic Light Emitting Display，OLED)。The flat display device has many advantages such as thin body, power saving, no radiation, and has been widely used. The existing flat display devices mainly include a liquid crystal display (LCD) and an organic light emitting display (OLED).
在平面显示器件中，薄膜晶体管(Thin Film Transistor，TFT)一般是用作开关元件来控制像素的作业，或是用作驱动元件来驱动像素。薄膜晶体管依其硅薄膜性质通常可分成非晶硅(a-Si)与多晶硅(poly-Si)两种。In a flat display device, a Thin Film Transistor (TFT) is generally used as a switching element to control a pixel or as a driving element to drive a pixel. Thin film transistors are generally classified into amorphous silicon (a-Si) and polycrystalline silicon (poly-Si) depending on their silicon film properties.
由于非晶硅本身自有的缺陷问题，如缺陷太多导致的开态电流低、迁移率低、稳定性差，使它在应用中受到限制，为了弥补非晶硅本身的缺陷，扩大其在相关领域的应用，低温多晶硅(Low Temperature Poly-Silicon，LTPS)技术应运而生。Due to the inherent defects of amorphous silicon, such as low on-state current, low mobility, and poor stability caused by too many defects, it is limited in application. In order to compensate for the defects of amorphous silicon itself, it is expanded. The application of the field, Low Temperature Poly-Silicon (LTPS) technology came into being.
低温多晶硅薄膜由于其原子排列规则，载流子迁移率高(10～300cm2/Vs)，应用于薄膜晶体管等电子元器件时，可使薄膜晶体管具有更高的驱动电流，因此在薄膜晶体管的制作工艺中广泛采用LTPS薄膜作为薄膜晶体管的核心结构之一的有源层的材料。Low-temperature polysilicon film has a high carrier mobility (10 to 300 cm 2 /Vs) due to its atomic arrangement and can be applied to electronic components such as thin film transistors, so that the thin film transistor has a higher driving current, and thus the thin film transistor The LTPS film is widely used as the material of the active layer of one of the core structures of the thin film transistor in the fabrication process.
现有的低温多晶硅薄膜晶体管通常包括：有源层、设于所述有源层上的栅极绝缘层、设于所述有源层上方的栅极绝缘层上的栅极、以及与所述有源层两端接触的漏极、与源极；其中，栅极绝缘层通常包括设于所述有源层上的氧化硅层、以及设于所述氧化硅层上的氮化硅层，利用氮化硅层与所述栅极接触以抵挡栅极中的离子扩散(Mobile ion)，然而氮化硅层对于长时间的电性操作而言，并不是一个良好的绝缘体，操作过程中，无论是N型薄膜晶体管还是P型薄膜晶体管，栅极绝缘层都很容易产生载流子注入(Carry trapping)的问题，进而降低了栅极绝缘层的可靠性，影响低温多晶硅薄膜晶体管的稳定性。A conventional low temperature polysilicon thin film transistor generally includes: an active layer, a gate insulating layer disposed on the active layer, a gate electrode disposed on a gate insulating layer above the active layer, and a drain and a source contacted at both ends of the active layer; wherein the gate insulating layer generally includes a silicon oxide layer disposed on the active layer, and a silicon nitride layer disposed on the silicon oxide layer, Contacting the gate with a silicon nitride layer to resist ion diffusion in the gate, however, the silicon nitride layer is not a good insulator for long-term electrical operation, during operation, Whether it is an N-type thin film transistor or a P-type thin film transistor, the gate insulating layer is prone to carrier trapping, which reduces the reliability of the gate insulating layer and affects the stability of the low-temperature polysilicon thin film transistor. .
发明内容Summary of the invention
本发明的目的在于提供一种低温多晶硅薄膜晶体管的制作方法，能够 在不增加制程光罩数的前提下制作能够同时抵挡离子扩散和抑制载流子注入的栅极绝缘层，提升栅极绝缘层的可靠性和低温多晶硅薄膜晶体管的稳定性。An object of the present invention is to provide a method for fabricating a low temperature polysilicon thin film transistor capable of The gate insulating layer capable of simultaneously resisting ion diffusion and suppressing carrier injection is formed without increasing the number of process masks, thereby improving the reliability of the gate insulating layer and the stability of the low-temperature polysilicon thin film transistor.
为实现上述目的，本发明提供了一种低温多晶硅薄膜晶体管的制作方法，包括如下步骤：To achieve the above object, the present invention provides a method for fabricating a low temperature polysilicon thin film transistor, comprising the following steps:
步骤1、提供一基板，在所述基板上沉积一低温多晶硅层，并对所述低温多晶硅层进行离子掺杂和图案化处理，形成有源层； Step 1. Providing a substrate, depositing a low temperature polysilicon layer on the substrate, and performing ion doping and patterning on the low temperature polysilicon layer to form an active layer;
步骤2、在所述有源层、及基板上沉积一氧化硅层； Step 2, depositing a silicon oxide layer on the active layer and the substrate;
步骤3、在所述氧化硅层上沉积一氮化硅层并利用含氧气体对所述氮化硅层进行氧化处理，将所述全部氮化硅层或者上层的部分氮化硅层氧化形成一氮氧化硅层，从而所述氮氧化硅层与氧化硅层或所述氮氧化硅层、氧化硅层与剩下的氮化硅层共同形成栅极绝缘层； Step 3, depositing a silicon nitride layer on the silicon oxide layer and oxidizing the silicon nitride layer with an oxygen-containing gas to oxidize the entire silicon nitride layer or a portion of the upper silicon nitride layer a silicon oxynitride layer, such that the silicon oxynitride layer and the silicon oxide layer or the silicon oxynitride layer, the silicon oxide layer and the remaining silicon nitride layer together form a gate insulating layer;
步骤4、在所述有源层上方的氮氧化硅层上形成栅极； Step 4, forming a gate on the silicon oxynitride layer above the active layer;
步骤5、在所述栅极、以及氮氧化硅层上沉积一层间绝缘层，并在所述层间绝缘层上形成与所述有源层的两端接触的源极与漏极。 Step 5. Deposit an interlayer insulating layer on the gate electrode and the silicon oxynitride layer, and form a source and a drain on the interlayer insulating layer in contact with both ends of the active layer.
所述步骤3中在氮化硅层沉积完成后，对所述氮化硅层进行快速热退火同时通入含氧气体将所述氮化硅层全部氧化成氮氧化硅层。After the deposition of the silicon nitride layer is completed in the step 3, the silicon nitride layer is subjected to rapid thermal annealing while introducing an oxygen-containing gas to completely oxidize the silicon nitride layer into a silicon oxynitride layer.
所述步骤3中先进行一段时间的氮化硅层沉积，然后通入含氧气体继续沉积，将上层的部分氮化硅层氧化成氮氧化硅层。In the step 3, a silicon nitride layer deposition is performed for a while, and then an oxygen-containing gas is introduced to continue deposition, and a part of the silicon nitride layer of the upper layer is oxidized to a silicon oxynitride layer.
所述步骤3中的含氧气体为氧气、水气、或一氧化二氮。The oxygen-containing gas in the step 3 is oxygen, moisture, or nitrous oxide.
所述栅极材料为钼。The gate material is molybdenum.
所述源极与漏极的材料为两层钛夹一层铝。The material of the source and the drain is two layers of titanium sandwiched with aluminum.
所述层间绝缘层的材料为氮化硅。The material of the interlayer insulating layer is silicon nitride.
所述步骤1中在低温多晶硅层中掺杂的离子为P型离子或N型离子。The ions doped in the low temperature polysilicon layer in the step 1 are P-type ions or N-type ions.
所述源极与漏极通过贯穿所述层间绝缘层和栅极绝缘层的两过孔与所述有源层的两端接触。The source and the drain are in contact with both ends of the active layer through two via holes penetrating the interlayer insulating layer and the gate insulating layer.
本发明还提供一种低温多晶硅薄膜晶体管的制作方法，包括如下步骤：The invention also provides a method for fabricating a low temperature polysilicon thin film transistor, comprising the following steps:
步骤1、提供一基板，在所述基板上沉积一低温多晶硅层，并对所述低温多晶硅层进行离子掺杂和图案化处理，形成有源层； Step 1. Providing a substrate, depositing a low temperature polysilicon layer on the substrate, and performing ion doping and patterning on the low temperature polysilicon layer to form an active layer;
步骤2、在所述有源层、及基板上沉积一氧化硅层； Step 2, depositing a silicon oxide layer on the active layer and the substrate;
步骤3、在所述氧化硅层上沉积一氮化硅层并利用含氧气体对所述氮化硅层进行氧化处理，将所述全部氮化硅层或者上层的部分氮化硅层氧化形成一氮氧化硅层，从而所述氮氧化硅层与氧化硅层或所述氮氧化硅层、氧化硅层与剩下的氮化硅层共同形成栅极绝缘层； Step 3, depositing a silicon nitride layer on the silicon oxide layer and oxidizing the silicon nitride layer with an oxygen-containing gas to oxidize the entire silicon nitride layer or a portion of the upper silicon nitride layer a silicon oxynitride layer, such that the silicon oxynitride layer and the silicon oxide layer or the silicon oxynitride layer, the silicon oxide layer and the remaining silicon nitride layer together form a gate insulating layer;
步骤4、在所述有源层上方的氮氧化硅层上形成栅极； Step 4, forming a gate on the silicon oxynitride layer above the active layer;
步骤5、在所述栅极、以及氮氧化硅层上沉积一层间绝缘层，并在所述层间绝缘层上形成与所述有源层的两端接触的源极与漏极； Step 5, depositing an interlayer insulating layer on the gate electrode and the silicon oxynitride layer, and forming a source and a drain on the interlayer insulating layer in contact with both ends of the active layer;
其中，所述栅极材料为钼；Wherein the gate material is molybdenum;
其中，所述源极与漏极的材料为两层钛夹一层铝；Wherein, the material of the source and the drain is two layers of titanium sandwiched with aluminum;
其中，所述层间绝缘层的材料为氮化硅、及氧化硅中的一种或多种的组合。The material of the interlayer insulating layer is a combination of one or more of silicon nitride and silicon oxide.
本发明的有益效果：本发明提供的一种低温多晶硅薄膜晶体管的制作方法，通过将与栅极接触的氮化硅层氧化成氮氧化硅层，采用氮氧化硅与栅极接触，该氮氧化硅层相比于氮化硅层，不仅可以抵挡离子扩散，还具有高电性稳定度，能够有效抑制栅极绝缘层的载流子注入，提升栅极绝缘层的可靠性和低温多晶硅薄膜晶体管的稳定性，制作方法简单，不需要增加制程光罩数。Advantageous Effects of Invention: The present invention provides a method for fabricating a low temperature polysilicon thin film transistor by oxidizing a silicon nitride layer in contact with a gate electrode to a silicon oxynitride layer, and contacting the gate electrode with silicon oxynitride, the nitrogen oxide Compared with the silicon nitride layer, the silicon layer not only resists ion diffusion, but also has high electrical stability, can effectively suppress carrier injection of the gate insulating layer, improve the reliability of the gate insulating layer, and low-temperature polysilicon thin film transistor. The stability, the production method is simple, and there is no need to increase the number of process masks.
附图说明DRAWINGS
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。The detailed description of the present invention and the accompanying drawings are to be understood,
附图中，In the drawings,
图1为本发明的低温多晶硅薄膜晶体管的制作方法的步骤1的示意图；1 is a schematic diagram of step 1 of a method for fabricating a low temperature polysilicon thin film transistor of the present invention;
图2为本发明的低温多晶硅薄膜晶体管的制作方法的步骤2的示意图；2 is a schematic diagram of step 2 of a method for fabricating a low temperature polysilicon thin film transistor of the present invention;
图3为本发明的低温多晶硅薄膜晶体管的制作方法的第一实施例的步骤3的示意图；3 is a schematic diagram of step 3 of the first embodiment of the method for fabricating a low temperature polysilicon thin film transistor of the present invention;
图4为本发明的低温多晶硅薄膜晶体管的制作方法的第二实施例的步骤3的示意图；4 is a schematic diagram of step 3 of a second embodiment of a method for fabricating a low temperature polysilicon thin film transistor of the present invention;
图5为本发明的低温多晶硅薄膜晶体管的制作方法的第一实施例的步骤4的示意图；5 is a schematic diagram of step 4 of the first embodiment of the method for fabricating a low temperature polysilicon thin film transistor of the present invention;
图6为本发明的低温多晶硅薄膜晶体管的制作方法的第二实施例的步骤4的示意图；6 is a schematic diagram of step 4 of a second embodiment of a method for fabricating a low temperature polysilicon thin film transistor of the present invention;
图7为本发明的低温多晶硅薄膜晶体管的制作方法的第一实施例的步骤5的示意图；7 is a schematic diagram of step 5 of the first embodiment of the method for fabricating a low temperature polysilicon thin film transistor of the present invention;
图8为本发明的低温多晶硅薄膜晶体管的制作方法的第二实施例的步骤5的示意图；8 is a schematic diagram of step 5 of a second embodiment of a method for fabricating a low temperature polysilicon thin film transistor of the present invention;
图9为本发明的低温多晶硅薄膜晶体管的制作方法的流程图。 9 is a flow chart of a method of fabricating a low temperature polysilicon thin film transistor of the present invention.
具体实施方式detailed description
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。In order to further clarify the technical means and effects of the present invention, the following detailed description will be made in conjunction with the preferred embodiments of the invention and the accompanying drawings.
请参阅图9，本发明提供一种低温多晶硅薄膜晶体管的制作方法，包括如下步骤：Referring to FIG. 9, the present invention provides a method for fabricating a low temperature polysilicon thin film transistor, comprising the following steps:
步骤1、请参阅图1，提供一基板1，在所述基板1上沉积一低温多晶硅层，并对所述低温多晶硅层进行离子掺杂和图案化处理，形成有源层2。 Step 1. Referring to FIG. 1, a substrate 1 is provided. A low temperature polysilicon layer is deposited on the substrate 1, and the low temperature polysilicon layer is ion doped and patterned to form an active layer 2.
具体地，所述基板1为透明基板，优选玻璃基板，所述步骤1包括：首先在所述基板1上沉积一非晶硅层，采用准分子激光晶化或固相结晶化的方式进行结晶形成低温多晶硅层，然后进行离子掺杂和图案化处理，形成有源层2。优选地，所述有源层2的厚度为
Figure PCTCN2016086723-appb-000001
Specifically, the substrate 1 is a transparent substrate, preferably a glass substrate. The step 1 includes first depositing an amorphous silicon layer on the substrate 1 and performing crystallization by excimer laser crystallization or solid phase crystallization. A low temperature polysilicon layer is formed, and then ion doping and patterning are performed to form the active layer 2. Preferably, the thickness of the active layer 2 is
Figure PCTCN2016086723-appb-000001
具体地，所述离子掺杂的离子为P型离子(如硼离子)，或N型离子(如磷离子)。Specifically, the ion-doped ions are P-type ions (such as boron ions) or N-type ions (such as phosphorus ions).
步骤2、请参阅图2，在所述有源层2、及基板1上沉积一氧化硅(SiOX)层31。 Step 2, see Figure 2, a deposition of silicon oxide (SiO X) on the layer 31 2, the active layer and the substrate 1.
优选地，所述氧化硅层31的厚度为
Figure PCTCN2016086723-appb-000002
Preferably, the thickness of the silicon oxide layer 31 is
Figure PCTCN2016086723-appb-000002
步骤3、在所述氧化硅层31上沉积一氮化硅(SiNX)层32并利用含氧气体对所述氮化硅层32进行氧化处理，将所述全部氮化硅层32或者上层的部分氮化硅层32氧化形成一氮氧化硅(SiON)层33，从而所述氮氧化硅层33与氧化硅层31或所述氮氧化硅层33、氧化硅层31与剩下的氮化硅层32共同形成栅极绝缘层3；。 Step 3, depositing a silicon nitride (SiN x ) layer 32 on the silicon oxide layer 31 and oxidizing the silicon nitride layer 32 by using an oxygen-containing gas, and the entire silicon nitride layer 32 or the upper layer A portion of the silicon nitride layer 32 is oxidized to form a silicon oxynitride (SiON) layer 33 such that the silicon oxynitride layer 33 and the silicon oxide layer 31 or the silicon oxynitride layer 33, the silicon oxide layer 31 and the remaining nitrogen The silicon layer 32 collectively forms a gate insulating layer 3;
优选地，所述步骤3中的含氧气体为氧气(O2)、水气(H2O)、或一氧化二氮(N2O)。Preferably, the oxygen-containing gas in the step 3 is oxygen (O 2 ), moisture (H 2 O), or nitrous oxide (N 2 O).
可选地，请参阅图3，在本发明的第一实施例中，所述步骤3中在氮化硅层32沉积完成后，对所述氮化硅层32进行快速热退火(Rapid Thermal Annealing，RTA)同时通入含氧气体将所述氮化硅层32全部氧化成氮氧化硅层33，也即形成的栅极绝缘层3包括自下而上层叠设置的氧化硅层31、及氮氧化硅层33。优选地，氮氧化硅层33的厚度为
Figure PCTCN2016086723-appb-000003
Optionally, referring to FIG. 3, in the first embodiment of the present invention, after the deposition of the silicon nitride layer 32 is completed in the step 3, the silicon nitride layer 32 is rapidly thermally annealed (Rapid Thermal Annealing). , RTA) simultaneously oxidizing the silicon nitride layer 32 to the silicon oxynitride layer 33 by introducing an oxygen-containing gas, that is, the gate insulating layer 3 is formed including the silicon oxide layer 31 and the nitrogen layer stacked from the bottom to the top. Silicon oxide layer 33. Preferably, the thickness of the silicon oxynitride layer 33 is
Figure PCTCN2016086723-appb-000003
可选地，请参阅图4，在本发明的第二实施例中，所述步骤3中先进行一段时间的氮化硅层32沉积，然后通入含氧气体继续沉积，将上层的部分氮化硅层32氧化成氮氧化硅层33，也即形成的栅极绝缘层3包括自下而上层叠设置的氧化硅层31、剩下的未被氧化的氮化硅层32、及氮氧化硅层33。优选地，所述剩下的未被氧化的氮化硅层32及氮氧化硅层33的总厚度为
Figure PCTCN2016086723-appb-000004
Optionally, referring to FIG. 4, in the second embodiment of the present invention, the silicon nitride layer 32 is deposited for a period of time in the step 3, and then an oxygen-containing gas is introduced to continue deposition, and a part of the upper layer is nitrogen. The silicon layer 32 is oxidized to the silicon oxynitride layer 33, that is, the gate insulating layer 3 is formed including a silicon oxide layer 31 stacked from the bottom up, a remaining unoxidized silicon nitride layer 32, and oxynitride. Silicon layer 33. Preferably, the total thickness of the remaining unoxidized silicon nitride layer 32 and silicon oxynitride layer 33 is
Figure PCTCN2016086723-appb-000004
需要说明的是，氮氧化硅层33同时具备氮化硅层32抵挡离子扩散的特性和氧化硅层31的高电性稳定度，采用氮氧化硅层33取代氮化硅层32与栅极接触，不仅可以抵挡离子扩散，还能够有效抑制栅极绝缘层的载流子注入，提升栅极绝缘层3的可靠性，整个过程不需要改变现有的低温多晶硅薄膜晶体管的制程，不需要增加额外的光罩或工序，只需要在沉积氮化硅层31时通入含氧气体，或是在氮化硅层31沉积结束后在含氧环境中进行快速热退火即可实现。It should be noted that the silicon oxynitride layer 33 has both the silicon nitride layer 32 resisting ion diffusion and the high electrical stability of the silicon oxide layer 31, and the silicon oxynitride layer 33 is used instead of the silicon nitride layer 32 in contact with the gate. It can not only resist ion diffusion, but also effectively suppress carrier injection of the gate insulating layer and improve the reliability of the gate insulating layer 3. The entire process does not need to change the process of the existing low-temperature polysilicon thin film transistor, and no additional need is added. The mask or process can be realized only by introducing an oxygen-containing gas during the deposition of the silicon nitride layer 31 or by rapid thermal annealing in an oxygen-containing atmosphere after the deposition of the silicon nitride layer 31.
步骤4、请参阅图5或图6，在所述有源层2上方的氮氧化硅层33上形成栅极4。 Step 4 Referring to FIG. 5 or FIG. 6, a gate electrode 4 is formed on the silicon oxynitride layer 33 above the active layer 2.
优选地，所述栅极4的材料为钼(Mo)，厚度为
Figure PCTCN2016086723-appb-000005
具体地，所述步骤4首先在所述氮氧化硅层33沉积一金属层，随后对所述金属层进行图案化，形成栅极4。Preferably, the material of the gate 4 is molybdenum (Mo), and the thickness is
Figure PCTCN2016086723-appb-000005
Specifically, the step 4 first deposits a metal layer on the silicon oxynitride layer 33, and then patterns the metal layer to form the gate electrode 4.
步骤5、请参阅图7或图8，在所述栅极4、以及氮氧化硅层33上沉积一层间绝缘层5，并在所述层间绝缘层5上形成与所述有源层2的两端接触的源极61与漏极62。 Step 5, referring to FIG. 7 or FIG. 8, an interlayer insulating layer 5 is deposited on the gate electrode 4 and the silicon oxynitride layer 33, and the active layer is formed on the interlayer insulating layer 5. The source 61 and the drain 62 are in contact with both ends of 2.
具体地，所述层间绝缘层5的材料为氮化硅、及氧化硅中的一种或多种的组合，优选地，所述层间绝缘层5包括自下而上层叠设置的一层氧化硅、及一层氮化硅，其中氧化硅的厚度为
Figure PCTCN2016086723-appb-000006
氮化硅的厚度为
Figure PCTCN2016086723-appb-000007
所述源极61与漏极62的材料为两层钛夹一层铝，第一层钛的厚度为
Figure PCTCN2016086723-appb-000008
第二层钛的厚度为
Figure PCTCN2016086723-appb-000009
铝的厚度为
Figure PCTCN2016086723-appb-000010
具体地，所述步骤5包括首先在所述栅极4、以及氮氧化硅层33上沉积一层间绝缘层5，随后图案化所述层间绝缘层5，形成贯穿所述层间绝缘层5、及栅极绝缘层3的两过孔，所述两过孔分别暴露出所述有源层2的两端，然后在所述层间绝缘层5上沉积金属层并图案化，形成通过两过孔分别与有源层2的两端接触的源极61与漏极62。Specifically, the material of the interlayer insulating layer 5 is a combination of one or more of silicon nitride and silicon oxide. Preferably, the interlayer insulating layer 5 includes a layer stacked from bottom to top. Silicon oxide, and a layer of silicon nitride, wherein the thickness of the silicon oxide is
Figure PCTCN2016086723-appb-000006
The thickness of silicon nitride is
Figure PCTCN2016086723-appb-000007
The material of the source 61 and the drain 62 is two layers of titanium sandwiched with aluminum, and the thickness of the first layer of titanium is
Figure PCTCN2016086723-appb-000008
The thickness of the second layer of titanium is
Figure PCTCN2016086723-appb-000009
The thickness of aluminum is
Figure PCTCN2016086723-appb-000010
Specifically, the step 5 includes first depositing an interlayer insulating layer 5 on the gate electrode 4 and the silicon oxynitride layer 33, and then patterning the interlayer insulating layer 5 to form through the interlayer insulating layer. 5. Two via holes of the gate insulating layer 3, the two via holes respectively exposing both ends of the active layer 2, and then depositing a metal layer on the interlayer insulating layer 5 and patterning, forming through The two vias are respectively connected to the source 61 and the drain 62 of both ends of the active layer 2.
综上所述，本发明提供的一种低温多晶硅薄膜晶体管的制作方法，通过将与栅极接触的氮化硅层氧化成氮氧化硅层，采用氮氧化硅与栅极接触，该氮氧化硅层相比于氮化硅层，不仅可以抵挡离子扩散，还具有高电性稳定度，能够有效抑制栅极绝缘层的载流子注入，提升栅极绝缘层的可靠性和低温多晶硅薄膜晶体管的稳定性,制作方法简单，不需要增加制程光罩数。In summary, the present invention provides a method for fabricating a low temperature polysilicon thin film transistor by oxidizing a silicon nitride layer in contact with a gate electrode to a silicon oxynitride layer, and contacting silicon oxide with a gate electrode, the silicon oxynitride. Compared with the silicon nitride layer, the layer not only resists ion diffusion, but also has high electrical stability, can effectively suppress carrier injection of the gate insulating layer, improve the reliability of the gate insulating layer, and improve the reliability of the low-temperature polysilicon thin film transistor. Stability, simple production method, no need to increase the number of process masks.
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形 都应属于本发明权利要求的保护范围。 In the above, various other changes and modifications can be made in accordance with the technical solutions and technical concept of the present invention, and all such changes and modifications can be made by those skilled in the art. All should fall within the scope of protection of the claims of the present invention.

Claims (15)

  1. 一种低温多晶硅薄膜晶体管的制作方法，包括如下步骤：A method for fabricating a low temperature polysilicon thin film transistor includes the following steps:
    步骤1、提供一基板，在所述基板上沉积一低温多晶硅层，并对所述低温多晶硅层进行离子掺杂和图案化处理，形成有源层；Step 1. Providing a substrate, depositing a low temperature polysilicon layer on the substrate, and performing ion doping and patterning on the low temperature polysilicon layer to form an active layer;
    步骤2、在所述有源层、及基板上沉积一氧化硅层；Step 2, depositing a silicon oxide layer on the active layer and the substrate;
    步骤3、在所述氧化硅层上沉积一氮化硅层并利用含氧气体对所述氮化硅层进行氧化处理，将所述全部氮化硅层或者上层的部分氮化硅层氧化形成一氮氧化硅层，从而所述氮氧化硅层与氧化硅层或所述氮氧化硅层、氧化硅层与剩下的氮化硅层共同形成栅极绝缘层；Step 3, depositing a silicon nitride layer on the silicon oxide layer and oxidizing the silicon nitride layer with an oxygen-containing gas to oxidize the entire silicon nitride layer or a portion of the upper silicon nitride layer a silicon oxynitride layer, such that the silicon oxynitride layer and the silicon oxide layer or the silicon oxynitride layer, the silicon oxide layer and the remaining silicon nitride layer together form a gate insulating layer;
    步骤4、在所述有源层上方的氮氧化硅层上形成栅极；Step 4, forming a gate on the silicon oxynitride layer above the active layer;
    步骤5、在所述栅极、以及氮氧化硅层上沉积一层间绝缘层，并在所述层间绝缘层上形成与所述有源层的两端接触的源极与漏极。Step 5. Deposit an interlayer insulating layer on the gate electrode and the silicon oxynitride layer, and form a source and a drain on the interlayer insulating layer in contact with both ends of the active layer.
  2. 如权利要求1所述的低温多晶硅薄膜晶体管的制作方法，其中，所述步骤3中在氮化硅层沉积完成后，对所述氮化硅层进行快速热退火同时通入含氧气体将所述氮化硅层全部氧化成氮氧化硅层。The method of fabricating a low temperature polysilicon thin film transistor according to claim 1, wherein in the step 3, after the deposition of the silicon nitride layer is completed, the silicon nitride layer is rapidly thermally annealed while introducing an oxygen-containing gas. The silicon nitride layer is all oxidized to a silicon oxynitride layer.
  3. 如权利要求1所述的低温多晶硅薄膜晶体管的制作方法，其中，所述步骤3中先进行一段时间的氮化硅层沉积，然后通入含氧气体继续沉积，将上层的部分氮化硅层氧化成氮氧化硅层。The method of fabricating a low-temperature polysilicon thin film transistor according to claim 1, wherein in the step 3, a silicon nitride layer is deposited for a period of time, and then an oxygen-containing gas is introduced to continue deposition, and a portion of the upper silicon nitride layer is deposited. Oxidation to a silicon oxynitride layer.
  4. 如权利要求1所述的低温多晶硅薄膜晶体管的制作方法，其中，所述步骤3中的含氧气体为氧气、水气、或一氧化二氮。The method of fabricating a low temperature polysilicon thin film transistor according to claim 1, wherein the oxygen-containing gas in the step 3 is oxygen, moisture, or nitrous oxide.
  5. 如权利要求1所述的低温多晶硅薄膜晶体管的制作方法，其中，所述栅极材料为钼。A method of fabricating a low temperature polysilicon thin film transistor according to claim 1, wherein said gate material is molybdenum.
  6. 如权利要求1所述的低温多晶硅薄膜晶体管的制作方法，其中，所述源极与漏极的材料为两层钛夹一层铝。The method of fabricating a low temperature polysilicon thin film transistor according to claim 1, wherein the material of the source and the drain is a layer of aluminum sandwiched between two layers of titanium.
  7. 如权利要求1所述的低温多晶硅薄膜晶体管的制作方法，其中，所述层间绝缘层的材料为氮化硅、及氧化硅中的一种或多种的组合。The method of fabricating a low temperature polysilicon thin film transistor according to claim 1, wherein the material of the interlayer insulating layer is a combination of one or more of silicon nitride and silicon oxide.
  8. 如权利要求1所述的低温多晶硅薄膜晶体管的制作方法，其中，所述步骤1中在低温多晶硅层中掺杂的离子为P型离子或N型离子。The method of fabricating a low temperature polysilicon thin film transistor according to claim 1, wherein the ions doped in the low temperature polysilicon layer in the step 1 are P-type ions or N-type ions.
  9. 如权利要求1所述的低温多晶硅薄膜晶体管的制作方法，其中，所述源极与漏极通过贯穿所述层间绝缘层和栅极绝缘层的两过孔与所述有源层的两端接触。The method of fabricating a low temperature polysilicon thin film transistor according to claim 1, wherein said source and drain pass through two via holes penetrating said interlayer insulating layer and said gate insulating layer and both ends of said active layer contact.
  10. 一种低温多晶硅薄膜晶体管的制作方法，包括如下步骤： A method for fabricating a low temperature polysilicon thin film transistor includes the following steps:
    步骤1、提供一基板，在所述基板上沉积一低温多晶硅层，并对所述低温多晶硅层进行离子掺杂和图案化处理，形成有源层；Step 1. Providing a substrate, depositing a low temperature polysilicon layer on the substrate, and performing ion doping and patterning on the low temperature polysilicon layer to form an active layer;
    步骤2、在所述有源层、及基板上沉积一氧化硅层；Step 2, depositing a silicon oxide layer on the active layer and the substrate;
    步骤3、在所述氧化硅层上沉积一氮化硅层并利用含氧气体对所述氮化硅层进行氧化处理，将所述全部氮化硅层或者上层的部分氮化硅层氧化形成一氮氧化硅层，从而所述氮氧化硅层与氧化硅层或所述氮氧化硅层、氧化硅层与剩下的氮化硅层共同形成栅极绝缘层；Step 3, depositing a silicon nitride layer on the silicon oxide layer and oxidizing the silicon nitride layer with an oxygen-containing gas to oxidize the entire silicon nitride layer or a portion of the upper silicon nitride layer a silicon oxynitride layer, such that the silicon oxynitride layer and the silicon oxide layer or the silicon oxynitride layer, the silicon oxide layer and the remaining silicon nitride layer together form a gate insulating layer;
    步骤4、在所述有源层上方的氮氧化硅层上形成栅极；Step 4, forming a gate on the silicon oxynitride layer above the active layer;
    步骤5、在所述栅极、以及氮氧化硅层上沉积一层间绝缘层，并在所述层间绝缘层上形成与所述有源层的两端接触的源极与漏极；Step 5, depositing an interlayer insulating layer on the gate electrode and the silicon oxynitride layer, and forming a source and a drain on the interlayer insulating layer in contact with both ends of the active layer;
    其中，所述栅极材料为钼；Wherein the gate material is molybdenum;
    其中，所述源极与漏极的材料为两层钛夹一层铝；Wherein, the material of the source and the drain is two layers of titanium sandwiched with aluminum;
    其中，所述层间绝缘层的材料为氮化硅、及氧化硅中的一种或多种的组合。The material of the interlayer insulating layer is a combination of one or more of silicon nitride and silicon oxide.
  11. 如权利要求10所述的低温多晶硅薄膜晶体管的制作方法，其中，所述步骤3中在氮化硅层沉积完成后，对所述氮化硅层进行快速热退火同时通入含氧气体将所述氮化硅层全部氧化成氮氧化硅层。The method of fabricating a low-temperature polysilicon thin film transistor according to claim 10, wherein in the step 3, after the deposition of the silicon nitride layer is completed, the silicon nitride layer is rapidly thermally annealed while introducing an oxygen-containing gas. The silicon nitride layer is all oxidized to a silicon oxynitride layer.
  12. 如权利要求10所述的低温多晶硅薄膜晶体管的制作方法，其中，所述步骤3中先进行一段时间的氮化硅层沉积，然后通入含氧气体继续沉积，将上层的部分氮化硅层氧化成氮氧化硅层。The method of fabricating a low-temperature polysilicon thin film transistor according to claim 10, wherein in the step 3, a silicon nitride layer is deposited for a period of time, and then an oxygen-containing gas is introduced to continue deposition, and a portion of the upper silicon nitride layer is formed. Oxidation to a silicon oxynitride layer.
  13. 如权利要求10所述的低温多晶硅薄膜晶体管的制作方法，其中，所述步骤3中的含氧气体为氧气、水气、或一氧化二氮。The method of fabricating a low temperature polysilicon thin film transistor according to claim 10, wherein the oxygen-containing gas in the step 3 is oxygen, moisture, or nitrous oxide.
  14. 如权利要求10所述的低温多晶硅薄膜晶体管的制作方法，其中，所述步骤1中在低温多晶硅层中掺杂的离子为P型离子或N型离子。The method of fabricating a low temperature polysilicon thin film transistor according to claim 10, wherein the ions doped in the low temperature polysilicon layer in the step 1 are P-type ions or N-type ions.
  15. 如权利要求10所述的低温多晶硅薄膜晶体管的制作方法，其中，所述源极与漏极通过贯穿所述层间绝缘层和栅极绝缘层的两过孔与所述有源层的两端接触。 The method of fabricating a low temperature polysilicon thin film transistor according to claim 10, wherein said source and drain pass through two via holes penetrating said interlayer insulating layer and said gate insulating layer and both ends of said active layer contact.
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