WO2015165174A1 - Thin film transistor and manufacturing method therefor, display substrate, and display device - Google Patents
Thin film transistor and manufacturing method therefor, display substrate, and display device Download PDFInfo
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- WO2015165174A1 WO2015165174A1 PCT/CN2014/084703 CN2014084703W WO2015165174A1 WO 2015165174 A1 WO2015165174 A1 WO 2015165174A1 CN 2014084703 W CN2014084703 W CN 2014084703W WO 2015165174 A1 WO2015165174 A1 WO 2015165174A1
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
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Definitions
- the present invention relates to the field of display technologies, and in particular, to a thin film transistor, a method for fabricating the same, a display substrate, and a display device.
- Both an oxide thin film transistor (TFT) and an amorphous silicon TFT can be used as a driving tube for an organic light-emitting diode (OLED) panel and a polymer light-emitting diode (PLED) panel. Wait for the display panel.
- an oxide TFT has a carrier concentration many times that of an amorphous silicon TFT.
- the oxide TFT can be prepared by a magnetron sputtering method, so that the use of the oxide TFT does not require a drastic change in the existing liquid crystal panel production line.
- oxide TFTs are more conducive to the production of large-area display panels than polysilicon technology due to the limitations of equipment required for processes such as ion implantation and laser crystallization.
- FIG. 1(a) to 1(c) show a process flow diagram of a prior art oxide TFT.
- a top gate process in which an oxide is indium gallium zinc oxide (IGZO) is taken as an example.
- IGZO indium gallium zinc oxide
- an indium gallium zinc oxide is an active layer TFT.
- the production process is as follows:
- a buffer layer 101 is deposited on the glass substrate, and an IGZO oxide semiconductor material layer is deposited on the buffer layer 101, and an active layer pattern 102 is formed by a patterning process, and silicon oxide (SiOx) is deposited on the active layer pattern to form an engraved layer.
- the barrier layer is etched and etched to form a pattern 103 as shown in FIG. 1(b).
- the etch barrier layer in the prior art may also be a pattern including via holes corresponding to the source and the drain, respectively. Thereafter, the source and drain layers are deposited, and the source, drain 104, and the like are formed.
- an oxide semiconductor material is used as an active layer, and the oxide semiconductor is sensitive to an etchant of a source and a drain, and a source is formed by etching the metal layer.
- a source is formed by etching the metal layer.
- the process of the drain in order to prevent the active layer from being affected by the etching liquid of the source and the drain, it is necessary to form an etch barrier layer on the active layer.
- the patterning process of the special etch barrier layer is required, so that the fabrication process of the oxide TFT is complicated, the fabrication time is long, and the cost is correspondingly high.
- the present invention provides a thin film transistor, a manufacturing method thereof, a display substrate, and a display device, which simplify the fabrication process of the thin film transistor, the display substrate, and the display device, and reduce the manufacturing cost.
- a method of fabricating a thin film transistor comprising:
- etch barrier material layer is a conductive material that blocks the source and drain etchants
- the initial etch barrier pattern Forming an active layer and an initial etch barrier pattern by using a patterning process for the active layer material layer and the etch barrier material layer, the initial etch barrier pattern comprising a first region, a second region, and a third a region; the first region and the third region are regions forming a source and a drain, respectively, and the second region is a region other than the first region and the third region in the initial etch barrier layer pattern;
- An annealing process is performed to convert the conductive material of the second region in the initial etch barrier pattern into an insulating material to form an etch barrier pattern.
- the source and the drain are also formed on at least a portion of the active layer and the initial etch barrier pattern.
- the etch barrier material layer is a metal material that blocks the source and drain metal etchants, and after the annealing process, the metal material of the second region is converted into a metal oxide.
- the etch barrier material layer is tin, and after the annealing process, the tin of the second region is converted into an oxide of tin.
- the annealing process comprises: annealing the temperature between 200-250 degrees Celsius in an air atmosphere, and performing annealing for 0.5-3 hours.
- the thin film transistor of the top gate structure before forming the active layer material layer, further comprising forming a buffer layer on the substrate, further comprising forming a gate insulating layer after forming the source and the drain And a gate electrode; for the thin film transistor of the bottom gate structure, before forming the active layer material layer, further comprising sequentially forming a gate electrode and a gate insulating layer on the substrate.
- the active layer material layer is an oxide semiconductor.
- a thin film transistor comprising: an active layer, an etch barrier layer, and a source and a drain; wherein the etch barrier layer is located on an upper surface of the active layer and includes a first region, a second region, and a third region, wherein the etch barrier layer of the first region and the third region comprises a conductive material that blocks a source and a drain etchant, and the second region is engraved
- the etch stop layer comprises an insulating material formed by the conductive material; the source and the drain are respectively located on the first region and the third region of the etch stop layer, and the second region is the etch stop layer An area other than the first area and the third area.
- the insulating material is formed by the annealing process of the conductive material.
- the conductive material is a metal material
- the insulating material is a metal oxide formed of the metal material
- the metal material is tin and the metal oxide is an oxide of tin.
- the source and the drain are in contact with at least a portion of the side surface of the active layer and the initial etch barrier layer.
- the active layer is an oxide semiconductor.
- the thin film transistor further includes a buffer layer under the active layer, a gate insulating layer over the source and the drain, and a gate electrode above the gate insulating layer.
- the thin film transistor further includes: a gate insulating layer under the active layer, and a gate electrode under the gate insulating layer.
- the above solution proposed by the present invention can optimize the following problem: by using a conductive material capable of blocking the etching liquid of the source and the drain as an etch barrier, and the etching barrier layer and the active layer are formed by one patterning process. And after the source and the drain are formed, the conductive material corresponding to the second region (including the gap between the source and the drain) is converted into an insulating material through an annealing process to prevent a short circuit between the source and the drain, Compared with the prior art, the patterning process formed by the etch barrier layer is omitted, which simplifies the entire manufacturing process, saves the manufacturing process, and reduces the manufacturing cost. Moreover, it is located at the source and the drain. The conductive material underneath is not changed in the annealing process, and the contact resistance between the active layer and the source and drain of the thin film transistor can be improved, and the driving ability of the thin film transistor can be improved.
- 1(a) to 1(c) are flow charts showing a manufacturing process of an oxide thin film transistor in the prior art
- FIG. 2 is a flow chart of a method for fabricating a thin film transistor according to the present invention.
- 3(a) to 3(d) are flowcharts showing a manufacturing process of the thin film transistor of the present invention.
- FIG. 4 is a flow chart showing a method of fabricating a thin film transistor in an embodiment of the present invention.
- 5(a) to 5(e) are flowcharts showing a manufacturing process of a thin film transistor according to an embodiment of the present invention.
- FIG. 6 is a schematic structural view of a thin film transistor of a bottom gate structure in an embodiment of the present invention.
- FIG. 2 is a flow chart showing a method of fabricating an oxide thin film transistor proposed by the present invention.
- 3(a) to 3(d) are schematic views showing a process flow for fabricating the oxide thin film transistor. As shown in Fig. 2 and Fig. 3(a) to 3(d), it includes:
- Step 201 forming an active layer material layer 301 on the substrate;
- the active layer material layer 301 may be an oxide semiconductor material such as indium gallium zinc oxide (IGZO) or the like;
- Step 202 forming an etch barrier material layer 302 on the active layer material layer 301.
- the etch barrier material layer 302 is an etchant for the source and the drain. a conductive material that blocks;
- Step 203 forming an active layer and an initial etch barrier pattern by using a patterning process on the active layer material layer 301 and the etch barrier material layer 302, as shown in FIG. 3(b); the initial etching
- the barrier layer pattern includes a first region 3021, a second region 3022, and a third region 3023, wherein the first region 3021 and the third region 3023 are regions forming a source and a drain, respectively, and the second region 3022 is the a region other than the first region 3021 and the third region 3023 in the initial etch barrier pattern, that is, a spacer region between the source and the drain; it can be understood that the first region of the initial etch barrier pattern
- the division of the second region and the third region is based on the final etch barrier pattern corresponding to different positions Structural features are divided.
- the difference between the initial etch barrier layer and the etch stop layer is that the material of the second region of the initial etch barrier layer changes after the annealing process, and therefore, the initial etch barrier layer is formed when the initial etch barrier pattern is formed.
- the material composition and the like of the three regions of the pattern There is no difference in the material composition and the like of the three regions of the pattern, and the positions corresponding to the three regions of the initial etch barrier pattern are in one-to-one correspondence with the positions of the three regions of the finally formed etch barrier layer.
- Step 204 forming a source 3031 and a drain 3032 in the first region 3021 and the third region 3023, respectively, by a patterning process;
- the source and the drain are further formed on at least part of the side of the active layer and the initial etch barrier layer pattern; the source and the drain are in contact with the active layer through the at least part of the side surface, and the source is enhanced Electrical contact between the pole and the drain and the active layer.
- Step 205 performing an annealing process to convert the conductive material of the second region 3022 in the initial etch barrier pattern into an insulating material to form an etch barrier pattern, as shown in FIG. 3(d).
- the conductive material is preferably a metal material, such as tin or the like; after the annealing process, the metal material of the second region 3022 is oxidized to an insulating metal oxide, such as tin oxide, metal material tin.
- Sn is insensitive to the source and drain etchants.
- tin can block the source and drain etchants from affecting the active layer, and in the annealing process, The tin exposed to the annealing environment can be converted into an insulating tin oxide (SnOx), which prevents short-circuit between the source and the drain, and satisfies the basic requirements of the transistor.
- the annealing process comprises: annealing the temperature between 200-250 degrees Celsius in an air atmosphere, and annealing for 0.5-3 hours, and exposing in the annealing environment under the annealing condition.
- the conductive material in the second region is converted into an insulating material to prevent short-circuit between the source and the drain, satisfying the basic requirements of the transistor.
- the forming the active layer and the initial etch barrier layer pattern by using the one-time patterning process on the active layer material layer 301 and the etch barrier material layer 302 specifically includes the following steps:
- Step 2031 coating a layer of photoresist on the etch barrier material layer
- Step 2032 exposing and developing the photoresist by using an oxide active layer mask, and etching the active layer material layer and the etch barrier material layer to form an active layer and an initial etch barrier layer. Graphics.
- the buffer layer is formed on the substrate, and after forming the source electrode 3031 and the drain electrode 3032, the gate insulating layer and the gate are further formed.
- An electrode; for the thin film transistor of the bottom gate structure, before forming the active layer material layer 301, the gate electrode and the gate insulating layer are sequentially formed on the substrate.
- FIG. 4 is a flow chart showing a method of fabricating a thin film transistor according to an embodiment of the present invention. As shown in FIG. 4, the specific process flow can be seen in FIG. 5(a) to 5(e), and the method includes:
- Step 401 deposit a buffer material on the substrate 501 to form a buffer layer 502, as shown in FIG. 5(a).
- the buffer layer is used for blocking the diffusion of small molecules in the substrate, and preventing the diffusion of small molecules from affecting the active layer.
- the buffer layer material may be a material such as silicon oxide or silicon nitride.
- the material of the substrate 501 includes glass, silicon wafer, quartz, plastic, silicon wafer substrate and the like.
- Step 402 depositing a layer of active layer material 503 on the buffer layer 502.
- the active layer material includes an oxide semiconductor such as indium gallium zinc oxide (IGZO) or the like.
- IGZO indium gallium zinc oxide
- Step 403 depositing an etch barrier material layer 504 on the active layer material layer 503, as shown in FIG. 5(a), and etching the active layer material layer 503 and etching by using one patterning process.
- the barrier layer material layer 504 forms a pattern of the active layer and the initial etch barrier layer as shown in FIG. 5(b).
- the initial etch barrier pattern includes a first region 5041, a second region 5042, and a third region 5043; the first region 5041 and the third region 5043 are regions forming a source and a drain, respectively, and the second The region 5042 is a region other than the first region 5041 and the third region 5043 in the initial etch barrier pattern, and the second region 5042 includes a gap between the source and the drain.
- the etch barrier material layer is made of a conductive material capable of blocking the source and drain etchants.
- the conductive material combines with oxygen to form a non-conductive insulating material, which prevents short circuits between the source and the drain.
- the conductive material capable of blocking the source and drain etching liquids comprises a metal material.
- the metal material tin (Sn) is used as an etch barrier material, and the metal material tin (Sn) is etched by source and drain. The liquid is insensitive.
- tin When tin is used as the etch barrier material, tin can block the source and drain etchants from affecting the active layer, and tin can be converted into an insulating layer during the annealing process. Tin oxide (SnOx) prevents short circuits between the source and the drain, meeting the basic requirements of thin film transistors.
- the embodiment of the present invention does not limit the specific material of the etch barrier layer, and satisfies other conductive materials that have an etch barrier effect on the source and drain etchants and can be converted into an insulating material in a subsequent annealing process. protected range.
- a conductive material capable of blocking the source and drain etching liquids is used as an etch barrier material, and an active layer and an etch barrier layer pattern are formed by one patterning process, which is omitted from the prior art.
- the patterning process formed by the etch barrier pattern alone simplifies the entire manufacturing process and saves the manufacturing process.
- the etch stop material layer 504 has a thickness of 50- Preferred
- the one-time patterning process in the step 403 includes performing a patterning process using an oxide mask.
- step 403 further includes:
- Step 4031 coating a layer of photoresist on the etch barrier material layer
- Step 4032 exposing and developing the photoresist by using an oxide active layer mask, and etching the active layer material layer and the etch barrier material layer to form an active layer and an initial etch barrier layer. Graphics.
- Step 404 deposit a layer of source and drain materials and etch them to form a source pattern 5051 and a drain pattern 5052, as shown in FIG. 5(c).
- the source and drain materials may be deposited by sputtering deposition, and the material thereof includes metal and other materials having conductive functions.
- the metal includes Mo, Pt, Al, Ti, Co, Au, Cu, etc., and other materials having a conductive function include doped polysilicon, such as metal nitrides such as TiN and TaN.
- a source and a drain material are uniformly sputter deposited on the substrate on which the active layer and the initial etch material layer pattern are formed, and then The electrode layout is etched to remove unnecessary portions, and a pair of oppositely disposed electrodes left after etching constitute a source pattern 5051 and a drain pattern 5052.
- Step 405 After the source and drain patterns are patterned, the conductive material in the second region 5042 is combined with oxygen to form a non-conductive insulating material by using an annealing process, as shown in FIG. 5(d), thereby preventing The source and the drain are short-circuited to have transistor characteristics, and the etch barrier pattern corresponding to the first region and the third region is not changed in the annealing process, and the existing conductive material characteristics are maintained, and the thin film transistor can be improved.
- the contact resistance between the active layer and the source and drain enhances the driving capability of the thin film transistor. Therefore, the etch barrier material proposed by the present invention replaces the conventional etch barrier material such as silicon oxide (SiOx) without affecting the performance of the device, and the thin film transistor is improved as a whole while reducing the patterning process. Performance.
- the annealing process comprises: annealing the temperature between 200-250 degrees Celsius and annealing for 0.5-3 hours in an air atmosphere.
- the tin (second region) exposed to the annealing environment can be converted into an insulating tin oxide (SnOx) during the annealing process to prevent short-circuit between source and drain, and at the same time
- the tin corresponding to the region and the third region does not change, and has good electrical conductivity, which can improve the contact resistance between the active layer and the source and the drain of the thin film transistor, and improve the driving ability of the thin film transistor.
- Step 406 depositing a gate insulating material on the substrate on which the source pattern 5051 and the drain pattern 5052 are formed to form a gate insulating layer 506, as shown in FIG. 5(e).
- the gate insulating layer 506 may be deposited by a low temperature CVD method, and the material thereof may be an insulating material including silicon dioxide, silicon nitride, silicon oxynitride, or the like, a combination of these materials, or the like.
- Step 407 depositing a gate material on the surface of the gate insulating layer and etching it to form a gate pattern 507, as shown in FIG. 5(e);
- the gate material is made of a metal, a semiconductor material, or the like.
- the oxide thin film transistor of the bottom gate structure is specifically fabricated in a similar manner to the top gate structure, as shown in FIG. 6, except that a gate pattern 507 is formed on the substrate 501 first. Then, a gate insulating layer 506 is formed on the gate pattern 507, and then an etch barrier material layer 503 is formed on the gate insulating layer 506. The subsequent process is the same as that of the top gate structure. For details, refer to the description of FIG. , will not repeat them here.
- the etching is performed.
- a special etch barrier patterning process is required.
- a conductive material having a blocking effect on the source and drain etching liquids is selected as the etch barrier material, and the active layer is applied by one patterning process.
- the material and the etch barrier material are simultaneously etched, and after forming the source and the drain, an annealing process is performed, so that the etch barrier material between the source and the drain, that is, the conductive material is combined with oxygen to form a non-conductive material.
- the insulating material prevents short circuits between the source and the drain, and functions as a conventional etch barrier. The entire process is simpler and less costly than prior art processes.
- the present invention also proposes a thin film transistor, as shown in FIG. 5(e) or FIG. 6,
- FIG. 5(e) shows a partial cross-sectional view of a thin film transistor of a top gate structure
- FIG. 6 shows a bottom gate structure.
- the thin film transistor includes an active layer 503, an etch stop layer 504, a source 5051, and a drain 5052.
- the etch stop layer 504 is located on an upper surface of the active layer 503 and includes a first region 5041.
- the second region 5042 and the third region 5043, the etch barrier layer of the first region 5041 and the third region 5043 includes a conductive material that blocks the etching liquid of the source 5051 and the drain 5052, and the second
- the etch stop layer of the region 5042 includes an insulating material formed of the conductive material; the source 5051 and the drain 5052 are respectively located at the etch stop layer 504
- the first region 5041 and the third region 5043 are regions of the etch barrier layer other than the first region 5041 and the third region 5043.
- the insulating material is formed by the annealing process of the conductive material.
- the conductive material is preferably a metal material; the insulating material is a metal oxide formed by oxidation of the metal material in an annealing process.
- the metal material is preferably tin and the metal oxide is an oxide of tin (SnOx).
- the source 5051 and the drain 5052 are in contact with at least a portion of the active layer 503 and the etch stop layer 504.
- the active layer is an oxide semiconductor.
- the thin film transistor is a thin film transistor of a top gate structure, further comprising: a buffer layer 502 under the active layer 503, a gate insulating layer 506 over the source and drain electrodes 505, and a gate insulating layer A gate electrode 507 above the layer.
- the thin film transistor is a thin film transistor of a bottom gate structure, further comprising: a gate insulating layer 506 under the active layer 503, and a gate electrode 507 under the gate insulating layer 506.
- the thin film transistor corresponds to the method of fabricating the thin film transistor described in the previous embodiment, so the specific details are described in detail in the description of the fabrication method, and details are not described herein again.
- the thin film transistor of the embodiment of the invention has the advantages of simple fabrication process and low cost.
- the present invention also proposes a display substrate comprising the aforementioned thin film transistor.
- the present invention also proposes a display device comprising the aforementioned display substrate.
- the display substrate and the display device according to the embodiments of the present invention have the advantages of simple manufacturing process and low manufacturing cost.
- the above fabrication method proposed by the present invention etches the active layer material and the etch barrier material by a patterning process in the fabrication process of the thin film transistor backplane, and the etch barrier material is used for source and drain
- the etchant has a blocking conductive material and performs an annealing process after forming the source and the drain, so that the conductive material of the etch barrier between the source and the drain combines with oxygen to form a non-conductive
- the insulating material forms an insulating material to prevent short-circuit between the source and the drain, and functions as a conventional etch barrier layer, which simplifies the entire manufacturing process, saves the manufacturing process, and reduces the manufacturing cost.
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Abstract
A thin film transistor and a manufacturing method therefor, a display substrate, and a display device. The method comprises: forming an active layer material layer (301); forming an etching barrier layer material layer (302) on the active layer material layer (301), the etching barrier layer material layer (302) being a conductive material for blocking source and drain etching liquids; performing a one-time patterning process on the active layer material layer and the etching barrier layer material layer to form an active layer pattern and an initial etching barrier layer pattern, wherein the initial etching barrier layer pattern comprises a first area (3021), a second area (3022) and a third area (3023), a source and a drain are respectively formed in the first area (3021) and the third area (3023), and the second area (3022) is an area in addition to the first area (3021) and the third area (3023); forming a source (3031) and a drain (3032) in the first area (3021) and the third area (3023) respectively by using the patterning process; and performing an annealing process to convert the conductive material in the second area (3022) in the initial etching barrier layer pattern to an insulation material, and forming an etching barrier layer pattern.
Description
本发明涉及显示技术领域，尤其涉及一种薄膜晶体管及其制作方法、显示基板、显示装置。The present invention relates to the field of display technologies, and in particular, to a thin film transistor, a method for fabricating the same, a display substrate, and a display device.
氧化物薄膜晶体管(Thin Film Transistor，TFT)与非晶硅TFT均可作为驱动管用于有机发光二极管(Organic Light-Emitting Diode，OLED)面板及高分子发光二极管(polymer light-emitting diode，PLED)面板等显示面板中。氧化物TFT与非晶硅TFT相比，其载流子浓度是非晶硅TFT的很多倍。另外，氧化物TFT可通过磁控溅射(Sputter)的方法制备，因此采用氧化物TFT无需大幅改变现有的液晶面板生产线。同时，由于没有离子注入及激光晶化等工艺所需设备的限制，相对于多晶硅技术，氧化物TFT更有利于大面积的显示面板的生产。Both an oxide thin film transistor (TFT) and an amorphous silicon TFT can be used as a driving tube for an organic light-emitting diode (OLED) panel and a polymer light-emitting diode (PLED) panel. Wait for the display panel. Compared with an amorphous silicon TFT, an oxide TFT has a carrier concentration many times that of an amorphous silicon TFT. In addition, the oxide TFT can be prepared by a magnetron sputtering method, so that the use of the oxide TFT does not require a drastic change in the existing liquid crystal panel production line. At the same time, oxide TFTs are more conducive to the production of large-area display panels than polysilicon technology due to the limitations of equipment required for processes such as ion implantation and laser crystallization.
图1(a)～图1(c)示出了现有技术中氧化物TFT的工艺流程图。如图1(a)～图1(c)所示，以氧化物为铟镓锌氧化物(IGZO)的顶栅工艺为例，现有技术中铟镓锌氧化物为有源层的TFT的制作流程如下：1(a) to 1(c) show a process flow diagram of a prior art oxide TFT. As shown in FIG. 1(a) to FIG. 1(c), a top gate process in which an oxide is indium gallium zinc oxide (IGZO) is taken as an example. In the prior art, an indium gallium zinc oxide is an active layer TFT. The production process is as follows:
在玻璃基板上沉积缓冲层101，并在缓冲层101上沉积IGZO氧化物半导体材料层，并利用构图工艺形成有源层图形102，在有源层图形上沉积硅氧化物(SiOx)，形成刻蚀阻挡层，并对其刻蚀形成如图1(b)所示的图形103，当然，现有技术中刻蚀阻挡层还可以是包含分别对应源、漏极的过孔的图形。之后，沉积源、漏极层，并形成源、漏极104等。A buffer layer 101 is deposited on the glass substrate, and an IGZO oxide semiconductor material layer is deposited on the buffer layer 101, and an active layer pattern 102 is formed by a patterning process, and silicon oxide (SiOx) is deposited on the active layer pattern to form an engraved layer. The barrier layer is etched and etched to form a pattern 103 as shown in FIG. 1(b). Of course, the etch barrier layer in the prior art may also be a pattern including via holes corresponding to the source and the drain, respectively. Thereafter, the source and drain layers are deposited, and the source, drain 104, and the like are formed.
上述现有技术中的薄膜晶体管制作方法中，利用氧化物半导体材料作为有源层，而所述氧化物半导体对源极、漏极的刻蚀液比较敏感，在刻蚀金属层形成源极、漏极的过程中，为防止所述有源层被源极、漏极的刻蚀液影响，因此需要在有源层上形成刻蚀阻挡层。通常情况
下需要进行专门的刻蚀阻挡层的构图工艺，使得氧化物TFT的制作工艺较为复杂，制作时间长，成本相应也较高。In the above method for fabricating a thin film transistor, an oxide semiconductor material is used as an active layer, and the oxide semiconductor is sensitive to an etchant of a source and a drain, and a source is formed by etching the metal layer. In the process of the drain, in order to prevent the active layer from being affected by the etching liquid of the source and the drain, it is necessary to form an etch barrier layer on the active layer. Usually
The patterning process of the special etch barrier layer is required, so that the fabrication process of the oxide TFT is complicated, the fabrication time is long, and the cost is correspondingly high.
发明内容Summary of the invention
有鉴于此，本发明提出了一种薄膜晶体管及其制作方法、显示基板和显示装置，以简化薄膜晶体管、显示基板和显示装置的制作工艺，降低制作成本。In view of this, the present invention provides a thin film transistor, a manufacturing method thereof, a display substrate, and a display device, which simplify the fabrication process of the thin film transistor, the display substrate, and the display device, and reduce the manufacturing cost.
根据本发明一方面，其提供了一种薄膜晶体管的制作方法，包括：According to an aspect of the present invention, there is provided a method of fabricating a thin film transistor, comprising:
在基板上形成有源层材料层；Forming an active layer material layer on the substrate;
在有源层材料层上形成刻蚀阻挡层材料层，所述刻蚀阻挡层材料层为对源极、漏极刻蚀液起阻挡作用的导电材料；Forming an etch barrier material layer on the active layer material layer, wherein the etch barrier material layer is a conductive material that blocks the source and drain etchants;
对所述有源层材料层和刻蚀阻挡层材料层采用一次构图工艺形成有源层和初始刻蚀阻挡层图形，所述初始刻蚀阻挡层图形包括第一区域、第二区域和第三区域；所述第一区域和第三区域分别为形成源极、漏极的区域，所述第二区域为所述初始刻蚀阻挡层图形中除第一区域与第三区域之外的区域；Forming an active layer and an initial etch barrier pattern by using a patterning process for the active layer material layer and the etch barrier material layer, the initial etch barrier pattern comprising a first region, a second region, and a third a region; the first region and the third region are regions forming a source and a drain, respectively, and the second region is a region other than the first region and the third region in the initial etch barrier layer pattern;
通过构图工艺在所述第一区域和第二区域上分别形成源极、漏极；Forming a source and a drain on the first region and the second region, respectively, by a patterning process;
进行退火工艺，使得所述初始刻蚀阻挡层图形中第二区域的导电材料转变成绝缘材料，形成刻蚀阻挡层图形。An annealing process is performed to convert the conductive material of the second region in the initial etch barrier pattern into an insulating material to form an etch barrier pattern.
其中，所述源极、漏极还形成在有源层、初始刻蚀阻挡层图形的至少部分侧面上。The source and the drain are also formed on at least a portion of the active layer and the initial etch barrier pattern.
其中，所述刻蚀阻挡层材料层为对源极、漏极金属刻蚀液起阻挡作用的金属材料，经退火工艺后，所述第二区域的金属材料转变为金属氧化物。Wherein, the etch barrier material layer is a metal material that blocks the source and drain metal etchants, and after the annealing process, the metal material of the second region is converted into a metal oxide.
其中，所述刻蚀阻挡层材料层为锡，经退火工艺后，所述第二区域的锡转变为锡的氧化物。Wherein, the etch barrier material layer is tin, and after the annealing process, the tin of the second region is converted into an oxide of tin.
其中，所述退火工艺包括：在空气氛围下，将退火温度设置在200-250摄氏度之间，进行时间为0.5-3个小时的退火。Wherein, the annealing process comprises: annealing the temperature between 200-250 degrees Celsius in an air atmosphere, and performing annealing for 0.5-3 hours.
其中，对于顶栅结构的薄膜晶体管，在形成有源层材料层之前还包括在基板上形成缓冲层，在形成源、漏极之后还包括形成栅绝缘层
和栅电极；对于底栅结构的薄膜晶体管，在形成有源层材料层之前还包括依次在基板上形成栅电极和栅绝缘层。Wherein, for the thin film transistor of the top gate structure, before forming the active layer material layer, further comprising forming a buffer layer on the substrate, further comprising forming a gate insulating layer after forming the source and the drain
And a gate electrode; for the thin film transistor of the bottom gate structure, before forming the active layer material layer, further comprising sequentially forming a gate electrode and a gate insulating layer on the substrate.
其中，所述有源层材料层为氧化物半导体。Wherein, the active layer material layer is an oxide semiconductor.
根据本发明另一方面，其提供了一种薄膜晶体管，包括：有源层、刻蚀阻挡层和源极、漏极；其中所述刻蚀阻挡层位于所述有源层的上表面且包括第一区域、第二区域和第三区域，所述第一区域和第三区域的刻蚀阻挡层包含对源极、漏极刻蚀液起阻挡作用的导电材料，所述第二区域的刻蚀阻挡层包含所述导电材料形成的绝缘材料；所述源极、漏极分别位于所述刻蚀阻挡层的第一区域和第三区域上，所述第二区域为所述刻蚀阻挡层中除第一区域与第三区域之外的区域。According to another aspect of the present invention, there is provided a thin film transistor comprising: an active layer, an etch barrier layer, and a source and a drain; wherein the etch barrier layer is located on an upper surface of the active layer and includes a first region, a second region, and a third region, wherein the etch barrier layer of the first region and the third region comprises a conductive material that blocks a source and a drain etchant, and the second region is engraved The etch stop layer comprises an insulating material formed by the conductive material; the source and the drain are respectively located on the first region and the third region of the etch stop layer, and the second region is the etch stop layer An area other than the first area and the third area.
其中，所述绝缘材料是所述导电材料经退火工艺而形成的。Wherein, the insulating material is formed by the annealing process of the conductive material.
其中，所述导电材料为金属材料，所述绝缘材料为所述金属材料形成的金属氧化物。Wherein, the conductive material is a metal material, and the insulating material is a metal oxide formed of the metal material.
其中，所述金属材料为锡，所述金属氧化物为锡的氧化物。Wherein the metal material is tin and the metal oxide is an oxide of tin.
其中，所述源极、漏极与有源层和初始刻蚀阻挡层的至少部分侧面接触。Wherein, the source and the drain are in contact with at least a portion of the side surface of the active layer and the initial etch barrier layer.
其中，所述有源层为氧化物半导体。Wherein, the active layer is an oxide semiconductor.
所述薄膜晶体管还包括：位于有源层之下的缓冲层，位于源极、漏极之上的栅绝缘层，位于栅绝缘层上面的栅电极。The thin film transistor further includes a buffer layer under the active layer, a gate insulating layer over the source and the drain, and a gate electrode above the gate insulating layer.
所述薄膜晶体管还包括：位于有源层之下的栅绝缘层，位于栅绝缘层之下的栅电极。The thin film transistor further includes: a gate insulating layer under the active layer, and a gate electrode under the gate insulating layer.
本发明提出的上述方案可以优化以下问题：通过采用能够对源极、漏极的刻蚀液起阻挡作用的导电材料作为刻蚀阻挡层，并且刻蚀阻挡层与有源层采用一次构图工艺形成，并在源极、漏极形成后，经过退火工艺将第二区域(包括源、漏极之间的间隙)对应的导电材料转变成绝缘材料，以防止源极和漏极之间短路，起到传统刻蚀阻挡层的作用，与现有技术相比，省略了刻蚀阻挡层单独形成的构图工艺，简化了整个制作过程，节省了制作工序，降低制作成本；并且，位于源、漏极之下的导电材料在退火工艺中未发生变化，能够改善薄膜晶体管的有源层和源、漏极之间的接触电阻，提升薄膜晶体管的驱动能力。
The above solution proposed by the present invention can optimize the following problem: by using a conductive material capable of blocking the etching liquid of the source and the drain as an etch barrier, and the etching barrier layer and the active layer are formed by one patterning process. And after the source and the drain are formed, the conductive material corresponding to the second region (including the gap between the source and the drain) is converted into an insulating material through an annealing process to prevent a short circuit between the source and the drain, Compared with the prior art, the patterning process formed by the etch barrier layer is omitted, which simplifies the entire manufacturing process, saves the manufacturing process, and reduces the manufacturing cost. Moreover, it is located at the source and the drain. The conductive material underneath is not changed in the annealing process, and the contact resistance between the active layer and the source and drain of the thin film transistor can be improved, and the driving ability of the thin film transistor can be improved.
图1(a)～图1(c)是现有技术中氧化物薄膜晶体管的制作工艺流程图；1(a) to 1(c) are flow charts showing a manufacturing process of an oxide thin film transistor in the prior art;
图2是本发明提出的薄膜晶体管的制作方法流程图；2 is a flow chart of a method for fabricating a thin film transistor according to the present invention;
图3(a)～图3(d)是本发明中薄膜晶体管的制作工艺流程图；3(a) to 3(d) are flowcharts showing a manufacturing process of the thin film transistor of the present invention;
图4是本发明实施例中的薄膜晶体管制作方法的流程图；4 is a flow chart showing a method of fabricating a thin film transistor in an embodiment of the present invention;
图5(a)～图5(e)是本发明实施例中薄膜晶体管的制作工艺流程图；5(a) to 5(e) are flowcharts showing a manufacturing process of a thin film transistor according to an embodiment of the present invention;
图6是本发明实施例中底栅结构的薄膜晶体管结构示意图。6 is a schematic structural view of a thin film transistor of a bottom gate structure in an embodiment of the present invention.
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明作进一步的详细说明。The present invention will be further described in detail below with reference to the specific embodiments of the invention,
图2示出了本发明提出的氧化物薄膜晶体管的制作方法流程图。图3(a)～3(d)示出了制作所述氧化物薄膜晶体管的工艺流程示意图。如图2、图3(a)～3(d)所示，其包括：2 is a flow chart showing a method of fabricating an oxide thin film transistor proposed by the present invention. 3(a) to 3(d) are schematic views showing a process flow for fabricating the oxide thin film transistor. As shown in Fig. 2 and Fig. 3(a) to 3(d), it includes:
步骤201：在基板上形成有源层材料层301；Step 201: forming an active layer material layer 301 on the substrate;
可选地，所述有源层材料层301可选用氧化物半导体材料，如铟镓锌氧化物(IGZO)等；Optionally, the active layer material layer 301 may be an oxide semiconductor material such as indium gallium zinc oxide (IGZO) or the like;
步骤202：在有源层材料层301上形成刻蚀阻挡层材料层302，如图3(a)所示，所述刻蚀阻挡层材料层302为对源极、漏极的刻蚀液起阻挡作用的导电材料；Step 202: forming an etch barrier material layer 302 on the active layer material layer 301. As shown in FIG. 3(a), the etch barrier material layer 302 is an etchant for the source and the drain. a conductive material that blocks;
步骤203：对所述有源层材料层301和刻蚀阻挡层材料层302采用一次构图工艺形成有源层和初始刻蚀阻挡层图形，如图3(b)所示；所述初始刻蚀阻挡层图形包括第一区域3021、第二区域3022和第三区域3023，所述第一区域3021和第三区域3023分别为形成源极、漏极的区域，所述第二区域3022为所述初始刻蚀阻挡层图形中除第一区域3021与第三区域3023之外的区域，即源极、漏极之间的间隔区域；可以理解的是，所述初始刻蚀阻挡层图形第一区域、第二区域、第三区域的划分是基于最终的刻蚀阻挡层图形对应不同位置的
结构特点划分的。初始刻蚀阻挡层和刻蚀阻挡层的差别在于经过退火工艺后，初始刻蚀阻挡层的第二区域的材料发生了变化，因此，在形成初始刻蚀阻挡层图形时，初始刻蚀阻挡层图形的三个区域的材料组成等并无差异，初始刻蚀阻挡层图形的三个区域对应的位置与最终形成的刻蚀阻挡层的三个区域的位置分别一一对应。为更形象的描述和便于理解，我们在最终的刻蚀阻挡层图形中示出了初始刻蚀阻挡层对应的三个区域，见图3(d)；Step 203: forming an active layer and an initial etch barrier pattern by using a patterning process on the active layer material layer 301 and the etch barrier material layer 302, as shown in FIG. 3(b); the initial etching The barrier layer pattern includes a first region 3021, a second region 3022, and a third region 3023, wherein the first region 3021 and the third region 3023 are regions forming a source and a drain, respectively, and the second region 3022 is the a region other than the first region 3021 and the third region 3023 in the initial etch barrier pattern, that is, a spacer region between the source and the drain; it can be understood that the first region of the initial etch barrier pattern The division of the second region and the third region is based on the final etch barrier pattern corresponding to different positions
Structural features are divided. The difference between the initial etch barrier layer and the etch stop layer is that the material of the second region of the initial etch barrier layer changes after the annealing process, and therefore, the initial etch barrier layer is formed when the initial etch barrier pattern is formed. There is no difference in the material composition and the like of the three regions of the pattern, and the positions corresponding to the three regions of the initial etch barrier pattern are in one-to-one correspondence with the positions of the three regions of the finally formed etch barrier layer. For a more vivid description and easy understanding, we show three regions corresponding to the initial etch barrier in the final etch barrier pattern, see Figure 3(d);
步骤204：通过构图工艺在所述第一区域3021和第三区域3023分别形成源极3031、漏极3032；Step 204: forming a source 3031 and a drain 3032 in the first region 3021 and the third region 3023, respectively, by a patterning process;
此外，所述源极、漏极还形成在有源层和初始刻蚀阻挡层图形的至少部分侧面；所述源极、漏极通过所述至少部分侧面与有源层形成接触，可增强源极、漏极与有源层的电性接触。In addition, the source and the drain are further formed on at least part of the side of the active layer and the initial etch barrier layer pattern; the source and the drain are in contact with the active layer through the at least part of the side surface, and the source is enhanced Electrical contact between the pole and the drain and the active layer.
步骤205：进行退火工艺，使得所述初始刻蚀阻挡层图形中第二区域3022的导电材料转变成绝缘材料，形成刻蚀阻挡层图形，见图3(d)。Step 205: performing an annealing process to convert the conductive material of the second region 3022 in the initial etch barrier pattern into an insulating material to form an etch barrier pattern, as shown in FIG. 3(d).
可选地，所述导电材料优选为金属材料，如锡等；经过退火工艺后，所述第二区域3022的金属材料会被氧化为绝缘的金属氧化物，如锡的氧化物，金属材料锡(Sn)对源极、漏极刻蚀液不敏感，在采用锡作为刻蚀阻挡层材料时，锡能够阻挡源极、漏极刻蚀液对有源层造成影响，并且在退火工艺中，暴露在退火环境的锡能够转变成绝缘的锡的氧化物(SnOx)，可防止源极、漏极之间短路，满足晶体管的基本要求。Optionally, the conductive material is preferably a metal material, such as tin or the like; after the annealing process, the metal material of the second region 3022 is oxidized to an insulating metal oxide, such as tin oxide, metal material tin. (Sn) is insensitive to the source and drain etchants. When tin is used as the etch barrier material, tin can block the source and drain etchants from affecting the active layer, and in the annealing process, The tin exposed to the annealing environment can be converted into an insulating tin oxide (SnOx), which prevents short-circuit between the source and the drain, and satisfies the basic requirements of the transistor.
可选地，所述退火工艺包括：在空气氛围下，将退火温度设置在200-250摄氏度之间，进行时间为0.5-3个小时的退火，在此种退火条件下，暴露在退火环境中的第二区域中的导电材料转变为绝缘材料，防止源极、漏极之间短路，满足晶体管的基本要求。Optionally, the annealing process comprises: annealing the temperature between 200-250 degrees Celsius in an air atmosphere, and annealing for 0.5-3 hours, and exposing in the annealing environment under the annealing condition. The conductive material in the second region is converted into an insulating material to prevent short-circuit between the source and the drain, satisfying the basic requirements of the transistor.
可选地，所述对所述有源层材料层301和刻蚀阻挡层材料层302采用一次构图工艺形成有源层和初始刻蚀阻挡层图形具体包括如下步骤：Optionally, the forming the active layer and the initial etch barrier layer pattern by using the one-time patterning process on the active layer material layer 301 and the etch barrier material layer 302 specifically includes the following steps:
步骤2031：在所述刻蚀阻挡层材料层上涂覆一层光刻胶；
Step 2031: coating a layer of photoresist on the etch barrier material layer;
步骤2032：利用氧化物有源层掩膜板对光刻胶进行曝光、显影，并对所述有源层材料层和刻蚀阻挡层材料层进行刻蚀形成有源层和初始刻蚀阻挡层图形。Step 2032: exposing and developing the photoresist by using an oxide active layer mask, and etching the active layer material layer and the etch barrier material layer to form an active layer and an initial etch barrier layer. Graphics.
此外，对于顶栅结构的薄膜晶体管的制作方法中，在形成有源层材料层301之前还包括在基板上形成缓冲层，在形成源极3031、漏极3032之后还包括形成栅绝缘层和栅电极；对于底栅结构的薄膜晶体管，在形成有源层材料层301之前还包括在基板上依次形成栅电极和栅绝缘层。In addition, in the method of fabricating the thin film transistor of the top gate structure, before forming the active layer material layer 301, the buffer layer is formed on the substrate, and after forming the source electrode 3031 and the drain electrode 3032, the gate insulating layer and the gate are further formed. An electrode; for the thin film transistor of the bottom gate structure, before forming the active layer material layer 301, the gate electrode and the gate insulating layer are sequentially formed on the substrate.
下面以顶栅结构的薄膜晶体管为例更详细的说明本发明的技术方案。The technical solution of the present invention will be described in more detail below by taking a thin film transistor of a top gate structure as an example.
图4示出了本发明实施例中提出的薄膜晶体管的制作方法流程图。如图4所示，具体工艺流程可参见图5(a)～5(e)，该方法包括：FIG. 4 is a flow chart showing a method of fabricating a thin film transistor according to an embodiment of the present invention. As shown in FIG. 4, the specific process flow can be seen in FIG. 5(a) to 5(e), and the method includes:
步骤401：在基板501上沉积一层缓冲材料，形成缓冲层502，见图5(a)。所述缓冲层用于阻挡基板中小分子的扩散，防止小分子的扩散对有源层造成影响，缓冲层材料可采用氧化硅、氮化硅等材料。Step 401: deposit a buffer material on the substrate 501 to form a buffer layer 502, as shown in FIG. 5(a). The buffer layer is used for blocking the diffusion of small molecules in the substrate, and preventing the diffusion of small molecules from affecting the active layer. The buffer layer material may be a material such as silicon oxide or silicon nitride.
可选地，所述基板501的材料包括玻璃、硅片、石英、塑料以及硅片基底等。Optionally, the material of the substrate 501 includes glass, silicon wafer, quartz, plastic, silicon wafer substrate and the like.
步骤402：在缓冲层502上沉积一层有源层材料层503。Step 402: depositing a layer of active layer material 503 on the buffer layer 502.
可选地，所述有源层材料包括氧化物半导体，如铟镓锌氧化物(IGZO)等。Alternatively, the active layer material includes an oxide semiconductor such as indium gallium zinc oxide (IGZO) or the like.
步骤403：在所述有源层材料层503上沉积一层刻蚀阻挡层材料层504，，如图5(a)所示，并采用一次构图工艺刻蚀有源层材料层503和刻蚀阻挡层材料层504，形成有源层和初始刻蚀阻挡层的图形，如图5(b)所示。所述初始刻蚀阻挡层图形包括第一区域5041、第二区域5042和第三区域5043；所述第一区域5041和第三区域5043分别为形成源极、漏极的区域，所述第二区域5042为所述初始刻蚀阻挡层图形中除第一区域5041与第三区域5043之外的区域，第二区域5042包括源极、漏极之间的间隙。所述刻蚀阻挡层材料层由能够阻挡源极、漏极刻蚀液的导电材料制成。在随后的退火中，第二区域
的导电材料与氧气结合成为不导电的绝缘材料，可以防止源极、漏极之间形成短路。所述能够阻挡源极、漏极刻蚀液的导电材料包括金属材料，本发明实施例以金属材料锡(Sn)作为刻蚀阻挡层材料进行说明，金属材料锡(Sn)对源、漏刻蚀液不敏感，在采用锡作为刻蚀阻挡层材料时，锡能够阻挡源、漏极刻蚀液对有源层造成影响，并且锡在退火工艺中，暴露在退火环境的锡能够转变成绝缘的锡的氧化物(SnOx)，可防止源极、漏极之间发生短路，满足薄膜晶体管的基本要求。但本发明实施例不对刻蚀阻挡层具体材料进行限定，满足对源极、漏极刻蚀液具有刻蚀阻挡作用并在后续退火工艺中能够转变为绝缘材料的其他导电材料也为本发明的保护范围。本发明实施例中，采用能够阻挡源极、漏极刻蚀液的导电材料作为刻蚀阻挡层材料，并采用一次构图工艺形成有源层和刻蚀阻挡层图形，相比现有技术，省略了刻蚀阻挡层图形单独形成的构图工艺，简化了整个制作过程，节省了制作工序。Step 403: depositing an etch barrier material layer 504 on the active layer material layer 503, as shown in FIG. 5(a), and etching the active layer material layer 503 and etching by using one patterning process. The barrier layer material layer 504 forms a pattern of the active layer and the initial etch barrier layer as shown in FIG. 5(b). The initial etch barrier pattern includes a first region 5041, a second region 5042, and a third region 5043; the first region 5041 and the third region 5043 are regions forming a source and a drain, respectively, and the second The region 5042 is a region other than the first region 5041 and the third region 5043 in the initial etch barrier pattern, and the second region 5042 includes a gap between the source and the drain. The etch barrier material layer is made of a conductive material capable of blocking the source and drain etchants. In the subsequent annealing, the second region
The conductive material combines with oxygen to form a non-conductive insulating material, which prevents short circuits between the source and the drain. The conductive material capable of blocking the source and drain etching liquids comprises a metal material. In the embodiment of the invention, the metal material tin (Sn) is used as an etch barrier material, and the metal material tin (Sn) is etched by source and drain. The liquid is insensitive. When tin is used as the etch barrier material, tin can block the source and drain etchants from affecting the active layer, and tin can be converted into an insulating layer during the annealing process. Tin oxide (SnOx) prevents short circuits between the source and the drain, meeting the basic requirements of thin film transistors. However, the embodiment of the present invention does not limit the specific material of the etch barrier layer, and satisfies other conductive materials that have an etch barrier effect on the source and drain etchants and can be converted into an insulating material in a subsequent annealing process. protected range. In the embodiment of the present invention, a conductive material capable of blocking the source and drain etching liquids is used as an etch barrier material, and an active layer and an etch barrier layer pattern are formed by one patterning process, which is omitted from the prior art. The patterning process formed by the etch barrier pattern alone simplifies the entire manufacturing process and saves the manufacturing process.
可选地，所述刻蚀阻挡层材料层504的厚度为50-
优选为
Optionally, the etch stop material layer 504 has a thickness of 50- Preferred
可选地，所述步骤403中的一次构图工艺包括利用氧化物掩膜板进行一次构图工艺。Optionally, the one-time patterning process in the step 403 includes performing a patterning process using an oxide mask.
具体地，利用氧化物掩膜板进行一次构图工艺时，步骤403进一步包括：Specifically, when the patterning process is performed by using the oxide mask, step 403 further includes:
步骤4031：在所述刻蚀阻挡层材料层上涂覆一层光刻胶；Step 4031: coating a layer of photoresist on the etch barrier material layer;
步骤4032：利用氧化物有源层掩膜板对光刻胶进行曝光、显影，并对所述有源层材料层和刻蚀阻挡层材料层进行刻蚀形成有源层和初始刻蚀阻挡层图形。Step 4032: exposing and developing the photoresist by using an oxide active layer mask, and etching the active layer material layer and the etch barrier material layer to form an active layer and an initial etch barrier layer. Graphics.
步骤404：沉积一层源极、漏极材料，并对其进行刻蚀，形成源极图形5051、漏极图形5052，如图5(c)所示。Step 404: deposit a layer of source and drain materials and etch them to form a source pattern 5051 and a drain pattern 5052, as shown in FIG. 5(c).
可选地，所述源极、漏极材料可以采用溅射沉积的方式进行沉积，其材质包括金属以及具有导电功能的其它材料。所述金属包括Mo、Pt、Al、Ti、Co、Au、Cu等，所述具有导电功能的其它材料包括掺杂多晶硅，如TiN、TaN等金属氮化物等。
Optionally, the source and drain materials may be deposited by sputtering deposition, and the material thereof includes metal and other materials having conductive functions. The metal includes Mo, Pt, Al, Ti, Co, Au, Cu, etc., and other materials having a conductive function include doped polysilicon, such as metal nitrides such as TiN and TaN.
可选地，具体在制备源极图形5051、漏极图形5052时，先在形成有有源层和初始刻蚀材料层图形的基板上均匀溅射沉积一层源极、漏极材料，然后依据电极版图进行刻蚀移除不需要的部分，刻蚀之后留下的一对相对设置的电极，构成源极图形5051、漏极图形5052。Optionally, in the preparation of the source pattern 5051 and the drain pattern 5052, a source and a drain material are uniformly sputter deposited on the substrate on which the active layer and the initial etch material layer pattern are formed, and then The electrode layout is etched to remove unnecessary portions, and a pair of oppositely disposed electrodes left after etching constitute a source pattern 5051 and a drain pattern 5052.
步骤405：在源极、漏极图形化之后，利用退火工艺，使所述第二区域5042中的导电材料与氧气结合成为不导电的绝缘材料，，如图5(d)所示，从而防止源极、漏极之间短路，使其具备晶体管特性，同时第一区域和第三区域对应的刻蚀阻挡层图形在退火工艺中未发生改变，保持既有的导电材料特性，能够改善薄膜晶体管的有源层和源极、漏极之间的接触电阻，提升薄膜晶体管的驱动能力。因此，在不影响器件性能的情况下，本发明提出的刻蚀阻挡层材料取代了传统的刻蚀阻挡层材料如硅氧化物(SiOx)，在减少构图工艺的同时，整体上提升了薄膜晶体管的性能。Step 405: After the source and drain patterns are patterned, the conductive material in the second region 5042 is combined with oxygen to form a non-conductive insulating material by using an annealing process, as shown in FIG. 5(d), thereby preventing The source and the drain are short-circuited to have transistor characteristics, and the etch barrier pattern corresponding to the first region and the third region is not changed in the annealing process, and the existing conductive material characteristics are maintained, and the thin film transistor can be improved. The contact resistance between the active layer and the source and drain enhances the driving capability of the thin film transistor. Therefore, the etch barrier material proposed by the present invention replaces the conventional etch barrier material such as silicon oxide (SiOx) without affecting the performance of the device, and the thin film transistor is improved as a whole while reducing the patterning process. Performance.
可选地，所述退火工艺包括：在空气氛围下，将退火温度设置在200-250摄氏度之间，进行时间为0.5-3个小时的退火。Optionally, the annealing process comprises: annealing the temperature between 200-250 degrees Celsius and annealing for 0.5-3 hours in an air atmosphere.
选用锡作为刻蚀阻挡层材料时，在退火过程中，暴露在退火环境的锡(第二区域)能够转变成绝缘的锡的氧化物(SnOx)，防止源、漏之间短路，同时第一区域和第三区域对应的锡未发生变化，具有良好的导电性能，能够改善薄膜晶体管的有源层和源、漏极之间的接触电阻，提升薄膜晶体管的驱动能力。When tin is used as the etch barrier material, the tin (second region) exposed to the annealing environment can be converted into an insulating tin oxide (SnOx) during the annealing process to prevent short-circuit between source and drain, and at the same time The tin corresponding to the region and the third region does not change, and has good electrical conductivity, which can improve the contact resistance between the active layer and the source and the drain of the thin film transistor, and improve the driving ability of the thin film transistor.
步骤406：在形成有源极图形5051、漏极图形5052的基板上沉积一层栅极绝缘材料，形成栅极绝缘层506，如图5(e)所示。Step 406: depositing a gate insulating material on the substrate on which the source pattern 5051 and the drain pattern 5052 are formed to form a gate insulating layer 506, as shown in FIG. 5(e).
可选地，所述栅极绝缘层506可通过低温CVD方法来沉积，其材料可以是绝缘材料，包括二氧化硅、氮化硅、氮氧化硅等，或者这些材料的组合等。Alternatively, the gate insulating layer 506 may be deposited by a low temperature CVD method, and the material thereof may be an insulating material including silicon dioxide, silicon nitride, silicon oxynitride, or the like, a combination of these materials, or the like.
步骤407：在所述栅极绝缘层表面沉积一层栅极材料，并对其进行刻蚀形成栅极图形507，如图5(e)所示；Step 407: depositing a gate material on the surface of the gate insulating layer and etching it to form a gate pattern 507, as shown in FIG. 5(e);
可选地，所述栅极材料采用金属、半导体材料等。Optionally, the gate material is made of a metal, a semiconductor material, or the like.
底栅结构的氧化物薄膜晶体管的具体制作方法与顶栅结构的类似，参见附图6所示，所不同的是先在基板501上形成栅极图形507，
之后再栅极图形507上形成栅极绝缘层506，之后在栅极绝缘层506上形成刻蚀阻挡材料层503，之后的工序与顶栅结构的制作工序相同，具体详见对图5的描述，在此不再赘述。The oxide thin film transistor of the bottom gate structure is specifically fabricated in a similar manner to the top gate structure, as shown in FIG. 6, except that a gate pattern 507 is formed on the substrate 501 first.
Then, a gate insulating layer 506 is formed on the gate pattern 507, and then an etch barrier material layer 503 is formed on the gate insulating layer 506. The subsequent process is the same as that of the top gate structure. For details, refer to the description of FIG. , will not repeat them here.
本领域技术人员应当理解，氧化物薄膜晶体管的制作工艺中，利用氧化物半导体材料形成有源层之后，由于所述氧化物半导体对金属源极、漏极的刻蚀液比较敏感，在刻蚀金属层形成源极、漏极的过程中，为防止所述有源层被腐蚀，因此需要在有源层上形成刻蚀阻挡层。而通常情况下就需要进行专门的刻蚀阻挡层的构图工艺。而本发明的上述实施例提出的氧化物薄膜晶体管的制作过程中，选用对源极、漏极刻蚀液具有阻挡作用的导电材料作为刻蚀阻挡层材料，且采用一次构图工艺对有源层材料和刻蚀阻挡层材料同时刻蚀，并在形成源极、漏极之后，进行退火工艺，使得源极、漏极之间的刻蚀阻挡层材料即所述导电材料与氧气结合形成不导电的绝缘材料，进而能够防止源极、漏极之间的短路，起到了传统刻蚀阻挡层的作用。整个过程相较于现有技术制作工序简单且成本有所降低。It should be understood by those skilled in the art that in the fabrication process of the oxide thin film transistor, after the active layer is formed by using the oxide semiconductor material, since the oxide semiconductor is sensitive to the etching liquid of the metal source and the drain, the etching is performed. In order to prevent the active layer from being corroded during the formation of the source and the drain of the metal layer, it is necessary to form an etch stop layer on the active layer. In general, a special etch barrier patterning process is required. In the fabrication process of the oxide thin film transistor proposed by the above embodiment of the present invention, a conductive material having a blocking effect on the source and drain etching liquids is selected as the etch barrier material, and the active layer is applied by one patterning process. The material and the etch barrier material are simultaneously etched, and after forming the source and the drain, an annealing process is performed, so that the etch barrier material between the source and the drain, that is, the conductive material is combined with oxygen to form a non-conductive material. The insulating material, in turn, prevents short circuits between the source and the drain, and functions as a conventional etch barrier. The entire process is simpler and less costly than prior art processes.
此外，上述方法描述中，由于每个步骤所采用的具体刻蚀工艺以及刻蚀形成的相应图形与现有技术基本相同，因此在此并未做详细阐述；但是本领域技术人员应当理解，采用其他任何对源、漏金属起刻蚀阻挡作用的导电材料，并在后续退火工艺中将源、漏极之间间隙处的导电材料转变成绝缘体材料的方案均在本发明限定的保护范围之内。In addition, in the above description of the method, since the specific etching process used in each step and the corresponding pattern formed by etching are substantially the same as those in the prior art, they are not described in detail herein; however, those skilled in the art should understand that Any other conductive material that acts as an etch barrier for the source and drain metal, and converts the conductive material at the gap between the source and the drain into an insulator material in a subsequent annealing process, is within the scope of protection defined by the present invention. .
本发明还提出了一种薄膜晶体管，如图5(e)或图6所示，图5(e)示出了顶栅结构的薄膜晶体管的部分剖面示意图，图6示出了底栅结构的薄膜晶体管的部分剖面示意图。所述薄膜晶体管包括：有源层503、刻蚀阻挡层504、源极5051、漏极5052；其中所述刻蚀阻挡层504位于所述有源层503的上表面，且包括第一区域5041、第二区域5042和第三区域5043，所述第一区域5041和第三区域5043的刻蚀阻挡层包含对源极5051、漏极5052刻蚀液起阻挡作用的导电材料，所述第二区域5042的刻蚀阻挡层包含所述导电材料形成的绝缘材料；所述源极5051、漏极5052分别位于所述刻蚀阻挡层504的
第一区域5041和第三区域5043，所述第二区域5042为所述刻蚀阻挡层中除第一区域5041与第三区域5043之外的区域。The present invention also proposes a thin film transistor, as shown in FIG. 5(e) or FIG. 6, FIG. 5(e) shows a partial cross-sectional view of a thin film transistor of a top gate structure, and FIG. 6 shows a bottom gate structure. A partial cross-sectional view of a thin film transistor. The thin film transistor includes an active layer 503, an etch stop layer 504, a source 5051, and a drain 5052. The etch stop layer 504 is located on an upper surface of the active layer 503 and includes a first region 5041. The second region 5042 and the third region 5043, the etch barrier layer of the first region 5041 and the third region 5043 includes a conductive material that blocks the etching liquid of the source 5051 and the drain 5052, and the second The etch stop layer of the region 5042 includes an insulating material formed of the conductive material; the source 5051 and the drain 5052 are respectively located at the etch stop layer 504
The first region 5041 and the third region 5043 are regions of the etch barrier layer other than the first region 5041 and the third region 5043.
可选地，所述绝缘材料是所述导电材料经退火工艺而形成的。Optionally, the insulating material is formed by the annealing process of the conductive material.
可选地，所述导电材料优选为金属材料；所述绝缘材料为在退火工艺，由所述金属材料氧化而成的金属氧化物。Optionally, the conductive material is preferably a metal material; the insulating material is a metal oxide formed by oxidation of the metal material in an annealing process.
可选地，所述金属材料优选为锡，所述金属氧化物为锡的氧化物(SnOx)。Optionally, the metal material is preferably tin and the metal oxide is an oxide of tin (SnOx).
可选地，所述源极5051、漏极5052与有源层503和刻蚀阻挡层504的至少部分侧面接触。Optionally, the source 5051 and the drain 5052 are in contact with at least a portion of the active layer 503 and the etch stop layer 504.
其中，所述有源层为氧化物半导体。Wherein, the active layer is an oxide semiconductor.
可选地，所述薄膜晶体管为顶栅结构的薄膜晶体管，其还包括：位于有源层503之下的缓冲层502，位于源极、漏极505之上的栅绝缘层506，位于栅绝缘层上面的栅电极507。Optionally, the thin film transistor is a thin film transistor of a top gate structure, further comprising: a buffer layer 502 under the active layer 503, a gate insulating layer 506 over the source and drain electrodes 505, and a gate insulating layer A gate electrode 507 above the layer.
可选地，所述薄膜晶体管为底栅结构的薄膜晶体管，其还包括：位于有源层503之下的栅绝缘层506，位于栅绝缘层506之下的栅电极507。Optionally, the thin film transistor is a thin film transistor of a bottom gate structure, further comprising: a gate insulating layer 506 under the active layer 503, and a gate electrode 507 under the gate insulating layer 506.
所述薄膜晶体管由于与前面实施例中描述的薄膜晶体管制作方法相对应，因此具体细节详见制作方法的描述，在此不再赘述。The thin film transistor corresponds to the method of fabricating the thin film transistor described in the previous embodiment, so the specific details are described in detail in the description of the fabrication method, and details are not described herein again.
本发明实施例的薄膜晶体管具有制作工序简单、成本低的优点。The thin film transistor of the embodiment of the invention has the advantages of simple fabrication process and low cost.
本发明还提出了一种显示基板，其包括前述的薄膜晶体管。The present invention also proposes a display substrate comprising the aforementioned thin film transistor.
本发明还提出了一种显示装置，其包括前述的显示基板。The present invention also proposes a display device comprising the aforementioned display substrate.
本发明实施例的显示基板和显示装置具有制作工序简单，制作成本低的优点。The display substrate and the display device according to the embodiments of the present invention have the advantages of simple manufacturing process and low manufacturing cost.
本发明提出的上述制作方法在薄膜晶体管背板的制作过程中，通过一次构图工艺对有源层材料和刻蚀阻挡层材料进行刻蚀，且所述刻蚀阻挡层材料采用对源极、漏极刻蚀液具有阻挡作用的导电材料，并在形成源极、漏极之后进行退火工艺，使得所述源极、漏极之间的刻蚀阻挡层的导电材料与氧气结合而形成不导电的绝缘材料，所形成的绝缘材料能够防止源极、漏极之间短路，起到了传统刻蚀阻挡层的作用，有效的简化了整个制作过程，节省了制作工序，降低制作成本。
The above fabrication method proposed by the present invention etches the active layer material and the etch barrier material by a patterning process in the fabrication process of the thin film transistor backplane, and the etch barrier material is used for source and drain The etchant has a blocking conductive material and performs an annealing process after forming the source and the drain, so that the conductive material of the etch barrier between the source and the drain combines with oxygen to form a non-conductive The insulating material forms an insulating material to prevent short-circuit between the source and the drain, and functions as a conventional etch barrier layer, which simplifies the entire manufacturing process, saves the manufacturing process, and reduces the manufacturing cost.
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。
The specific embodiments of the present invention have been described in detail in the foregoing detailed description of the embodiments of the present invention. All modifications, equivalents, improvements, etc., made within the spirit and scope of the invention are intended to be included within the scope of the invention.
Claims (17)
- 一种薄膜晶体管的制作方法，包括：A method of fabricating a thin film transistor, comprising:在基板上形成有源层材料层；Forming an active layer material layer on the substrate;在有源层材料层上形成刻蚀阻挡层材料层，所述刻蚀阻挡层材料层为对源极、漏极刻蚀液起阻挡作用的导电材料；Forming an etch barrier material layer on the active layer material layer, wherein the etch barrier material layer is a conductive material that blocks the source and drain etchants;对所述有源层材料层和刻蚀阻挡层材料层采用一次构图工艺形成有源层和初始刻蚀阻挡层图形，所述初始刻蚀阻挡层图形包括第一区域、第二区域和第三区域；所述第一区域和第三区域分别为形成源、漏极的区域，所述第二区域为所述初始刻蚀阻挡层图形中除第一区域与第三区域之外的区域；Forming an active layer and an initial etch barrier pattern by using a patterning process for the active layer material layer and the etch barrier material layer, the initial etch barrier pattern comprising a first region, a second region, and a third a region; the first region and the third region are regions forming a source and a drain, respectively, and the second region is a region other than the first region and the third region in the initial etch barrier pattern;通过构图工艺在所述第一区域和第二区域上分别形成源极、漏极；Forming a source and a drain on the first region and the second region, respectively, by a patterning process;进行退火工艺，使得所述初始刻蚀阻挡层图形中第二区域的导电材料转变成绝缘材料，形成刻蚀阻挡层图形。An annealing process is performed to convert the conductive material of the second region in the initial etch barrier pattern into an insulating material to form an etch barrier pattern.
- 如权利要求1所述的薄膜晶体管的制作方法，其中，所述源极、漏极还形成在有源层、初始刻蚀阻挡层图形的至少部分侧面上。The method of fabricating a thin film transistor according to claim 1, wherein the source and the drain are further formed on at least a portion of an active layer and an initial etch barrier pattern.
- 如权利要求1-2任一项所述的薄膜晶体管的制作方法，其中，所述刻蚀阻挡层材料层为对源极、漏极刻蚀液起阻挡作用的金属材料，经退火工艺后，所述第二区域的金属材料转变为金属氧化物。The method of fabricating a thin film transistor according to any one of claims 1 to 2, wherein the etch barrier material layer is a metal material that blocks a source and a drain etchant, and after an annealing process, The metal material of the second region is converted into a metal oxide.
- 如权利要求3所述的薄膜晶体管的制作方法，其中，所述刻蚀阻挡层材料层为锡，经退火工艺后，所述第二区域的锡转变为锡的氧化物。The method of fabricating a thin film transistor according to claim 3, wherein the etch barrier material layer is tin, and after the annealing process, the tin of the second region is converted into an oxide of tin.
- 如权利要求1-4任一项所述的薄膜晶体管的制作方法，其中，所述退火工艺包括：在空气氛围下，将退火温度设置在200-250摄氏度之间，进行时间为0.5-3个小时的退火。The method of fabricating a thin film transistor according to any one of claims 1 to 4, wherein the annealing process comprises: setting an annealing temperature between 200 and 250 degrees Celsius in an air atmosphere, and performing a time of 0.5 to 3 An hour of annealing.
- 如权利要求1-5任一项所述的薄膜晶体管的制作方法，其中，对于顶栅结构的薄膜晶体管，在形成有源层材料层之前还包括在基板上形成缓冲层，在形成源极、漏极之后还包括形成栅绝缘层和栅电极；对于底栅结构的薄膜晶体管，在形成有源层材料层之前还包括依次在基板上形成栅电极和栅绝缘层。 The method of fabricating a thin film transistor according to any one of claims 1 to 5, wherein, for the thin film transistor of the top gate structure, before forming the active layer material layer, further comprising forming a buffer layer on the substrate, forming a source, The drain further includes forming a gate insulating layer and a gate electrode; and for the thin film transistor of the bottom gate structure, before forming the active layer material layer, further comprising sequentially forming a gate electrode and a gate insulating layer on the substrate.
- 如权利要求1-6任一项所述的薄膜晶体管的制作方法，其中，所述有源层材料层为氧化物半导体。The method of fabricating a thin film transistor according to any one of claims 1 to 6, wherein the active layer material layer is an oxide semiconductor.
- 一种薄膜晶体管，其特征在于，包括：有源层、刻蚀阻挡层和源极、漏极；其中所述刻蚀阻挡层位于所述有源层的上表面且包括第一区域、第二区域和第三区域，所述第一区域和第三区域的刻蚀阻挡层包含对源极、漏极刻蚀液起阻挡作用的导电材料，所述第二区域的刻蚀阻挡层包含所述导电材料形成的绝缘材料；所述源极、漏极分别位于所述刻蚀阻挡层的第一区域和第三区域上，所述第二区域为所述刻蚀阻挡层中除第一区域与第三区域之外的区域。A thin film transistor, comprising: an active layer, an etch barrier layer, and a source and a drain; wherein the etch barrier layer is located on an upper surface of the active layer and includes a first region and a second a region and a third region, the etch stop layer of the first region and the third region includes a conductive material that blocks a source and a drain etchant, and the etch stop layer of the second region includes the An insulating material formed of a conductive material; the source and the drain are respectively located on the first region and the third region of the etch stop layer, and the second region is the first region and the etch stop layer An area outside the third area.
- 如权利要求8所述的薄膜晶体管，其中，所述绝缘材料是所述导电材料经退火工艺而形成的。The thin film transistor according to claim 8, wherein said insulating material is formed by said annealing process of said conductive material.
- 如权利要求8-9任一项所述的薄膜晶体管，其中，所述导电材料为金属材料，所述绝缘材料为所述金属材料形成的金属氧化物。The thin film transistor according to any one of claims 8 to 9, wherein the conductive material is a metal material, and the insulating material is a metal oxide formed of the metal material.
- 如权利要求10所述的薄膜晶体管，其中，所述金属材料为锡，所述金属氧化物为锡的氧化物。The thin film transistor according to claim 10, wherein said metal material is tin and said metal oxide is an oxide of tin.
- 如权利要求8-11任一项所述的薄膜晶体管，其中，所述源极、漏极与有源层和刻蚀阻挡层的至少部分侧面接触。The thin film transistor according to any one of claims 8 to 11, wherein the source and the drain are in contact with at least a portion of an active layer and an etch stop layer.
- 如权利要求8-11任一项所述的薄膜晶体管，其中，所述有源层为氧化物半导体。The thin film transistor according to any one of claims 8 to 11, wherein the active layer is an oxide semiconductor.
- 如权利要求8-11任一项所述的薄膜晶体管，其还包括：位于有源层之下的缓冲层，位于源极、漏极之上的栅绝缘层，位于栅绝缘层上面的栅电极。The thin film transistor according to any one of claims 8 to 11, further comprising: a buffer layer under the active layer, a gate insulating layer over the source and the drain, and a gate electrode over the gate insulating layer .
- 如权利要求8-11任一项所述的薄膜晶体管，其还包括：位于有源层之下的栅绝缘层，位于栅绝缘层之下的栅电极。The thin film transistor according to any one of claims 8 to 11, further comprising: a gate insulating layer under the active layer, and a gate electrode under the gate insulating layer.
- 一种显示基板，其特征在于，包括如权利要求8-15任一项所述的薄膜晶体管。A display substrate comprising the thin film transistor according to any one of claims 8-15.
- 一种显示装置，其特征在于，包括如权利要求16所述的显示基板。 A display device comprising the display substrate of claim 16.
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| CN104241394A (en) | 2014-08-29 | 2014-12-24 | 京东方科技集团股份有限公司 | Thin film transistor, corresponding manufacturing method of thin film transistor, display substrate and display device |
| CN104934330A (en) * | 2015-05-08 | 2015-09-23 | 京东方科技集团股份有限公司 | Film transistor and preparation method thereof, array substrate and display panel |
| CN105097944A (en) * | 2015-06-25 | 2015-11-25 | 京东方科技集团股份有限公司 | Thin film transistor, fabrication method thereof, array substrate and display device |
| CN108206139B (en) * | 2018-01-02 | 2021-09-10 | 京东方科技集团股份有限公司 | Oxide thin film transistor, manufacturing method thereof and array substrate |
| CN110299322B (en) * | 2019-07-03 | 2022-03-08 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method thereof and display device |
| CN113345924B (en) * | 2021-06-03 | 2024-06-11 | 京东方科技集团股份有限公司 | Display panel, manufacturing method thereof and display device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101950733A (en) * | 2010-08-02 | 2011-01-19 | 友达光电股份有限公司 | Manufacturing method of pixel structure and manufacturing method of organic light-emitting component |
| CN102651401A (en) * | 2011-12-31 | 2012-08-29 | 京东方科技集团股份有限公司 | Thin-film transistor, array substrate and manufacturing method and display device thereof |
| US20120256176A1 (en) * | 2011-04-06 | 2012-10-11 | Samsung Mobile Display Co., Ltd. | Thin film transistor, organic luminescence display including the same, and method of manufacturing the organic luminescence display |
| CN103500738A (en) * | 2013-10-14 | 2014-01-08 | 南京中电熊猫液晶显示科技有限公司 | Semiconductor device containing etching barrier layer as well as manufacturing method and application of semiconductor device |
| CN103972299A (en) * | 2014-04-28 | 2014-08-06 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method of thin film transistor, display substrate and display device |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000022612A1 (en) * | 1998-10-12 | 2000-04-20 | Fujitsu Limited | Magnetic sensor, magnetic head, magnetic encoder, and hard disk drive |
| US6797388B1 (en) * | 1999-03-18 | 2004-09-28 | Ppg Industries Ohio, Inc. | Methods of making low haze coatings and the coatings and coated articles made thereby |
| EP1345277A4 (en) * | 2000-12-21 | 2005-02-16 | Fujitsu Ltd | Magnetoresistive device, magnetic head, and magnetic disk player |
| TWI416738B (en) * | 2006-03-21 | 2013-11-21 | Semiconductor Energy Lab | Nonvolatile semiconductor memory device |
| KR101277606B1 (en) * | 2006-03-22 | 2013-06-21 | 삼성디스플레이 주식회사 | Display device and manufacturing method thereof |
| KR101345376B1 (en) * | 2007-05-29 | 2013-12-24 | 삼성전자주식회사 | Fabrication method of ZnO family Thin film transistor |
| CN101719493B (en) * | 2008-10-08 | 2014-05-14 | 株式会社半导体能源研究所 | Display device |
| KR20110093113A (en) * | 2010-02-11 | 2011-08-18 | 삼성전자주식회사 | Thin film transistor array substrate and method of fabricating the same |
| US8435891B2 (en) * | 2011-06-02 | 2013-05-07 | International Business Machines Corporation | Converting metal mask to metal-oxide etch stop layer and related semiconductor structure |
| JP5906132B2 (en) * | 2012-05-09 | 2016-04-20 | 株式会社ジャパンディスプレイ | Display device |
-
2014
- 2014-04-28 CN CN201410174331.7A patent/CN103972299B/en active Active
- 2014-08-19 US US14/653,134 patent/US9704998B2/en active Active
- 2014-08-19 WO PCT/CN2014/084703 patent/WO2015165174A1/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101950733A (en) * | 2010-08-02 | 2011-01-19 | 友达光电股份有限公司 | Manufacturing method of pixel structure and manufacturing method of organic light-emitting component |
| US20120256176A1 (en) * | 2011-04-06 | 2012-10-11 | Samsung Mobile Display Co., Ltd. | Thin film transistor, organic luminescence display including the same, and method of manufacturing the organic luminescence display |
| CN102651401A (en) * | 2011-12-31 | 2012-08-29 | 京东方科技集团股份有限公司 | Thin-film transistor, array substrate and manufacturing method and display device thereof |
| CN103500738A (en) * | 2013-10-14 | 2014-01-08 | 南京中电熊猫液晶显示科技有限公司 | Semiconductor device containing etching barrier layer as well as manufacturing method and application of semiconductor device |
| CN103972299A (en) * | 2014-04-28 | 2014-08-06 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method of thin film transistor, display substrate and display device |
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| CN103972299B (en) | 2016-03-30 |
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