CN100339964C - Method for making MOS having light doped drain electrode - Google Patents
Method for making MOS having light doped drain electrode Download PDFInfo
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- CN100339964C CN100339964C CNB2005100696150A CN200510069615A CN100339964C CN 100339964 C CN100339964 C CN 100339964C CN B2005100696150 A CNB2005100696150 A CN B2005100696150A CN 200510069615 A CN200510069615 A CN 200510069615A CN 100339964 C CN100339964 C CN 100339964C
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Abstract
The present invention has a purpose for providing a method for making a metal oxide semiconductor with a light doped drain electrode. A gate electrode, a p-shaped ion heavily doped region and an n-shaped ion lightly doped region are simultaneously defined by a photo mask, and a contact window and an n-shaped ion heavily doped region can be simultaneously defined by another photo mask. Therefore, the present invention only needs six photo masks to complete the process of a thin film transistor (TFT) of the light doped drain electrode. Thus, not only is the purpose of reducing the frequency of use of the photo masks of the polycrystalline SiTFT obtained, but also volume production speed and yield are increased because of the reduction of processing steps.
Description
Technical field
The present invention relates to a kind of thin-film transistor and manufacture method thereof, particularly relate to a kind of thin-film transistor and manufacture method thereof that in technology, can reduce the photomask access times.
Background technology
Thin-film transistor (thin film transistor, TFT) for active matrix type flat-panel screens active element (active element) commonly used, be used for driving devices such as active formula LCD (active matrix type liquidcrystal display), active formula organic electro-luminescent display (active matrix type organicelectroluminescent display), image sensor.Usually, according to the composition of thin-film transistor semiconductor silicon rete, thin-film transistor can be divided into polycrystalline SiTFT and amorphous silicon film transistor.
For the element of realizing high-fineness and pixel are arranged, polysilicon replaces amorphous silicon gradually and becomes the development main flow of thin-film transistor technologies.Yet, the processing step of generally making polysilicon component but far beyond general amorphous silicon element technology come complicated and consuming time.
Please refer to Fig. 1 a to 1h, show the profile of a traditional CMOS thin film transistor (CMOS) making flow process.At first, see also Fig. 1 a, a substrate 10 is provided, have a resilient coating 11 and an amorphous silicon layer 12 on it.Then, make amorphous silicon layer 12 carry out crystallization and form polysilicon layer, and via this polysilicon layer of photoetching process after etching to form a silicon island 13n and 13p (siliconisland), shown in Fig. 1 b.
Please refer to shown in Fig. 1 c, the first photoresist layer 20 that forms a patterning is in this substrate 10, to expose the subregion of definition as the silicon island 13n of n transistor npn npn.Then, utilize this first photoresist layer 20 the silicon island 13n that exposes to be carried out a n type ion doping injection technology, to form n as mask
+Doped region 18n.
Please refer to shown in Fig. 1 d, remove the first photoresist layer 20, and form one second photoresist layer 21 in this substrate 10, and further expose and this n
+The part silicon island 13n that doped region 18n is adjacent.Then, carry out a n type ion doping injection technology as mask, make at n with the second photoresist layer 21
+The other polysilicon layer of doped region 18n forms n
- Doped region 28.
Please refer to Fig. 1 e, after removing the second photoresist layer 21, form one the 3rd photoresist layer 22 in this substrate, and expose subregion as the silicon island 13p of p transistor npn npn.Then, utilize the 3rd photoresist layer 22 the silicon island 13p that exposes to be carried out a p type ion doping injection technology, to form P as mask
+Doped region 18p.
Please refer to shown in Fig. 1 f, after removing the 3rd photoresist layer 22, form an insulating barrier 15 and a conducting shell (not icon) in said structure, and define this conducting shell, to form grid layer 16p and 16n via the photoengraving carving technology.This grid layer 16p and 16n are formed at respectively on undoped polycrystalline silicon layer (channel region) 19p and 19n of this silicon island 13p and 13n.
Please refer to Fig. 1 g, form one silica layer 30, and carry out the photoengraving carving technology to form contact hole 30a in said structure.Then, please refer to Fig. 1 h, define a metal level by the photoengraving carving technology, with formation source/drain contact region 35 in contact hole 30a.
Please refer to Fig. 1 i, form a protective layer 40, through this protective layer 40 of photoetching process after etching, to form the contact hole 40a that always passes to source/drain contact region 35 in said structure; At last, form a transparency electrode, and after photoetching process and etching, form a pixel electrode 50 in contact hole 40a place in said structure.By the processing step of above-mentioned traditional polycrystalline SiTFT as can be known, need use nearly 9 road photomasks carries out repeatedly the photoengraving carving technology and just can finish traditional polycrystalline SiTFT.So complicated manufacture method not only makes the technology cost of polycrystalline SiTFT improve and productive rate decline, and further makes the rate of finished products of polycrystalline SiTFT reduce.
In order to solve the problem that above-mentioned its complicated technology of conventional thin film transistor is caused, a kind of thin-film transistor manufacture that reduces the photomask access times also is suggested, and please refer to Fig. 2 a to 2e, shows the making flow process profile of an existing thin-film transistor.At first, please refer to Fig. 2 a, a substrate 100 is provided, be formed with a protective layer 105, polysilicon layer 110n and 110p, an insulating barrier 120 on it in regular turn, reach a conductive layer 130.
Shown in Fig. 2 b, utilize photoengraving carving technology definition as the polysilicon layer 110p of the p transistor npn npn conductive layer 130 on it to form a grid layer 132p.Then, utilize a photoresist layer 140 to carry out a p type ion doping injection technology as mask, form P with grid layer 132p
+ Doped region 180p.
Please refer to shown in Fig. 2 c, remove this photoresist layer 140, and form a photoresist layer 150 in p transistor npn npn and part as the polysilicon layer 110n of the n transistor npn npn conductive layer 130 on it on, define the grid layer 132n of n transistor npn npn via etching, and utilize grid layer 132n to carry out a n type ion doping injection technology as mask, form n
+ Doped region 180n.
Please refer to Fig. 2 d, the photoresist layer 150 on the isotropic etching grid layer 132n obtains less photoresist layer 150a to remove each preset distance 129 about it.Then, make etching mask etching grid layer 132n, obtain grid layer 132n ', and utilize grid layer 132n ' to carry out a n type ion doping injection technology, make at n as mask with photoresist layer 150a
+The other not doped region of doped region 180n forms n
- Doped region 184.
Please refer to Fig. 2 e, after removing photoresist layer 150a, form one first silicon oxide layer 151, and carry out photoetching process and be etched with forming first contact hole 160.Then, formation source/drain contact region 162 is in contact hole 160, and wherein this source/drain contact region 162 is formed through the photoengraving carving technology by a metal level.
At last, please refer to Fig. 2 f, form one second silicon oxide layer 182, through this second silicon oxide layer 182 of photoetching process after etching, to form second contact hole 170 that always passes to source/drain contact region 162 in said structure; At last, form a transparency electrode, and after photoetching process and etching, form a pixel electrode 190 in second contact hole, 170 places in said structure.In the thin-film transistor manufacture of above-mentioned existing minimizing photomask access times, though can reduce the photomask access times, above-mentioned technology most critical and where the shoe pinches need promptly to be this photoresist layer 150 of isotropic etching to remove each preset distance 129 about it.Yet this step easily causes processing range (process window) narrow and wayward, is unfavorable for actual production.
Therefore, in that limited the reaching of processing range do not increased under the prerequisite of difficulty in process degree, reaching the purpose of the photomask access times that reduce polycrystalline SiTFT technology, is the emphasis of needing research on the current thin film transistor process technologies badly.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of method for making MOS with lightly doped drain, can utilize one photomask to define gate electrode, p type ion heavily doped region and n type ion light doping section simultaneously, and can utilize another road photomask to define contact hole and n type ion heavily doped region simultaneously.Therefore, the present invention only needs 6 road photomasks, can finish technology with lightly doped drain electrode film transistor, not only can reach the purpose of the photomask access times that reduce polycrystalline SiTFT technology thus, and, therefore can improve volume production speed and increase rate of finished products because the step of technology reduces.
Another object of the present invention is to propose a kind of method for making MOS with lightly doped drain, promptly utilize six road photomasks to finish to have lightly doped drain (lightly doped drain, LDD) technology of the CMOS thin film transistor of structure (CMOS) reduces the required step of prior art.
According to one embodiment of the present invention, the method for making MOS with lightly doped drain of the present invention may further comprise the steps.At first, provide a substrate, this substrate comprises a lightly doped drain (LDD) district and a p type metal oxide semiconductor (PMOS) district.Forming one first island semiconductor floor distinguishes in this p type metal oxide semiconductor (PMOS) in this lightly doped drain (LDD) district and one second island semiconductor floor, wherein this first island semiconductor layer comprises a channel region, a light dope fate, an and source/drain electrode fate, and this second island semiconductor layer comprises a channel region, and a source/drain electrode fate.Form a gate insulator and one first conductive layer in regular turn in this substrate.The first photoresist layer that forms a patterning wherein is positioned at the thickness of the thickness of the first photoresist layer on this first and second island semiconductor layer channel region greater than the first photoresist layer of the light dope fate that is positioned at this first island semiconductor layer and source/drain electrode fate to cover this first conductive layer of this second island semiconductor layer channel region and this first island semiconductor layer top.The first photoresist layer with this patterning is this first conductive layer of mask etching, to form a first patterning conducting layer.A p type ion heavy doping technology is carried out in the source/drain electrode fate of this second island semiconductor layer, to form one source/drain region.Removal is positioned at first conductive layer of the light dope fate and the source-drain electrode fate of the first island semiconductor layer.A n type ion light dope technology is carried out in the light dope fate of this first island semiconductor layer, to form a lightly mixed drain area.Remove the first residual photoresist layer, then form an interlayer dielectric layer on this substrate.Form a perforation and a blind hole in this interlayer dielectric layer, wherein this perforation is corresponding to this first island semiconductor layer source/drain electrode fate and expose this source/drain electrode fate, and this blind hole is corresponding to this second island semiconductor layer source/drain region but do not expose this second island semiconductor layer source/drain region.See through this perforation and carry out a n type ion heavy doping technology, make the source/drain electrode fate of the second island semiconductor layer form one source/drain region.
For purpose of the present invention, feature can be become apparent, following conjunction with figs. and preferred embodiment are to illustrate in greater detail the present invention.
Description of drawings
Fig. 1 a to 1i makes the profile of flow process for showing a traditional CMOS thin film transistor.
Fig. 2 a to 2f makes the flow process profile for showing an existing thin-film transistor that reduces the photomask access times.
Fig. 3 a to 3m is for showing the flow process profile of the method for making MOS with lightly doped drain shown in one embodiment of the present invention.
Fig. 4 a and 4b are for showing the generalized section of the method for making MOS with lightly doped drain shown in another preferred embodiment of the present invention.
The simple symbol explanation
Substrate～10; Resilient coating～11; Amorphous silicon layer～12; Silicon island～13n and 13p; Insulating barrier～15; Grid layer～16p and 16n n
+Doped region～18n; P
+Doped region～18p; Channel region～19p and 19n; First photoresist layer～20; Second photoresist layer～21; The 3rd photoresist layer～22; n
-Doped region～28; Silicon oxide layer～30; Contact hole～30a; Source/drain contact region～35; Protective layer～40; Contact hole～40a; Pixel electrode～50; Substrate～100; Protective layer～105; Polysilicon layer～110n and 110p; Insulating barrier～120; Preset distance～129; Conductive layer～130; Grid layer～132n and 132p; Grid layer～132n; Photoresist layer～140; Photoresist layer～150; Photoresist layer～150a; First silicon oxide layer～151; Second silicon oxide layer 152; First contact hole～160; Source/drain contact region 162; Second contact hole～170; P
+Doped region～180p; n
+Doped region～180n; n
-Doped region～184; Pixel electrode～190; Substrate～200; Resilient coating～202; First island semiconductor layer～204; The second island semiconductor layer 204P; Gate insulator～208; First conductive layer～210 and 210 '; First photoresist layer～212 and 212 '; Interlayer dielectric layer～214; Second photoresist layer～216 and 216 '; First opening～217; Second opening～218; Perforation～221; Blind hole～222; First contact hole～230; Source/drain contact region～234; Protective layer 236; Second contact hole～238; Pixel electrode～242; Silicon nitride layer～255; Channel region～260 and 260P; Source/drain electrode fate～262 and 262P; Light dope fate～264; First grid electrode～266P; Second gate electrode～266; Source/drain region～267 and 267P; Lightly mixed drain area～268; First thickness～t1; Second thickness～t2; The 3rd thickness～t3; The 4th thickness～t4; P-type mos district～P; Lightly mixed drain area～LDD.
Embodiment
The invention provides a kind of method for making MOS, can effectively reduce the photomask access times of thin-film transistor technology, reduce process complexity and increase rate of finished products with lightly doped drain.This metal-oxide semiconductor (MOS) with lightly doped drain is applied to a Thin Film Transistor-LCD.Below exemplify one and meet the preferred embodiment with method for making MOS of lightly doped drain of the present invention, conjunction with figs. is described in detail as follows now:
At first, seeing also Fig. 3 a, a substrate 200 is provided, can for example be the used suitable substrate of LCD, and this substrate 200 comprises a P-type mos district P and a lightly mixed drain area LDD.Then, in this substrate 200, form a resilient coating 202 and a semi-conductor layer in regular turn.Then, use one first photomask and through a photoengraving carving technology define this semiconductor layer with form one first island semiconductor floor 204 in this lightly mixed drain area LDD and one second island semiconductor floor 204p in P-type mos district P, wherein this first island semiconductor layer 204 comprises a channel region 260, be positioned at the light dope fate 264 that these channel region both sides have a specific width, an and the source/drain electrode fate 262 that is positioned at side, light dope fate, and this second island semiconductor layer 204P comprises a channel region 260P, and a source/drain electrode fate 262P that is positioned at these channel region both sides.This resilient coating 202 can comprise silicon nitride and silica; And this semiconductor layer comprises silicon layer, that is can be polysilicon layer, monocrystalline silicon layer or amorphous silicon layer, is the example explanation with a polysilicon layer in the present embodiment.It is special at this mode that forms polysilicon layer to be there is no special limit, the formation method of this polysilicon layer can for example be to form an amorphous silicon layer on aforesaid substrate, then again this amorphous silicon layer is carried out an excimer laser (ELA) annealing process or a heat treatment, its temperature range can be 500～650 ℃ approximately, so that amorphous silicon layer is through the long brilliant polysilicon layer that forms of solid phase.
Then, see also Fig. 3 b, compliance forms a gate insulator 208 and one first conductive layer 210 on this substrate 200, to cover this first island semiconductor layer 204 and this second island semiconductor layer 204P fully in regular turn.Wherein this gate insulator 208 can for example be a silicon oxide layer, and the thickness range of this gate insulator 208 is preferably between 500 to 2000 , and better thickness range is between 800 to 1500 ; The composition of this conductive layer 210 can for example be aluminium, titanium, tantalum, chromium, molybdenum, tungsten molybdenum or by above-mentioned metal the alloy-layer formed arbitrarily or laminated thing etc.The generation type of this first conductive layer 210 is also unrestricted, can for example be vapour deposition process, sputtering method or vacuum vapour deposition.
Then, see also Fig. 3 c, use one second photomask to form the first photoresist layer 212 of a patterning to cover this first conductive layer 210 of this second island semiconductor layer 204P channel region 260P and these first island semiconductor layer, 204 tops.It should be noted that, this first photoresist layer 212 need have different thickness in design, the first photoresist layer 212 that wherein is formed on this first and second island semiconductor layer 204 and 204P channel region 260 and the 260P has one first thickness t 1, and the light dope fate 264 and the first photoresist layer 212 on source/drain electrode fate 262 that are formed at this first island semiconductor layer 204 have one second thickness t 2, at this, the ratio of this first thickness t 1 and this second thickness t 2 is between 10: 9 to 3: 1 scope.This generation type with first photoresist layer 212 of different-thickness can for example be a photoetching process of utilizing halftoning site photomask (halftone mask).
Then, see also Fig. 3 d, utilize this first photoresist layer 212 as etching mask, and with this first conductive layer 210 of an anisotropic etching process etching and this first photoresist layer 212, remove first conductive layer 210 that is not covered by this first photoresist layer 212, forming a first patterning conducting layer 210 ' on this first island semiconductor layer 204, and form a first grid electrode 266P on this second island semiconductor layer 204P channel region 260P.The purpose that formation has the first photoresist layer 212 of this different-thickness is, when this first photoresist layer 412 behind this etching step, can make this have the first photoresist layer 212 of second thickness t 2 (that is be positioned at the light dope fate 264 of this first island semiconductor layer 204 and the first photoresist layer 212 on source/drain electrode fate 262) can be removed fully, and the first photoresist layer 212 ' of residual fraction (the former first photoresist layer 212 with first thickness t 1) is on first conductive layer 210 of this first and second island semiconductor layer 204 and 204P channel region 260 and 260P top.
Then, still see also Fig. 3 d, with this first patterning conducting layer 210 ' and this first grid electrode 266P is mask, carries out a p type ion heavy doping technology, so that source/drain electrode fate 262P of this second island semiconductor layer 204P forms one source/drain region 267P.In one embodiment of the present invention, the dosage of this p type ion heavy doping technology for example is the dosage of follow-up n type ion light dope technology of carrying out more than 100 times.
Then, see also Fig. 3 e, with this first residual photoresist layer 212 ' as etching mask and with this gate insulator 208 as etching stopping layer, first conductive layer 210 ' on this first island semiconductor layer 204 of etching is to form one second gate electrode 266.Then, be mask with this second gate electrode 266 again, a n type ion light dope technology is carried out in light dope fate 264 and source/drain electrode fate 262 to this first island semiconductor layer 204, make the light dope fate 264 of the first island semiconductor layer 204 form a lightly mixed drain area 268, please refer to Fig. 3 f.In the step of n type ion light dope technology, because the dosage of this n type ion light dope technology is far below the dosage of this p type ion heavy doping technology, so this n type ion light dope technology can't have influence on source/drain region 267P of this first island semiconductor layer 204P.
Then, see also Fig. 3 g, remove the first photoresist layer 212 ' that residues on grid 266 and the 266P, and the smooth property covered formation one interlayer dielectric layer 214 is on this substrate 200.The material of this interlayer dielectric layer 214 can be identical with this gate insulator 208, be silica or silicon nitride layer for example, and the thickness range of this interlayer dielectric layer 214 is between 3000 to 5000 .Then, use one the 3rd photomask to form one and have the second photoresist layer 216 of different-thickness on this interlayer dielectric layer 214, this second photoresist layer 216 with different-thickness has first opening 217 and second opening 218, wherein this first opening 217 runs through this second photoresist layer 216, and corresponding to the top of the source/drain electrode fate 262 of this first island semiconductor layer 204, and expose this interlayer dielectric layer 214 of source/262 tops, drain electrode fate that are positioned at this first island semiconductor layer 204.In addition, this second opening is corresponding to source/drain region 267P of this second island semiconductor layer 204P but do not run through this second photoresist layer 216, and do not expose this interlayer dielectric layer 214 of the source/drain region 267P top that is positioned at this second island semiconductor layer 204P.In other words, the second photoresist layer 216 in being formed at this second opening 218 has one the 3rd thickness t 3, other 216 on the second photoresist layer has one the 4th thickness t 4, and wherein the ratio of the 4th thickness t 4 and the 3rd thickness t 3 is between 10: 9 to 3: 1 scope.This generation type with second photoresist layer 216 of different-thickness can for example be a photoetching process of utilizing halftoning site photomask (halftone mask).In addition, this first opening 217 be positioned at fully this source/drain electrode fate 262 directly over scope, and the horizontal range of this first opening 217 and the channel region 260 of this first island semiconductor layer 204 for example is 0.75 μ m between 0.4 μ m to 1 μ m at this.
Then, see also Fig. 3 h, with this second photoresist layer 216 with different-thickness as etching mask, and with an anisotropic etching process etching this second photoresist layer 216 and interlayer dielectric layer 214, remove the interlayer dielectric layer 214 that is not covered fully by this second photoresist layer 216, forming the gate insulator 208 that a perforation 221 runs through this interlayer dielectric layer 214 and exposes source/262 tops, drain electrode fate of this first island semiconductor layer 204, and form a blind hole 222 partial penetrations this interlayer dielectric layer 214 corresponding to this second island semiconductor layer 204P source/drain region 267P.Focusing on of this etching step, be positioned at interlayer dielectric layer 214 directly over this second island semiconductor layer 204P source/drain region 267P etched after, still possess a preset thickness, to prevent the influence of this source/drain region 267P to follow-up n type ion heavy doping technology.The purpose that formation has the second photoresist layer 216 of this different-thickness is, when this second photoresist layer 216 behind this etching step, can make this have the second photoresist layer 216 of the 3rd thickness t 3 second photoresist layer 216 of source/262 tops, drain electrode fate of this first island semiconductor layer 204 (that is be positioned at) can be removed, and on the interlayer dielectric layer 214 in the zone of the second photoresist layer 216 ' of residual fraction (the former second photoresist layer 216 with first thickness t 4) outside this perforation 221 and this blind hole 222.
Then, see also Fig. 3 i, as mask, see through this perforation 221 and carry out a n type ion heavy doping technology, so that the source of this first island semiconductor layer 204/drain electrode fate 262 forms one source/drain region 267 with this interlayer dielectric layer 214.Then, as etching stopping layer,,, see also Fig. 3 j with this source/drain region 267 and 267P to form first contact hole 230 via this perforation 221 and this interlayer dielectric layer 214 ' of blind hole 222 etchings and this gate insulator 208.
Then, see also Fig. 3 k, form one second conductive layer (not shown) on this interlayer dielectric layer 214, and insert in this first contact hole 230.Then, define second conductive layer to form multiple source/drain contact region 234 with a photoengraving carving technology.In this step, use one the 4th photomask that this second conductive layer is advanced shape one Patternized technique.
Then, see also Fig. 3 l, form a protective layer 236 on this interlayer dielectric layer 214, and use one the 5th photomask to define this protective layer 236 to form a plurality of second contact holes 238, expose this source/drain contact region 234 via a photoengraving carving technology.Then, the smooth property covered formation one transparency conducting layer (not shown) and is inserted in this second contact hole 238 on this protective layer 236.At last, define second conductive layer to form pixel electrode 242, see also Fig. 3 m with a photoengraving carving technology.In this step, use one the 6th photomask that this transparency conducting layer is advanced shape one Patternized technique.So far, finish the preferred embodiment that utilizes six road photomasks to finish to have lightly doped drain CMOS thin film transistor (CMOS) technology of (LDD) structure of the present invention.
In addition, in another preferred embodiment of the present invention, after finishing the step of carrying out a n type ion heavy doping technology with this interlayer dielectric layer 214 as mask (shown in Fig. 3 i), can be further comprising the steps of.At first, the smooth property covered formation one silicon nitride layer 255 and inserts in this first contact hole 230, shown in Fig. 4 a this silicon nitride layer 255 on this interlayer dielectric layer 214.Then, whole semiconductor structure is carried out a heat treatment, for example a quick thermal treatment process (RTP) injects the damage that is caused to eliminate by ion.In this step, the part nitrogen-atoms of this silicon nitride layer 255 can be imported in the interface of this interlayer dielectric layer and this semiconductor layer, the reliability that helps to lower the quantity of suspension key (dangling bonds) and improve this semiconductor element.Then, remove the silicon nitride layer 255 that is formed at this first contact hole interior 230, to expose this source/drain region 267 and 267P.
Inject owing to adopt the technology of self-aligned to do ion in the present invention, therefore do not need to utilize extra photomask to make the screen of ion implantation technology, total can be saved three road photomasks than prior art.And in technology of the present invention, form gate electrode earlier, carrying out ion doping technology afterwards, therefore, the live width of gate electrode (Critical dimension) is very easily controlled, and can avoid prior art because of carrying out the required additionally alignment procedures repeatedly of doping process earlier.In sum, the present invention compared with prior art, the present invention only uses 6 road photomasks can finish the thin-film transistor of function same as the prior art and because the step of technology of the present invention reduces, therefore can improve volume production speed and increase rate of finished products, and production cost is significantly reduced.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, thus protection scope of the present invention should with accompanying Claim the person of being defined be as the criterion.
Claims (11)
1, a kind of method for making MOS with lightly doped drain comprises:
One substrate is provided, and this substrate comprises a lightly mixed drain area and a p type metal oxide semiconductor district;
Form one first island semiconductor floor in this lightly mixed drain area and one second island semiconductor floor in this p type metal oxide semiconductor district, wherein this first island semiconductor layer comprises a channel region, a light dope fate, an and source/drain electrode fate, and this second island semiconductor layer comprises a channel region, and a source/drain electrode fate;
Form a gate insulator and one first conductive layer in regular turn in this substrate;
The first photoresist layer that forms a patterning wherein is positioned at the thickness of the thickness of the first photoresist layer on this first and second island semiconductor layer channel region greater than the first photoresist layer of the light dope fate that is positioned at this first island semiconductor layer and source/drain electrode fate to cover this first conductive layer of this second island semiconductor layer channel region and this first island semiconductor layer top;
The first photoresist layer with this patterning is this first conductive layer of mask etching, to form a first patterning conducting layer;
A p type ion heavy doping technology is carried out in the source/drain electrode fate of this second island semiconductor layer, to form one source/drain region;
Removal is positioned at first conductive layer of the light dope fate and the source-drain electrode fate of the first island semiconductor layer;
A n type ion light dope technology is carried out in the light dope fate of this first island semiconductor layer, to form a lightly mixed drain area;
Remove the first residual photoresist layer;
Form an interlayer dielectric layer on this substrate;
Form a perforation and a blind hole in this interlayer dielectric layer, wherein this perforation is corresponding to this first island semiconductor layer source/drain electrode fate and expose this source/drain electrode fate, and this blind hole is corresponding to this second island semiconductor layer source/drain region but do not expose this second island semiconductor layer source/drain region;
See through this perforation and carry out a n type ion heavy doping technology, make the source/drain electrode fate of the second island semiconductor layer form one source/drain region.
2, the method for making MOS with lightly doped drain as claimed in claim 1 was wherein forming semi-conductor layer before this substrate, also comprised forming a resilient coating in this substrate.
3, the method for making MOS with lightly doped drain as claimed in claim 1, wherein the dosage of this p type ion doping technology is greater than the dosage of this n type ion light dope technology more than 100 times.
4, the method for making MOS with lightly doped drain as claimed in claim 1, wherein this first photoresist layer uses the technology of halftoning site photomask to form.
5, the method for making MOS with lightly doped drain as claimed in claim 1 also comprises:
Be positioned at interlayer dielectric layer on this source/drain electrode and gate insulator exposing this source/drain electrode via this perforation and this blind hole etching, and form a plurality of first contact holes;
Formation source/drain contact region is in this first contact hole;
Form a protective layer in this substrate, wherein this protective layer has second contact hole and exposes this source/drain contact region; And
Form a pixel electrode, be electrically connected with this source/drain contact region via this second contact hole.
6, the method for making MOS with lightly doped drain as claimed in claim 5 wherein after the step that forms this first contact hole, also comprises:
Form silicon nitride layer in this substrate;
Carry out a heat treatment; And
Remove the silicon nitride layer that is formed in this first contact hole.
7, the method for making MOS with lightly doped drain as claimed in claim 6, wherein the thickness range of this silicon nitride layer is between 500 to 2000 .
8, the method for making MOS with lightly doped drain as claimed in claim 1, wherein, be arranged in light dope fate and the first photoresist layer of source/drain electrode fate and the step of first conductive layer of this first island semiconductor layer in removal, have the first photoresist layer of part and first conductive layer to residue in this first and second island semiconductor layer channel region top.
9, the method for making MOS with lightly doped drain as claimed in claim 1 wherein, in the step that forms this perforation and this blind hole, utilizes patterning second a photoresist layer with different-thickness to be formed by mask.
10, the method for making MOS with lightly doped drain as claimed in claim 9, wherein this patterning second photoresist layer with different-thickness uses halftoning site photo-marsk process to form.
11, the method for making MOS with lightly doped drain as claimed in claim 1, wherein this metal-oxide semiconductor (MOS) with lightly doped drain is applied to a Thin Film Transistor-LCD.
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| CNB2005100696150A CN100339964C (en) | 2005-04-29 | 2005-04-29 | Method for making MOS having light doped drain electrode |
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| CN100466234C (en) * | 2005-12-08 | 2009-03-04 | 中华映管股份有限公司 | Film transistor mfg. method |
| CN100426490C (en) * | 2006-07-25 | 2008-10-15 | 友达光电股份有限公司 | Active element substrate and forming method thereof |
| CN101060126A (en) * | 2007-03-27 | 2007-10-24 | 友达光电股份有限公司 | Thin film transistor and pixel structure and its manufacture method |
| CN101488478B (en) * | 2008-01-17 | 2012-06-06 | 中芯国际集成电路制造(上海)有限公司 | Integrated method for protecting polycrystalline and substrate surface |
| KR20120121931A (en) * | 2010-02-19 | 2012-11-06 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device and method for manufacturing the same |
| CN103996656A (en) * | 2014-04-30 | 2014-08-20 | 京东方科技集团股份有限公司 | Manufacturing method of display substrate and display substrate |
| CN104064472B (en) | 2014-06-13 | 2017-01-25 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method thereof and display device |
| CN105140124B (en) * | 2015-07-29 | 2018-12-11 | 武汉华星光电技术有限公司 | A kind of production method of polycrystalline SiTFT |
| CN107403758B (en) * | 2017-08-09 | 2022-09-23 | 京东方科技集团股份有限公司 | Array substrate, preparation method thereof and display device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6734034B2 (en) * | 2001-04-30 | 2004-05-11 | Hannstar Display Corporation | Transistor and associated driving device |
| CN1525554A (en) * | 2003-02-26 | 2004-09-01 | 友达光电股份有限公司 | Method for producing low-temperature polysilicon thin film transistor |
| US6902961B2 (en) * | 2003-05-28 | 2005-06-07 | Au Optronics Corp. | Method of forming a CMOS thin film transistor device |
-
2005
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6734034B2 (en) * | 2001-04-30 | 2004-05-11 | Hannstar Display Corporation | Transistor and associated driving device |
| CN1525554A (en) * | 2003-02-26 | 2004-09-01 | 友达光电股份有限公司 | Method for producing low-temperature polysilicon thin film transistor |
| US6902961B2 (en) * | 2003-05-28 | 2005-06-07 | Au Optronics Corp. | Method of forming a CMOS thin film transistor device |
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