CN105140124B - A kind of production method of polycrystalline SiTFT - Google Patents
A kind of production method of polycrystalline SiTFT Download PDFInfo
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- CN105140124B CN105140124B CN201510457944.6A CN201510457944A CN105140124B CN 105140124 B CN105140124 B CN 105140124B CN 201510457944 A CN201510457944 A CN 201510457944A CN 105140124 B CN105140124 B CN 105140124B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 38
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 84
- 239000011521 glass Substances 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 40
- 229920005591 polysilicon Polymers 0.000 claims abstract description 39
- 238000005468 ion implantation Methods 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 16
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 11
- 238000005516 engineering process Methods 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 238000005224 laser annealing Methods 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 239000010409 thin film Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 29
- 238000005530 etching Methods 0.000 description 17
- 150000002500 ions Chemical class 0.000 description 16
- 230000000295 complement effect Effects 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 8
- 229910044991 metal oxide Inorganic materials 0.000 description 6
- 150000004706 metal oxides Chemical class 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 6
- 239000002184 metal Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000008034 disappearance Effects 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 208000019901 Anxiety disease Diseases 0.000 description 1
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- 230000008859 change Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
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- 230000003628 erosive effect Effects 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
Abstract
A kind of production method the invention discloses polycrystalline SiTFT includes: to provide a glass substrate, and buffer layer and polysilicon layer are sequentially formed on the glass substrate；It is coated with a photoresist on the polysilicon layer, and the photoresist is exposed and is etched using half-tone mask light shield；High dose P doping is ion implanted, forms N+；Insulating layer and grid layer are sequentially formed on the full surface of the glass substrate；It is coated with a photoresist on the grid layer, and the photoresist is exposed using half-tone mask light shield；High dose B doping is ion implanted, forms P+.The present invention can be reduced light shield number, can effectively reduce cost.
Description
[technical field]
The present invention relates to field of display technology, in particular to a kind of production method of polycrystalline SiTFT.
[background technique]
In LTPS (Low Temperature Poly-silicon, low-temperature polysilicon silicon technology) existing manufacture craft, it is
Completion CMos (complementary metal oxide semiconductor, Complementary Metal Oxide Semiconductor) and
The definition of gate (grid), and LDD (asymmetric lightly doped drain) is formed, need 4 common masks that could complete, it is more promising
The effect of LDD and the technique for using 5 masks.Therefore, traditional handicraft will lead to the anxiety of PH production capacity, device requirement quantity
Greatly, and it is at high cost.
Therefore, it is necessary to propose a kind of new technical solution, to solve the above technical problems.
[summary of the invention]
The purpose of the present invention is to provide a kind of production methods of polycrystalline SiTFT, can be reduced light shield number, energy
It effectively reduces cost.
To solve the above problems, technical scheme is as follows:
A kind of production method of polycrystalline SiTFT, the production method of the polycrystalline SiTFT include:
One glass substrate is provided, buffer layer and polysilicon layer are sequentially formed on the glass substrate；
It is coated with a photoresist on the polysilicon layer, and the photoresist is exposed and is carved using half-tone mask light shield
Erosion；
High dose P doping is ion implanted, forms N+；
Insulating layer and grid layer are sequentially formed on the full surface of the glass substrate；
It is coated with a photoresist on the grid layer, and the photoresist is exposed using half-tone mask light shield；
High dose B doping is ion implanted, forms P+.
Preferably, in the production method of the polycrystalline SiTFT, polycrystalline is formed on the glass substrate
The step of silicon layer, comprising:
An amorphous silicon layer is formed on the buffer layer；
Quasi-molecule laser annealing operation is carried out to the amorphous silicon layer, forms polysilicon layer.
Preferably, in the production method of the polycrystalline SiTFT, polycrystalline is formed on the glass substrate
After the step of silicon layer, further includes:
Light diaphoretic prescription amount B doping is ion implanted, forms channel.
Preferably, described to use half-tone mask light shield pair in the production method of the polycrystalline SiTFT
The step of photoresist is exposed and etches, comprising:
The photoresist is exposed using half-tone mask light shield；
Etch away extra polysilicon；
Etch away the photoresist of half exposure.
Preferably, in the production method of the polycrystalline SiTFT, the ion implantation high dose P doping,
After the step of forming N+, further includes:
Get rid of the remaining photoresist.
Preferably, in the production method of the polycrystalline SiTFT, a photoresist is coated on the grid layer,
And after the step of being exposed using half-tone mask light shield to the photoresist, further includes:
Etch away extra grid.
Preferably, in the production method of the polycrystalline SiTFT, the B dosage is lower than the high dose P.
Preferably, in the production method of the polycrystalline SiTFT, the ion implantation high dose B doping,
After the step of forming P+, further includes:
Etch away the photoresist of half exposure；
Etch away exposed grid；
Get rid of the remaining photoresist.
Preferably, described to get rid of the remaining photoresist in the production method of the polycrystalline SiTFT
The step of after, further includes:
Low dosage P doping is ion implanted, forms N-.
Preferably, described to get rid of the remaining photoresist in the production method of the polycrystalline SiTFT
The step of before, further includes:
Low dosage P doping is ion implanted, forms N-.
Compared with the prior art, the present invention completes CMos (Complementary Metal using 2 half-tone mask light shields
Oxide Semiconductor, complementary metal oxide semiconductor) and grid definition, and form LDD.So that mask
Quantity has been reduced to 2 from 4, greatly improves competitiveness；Therefore the production of polycrystalline SiTFT provided by the invention
Method can effectively reduce light shield number, and can effectively reduce cost.
For above content of the invention can be clearer and more comprehensible, preferred embodiment is cited below particularly, and cooperate institute's accompanying drawings, makees
Detailed description are as follows.
[Detailed description of the invention]
Fig. 1 is the implementation process schematic diagram of the production method of polycrystalline SiTFT provided in an embodiment of the present invention；
Fig. 2 is the implementation process schematic diagram of the production method for the polycrystalline SiTFT that the embodiment of the present invention one provides；
Fig. 3 is the implementation process schematic diagram of the production method of polycrystalline SiTFT provided by Embodiment 2 of the present invention；
Fig. 4 is provided in an embodiment of the present invention to sequentially form buffer layer on the glass substrate and the structure of polysilicon layer is shown
It is intended to；
Fig. 5 is the structural schematic diagram of ion implantation light diaphoretic prescription amount B doping provided in an embodiment of the present invention；
Fig. 6 A and Fig. 6 B are the structural schematic diagram provided in an embodiment of the present invention for being coated with a photoresist on the polysilicon layer；
Fig. 7 A and Fig. 7 B are the structural schematic diagram provided in an embodiment of the present invention for etching away extra polysilicon；
Fig. 8 A and Fig. 8 B are the structural schematic diagram of the photoresist 13 provided in an embodiment of the present invention for etching away half exposure；
Fig. 9 A and Fig. 9 B are that ion implantation high dose P provided in an embodiment of the present invention adulterates the structural schematic diagram to form N+；
Figure 10 A and Figure 10 B are the structural schematic diagram provided in an embodiment of the present invention for getting rid of the remaining photoresist；
Figure 11 A and Figure 11 B are the structural schematic diagram provided in an embodiment of the present invention for forming insulating layer and grid layer；
Figure 12 A and Figure 12 B are the structural schematic diagram provided in an embodiment of the present invention that a photoresist is coated on grid layer；
Figure 13 A and Figure 13 B are the structural schematic diagram provided in an embodiment of the present invention for etching away extra grid；
Figure 14 A and Figure 14 B are that ion implantation high dose B provided in an embodiment of the present invention adulterates the structural representation to form P+
Figure；
Figure 15 A and Figure 15 B are the structural schematic diagram of the photoresist provided in an embodiment of the present invention for etching away half exposure；
Figure 16 A and Figure 16 B are the structural schematic diagram provided in an embodiment of the present invention for etching away exposed grid；
Figure 17 A and Figure 17 B are that ion implantation low dosage P provided in an embodiment of the present invention adulterates the structural representation to form N-
Figure；
Figure 18 A and Figure 18 B are the structural schematic diagram provided in an embodiment of the present invention for getting rid of remaining photoresist.
[specific embodiment]
The word " embodiment " used in this specification means serving as example, example or illustration.In addition, this specification and institute
The article " one " used in attached claim can generally be interpreted to mean " one or more ", unless specified otherwise or
Guiding singular is understood from context.
In embodiments of the present invention, the present invention completes CMos (Complementary using 2 half-tone mask light shields
Metal Oxide Semiconductor, complementary metal oxide semiconductor) and grid definition, and form LDD.To make
It obtains number of masks and has been reduced to 2 from 4, greatly improve competitiveness；Therefore polycrystalline SiTFT provided by the invention
Production method can effectively reduce light shield number, and can effectively reduce cost.
Referring to Fig. 1, Fig. 1 is the implementation process of the production method of polycrystalline SiTFT provided in an embodiment of the present invention
Schematic diagram；The production method of the polycrystalline SiTFT mainly comprises the steps that
In step s101, a glass substrate is provided, buffer layer and polysilicon are sequentially formed on the glass substrate
Layer；
In embodiments of the present invention, the step of forming polysilicon layer on the glass substrate, comprising:
An amorphous silicon layer is formed on the buffer layer；
Quasi-molecule laser annealing operation is carried out to the amorphous silicon layer, forms polysilicon layer.
In step s 102, a photoresist is coated on the polysilicon layer, and using half-tone mask light shield to the light
Resistance is exposed and etches；
In embodiments of the present invention, the step that the photoresist is exposed and is etched using half-tone mask light shield
Suddenly, comprising:
The photoresist is exposed using half-tone mask light shield；
Etch away extra polysilicon；
Etch away the photoresist of half exposure.
In step s 103, IMP (IMPLANT, ion implantation) high dose P doping, forms N+；
In step S104, insulating layer and grid layer are sequentially formed on the full surface of the glass substrate；
In embodiments of the present invention, the step of forming insulating layer on the full surface of the glass substrate, comprising:
One insulating layer is deposited on the full surface of the glass substrate using chemical vapor deposition.
In the step of forming grid layer on the full surface of the glass substrate, comprising:
One grid layer is deposited on the insulating layer using physical vapour deposition (PVD).
In step s105, a photoresist is coated on the grid layer, and using half-tone mask light shield to the photoresist
It is exposed；
In step s 106, high dose B doping is ion implanted in IMP, forms P+.
In embodiments of the present invention, the B dosage is lower than the high dose P, in order to avoid cause the disappearance of N+.
In order to illustrate technical solutions according to the invention, the following is a description of specific embodiments.
Embodiment one
Referring to Fig. 2, Fig. 2 is the realization stream of the production method for the polycrystalline SiTFT that the embodiment of the present invention one provides
Journey schematic diagram；It is mainly comprised the steps that
In step s 201, a glass substrate is provided, buffer layer and polysilicon are sequentially formed on the glass substrate
Layer；
In embodiments of the present invention, the step of forming polysilicon layer on the glass substrate, comprising:
An amorphous silicon layer is formed on the buffer layer；
Quasi-molecule laser annealing operation is carried out to the amorphous silicon layer, forms polysilicon layer.
In step S202, light diaphoretic prescription amount B doping is ion implanted in IMP, forms channel；
In step S203, a photoresist is coated on the polysilicon layer, and using half-tone mask light shield to the light
Resistance is exposed and etches；
In embodiments of the present invention, the step that the photoresist is exposed and is etched using half-tone mask light shield
Suddenly, comprising:
The photoresist is exposed using half-tone mask light shield；
Etch away extra polysilicon；
Etch away the photoresist of half exposure.
In step S204, high dose P doping is ion implanted in IMP, forms N+；
In step S205, the remaining photoresist is got rid of；
In step S206, insulating layer and grid layer are sequentially formed on the full surface of the glass substrate；
In embodiments of the present invention, the step of forming insulating layer on the full surface of the glass substrate, comprising:
One insulating layer is deposited on the full surface of the glass substrate using chemical vapor deposition.
In the step of forming grid layer on the full surface of the glass substrate, comprising:
One grid layer is deposited on the insulating layer using physical vapour deposition (PVD).
In step S207, a photoresist is coated on the grid layer, and using half-tone mask light shield to the photoresist
It is exposed；
In step S208, extra grid is etched away；
In step S209, high dose B doping is ion implanted in IMP, forms P+.
In embodiments of the present invention, the B dosage is lower than the high dose P, in order to avoid cause the disappearance of N+.
In step S210, the photoresist of half exposure is etched away；
In step S211, exposed grid is etched away.
In step S212, the remaining photoresist is got rid of.
In step S213, low dosage P doping is ion implanted in IMP, forms N-.
Embodiment two
Referring to Fig. 3, Fig. 3 is the realization stream of the production method of polycrystalline SiTFT provided by Embodiment 2 of the present invention
Journey schematic diagram；It is mainly comprised the steps that
In step S301, a glass substrate is provided, buffer layer and polysilicon are sequentially formed on the glass substrate
Layer；
Referring to Fig. 4, sequentially forming buffer layer and polysilicon layer on the glass substrate to be provided in an embodiment of the present invention
Structural schematic diagram.Buffer layer 11 is formed first on the glass substrate 10, then, 11 formation one are non-on the buffer layer
Crystal silicon layer；Quasi-molecule laser annealing operation is carried out to the amorphous silicon layer, forms polysilicon layer 12.
In embodiments of the present invention, the step of forming polysilicon layer on the glass substrate, comprising:
An amorphous silicon layer is formed on the buffer layer；
Quasi-molecule laser annealing operation is carried out to the amorphous silicon layer, forms polysilicon layer.
In step s 302, light diaphoretic prescription amount B doping is ion implanted in IMP, forms channel；
Referring to Fig. 5, for the structural schematic diagram of ion implantation light diaphoretic prescription amount B doping provided in an embodiment of the present invention.In this reality
It applies in example, in undefined NTFT (N+) and PTFT (P+), is implanted into a small amount of boron for adjusting TFT with ion implantation technology
The voltage of (Thin Film Transistor, thin film transistor (TFT)).Specifically, the polysilicon on whole face glass substrate is all implanted into
A small amount of boron.
In step S303, a photoresist is coated on the polysilicon layer, and using half-tone mask light shield to the light
Resistance is exposed and etches；
Fig. 6 A and Fig. 6 B is please referred to, is the structural representation provided in an embodiment of the present invention for being coated with a photoresist on the polysilicon layer
Figure.Firstly, being coated with a photoresist 13 on the polysilicon layer 12, then, and using half-tone mask light shield to the photoresist 13
It is exposed and etches.In the present embodiment, Cmos is made of on one piece of glass substrate NTFT (N+) and PTFT (P+), because
This, the region of another TFT needs photoresist to block while making one of TFT.In the present embodiment, in primary half color
Adjust the pattern that active layers NTFT and PTFT is defined in mask light shield exposure development.
Fig. 7 A and Fig. 7 B are the structural schematic diagram provided in an embodiment of the present invention for etching away extra polysilicon.In this implementation
In example, using etching technics, two kinds of TFT on one piece of glass substrate are removed extra polysilicon by etching simultaneously, are formed
Active layers NTFT and PTFT pattern.
Fig. 8 A and Fig. 8 B are the structural schematic diagram of the photoresist provided in an embodiment of the present invention for etching away half exposure.In this reality
It applies in example, forms the photoresist pattern such as Fig. 8 A and Fig. 8 B after using cineration technics (photoresist etching) photoresist being uniformly thinned.
In embodiments of the present invention, the step that the photoresist is exposed and is etched using half-tone mask light shield
Suddenly, comprising:
The photoresist is exposed using half-tone mask light shield；
Etch away extra polysilicon；
Etch away the photoresist of half exposure.
In step s 304, high dose P doping is ion implanted in IMP, forms N+；
Fig. 9 A and Fig. 9 B is please referred to, adulterates the structure to form N+ for ion implantation high dose P provided in an embodiment of the present invention
Schematic diagram.In the present embodiment, NTFT (N+) is formed using ion implantation technology, the region PTFT (P+) needs light in this process
Resistance, which shelters from, to be avoided being ion implanted.
In step S305, the remaining photoresist is got rid of；
Figure 10 A and Figure 10 B is please referred to, is the structural representation provided in an embodiment of the present invention for getting rid of the remaining photoresist
Figure.In the present embodiment, technique is removed using strip and washes off active layers NTFT and PTFT on whole photoresists, so far NTFT with
The defined completion of the region of PTFT, and implanting ions form the area N+ for the position N+ in the region NTFT.
In step S306, insulating layer and grid layer are sequentially formed on the full surface of the glass substrate；
Figure 11 A and Figure 11 B is please referred to, for the structural representation provided in an embodiment of the present invention for forming insulating layer and grid layer
Figure.Firstly, forming insulating layer 14 on the full surface of the glass substrate 10, grid layer 15 is then formed on insulating layer 14.?
In the present embodiment, one layer of insulating film (insulating layer), Zhi Houyong are deposited on whole face glass substrate using chemical vapor deposition process
Physical vapor film-forming process deposits layer of metal film (grid layer).
In embodiments of the present invention, the step of forming insulating layer on the full surface of the glass substrate, comprising:
One insulating layer is deposited on the full surface of the glass substrate using chemical vapor deposition.
In the step of forming grid layer on the full surface of the glass substrate, comprising:
One grid layer is deposited on the insulating layer using physical vapour deposition (PVD).
In step S307, a photoresist is coated on the grid layer, and using half-tone mask light shield to the photoresist
It is exposed；
Figure 12 A and Figure 12 B is please referred to, is the structural representation provided in an embodiment of the present invention for being coated with a photoresist on grid layer
Figure.Firstly, being coated with a photoresist 16 on the grid layer 15, then, the photoresist 16 is carried out using half-tone mask light shield
Exposure.In the present embodiment, the scan line pattern of NTFT and PTFT are defined in a half-tone mask light shield exposure development.
In step S308, extra grid is etched away；
Figure 13 A and Figure 13 B is please referred to, is the structural schematic diagram provided in an embodiment of the present invention for etching away extra grid.
In the present embodiment, using etching technics, the scan line of two kinds of TFT on one piece of glass substrate is more by etching removal simultaneously
Remaining metal film forms the scan line pattern of NTFT and PTFT.
In step S309, high dose B doping is ion implanted in IMP, forms P+.
Figure 14 A and Figure 14 B is please referred to, adulterates the knot to form P+ for ion implantation high dose B provided in an embodiment of the present invention
Structure schematic diagram.In the present embodiment, PTFT (P+) is formed using ion implantation technology, in this process NTFT (N+) regional channel
Position needs photoresist to shelter to avoid that (it is since it is desired that reduce illumination once fixed that the region NTFT, which is not blocked all, by ion implantation
Adopted whole scan line).Because N+ and P+ can mutually neutralize counteracting, so this time PTFT ion implantation dosage will be less than previous formation
Ion implantation dosage when NTFT.
In embodiments of the present invention, the B dosage is lower than the high dose P, in order to avoid cause the disappearance of N+.
In step s310, the photoresist of half exposure is etched away；
Figure 15 A and Figure 15 B is please referred to, is the structural schematic diagram of the photoresist provided in an embodiment of the present invention for etching away half exposure.
In the present embodiment, it is formed as shown in fig. 15 a and fig. 15b after using cineration technics (photoresist etching) photoresist being uniformly thinned
Photoresist pattern.
In step S311, exposed grid is etched away.
Figure 16 A and Figure 16 B is please referred to, is the structural schematic diagram provided in an embodiment of the present invention for etching away exposed grid.
In the present embodiment, the extra metal in NTFT scan line two sides is further removed using etching technics, formation NTFT is final to be swept
Retouch line pattern.
In step S312, low dosage P doping is ion implanted in IMP, forms N-.
Figure 17 A and Figure 17 B is please referred to, adulterates the knot to form N- for ion implantation low dosage P provided in an embodiment of the present invention
Structure schematic diagram.In the present embodiment, the position N- in the region NTFT is formed using self-align ion implantation technology, herein technique
Ion implantation dosage can reinforce N+, weaken the region P+, therefore dosage can be far smaller than the ion implantation dosage in the region P+.
In step S313, the remaining photoresist is got rid of.
Figure 18 A and Figure 18 B is please referred to, is the structural schematic diagram provided in an embodiment of the present invention for getting rid of remaining photoresist.
In the present embodiment, whole photoresists on glass substrate are washed off using strip technique, so far CMOS completes.
In conclusion the present invention completes CMos (Complementary Metal using 2 half-tone mask light shields
Oxide Semiconductor, complementary metal oxide semiconductor) and grid definition, and form LDD.So that mask
Quantity has been reduced to 2 from 4, greatly improves competitiveness；Therefore the production of polycrystalline SiTFT provided by the invention
Method can effectively reduce light shield number, and can effectively reduce cost.
Although the present invention, those skilled in the art have shown and described relative to one or more implementations
It will be appreciated that equivalent variations and modification based on the reading and understanding to the specification and drawings.The present invention includes all such repairs
Change and modification, and is limited only by the scope of the following claims.In particular, to various functions executed by the above components, use
It is intended to correspond in the term for describing such component and executes the specified function of the component (such as it is functionally of equal value
) random component (unless otherwise instructed), even if in structure with execute the exemplary of this specification shown in this article and realize
The open structure of function in mode is not equivalent.In addition, although the special characteristic of this specification is relative to several realization sides
Only one in formula is disclosed, but this feature can with such as can be for a given or particular application expectation and it is advantageous
One or more other features combinations of other implementations.Moreover, with regard to term " includes ", " having ", " containing " or its deformation
For being used in specific embodiments or claims, such term is intended to wrap in a manner similar to the term " comprising "
It includes.
In conclusion although the present invention has been disclosed above in the preferred embodiment, but above preferred embodiment is not to limit
The system present invention, those skilled in the art can make various changes and profit without departing from the spirit and scope of the present invention
Decorations, therefore protection scope of the present invention subjects to the scope of the claims.
Claims (9)
1. a kind of production method of polycrystalline SiTFT, which is characterized in that the production side of the polycrystalline SiTFT
Method includes:
One glass substrate is provided, buffer layer and polysilicon layer are sequentially formed on the glass substrate；
A small amount of boron is implanted into for adjusting the voltage of TFT thin film transistor (TFT) with ion implantation technology, wherein in whole face glass substrate
On polysilicon be all implanted into a small amount of boron；
It is coated with a photoresist on the polysilicon layer, and the photoresist is exposed and is etched using half-tone mask light shield；
The pattern of active layers NTFT and PTFT is defined in a half-tone mask light shield exposure development；
High dose P doping is ion implanted, forms N+, the photoresist is made to shelter from a regional channel position of PTFT；
Insulating layer and grid layer are sequentially formed on the full surface of the glass substrate；
It is coated with a photoresist on the grid layer, and the photoresist is exposed using half-tone mask light shield；Primary half
The scan line pattern of NTFT and PTFT are defined in tone mask light shield exposure development；And
High dose B doping is ion implanted, forms P+, wherein the ion implantation dosage of PTFT is less than ion when forming NTFT and plants
Enter dosage, the photoresist is made to shelter from a regional channel position of NTFT, wherein the B dosage is lower than the high dose P.
2. the production method of polycrystalline SiTFT according to claim 1, which is characterized in that in the glass substrate
The step of upper formation polysilicon layer, comprising:
An amorphous silicon layer is formed on the buffer layer；And
Quasi-molecule laser annealing operation is carried out to the amorphous silicon layer, forms polysilicon layer.
3. the production method of polycrystalline SiTFT according to claim 1 or 2, which is characterized in that in the glass
After the step of forming polysilicon layer on substrate, further includes:
Light diaphoretic prescription amount B doping is ion implanted, forms channel.
4. the production method of polycrystalline SiTFT according to claim 1, which is characterized in that described to use halftoning
The step of mask light shield is exposed and etches to the photoresist, comprising:
The photoresist is exposed using half-tone mask light shield；
Etch away extra polysilicon；And
Etch away the photoresist of half exposure.
5. the production method of polycrystalline SiTFT according to claim 1, which is characterized in that the ion implantation is high
After the step of dosage P doping, formation N+, further includes:
Get rid of the remaining photoresist.
6. the production method of polycrystalline SiTFT according to claim 1, which is characterized in that on the grid layer
It is coated with a photoresist, and after the step of being exposed using half-tone mask light shield to the photoresist, further includes:
Etch away extra grid.
7. the production method of polycrystalline SiTFT according to claim 1, which is characterized in that the ion implantation is high
After the step of dosage B doping, formation P+, further includes:
Etch away the photoresist of half exposure；
Etch away exposed grid；And
Get rid of the remaining photoresist.
8. the production method of polycrystalline SiTFT according to claim 7, which is characterized in that it is described get rid of it is remaining
The photoresist the step of after, further includes:
Low dosage P doping is ion implanted, forms N-.
9. the production method of polycrystalline SiTFT according to claim 7, which is characterized in that it is described get rid of it is remaining
The photoresist the step of before, further includes:
Low dosage P doping is ion implanted, forms N-.
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| PCT/CN2015/086251 WO2017015981A1 (en) | 2015-07-29 | 2015-08-06 | Method for manufacturing polysilicon thin-film transistor |
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