CN110112099A - The method for making LTPS TFT substrate - Google Patents
The method for making LTPS TFT substrate Download PDFInfo
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- CN110112099A CN110112099A CN201910274244.1A CN201910274244A CN110112099A CN 110112099 A CN110112099 A CN 110112099A CN 201910274244 A CN201910274244 A CN 201910274244A CN 110112099 A CN110112099 A CN 110112099A
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- 239000000758 substrate Substances 0.000 title claims abstract description 58
- 238000000034 method Methods 0.000 title claims abstract description 30
- 229910052751 metal Inorganic materials 0.000 claims abstract description 102
- 239000002184 metal Substances 0.000 claims abstract description 102
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 80
- 229920005591 polysilicon Polymers 0.000 claims abstract description 79
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 52
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 52
- 239000010703 silicon Substances 0.000 claims abstract description 52
- 229920002120 photoresistant polymer Polymers 0.000 claims description 53
- 238000000059 patterning Methods 0.000 claims description 47
- 238000005530 etching Methods 0.000 claims description 37
- 238000004519 manufacturing process Methods 0.000 claims description 29
- 238000005468 ion implantation Methods 0.000 claims description 22
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 17
- 238000001039 wet etching Methods 0.000 claims description 14
- 238000004380 ashing Methods 0.000 claims description 10
- 239000010949 copper Substances 0.000 claims description 10
- 238000005224 laser annealing Methods 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical group [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 5
- 239000004411 aluminium Substances 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 229910052750 molybdenum Inorganic materials 0.000 claims description 5
- 239000011733 molybdenum Substances 0.000 claims description 5
- ZPZCREMGFMRIRR-UHFFFAOYSA-N molybdenum titanium Chemical compound [Ti].[Mo] ZPZCREMGFMRIRR-UHFFFAOYSA-N 0.000 claims description 5
- 229910001069 Ti alloy Inorganic materials 0.000 claims description 4
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical group O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 claims description 4
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 246
- 150000002500 ions Chemical group 0.000 description 28
- 239000010408 film Substances 0.000 description 11
- 239000011229 interlayer Substances 0.000 description 6
- 239000002253 acid Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000004615 ingredient Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- BJEPYKJPYRNKOW-REOHCLBHSA-N (S)-malic acid Chemical compound OC(=O)[C@@H](O)CC(O)=O BJEPYKJPYRNKOW-REOHCLBHSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- BJEPYKJPYRNKOW-UHFFFAOYSA-N alpha-hydroxysuccinic acid Natural products OC(=O)C(O)CC(O)=O BJEPYKJPYRNKOW-UHFFFAOYSA-N 0.000 description 1
- 150000003863 ammonium salts Chemical class 0.000 description 1
- 229910001423 beryllium ion Inorganic materials 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000001630 malic acid Substances 0.000 description 1
- 235000011090 malic acid Nutrition 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Thin Film Transistor (AREA)
Abstract
The present invention proposes a kind of method for making LTPS TFT substrate, comprising: provides a substrate, forms a buffer layer on the substrate, form a patterned polysilicon silicon active layer on the buffer layer；Form the gate insulating layer for covering the patterned polysilicon silicon active layer；The metal layer with step structure is formed on the gate insulating layer；Using the metal layer with step structure as shielding layer, the patterned polysilicon silicon active layer is ion implanted, channel region, lightly doped region, heavily doped region are obtained.
Description
Technical field
The present invention relates to field of display technology, in particular to a kind of method for making LTPS TFT substrate.
Background technique
Low-temperature polysilicon film transistor (LTPS TFT) substrate can be applied to liquid crystal display (LCD) and active-matrix
The high-orders displays such as Organic Light Emitting Diode (AMOLED).Low-temperature polysilicon film transistor is gathered around compared to other thin film transistor (TFT)s
There is higher carrier mobility, higher carrier mobility will lead to hot carrier's effect, in some instances it may even be possible to will cause film
The failure of transistor.
In order to avoid the generation of hot carrier's effect can pass through ion implantation when making low-temperature polysilicon film transistor
Mode form shallow doping transition region in the source electrode and drain electrode of low-temperature polysilicon film transistor.But to low-temperature polysilicon film
When the source electrode and drain electrode of transistor carries out ion implantation operation, it is difficult to which the source electrode and drain electrode in polysilicon layer two sides is formed symmetrically
Shallow doping transition region, this causes the offset of doping deviation or area of grid.
Therefore, it is necessary to a kind of method for making LTPS TFT substrate be provided, to solve the problems of prior art.
Summary of the invention
The purpose of the present invention is to provide a kind of methods for making LTPS TFT substrate, in solution in the prior art PI layers
The technical issues of adulterating deviation or area of grid offset.
In order to solve the above technical problems, the present invention provides a kind of method for making LTPS TFT substrate, which is characterized in that packet
Include following steps:
S11, a substrate is provided, forms a buffer layer on the substrate, it is more to form a patterning on the buffer layer
Crystal silicon active layer；
S12, form the gate insulating layer for covering the patterned polysilicon silicon active layer, on the gate insulating layer according to
Sequence forms a first metal layer and a second metal layer；
S13, it is coated with photoresist in the second metal layer, obtains corresponding to the patterned polysilicon after exposed, display
A patterning photoresist layer of top in the middle part of silicon active layer；
S14, using the patterning photoresist layer as shielding layer, the is carried out to the first metal layer and the second metal layer
Primary etching, wherein the etch-rate of the second metal layer is greater than the etch-rate of the first metal layer, so that after etching
The second metal layer line width be less than etching after the first metal layer line width；
S15, the edge that the patterning photoresist layer is ashed using second of etching, so that the patterning after ashing
The line width of photoresist layer and the line width of the second metal layer are substantially the same；
S16, using the second metal layer and the first metal layer as shielding layer, to the patterned polysilicon silicon active layer
It is ion implanted, obtains being located in the middle part of the patterned polysilicon silicon active layer and correspond to the channel region of the patterning photoresist layer
Two heavily doped regions on the outside of two lightly doped regions, described two lightly doped regions on the outside of domain, the channel region；And
S17, removing remove the patterning photoresist layer.
The method of production LTPS TFT substrate according to the present invention, forms a figure on the buffer layer in step s 11
The step of case polysilicon active layer includes:
An amorphous silicon layer is formed on the buffer layer；
Quasi-molecule laser annealing processing is carried out to the amorphous silicon layer, the amorphous silicon layer is formed as into a polysilicon
Layer；And
The polysilicon layer is patterned, to form the patterned polysilicon silicon active layer.
The method of production LTPS TFT substrate according to the present invention, the material of the first metal layer are molybdenum (Mo) or molybdenum titanium
Alloy (MoTi), the material of the second metal layer are copper (Cu).
The method of production LTPS TFT substrate according to the present invention, the first time are etched to wet etching, and described second
It is etched to dry ecthing.
The method of production LTPS TFT substrate according to the present invention, it is active to the patterned polysilicon in the step S6
The ion implantation that layer is carried out is N-type ion implantation or P-type ion implantation.
The present invention also provides a kind of methods for making LTPS TFT substrate, which comprises the following steps:
S21, a substrate is provided, forms a buffer layer on the substrate, it is more to form a patterning on the buffer layer
Crystal silicon active layer；
S22, form the gate insulating layer for covering the patterned polysilicon silicon active layer, on the gate insulating layer according to
Sequence forms a first metal layer and a second metal layer；
S23, it is coated with photoresist in the second metal layer, obtains corresponding to the patterned polysilicon after exposed, display
A patterning photoresist layer of top in the middle part of silicon active layer；
S24, using the patterning photoresist layer as shielding layer, to the second metal layer carry out first time etching so that erosion
The line width of the second metal layer after quarter is less than the line width of the patterning photoresist layer after etching；
S25, using the patterning photoresist layer as shielding layer, second is carried out to the first metal layer and is etched, described the
Second etch and the edge for being ashed the patterning photoresist layer, so that the line width of the first metal layer after etching is greater than described
The line width of second metal layer, the line width generally phase of the line width and the second metal layer of the patterning photoresist layer after ashing
Together,；
S26, using the second metal layer and the first metal layer as shielding layer, to the patterned polysilicon silicon active layer
It is ion implanted, obtains being located in the middle part of the patterned polysilicon silicon active layer and correspond to the channel region of the patterning photoresist layer
Two heavily doped regions on the outside of two lightly doped regions, described two lightly doped regions on the outside of domain, the channel region；And
S27, removing remove the patterning photoresist layer.
The method of production LTPS TFT substrate according to the present invention, forms a figure on the buffer layer in the step s 21
The step of case polysilicon active layer includes:
An amorphous silicon layer is formed on the buffer layer；
Quasi-molecule laser annealing processing is carried out to the amorphous silicon layer, the amorphous silicon layer is formed as into a polysilicon
Layer；And
The polysilicon layer is patterned, to form the patterned polysilicon silicon active layer.
The method of production LTPS TFT substrate according to the present invention, the material of the first metal layer are tin indium oxide
(Indium Tin Oxide, ITO), the material of the second metal layer are aluminium (Al).
The method of production LTPS TFT substrate according to the present invention, the first time are etched to wet etching, and described second
It is etched to dry ecthing.
The method of production LTPS TFT substrate according to the present invention, it is active to the patterned polysilicon in the step S6
The ion implantation that layer is carried out is N-type ion implantation or P-type ion implantation.
The present invention proposes a kind of method for making LTPS TFT substrate.By carrying out gradation etching to more metal layers, and
Using dry ecthing come the edge of ashing pattern photoresist layer so that etching be ashed after the more metal layers formed it is ladder-like
Structure, then patterned polysilicon silicon active layer is ion implanted using this step structure as shielding layer obtains channel region, light
Doped region, heavily doped region.Compared to the prior art, the present invention, which is formed by step structure, has autoregistration effect, because
This alignment precision is high, not will cause the offset of doping deviation or area of grid.In addition, the present invention reduces by one of light shield, and it is not required to
Half-tone mask plate (Half Tone Mask, HTM) is used, reduce the manufacturing cost of production LTPS TFT substrate.
Detailed description of the invention
Figure 1A to 1H is the manufacturing process according to a kind of method for making LTPS TFT substrate of the embodiment of the present invention one.
Fig. 2A to 2H is the manufacturing process according to a kind of method for making LTPS TFT substrate of the embodiment of the present invention two.
Specific embodiment
The explanation of following embodiment is to can be used to the particular implementation of implementation to illustrate the present invention with reference to additional schema
Example.The direction term that the present invention is previously mentioned, such as "upper", "lower", "front", "rear", "left", "right", "inner", "outside", " side "
Deng being only the direction with reference to annexed drawings.Therefore, the direction term used be to illustrate and understand the present invention, rather than to
The limitation present invention.The similar unit of structure is to be given the same reference numerals in the figure.
The present invention proposes a kind of production low-temperature polysilicon film transistor (Low Temperature
Polycrystalline Silicon Thin-Film Transistor, LTPS TFT) substrate method.By to multilayer gold
Belong to layer and carry out gradation etching, and using dry ecthing come the edge of ashing pattern photoresist layer so that etching be ashed after it is described
More metal layers form step structure, then carry out ion to patterned polysilicon silicon active layer using this step structure as shielding layer
Implantation, obtains channel region, lightly doped region, heavily doped region.Compared to the prior art, the present invention is formed by ladder-like knot
Structure has autoregistration effect, therefore alignment precision is high, not will cause the offset of doping deviation or area of grid.In addition, of the invention
It reduces by one of light shield, and does not need to reduce production LTPS TFT base using half-tone mask plate (Half Tone Mask, HTM)
The manufacturing cost of plate.
There are two types of embodiments for present invention tool, and detailed description are as follows.
Embodiment one
Figure 1A is please referred to 1H.Figure 1A to 1H is a kind of side for making LTPS TFT substrate according to the embodiment of the present invention one
The manufacturing process of method.It the described method comprises the following steps.
Firstly, as shown in Figure 1A, in step s 11, providing a substrate 10, forming a buffer layer on the substrate 10
11, a patterned polysilicon silicon active layer 12 is formed on the buffer layer 11.
It can use commonly known technique in the technical field of the invention and form the patterned polysilicon silicon active layer
12, for example, the step of forming patterned polysilicon silicon active layer 12 may include:
An amorphous silicon layer is formed on the buffer layer 11；
Quasi-molecule laser annealing (Excimer Laser Annealing, ELA) processing is carried out to the amorphous silicon layer, with
The amorphous silicon layer is formed as into a polysilicon layer；And
The polysilicon layer is patterned, to form the patterned polysilicon silicon active layer 12.
Secondly, as shown in Figure 1B, in step s 12, forming the grid for covering the patterned polysilicon silicon active layer 12
Insulating layer 13 sequentially forms a first metal layer (bottom metal layer) 141 and one second metal on the gate insulating layer 13
Layer (top layer metallic layer) 142.In the present embodiment, the material of the first metal layer 141 is molybdenum (Mo) or molybdenum titanium alloy
(MoTi), the material of the second metal layer 142 is copper (Cu).
Then, as shown in Figure 1 C, in step s 13, photoresist, exposed, display are coated in the second metal layer 142
The patterning photoresist layer 15 for corresponding to the 12 middle part top of patterned polysilicon silicon active layer is obtained afterwards.
It then, as shown in figure iD, is shielding layer with the patterning photoresist layer 15, to first gold medal in step S14
Belong to layer 141 and the second metal layer 142 carries out first time etching, wherein the etch-rate of the second metal layer 142 is greater than
The etch-rate of the first metal layer 141, so that the line width of the second metal layer 102 after etching is less than the institute after etching
State the line width of the first metal layer 101.
In a preferred embodiment, the first time is etched to wet etching, bottom metal layer 141 and top layer metallic layer
142 form step structure after wet etching, as shown in figure iD.It can be formed to realize metal layer after wet etching ladder-like
Structure, it is molybdenum (Mo) to material that the wet etching acid solution that ingredient includes hydrogen peroxide, ammonium salt, malic acid etc., which can be used, to come or molybdenum titanium closes
The bottom metal layer 141 and material of golden (MoTi) are that the top layer metallic layer 142 of copper (Cu) carries out wet etching simultaneously.Due to described wet
It etches acid solution and the etch-rate of molybdenum (Mo) or molybdenum titanium alloy (MoTi) is compared faster to the etch-rate of copper (Cu), therefore underlying metal
Layer 141 forms step structure with top layer metallic layer 142 after wet etching.
Later, as referring to figure 1E, in step S15, the patterning photoresist layer 15 is ashed using second of etching
Edge, so that the line width of the line width and the second metal layer 102 of the patterning photoresist layer 15 after ashing is substantially the same.
In a preferred embodiment, described to be etched to dry ecthing for the second time.For example, second etching include with
Oxygen (O2) come be ashed it is described patterning photoresist layer 15 edge.
Further, as shown in fig. 1F, in step s 16, with the second metal layer 102 and the first metal layer 101
For shielding layer, ion implantation 1000 is carried out to the patterned polysilicon silicon active layer 12, obtains being located at the patterned polysilicon
It is two light on the outside of the channel region 161 of 12 middle part of active layer and the corresponding patterning photoresist layer 15, the channel region 161
Two heavily doped regions 163 on the outside of doped region 162, described two lightly doped regions 162.
The ion implantation carried out in the step S16 to the patterned polysilicon silicon active layer can be N-type ion plant
Enter or P-type ion is implanted into.Specifically, the production method of LTPS TFT substrate of the invention is suitable for NMOS type and pmos type simultaneously
LTPS TFT substrate.By taking NMOS type LTPS TFT substrate as an example, ion that the patterned polysilicon silicon active layer 12 is carried out
Implantation is N-type ion doping, and the ion mixed is phosphorus (P) ion or other N-type element ions.Similarly, for pmos type
For LTPS TFT substrate, the ion implantation carried out to the patterned polysilicon silicon active layer 12 is P-type ion doping, is mixed
The ion entered is boron (B) ion or other p-type element ions.
Come again, as shown in Figure 1 G, in step S17, removing removes the patterning photoresist layer 15.
Finally, as shown in fig. 1H, in step S18, forming remaining composition part of entire LTPS TFT, and form pixel
Electrode.For example, can be initially formed interbedded insulating layer (Interlayer Dielectric, ILD) 17 covers the second metal layer
102, the first metal layer 101, the gate insulating layer 13.Then, in the interlayer insulating film 17 and the gate insulator
Aperture 171 is formed in layer 13, and deposits a source/drain layer 18, and the source/drain layer 18 is made to fill up the aperture 171.Then,
A flatness layer 19 is deposited on the source/drain layer 18 and the interlayer insulating film 17.Finally, forming a pixel by patterning
Electrode 50, the pixel electrode 50 connect the source/drain layer 18.
Embodiment two
A to 2H referring to figure 2..Fig. 2A to 2H is a kind of side for making LTPS TFT substrate according to the embodiment of the present invention two
The manufacturing process of method.It the described method comprises the following steps.
Firstly, as shown in Figure 2 A, in the step s 21, providing a substrate 10, forming a buffer layer on the substrate 10
11, a patterned polysilicon silicon active layer 12 is formed on the buffer layer 11.
It can use commonly known technique in the technical field of the invention and form the patterned polysilicon silicon active layer
12, for example, the step of forming patterned polysilicon silicon active layer 12 may include:
An amorphous silicon layer is formed on the buffer layer 11；
Quasi-molecule laser annealing (Excimer Laser Annealing, ELA) processing is carried out to the amorphous silicon layer, with
The amorphous silicon layer is formed as into a polysilicon layer；And
The polysilicon layer is patterned, to form the patterned polysilicon silicon active layer 12.
Secondly, as shown in Figure 2 B, in step S22, forming the grid for covering the patterned polysilicon silicon active layer 12
Insulating layer 13 sequentially forms a first metal layer (bottom metal layer) 141 and one second metal on the gate insulating layer 13
Layer (top layer metallic layer) 142.In the present embodiment, the material of the first metal layer 141 is tin indium oxide (Indium Tin
Oxide, ITO), the material of the second metal layer 142 is aluminium (Al).
Then, as shown in Figure 2 C, in step S23, photoresist, exposed, display are coated in the second metal layer 142
The patterning photoresist layer 15 for corresponding to the 12 middle part top of patterned polysilicon silicon active layer is obtained afterwards.
It then, as shown in Figure 2 D, in step s 24, is shielding layer with the patterning photoresist layer 15, to second gold medal
Belong to layer 142 and carry out first time etching, so that the line width of the second metal layer 102 after etching is less than the pattern after etching
Change the line width of photoresist layer 15.
In a preferred embodiment, the first time is etched to wet etching.It includes nitric acid, phosphorus that ingredient, which can be used,
The wet etching acid solution of acid, acetic acid, water etc. to carry out wet etching to the top layer metallic layer 142 that material is aluminium (Al).The wet etching
Acid solution only can have etching action to the top layer metallic layer 142 that material is aluminium (Al), without being tin indium oxide (ITO) to material
Bottom metal layer 141 have etching action.
It later, as shown in Figure 2 E, in step s 25, is shielding layer with the patterning photoresist layer 15, to first gold medal
Belong to layer 141 and carries out second of etching, the edge etched for the second time and be ashed the patterning photoresist layer 15, so that after etching
The first metal layer 101 line width be greater than the second metal layer 102 line width, the patterning photoresist layer after ashing
The line width of 15 line width and the second metal layer 102 is substantially the same.
In a preferred embodiment, described to be etched to dry ecthing for the second time.For example, second of etching includes first
With oxygen (O2) come the first metal layer 141 described in dry ecthing, and it is ashed the edge of the patterning photoresist layer 15 later.
Bottom metal layer 141 forms after by first time, etching is etched with second ladder-like with top layer metallic layer 142
Structure, as shown in Figure 2 E.
Further, as shown in Figure 2 F, in step S26, with the second metal layer 102 and the first metal layer 101
For shielding layer, ion implantation 1000 is carried out to the patterned polysilicon silicon active layer 12, obtains being located at the patterned polysilicon
It is two light on the outside of the channel region 161 of 12 middle part of active layer and the corresponding patterning photoresist layer 15, the channel region 161
Two heavily doped regions 163 on the outside of doped region 162, described two lightly doped regions 162.
The ion implantation carried out in the step S26 to the patterned polysilicon silicon active layer can be N-type ion plant
Enter or P-type ion is implanted into.Specifically, the production method of LTPS TFT substrate of the invention is suitable for NMOS type and pmos type simultaneously
LTPS TFT substrate.By taking NMOS type LTPS TFT substrate as an example, ion that the patterned polysilicon silicon active layer 12 is carried out
Implantation is N-type ion doping, and the ion mixed is phosphorus (P) ion or other N-type element ions.Similarly, for pmos type
For LTPS TFT substrate, the ion implantation carried out to the patterned polysilicon silicon active layer 12 is P-type ion doping, is mixed
The ion entered is boron (B) ion or other p-type element ions.
Come again, as shown in Figure 1 G, in step s 27, removing removes the patterning photoresist layer 15.
Finally, as shown in fig. 1H, in step S28, forming remaining composition part of entire LTPS TFT, and form pixel
Electrode.For example, can be initially formed interbedded insulating layer (Interlayer Dielectric, ILD) 17 covers the second metal layer
102, the first metal layer 101, the gate insulating layer 13.Then, in the interlayer insulating film 17 and the gate insulator
Aperture 171 is formed in layer 13, and deposits a source/drain layer 18, and the source/drain layer 18 is made to fill up the aperture 171.Then,
A flatness layer 19 is deposited on the source/drain layer 18 and the interlayer insulating film 17.Finally, forming a pixel by patterning
Electrode 50, the pixel electrode 50 connect the source/drain layer 18.
Above-described embodiment one and embodiment two are with two metal layers (i.e. bottom metal layer 141 and top layer metallic layer
142) concept of the present invention is illustrated for, illustrates how to be ion implanted by the metal layer with step structure, with shape
At the channel region 161, lightly doped region 162, heavily doped region 163 of patterned polysilicon silicon active layer 12.However, the present invention is not
It is limited to this.Metal layer quantity of the invention can also be three layers or more.As long as by etching by several times so that the multilayer is golden
Belonging to layer has step structure, and it is dense can to form different doping in patterned polysilicon silicon active layer 12 after being ion implanted
The region of degree solves the technical issues of doping deviation existing in the prior art or area of grid deviate whereby.
Compared to the prior art, the present invention proposes a kind of method for making LTPS TFT substrate.By to more metal layers
Gradation etching is carried out, and using dry ecthing come the edge of ashing pattern photoresist layer, so that etching and the multilayer after ashing
Metal layer forms step structure, then carries out ion plant to patterned polysilicon silicon active layer using this step structure as shielding layer
Enter, obtains channel region, lightly doped region, heavily doped region.Compared to the prior art, the present invention is formed by step structure
With autoregistration effect, therefore alignment precision is high, not will cause the offset of doping deviation or area of grid.In addition, the present invention subtracts
Few one of light shield, and do not need to reduce production LTPS TFT substrate using half-tone mask plate (Half Tone Mask, HTM)
Manufacturing cost.
In conclusion although the present invention has been disclosed above in the preferred embodiment, but above preferred embodiment is not to limit
The system present invention, those skilled in the art can make various changes and profit without departing from the spirit and scope of the present invention
Decorations, therefore protection scope of the present invention subjects to the scope of the claims.
Claims (10)
1. a kind of method for making LTPS TFT substrate, which comprises the following steps:
S11, a substrate is provided, forms a buffer layer on the substrate, forms a patterned polysilicon on the buffer layer
Active layer；
S12, the gate insulating layer for covering the patterned polysilicon silicon active layer is formed, on the gate insulating layer sequentially shape
At a first metal layer and a second metal layer；
S13, it is coated with photoresist in the second metal layer, obtains having corresponding to the patterned polysilicon after exposed, display
A patterning photoresist layer of top in the middle part of active layer；
S14, using the patterning photoresist layer as shielding layer, the first metal layer and the second metal layer are carried out for the first time
Etching, wherein the etch-rate of the second metal layer is greater than the etch-rate of the first metal layer, so that the institute after etching
The line width for stating second metal layer is less than the line width of the first metal layer after etching；
S15, the edge that the patterning photoresist layer is ashed using second of etching, so that the patterning photoresist after ashing
The line width of the line width and the second metal layer of layer is substantially the same；
S16, using the second metal layer and the first metal layer as shielding layer, the patterned polysilicon silicon active layer is carried out
Ion implantation, obtain being located in the middle part of the patterned polysilicon silicon active layer and the channel region of the corresponding patterning photoresist layer,
Two heavily doped regions on the outside of two lightly doped regions, described two lightly doped regions on the outside of the channel region；And
S17, removing remove the patterning photoresist layer.
2. the method for production LTPS TFT substrate according to claim 1, which is characterized in that in step s 11 described
A step of patterned polysilicon silicon active layer is formed on buffer layer include:
An amorphous silicon layer is formed on the buffer layer；
Quasi-molecule laser annealing processing is carried out to the amorphous silicon layer, the amorphous silicon layer is formed as into a polysilicon layer；And
The polysilicon layer is patterned, to form the patterned polysilicon silicon active layer.
3. the method for production LTPS TFT substrate according to claim 1, which is characterized in that the material of the first metal layer
Matter is molybdenum (Mo) or molybdenum titanium alloy (MoTi), and the material of the second metal layer is copper (Cu).
4. the method for production LTPS TFT substrate according to claim 3, which is characterized in that the first time is etched to wet
Etching, it is described to be etched to dry ecthing for the second time.
5. the method for production LTPS TFT substrate according to claim 1, which is characterized in that described in the step S6
The ion implantation that patterned polysilicon silicon active layer is carried out is N-type ion implantation or P-type ion implantation.
6. a kind of method for making LTPS TFT substrate, which comprises the following steps:
S21, a substrate is provided, forms a buffer layer on the substrate, forms a patterned polysilicon on the buffer layer
Active layer；
S22, the gate insulating layer for covering the patterned polysilicon silicon active layer is formed, on the gate insulating layer sequentially shape
At a first metal layer and a second metal layer；
S23, it is coated with photoresist in the second metal layer, obtains having corresponding to the patterned polysilicon after exposed, display
A patterning photoresist layer of top in the middle part of active layer；
S24, using the patterning photoresist layer as shielding layer, to the second metal layer carry out first time etching so that etching after
The second metal layer line width be less than etching after the patterning photoresist layer line width；
S25, using the patterning photoresist layer as shielding layer, second is carried out to the first metal layer and is etched, described second
The edge for etching and being ashed the patterning photoresist layer, so that the line width of the first metal layer after etching is greater than described second
The line width of the line width of metal layer, the line width and the second metal layer of the patterning photoresist layer after ashing is substantially the same,；
S26, using the second metal layer and the first metal layer as shielding layer, the patterned polysilicon silicon active layer is carried out
Ion implantation, obtain being located in the middle part of the patterned polysilicon silicon active layer and the channel region of the corresponding patterning photoresist layer,
Two heavily doped regions on the outside of two lightly doped regions, described two lightly doped regions on the outside of the channel region；And
S27, removing remove the patterning photoresist layer.
7. the method for production LTPS TFT substrate according to claim 6, which is characterized in that in the step s 21 described
A step of patterned polysilicon silicon active layer is formed on buffer layer include:
An amorphous silicon layer is formed on the buffer layer；
Quasi-molecule laser annealing processing is carried out to the amorphous silicon layer, the amorphous silicon layer is formed as into a polysilicon layer；And
The polysilicon layer is patterned, to form the patterned polysilicon silicon active layer.
8. the method for production LTPS TFT substrate according to claim 6, which is characterized in that the material of the first metal layer
Matter is tin indium oxide (Indium Tin Oxide, ITO), and the material of the second metal layer is aluminium (Al).
9. the method for production LTPS TFT substrate according to claim 8, which is characterized in that the first time is etched to wet
Etching, it is described to be etched to dry ecthing for the second time.
10. the method for production LTPS TFT substrate according to claim 6, which is characterized in that institute in the step S6
Stating the ion implantation that patterned polysilicon silicon active layer is carried out is N-type ion implantation or P-type ion implantation.
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