CN106601822A - Thin-film transistor and preparation method thereof - Google Patents
Thin-film transistor and preparation method thereof Download PDFInfo
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- CN106601822A CN106601822A CN201611198824.XA CN201611198824A CN106601822A CN 106601822 A CN106601822 A CN 106601822A CN 201611198824 A CN201611198824 A CN 201611198824A CN 106601822 A CN106601822 A CN 106601822A
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- 239000010409 thin film Substances 0.000 title claims abstract description 32
- 238000002360 preparation method Methods 0.000 title claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 72
- 229920005591 polysilicon Polymers 0.000 claims abstract description 62
- 238000000034 method Methods 0.000 claims abstract description 40
- 229910052751 metal Inorganic materials 0.000 claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- 238000009413 insulation Methods 0.000 claims description 51
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 239000002019 doping agent Substances 0.000 claims description 10
- 150000002500 ions Chemical class 0.000 claims description 9
- 239000013078 crystal Substances 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 8
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- -1 cushion Substances 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 5
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 4
- 238000004380 ashing Methods 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 3
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- 238000001259 photo etching Methods 0.000 claims description 3
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- 238000005265 energy consumption Methods 0.000 description 4
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
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- 238000010276 construction Methods 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
- H01L2029/42388—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor characterised by the shape of the insulating material
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a low-temperature polysilicon thin-film transistor which comprises a substrate, a buffering layer, a polysilicon layer, a semiconductor layer, a gate insulating layer, a metal gate electrode layer, an interconnecting layer and source-and-drain electrodes, wherein the substrate, the buffering layer, the polysilicon layer, the semiconductor layer, the gate insulating layer, the metal gate electrode layer, the interconnecting layer and the source-and-drain electrodes are successively arranged from bottom to top. The source-and-drain electrodes successively penetrate through the interconnecting layer and the gate insulating layer and are connected with the semiconductor layer, wherein the semiconductor layer comprises a polysilicon region, a source-and-drain electrode contact region and a lightly doped region, wherein the source-and-drain electrode contact region and the lightly doped region are formed through ion doping. The lightly doped region is arranged between the polysilicon layer and the source-and-drain electrode contact region. The source-and-drain electrodes are connected with the source-and-drain electrode contact region. The gate insulating layer has different thicknesses in a height direction and is step-shaped. The high step portion of the gate insulating layer faces the lightly doped region. The low step portion of the gate insulating layer faces the source-and-drain electrode contact region. The thin-film transistor and the preparation method have advantages of reducing number of light shields, reducing production cost reduction, reducing process steps, and saving process time. Furthermore the low-temperature polysilicon thin-film transistor with low cost is realized in a real sense.
Description
Technical field
The present invention relates to the manufacture craft field of thin film transistor (TFT), more particularly to a kind of thin film transistor (TFT) and its preparation side
Method.
Background technology
Low-temperature polysilicon silicon technology (Low Temperature Poly-silicon, LTPS) is initially to reduce notebook
The energy consumption of computer display screen, makes notebook computer seem technology that is thinner lighter and researching and developing, about in nineteen nineties
Mid-term starts to move towards the trial period.With the development of FPD, high-resolution, the panel demand of low energy consumption is constantly suggested.
Low temperature polycrystalline silicon (Low Temperature Poly-Silicon, LTPS) due to higher electron mobility, and in liquid
Crystal display (Liquid Crystal Display, LCD) and organic light emitting diode display Organic Light
Emitting Diode, OLED) attention of industry has been obtained in technology, it is considered to realize that inexpensive full color flat panel shows important
Material.For FPD, there is fast high-resolution, reaction speed, high brightness, high opening using low-temperature polysilicon silicon materials
The advantages of rate, low energy consumption, and low temperature polycrystalline silicon can make at low temperature, and can be used to make C-MOS circuits, thus it is extensive
Research, to reach panel high-resolution, the demand of low energy consumption.
Low temperature polycrystalline silicon is a branch of polysilicon (poly-Si) technology.The molecular structure of polysilicon is in a crystal grain
In ordered state be neat and directive, therefore electron mobility is than arranging the fast 200- of mixed and disorderly non-crystalline silicon (a-Si)
300 times, greatly improve the reaction speed of FPD.
The technology of low temperature polycrystalline silicon referred to less than at a temperature of 600 DEG C, and on substrate even plastic base polycrystalline is generated
The technique of silicon thin film, it is a branch of polycrystalline silicon technology.For display manufacturing, there is many using polycrystalline silicon material
A little, as thin film circuit can do it is less thinner, power consumption is more low.
At the initial stage of polycrystalline silicon technology development, in order to substrate is changed into into polysilicon structure from amorphous silicon structures (a-Si)
(P-Si), just must be by the high-temperature oxidation procedure of one laser annealing, now the temperature of substrate will be more than 1000 DEG C.Many institute's weeks
Know, simple glass will soften at these elevated temperatures melting, cannot normally use at all, and only quartz glass can be handled so
High-temperature process.And quartz glass is not only expensive and size is all smaller, it is impossible to as the panel of display, therefore, it is right
The research of low-temperature polysilicon silicon technology is particularly important.
Because high-order display screen is constantly favored by people so that low-temperature polysilicon film transistor (LTPS-TFT) is no
It is disconnected to grow development.But relative to amorphous silicon film transistor (a-Si TFT), LTPS TFT processing procedures and technique are more complicated, such as
What Simplified flowsheet further reduces production cost becomes its object paid close attention to.
The content of the invention
The technical problem to be solved is the preparation method processing step of current low-temperature polysilicon film transistor
Complexity, process time length, light shield number are more and production cost is high.
In order to solve above-mentioned technical problem, the invention provides a kind of low-temperature polysilicon film transistor and its preparation side
Method.
According to the first aspect of the invention, there is provided a kind of low-temperature polysilicon film transistor, it is from bottom to up successively
Including substrate, cushion, semiconductor layer, gate insulation layer, metal gate electrode layer, interconnection layer and source-drain electrode, the source-drain electrode is successively
Connect with the semiconductor layer through the interconnection layer and the gate insulation layer, wherein, the semiconductor layer include multi-crystal silicon area,
Source-drain electrode contact zone and lightly doped district that Jing ion dopings are formed respectively, the lightly doped district is located at the polysilicon layer and institute
State between source-drain electrode contact zone, the source-drain electrode connects with the source-drain electrode contact zone；
The gate insulation layer has in the height direction different-thickness and is stepped, the high end difference of the gate insulation layer
Relative with the lightly doped district, the low end difference of the gate insulation layer is relative with the source-drain electrode contact zone.
Thin film transistor (TFT) as above, wherein, between the high end difference of the gate insulation layer and the low end difference
Ladder spacing is d, and by adjusting the size of the ladder spacing d lightly doped district and the source-drain electrode contact zone are adjusted
Interior ion concentration is poor.
Thin film transistor (TFT) as above, wherein, the dopant dose of the source-drain electrode contact zone is 1015cm-2, it is described
The dopant dose of lightly doped district is 1013cm-2。
Thin film transistor (TFT) as above, wherein, the dopant is nitrogen dopant.
The present invention solves the committed step of above-mentioned technical problem：The gate insulation layer is etched in using dry carving technology to exist
Performing etching in short transverse makes it that stairstepping is presented, and ladder spacing is d.
According to the second aspect of the invention, there is provided a kind of manufacture method of thin film transistor (TFT), it is comprised the following steps：
S101, on substrate buffer layer；
S102, on the cushion deposition of amorphous silicon layers；The amorphous silicon layer is made annealing treatment, so that described non-
Crystal silicon layer is changed into polysilicon layer；
Deposit on S103, the region not covered by the polysilicon layer on the polysilicon layer and on the cushion
Gate insulation layer；
S104, on described gate insulation layer deposited metal gate electrode layer；
S105, the metal gate electrode layer zone line deposit photoresist layer；
S106, adopted wet-etching technique to etch the metal gate electrode layer, by controlling etch period, made the metal gate
The electrode layer waste that size is inside contracted compared with the photoresist layer thereon is L, and the scope of L is between 0 to 1.5um；
S107, the gate insulation layer to exposing carry out dry etching, by controlling etch period, make the gate insulation layer exist
It is stepped in short transverse, the ladder spacing between the high end difference of the gate insulation layer and the low end difference is d；
S108, realized using the ladder-type structure of the gate insulator by carrying out Nitrogen ion to the polysilicon layer
Doping, while source-drain electrode contact zone and lightly doped district are formed respectively at the two ends of the polysilicon layer, the gate insulation layer
High end difference is relative with the lightly doped district, and the low end difference of the gate insulation layer is relative with the source-drain electrode contact zone；
S109：Interconnection layer is set on the metal gate electrode layer, is formed with the interconnection layer and is extended to the source and drain
The via structure in electrode contact area；
S110：Source-drain electrode is formed on the interconnection layer, the source-drain electrode is by the via structure and the source
Drain electrode contact zone connects.
The preparation method of thin film transistor (TFT) as above, wherein, in step S101, the cushion includes being arranged at
Silicon buffer layer and the silica cushion being arranged on the nitridation silicon buffer layer are nitrogenized on the substrate.
The preparation method of thin film transistor (TFT) as above, wherein, also there is step between step S102 and step S103
Rapid S1021, wherein,
S1021, carry out photoetching to the polysilicon layer to form patterned polysilicon layer.
The preparation method of thin film transistor (TFT) as above, wherein, also there is step between step S1021 step S103
S1022, wherein, boron doping is carried out to the raceway groove on the patterned polysilicon layer surface.
The preparation method of thin film transistor (TFT) as above, wherein, in step S105, by exposure machine to the photoresistance
Layer carries out patterned process, then carries out baking process to the photoresist layer.
The preparation method of thin film transistor (TFT) as above, wherein, also deposit between step S108 and step S109
In step S1081, wherein,
S1081, ashing process is carried out to the photoresist layer.
Compared with prior art, one or more embodiments in such scheme can have the advantage that or beneficial effect
Really：
The present invention is larger based on wet etching waste, and the less feature of dry etching waste, by photoresistance exposure, wet etching and dry
The method that quarter combines so that insulating barrier forms in the height direction certain step difference, is carried out to P-Si based on hierarchic structure
Primary ions are injected and form source and drain contact zone and the different work(of lightly doped region (lightly drain doping, LDD) two
The purpose in energy region, simplifies making technology.
The present invention with reference to wet etching and dry etching process characteristic, by light shield technique complete source-drain electrode contact zone with
The definition in LDD region domain, compared with traditional handicraft 1 road light shield is reduced.
Other features and advantages of the present invention will illustrate in the following description, and partly become from specification
It is clear that or being understood by implementing the present invention.The purpose of the present invention and other advantages can be by wanting in specification, right
Seek structure specifically noted in book and accompanying drawing to realize and obtain.
Description of the drawings
Accompanying drawing is used for providing a further understanding of the present invention, and constitutes a part for specification, the reality with the present invention
Apply example to be provided commonly for explaining the present invention, be not construed as limiting the invention.In the accompanying drawings：
Fig. 1 shows the structural representation formed in the embodiment of the present invention after photoresist layer；
Fig. 2 shows the structural representation etched in the embodiment of the present invention after metal gate electrode layer；
Fig. 3 is shown in the embodiment of the present invention carries out the structural representation after dry etching to gate insulation layer；
Fig. 4 shows in the embodiment of the present invention after photoresistance ashing and is formed after source-drain electrode contact zone and lightly doped district
Structural representation；
Fig. 5 shows the structural representation of embodiment of the present invention low-temperature polysilicon film transistor.
In the accompanying drawings, identical part uses identical reference.Accompanying drawing is not according to actual ratio.
Specific embodiment
Describe embodiments of the present invention in detail below with reference to drawings and Examples, how the present invention is applied whereby
Technological means solving technical problem, and reach technique effect realize that process can fully understand and implement according to this.Need explanation
As long as not constituting conflict, each embodiment and each feature in each embodiment in the present invention can be combined with each other,
The technical scheme for being formed is within protection scope of the present invention.
To solve preparation method processing step complexity, process time length, the light shield of current low-temperature polysilicon film transistor
Number is more and the technological deficiency such as production cost height, embodiments provides a kind of low-temperature polysilicon film transistor.This
The low-temperature polysilicon film transistor of inventive embodiments mainly includes substrate, cushion, semiconductor layer, gate insulation layer, metal gate
Electrode layer, interconnection layer and source-drain electrode.
Fig. 1 shows the structural representation of embodiment of the present invention low-temperature polysilicon film transistor.As shown in figure 1, this reality
The low-temperature polysilicon film transistor for applying example it is critical only that：The gate insulation layer 104 is etched in height using dry carving technology
Performing etching on direction makes it that stairstepping is presented, and ladder spacing is d；
Further, realize that primary ions injection forms source-drain electrode contact zone 106 simultaneously by adjusting ladder spacing d
With lightly doped district 107；
Especially, semiconductor layer includes multi-crystal silicon area 103, source-drain electrode contact zone 106 and lightly doped district 107, multi-crystal silicon area
103 both sides form lightly doped district 107 by the position of the high stepcoverage of gate insulation layer 104, and dopant dose is 1013cm-2；
Especially, the outside of lightly doped district 107 forms source-drain electrode contact zone by the position of the low stepcoverage of gate insulation layer 104
106, dopant dose is 1015cm-2；
Further, the metal gate electrode layer 105 adopted wet-etching technique etching to obtain, and etching waste is L, L=0
～1.5；
Additionally, as shown in figure 5, embodiment of the present invention low-temperature polysilicon film transistor also includes substrate 101, is arranged at base
(semiconductor layer includes polysilicon layer 103, source and drain electricity for cushion 102 on plate 101, the semiconductor layer being arranged on cushion 102
Pole contact zone 106 and lightly doped district 107), the gate insulation layer 104 that is arranged on semiconductor layer and cushion 102, to be arranged at grid exhausted
Metal gate electrode layer 105 in edge layer 104, the interconnection layer being arranged on the gate insulation layer 104 and metal gate electrode layer 105
108 and the source-drain electrode 109 that is arranged on interconnection layer 108.
Substrate 101 is ceramic substrate, glass substrate or quartz base plate.
Gate insulator 104 can be composite insulation layer, specifically, by one first dielectric layer, one second dielectric layer and
3rd dielectric layer is constituted；The compactness of each layer dielectric layer increases successively according to the order formed in manufacture process, i.e. the first dielectric
The dielectric layers of layer the second dielectric layers of ＜ ＜ the 3rd；First dielectric layer is SiO2, the second dielectric layer is SiON, and the 3rd dielectric layer is
SiNx；Wherein the 3rd dielectric layer is used to stop aqueous vapor and metal ion, and the second dielectric layer is used to improving the first dielectric layer and the
Three dielectric interface contact continuities；
Further, the thickness of first dielectric layer is more than second dielectric layer；
Further, thickness of the thickness of first dielectric layer more than the 3rd dielectric layer；
The composite insulation layer of the present embodiment can also be four layers or five layers, it is ensured that the fine and close sexual intercourse of each dielectric layer is pressed
Increase successively according to the order formed in manufacture process.
Further, the material of metal gate electrode layer 105 includes：Tungsten, chromium, aluminium, molybdenum and copper.
Preferably, source-drain electrode contact hole is formed in the interconnection layer 108 and gate insulation layer 104.
Preferably, the polysilicon layer 103 is arranged at the zone line on cushion 102；
Preferably, the lightly doped district 107 is located at the both sides of polysilicon layer 103 on cushion 102；
Preferably, the source-drain electrode contact zone 106 is located at the both sides of lightly doped district 107 on cushion 102；
Preferably, the gate insulation layer 104 is arranged at polysilicon layer 103, lightly doped district 107 and source-drain electrode contact zone
With 106 groups of polysilicon layer 103, lightly doped district 107 and source-drain electrode contact zone on cushion 102 on the public domain of 106 compositions
Into the unlapped region in public domain on.
Preferably, the metal gate electrode layer 105 is arranged on gate insulation layer 104 and only covers gate insulation layer 104
Zone line；
Preferably, the interconnection layer 108 is arranged at metal gate electrode layer 105 and is not covered by metal gate electrode layer 105
Gate insulation layer 104 on.
Preferably, the source-drain electrode 1091 and 1092 is arranged on interconnection layer 108, and by being arranged at interconnection layer 108
Turn on the source-drain electrode contact hole on gate insulation layer 104 and source-drain electrode contact zone 106.
Preferably, the substrate 101 is ceramic substrate, glass substrate or quartz base plate.
Preferably, described cushion 102 is double-decker, and including the silicon nitride being arranged on substrate 101
(SiNx) cushion and be arranged at nitridation silicon buffer layer on silica (SiO2) cushion.
Cushion 102 can prevent the metal ion in substrate 101 from diffusing in thin film transistor (TFT) and affecting film crystal
The electrical property of pipe.
Preferably, the thickness of cushion 102 is between 1nm～25nm.
The embodiment of the present invention additionally provides a kind of manufacture method of low-temperature polysilicon film transistor, the manufacture of the present embodiment
Method is：Formed and interconnected including substrate 101, cushion 102, semiconductor layer, gate insulation layer 104, metal gate electrode layer 105 successively
Layer 108 and source-drain electrode 109 are in interior sandwich construction.
A kind of manufacture method of low-temperature polysilicon film transistor, it includes：
S1, offer substrate 101；Substrate 101 is glass substrate or ceramic substrate.
S2, on the substrate 101 buffer layer 102；Cushion 102 includes double-decker, and including being arranged at base
Silicon nitride (SiN on plate 101x) cushion and be arranged at nitridation silicon buffer layer on silica (SiO2) cushion, buffering
Layer 102 can prevent the metal ion in substrate 101 from diffusing in thin film transistor (TFT) and affecting the electrical property of thin film transistor (TFT).
Forming the concrete grammar of cushion 102 on the substrate 101 is：Deposited on the substrate 101 using chemical vapour deposition technique
Cushion 102.
S3, on the cushion 102 deposition of amorphous silicon layers, it is possible to use chemical vapour deposition technique is on cushion 102
Deposition of amorphous silicon layers；The amorphous silicon layer is heated, to reduce Determination of Hydrogen Content in Film；
S4, the amorphous silicon layer surface is cleaned to go the removal of impurity with ozone-water and hydrogen fluoride/ozone-water, and described
Amorphous silicon layer surface forms layer of silicon dioxide layer；
Amorphous silicon layer is carried out to cause the surface away from cushion 102 of amorphous silicon layer to form one layer of titanium dioxide after thermal oxide
Silicon layer, one layer of non-crystalline silicon in the upper surface of amorphous silicon layer is oxidized to form layer of silicon dioxide layer.
S5, the amorphous silicon layer is made annealing treatment, so that amorphous silicon layer is changed into polysilicon layer, to the polysilicon
Layer carries out photoetching, forms patterned polysilicon layer 103；
It is specially the method that amorphous silicon layer is changed into polysilicon layer：Laser quasi-molecule annealing is carried out to amorphous silicon layer
Or solid-phase crystallization is processed and makes amorphous silicon therein be polysilicon, so that amorphous silicon layer is changed into polysilicon layer 103.
S6, the raceway groove to the graphical polysilicon layer surface carry out boron doping, to adjust the low-temperature polysilicon film
The threshold voltage of transistor.
S7, clean the surface of the polysilicon layer 103 with ozone-water and hydrogen fluoride/ozone-water；
S8, using chemical vapour deposition technique on the polysilicon layer 103 and on cushion 102 not by polysilicon layer
Gate insulation layer 104 is deposited on 103 regions for covering；
S9, using physical vaporous deposition on described gate insulation layer 104 deposited metal gate electrode layer 105；
S10, the zone line in the metal gate electrode layer 105 by the way of spin coating or printing deposit photoresist layer 110,
Patterned process is carried out by exposure machine to be formed the pattern lightly doped district of photoresist layer 110 as shown in Figure 1 and then to enter photoresist layer 110
Dry after row, prevent photoresist layer 110 from deforming in subsequent technique.
S11, adopted wet-etching technique etch metal gate electrode layer 105, by control etch period, make metal gate electrode layer
The little pattern dimension of photoresist layer 110 thereon of 105 pattern dimensions, its waste is L, L=0～1.5um.
Using wet-etching technique etching metal gate electrode layer 105 after structure it is as shown in Figure 2.
S12, dry etching is carried out to gate insulation layer 104, by controlling etch period, make gate insulation layer 104 in the height direction
It is stepped, ladder spacing is d；The structure after dry etching is carried out to gate insulation layer 104 as shown in Figure 3.
S13, with reference to Fig. 3 and Fig. 4, ion doping is carried out to the polysilicon layer 103, using the rank of gate insulator 104
Trapezium structure realizing being injected by primary ions, while forming source-drain electrode contact zone 106 and lightly doped district 107；
More specifically, carrying out heavy doping to polysilicon layer by ion implantation apparatus, heavy doping adopts N doping, in polysilicon
The both sides of layer 103 form lightly doped district 107 by the position of the high stepcoverage of gate insulation layer 104, and N doping dosage is 1013cm-2；
Meanwhile, form source positioned at the outside of lightly doped district 107 and by the part of the low stepcoverage of gate insulation layer 104 in polysilicon layer 103
Drain electrode contact zone 106, N doping dosage is 1015cm-2。
Primary ions injection is carried out to P-Si based on hierarchic structure and realizes forming source and drain contact zone and lightly doped region
The purpose in (lightly drain doping, LDD) two difference in functionality regions.
S13, photoresist layer 110 is ashed by oxygen plasma；Photoresistance ashing after and formed source-drain electrode contact
Structure behind area 106 and lightly doped district 107 is as shown in Figure 4.
S14, as shown in figure 5, using chemical vapour deposition technique on the metal gate electrode layer 105 and not by metal gate electricity
Interconnection layer 108 is deposited on the gate insulation layer 104 that pole layer 105 is covered；It is engraved on interconnection layer 108 and gate insulation layer 104 by light and is made
It is standby to obtain source-drain electrode contact hole；
S15, on the interconnection layer 108 depositing metal membrane layer, and by being lithographically formed source-drain electrode as shown in Figure 5
109, to complete the making of this case thin film transistor (TFT).
Flatness layer (not shown) is set on the source-drain electrode 109 and interconnection layer 108 or other LCD or OLED are aobvious
Show structure, to complete the making of whole display floaters, specific making step is prior art, be will not be described here.
Although describing the present invention herein with reference to specific embodiment, it should be understood that, these realities
Apply the example that example is only principles and applications.It should therefore be understood that can carry out to exemplary embodiment
Many modifications, and other arrangements are can be designed that, without departing from the spirit of the invention that claims are limited
And scope.It should be understood that can be by way of different from described by original claim come with reference to different appurtenances
Profit is required and feature specifically described herein.It will also be appreciated that the feature with reference to described by separate embodiments can be used
In other described embodiments.
Claims (10)
1. a kind of thin film transistor (TFT), it is characterised in that it includes successively from bottom to up substrate, cushion, semiconductor layer, gate insulation
Layer, metal gate electrode layer, interconnection layer and source-drain electrode, the source-drain electrode sequentially passes through the interconnection layer and the gate insulation layer and institute
State semiconductor layer to connect, wherein, the semiconductor layer includes the source-drain electrode contact that multi-crystal silicon area, Jing ion dopings are formed respectively
Area and lightly doped district, the lightly doped district is located between the multi-crystal silicon area and the source-drain electrode contact zone, the source-drain electrode
Connect with the source-drain electrode contact zone；
The gate insulation layer has in the height direction different-thickness and is stepped, the high end difference of the gate insulation layer and institute
State lightly doped district relative, the low end difference of the gate insulation layer is relative with the source-drain electrode contact zone.
2. thin film transistor (TFT) as claimed in claim 1, it is characterised in that
Ladder spacing between the high end difference of the gate insulation layer and the low end difference is d, by adjusting between the ladder
Size away from d is poor to adjust the ion concentration in the lightly doped district and the source-drain electrode contact zone.
3. thin film transistor (TFT) as claimed in claim 1, it is characterised in that the dopant dose of the source-drain electrode contact zone is
1015cm-2, the dopant dose of the lightly doped district is 1013cm-2。
4. thin film transistor (TFT) as claimed in claim 1, it is characterised in that the dopant is nitrogen dopant.
5. a kind of preparation method of thin film transistor (TFT), it is characterised in that comprise the following steps：
S101, on substrate buffer layer；
S102, on the cushion deposition of amorphous silicon layers；The amorphous silicon layer is made annealing treatment, so that the non-crystalline silicon
Layer is changed into polysilicon layer；
Grid are deposited on S103, the region not covered by the polysilicon layer on the polysilicon layer and on the cushion exhausted
Edge layer；
S104, on described gate insulation layer deposited metal gate electrode layer；
S105, the metal gate electrode layer zone line deposit photoresist layer；
S106, adopted wet-etching technique to etch the metal gate electrode layer, by controlling etch period, made the metal gate electrode
The layer waste that size is inside contracted compared with the photoresist layer thereon is L, and the scope of L is between 0 to 1.5um；
S107, the gate insulation layer to exposing carry out dry etching, by controlling etch period, make the gate insulation layer in height
It is stepped on direction, the ladder spacing between the high end difference of the gate insulation layer and the low end difference is d；
S108, realize being mixed by carrying out Nitrogen ion to the polysilicon layer using the ladder-type structure of the gate insulator
It is miscellaneous, while forming source-drain electrode contact zone and lightly doped district, the height of the gate insulation layer respectively at the two ends of the polysilicon layer
End difference is relative with the lightly doped district, and the low end difference of the gate insulation layer is relative with the source-drain electrode contact zone；
S109, on the metal gate electrode layer interconnection layer is set, is formed with the interconnection layer and extends to the source-drain electrode
The via structure of contact zone；
S110, source-drain electrode is formed on the interconnection layer, the source-drain electrode is by the via structure and source and drain electricity
Pole contact zone connects.
6. it is described according to the preparation method of the thin film transistor (TFT) described in claim 5, it is characterised in that in step S101
Cushion includes the nitridation silicon buffer layer being arranged on the substrate and the titanium dioxide being arranged on the nitridation silicon buffer layer
Silicon buffer layer.
7. according to the preparation method of the thin film transistor (TFT) described in claim 5, it is characterised in that in step S102 and step
Also there is step S1021 between S103, wherein,
S1021, carry out photoetching to the polysilicon layer to form patterned polysilicon layer.
8. according to the preparation method of the thin film transistor (TFT) described in claim 7, it is characterised in that in step S1021 step
Also there is step S1022 between S103, wherein, boron doping is carried out to the raceway groove on the patterned polysilicon layer surface.
9., according to the preparation method of the thin film transistor (TFT) described in claim 5, it is characterised in that in step S105, pass through
Exposure machine carries out patterned process to the photoresist layer, then carries out baking process to the photoresist layer.
10. the preparation method of the thin film transistor (TFT) according to any one in claim 5 to 9, it is characterised in that described
Also there is step S1081 between step S108 and step S109, wherein,
S1081, ashing process is carried out to the photoresist layer.
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