CN106449655A - Thin film transistor array substrate and manufacturing method thereof - Google Patents
Thin film transistor array substrate and manufacturing method thereof Download PDFInfo
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- CN106449655A CN106449655A CN201610908930.6A CN201610908930A CN106449655A CN 106449655 A CN106449655 A CN 106449655A CN 201610908930 A CN201610908930 A CN 201610908930A CN 106449655 A CN106449655 A CN 106449655A
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- 239000010409 thin film Substances 0.000 title claims abstract description 50
- 239000000758 substrate Substances 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 24
- 238000005530 etching Methods 0.000 claims abstract description 10
- 239000010410 layer Substances 0.000 claims description 215
- 238000000034 method Methods 0.000 claims description 41
- 239000011229 interlayer Substances 0.000 claims description 25
- 239000012212 insulator Substances 0.000 claims description 24
- 229920005591 polysilicon Polymers 0.000 claims description 22
- 238000002161 passivation Methods 0.000 claims description 19
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 10
- 230000008569 process Effects 0.000 claims description 9
- 230000004888 barrier function Effects 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 4
- 238000005224 laser annealing Methods 0.000 claims description 4
- 238000006356 dehydrogenation reaction Methods 0.000 claims description 3
- 230000003139 buffering effect Effects 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 230000007547 defect Effects 0.000 abstract description 14
- 238000002425 crystallisation Methods 0.000 abstract description 6
- 230000008025 crystallization Effects 0.000 abstract description 6
- 238000000206 photolithography Methods 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 description 16
- 238000010586 diagram Methods 0.000 description 8
- 229920001621 AMOLED Polymers 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 239000010408 film Substances 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- -1 phosphonium ion Chemical class 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- CKHJYUSOUQDYEN-UHFFFAOYSA-N gallium(3+) Chemical compound [Ga+3] CKHJYUSOUQDYEN-UHFFFAOYSA-N 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004040 coloring Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 239000004922 lacquer Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides a thin film transistor array substrate and a manufacturing method thereof. The manufacturing method of the thin film transistor array substrate is characterized by deposing a thicker amorphous silicon layer so that crystallization quality of a polycrystalline silicon layer acquired after crystallization processing is good; and then using a gray scale photomask photolithography to carry out thinning etching on a channel area of an active layer so that a thickness of the channel area of the active layer is reduced, the channel area possesses a less defect mode number and an output characteristic of a TFT device is increased. A source/drain electrode contact area maintains an original thick thickness so that a good conductive capability is kept and good contact between the source/drain electrode contact area and a source/drain electrode is guaranteed. By using the thin film transistor array substrate, the channel area of the active layer is set to be a thin thickness and the source/drain electrode contact area is set to be the thick thickness so that the channel area possesses the less defect mode number and the output characteristic of the TFT device is increased.
Description
Technical field
The present invention relates to display technology field, more particularly, to a kind of thin-film transistor array base-plate and preparation method thereof.
Background technology
With the development of Display Technique, the plane such as liquid crystal display (Liquid Crystal Display, LCD) display dress
Put because having the advantages that high image quality, power saving, fuselage be thin and applied range, and be widely used in mobile phone, TV, individual number
The various consumption electronic products such as word assistant, digital camera, notebook computer, desk computer, become the master in display device
Stream.
Organic LED display device (Organic Light Emitting Display, OLED) has spontaneous
Light, driving voltage are low, luminous efficiency is high, response time is short, definition and contrast is high, nearly 180 ° of visual angles, use temperature range
Many advantages, such as width, achievable Flexible Displays and large area total colouring, it is known as by industry being the display having development potentiality most
Device.
OLED according to type of drive can be divided into passive matrix OLED (Passive Matrix OLED, PMOLED) and
Active array type OLED (Active Matrix OLED, AMOLED) two big class, i.e. direct addressin and thin film transistor (TFT) (Thin
Film Transistor, TFT) matrix addressing two class.Wherein, AMOLED has the pixel of the arrangement in array, belongs to actively aobvious
Show type, luminous efficacy is high, is typically used as the large scale display device of fine definition.
LCD and AMOLED display floater generally have thin-film transistor array base-plate as shown in Figure 1, described film crystal
Underlay substrate 100 that pipe array base palte includes setting gradually from top to bottom, light shield layer 200, cushion 300, active layer 400, grid
Pole insulating barrier 500, grid 600, interlayer insulating film 700, source-drain electrode 800, flatness layer 900, public electrode 910, passivation layer 920,
And pixel electrode 930, described LCD and AMOLED display floater are by the TFT switch on thin-film transistor array base-plate and picture
Plain electrode 930 reaches the control to liquid crystal or OLED, thus realizing display effect.And it is more next with the requirement to display effect
Higher, active layer 400 gradually can not meet demand using the thin-film transistor array base-plate that non-crystalline silicon (a-Si) makes, and has more
The polysilicon (poly-Si) of high electron mobility becomes the routine techniquess making high-resolution display panel.And Poly-Si TFT
Output characteristics affected by the overall defect state number in the channel region 410 of active layer 400, the channel region 410 of active layer 400
In overall defect state number be equal to defect state density and channel region 410 volume product.In producing at this stage, Poly-Si is usual
It is to pass through quasi-molecule laser annealing (ELA) crystallization by a-Si to form, relatively thin a-Si layer is also easy to produce higher lacking after ELA crystallization
The sunken density of states, and thicker a-Si layer defect state density after ELA crystallization is relatively low, but the volume of channel region 410 can be made to increase,
Thus increasing the overall defect state number of channel region.
Content of the invention
It is an object of the invention to provide a kind of manufacture method of thin-film transistor array base-plate, channel region can be made to have
Less defect state number, the output characteristics of lifting TFT device.
The present invention also aims to providing a kind of thin-film transistor array base-plate, channel region has less defect state number
Mesh, TFT device has preferable output characteristics.
For achieving the above object, present invention firstly provides a kind of manufacture method of thin-film transistor array base-plate, including such as
Lower step：
Step 1, offer one underlay substrate, buffer layer on described underlay substrate, described cushion deposit non-
Crystal silicon layer, carries out Crystallizing treatment so as to be converted into polysilicon layer to described amorphous silicon layer；
Step 2, on described polysilicon layer formed photoresist layer, using a gray-level mask, described photoresist layer is exposed showing
Shadow, obtains a photoresistance figure, described photoresistance figure include two first photoresistance sections positioned at two ends and be located at two first photoresistance sections it
Between the second photoresistance section, the thickness of described first photoresistance section is more than the thickness of described second photoresistance section；
Step 3, with described photoresistance figure as etching barrier layer, described polysilicon layer is etched process, removes described
The region not covered by described photoresistance figure on polysilicon layer, obtains active layer；
Step 4, described photoresistance figure is etched process, removes and be located at the second middle photoresistance section, and thinning is located at
The first photoresistance section at two ends；
Step 5, with the first photoresistance section of two ends thinning as etching barrier layer, described active layer is etched process, make
The thickness thinning in the region between two first photoresistance sections is located on described active layer, forms channel region, corresponding on described active layer
Region below two first photoresistance sections forms source contact area and drain contact region respectively；
Peel off remaining first photoresistance section；
Step 6, the channel region to described active layer carry out p-type or N-type ion is lightly doped, and the source electrode of described active layer is connect
Tactile area and drain contact region carry out N-type or p-type ion heavy doping；
Step 7, on described active layer and cushion formed gate insulator, on described gate insulator formed correspond to
Grid above described active layer；
Interlayer dielectric layer is formed on described grid and gate insulator, on described interlayer dielectric layer with gate insulator
Formed and correspond respectively to the first through hole above described source contact area and drain contact region and the second through hole；
Source electrode and drain electrode formed on described interlayer dielectric layer, described source electrode and drain electrode pass through respectively described first through hole with
Second through hole is contacted with described source contact area and drain contact region.
Described step 1 also includes：Before buffer layer on described underlay substrate, described underlay substrate is formed and hides
Photosphere, described light shield layer is corresponding with the active layer being subsequently formed, and at least covers the channel region of described active layer.
The material of described light shield layer is metal, and described step 1 forms described light shield layer using physical vaporous deposition.
Described step 1 also includes：Before Crystallizing treatment is carried out to described amorphous silicon layer, described amorphous silicon layer is gone
Hydrogen is processed.
In described step 1, Crystallizing treatment is carried out to described amorphous silicon layer using quasi-molecule laser annealing method.
Optionally, the manufacture method of the thin-film transistor array base-plate of the present invention also includes step 8：In described source electrode, leakage
Form flatness layer on pole and interlayer dielectric layer, public electrode is formed on described flatness layer in described public electrode and flatness layer
Upper formation passivation layer；
Third through-hole above corresponding to described drain electrode is formed on described passivation layer and flatness layer；
Pixel electrode is formed on described passivation layer, described pixel electrode is connected with described drain electrode by described third through-hole
Touch.
The present invention also provides a kind of thin-film transistor array base-plate, including：Underlay substrate, on described underlay substrate
Cushion, located at the active layer on described cushion, the gate insulator on described active layer and cushion, located at described
Grid on gate insulator and above corresponding described active layer, the interlayer dielectric on described grid and gate insulator
Layer and the source electrode on described interlayer dielectric layer and drain electrode；
Described active layer is polysilicon layer, described active layer include source contact area positioned at two ends and drain contact region with
And it is located at the channel region between described source contact area and drain contact region；Described source contact area and the thickness of drain contact region
It is all higher than the thickness of described channel region；
Described interlayer dielectric layer and gate insulator are provided with and correspond respectively to described source contact area and drain contact region
The first through hole of top and the second through hole；Described source electrode and drain electrode are respectively by described first through hole and the second through hole and described source
Pole contact area and drain contact region contact.
Also include located at the light shield layer between described underlay substrate and cushion, described light shield layer is relative with described active layer
Should, and at least cover the channel region of described active layer.
The material of described light shield layer is metal, and described channel region is p-type or N-type ion lightly doped district, described source contact
Area and drain contact region are N-type or p-type ion heavily doped region.
Optionally, the thin-film transistor array base-plate of the present invention also includes：Located at described source electrode, drain electrode and interlayer dielectric
Flatness layer on layer, located at the public electrode on described flatness layer, the passivation layer on described public electrode and flatness layer, with
And the pixel electrode on described passivation layer；
Described passivation layer and flatness layer are provided with the third through-hole corresponding to described drain electrode top, and described pixel electrode passes through
Described third through-hole is contacted with described drain electrode.
Beneficial effects of the present invention：A kind of manufacture method of thin-film transistor array base-plate that the present invention provides, by heavy
Amass thicker amorphous silicon layer so that the crystalline quality of the polysilicon layer obtaining after Crystallizing treatment preferably, adopts GTG light afterwards
Lacquer finish lithography carries out thinning etching so that the thickness of the channel region of active layer is thinning to the channel region of active layer, so that ditch
Road area has less defect state number, the output characteristics of lifting TFT device, and source drain contact area maintains original thicker thickness
Degree, thus keep preferable conductive capability preferably contact it is ensured that having between source drain contact area and source/drain.The present invention
A kind of thin-film transistor array base-plate providing, by the channel region of active layer is set to relatively thin thickness, source/drain is connect
Tactile area is set to thicker thickness, so that channel region has less defect state number, lifts the output characteristics of TFT device,
Make source drain contact area keep preferable conductive capability it is ensured that having between source drain contact area and source/drain preferably simultaneously
Contact.
In order to be able to be further understood that feature and the technology contents of the present invention, refer to detailed below in connection with the present invention
Illustrate and accompanying drawing, but accompanying drawing only provides and uses with reference to explanation, is not used for the present invention is any limitation as.
Brief description
Below in conjunction with the accompanying drawings, by the specific embodiment detailed description to the present invention, technical scheme will be made
And other beneficial effects are apparent.
In accompanying drawing,
Fig. 1 is the structural representation of existing thin-film transistor array base-plate；
Fig. 2 is the flow chart of the manufacture method of thin-film transistor array base-plate of the present invention；
Fig. 3-4 is the schematic diagram of the step 1 of manufacture method of thin-film transistor array base-plate of the present invention；
Fig. 5-6 is the schematic diagram of the step 2 of manufacture method of thin-film transistor array base-plate of the present invention；
Fig. 7 is the schematic diagram of the step 3 of manufacture method of thin-film transistor array base-plate of the present invention；
Fig. 8 is the schematic diagram of the step 4 of manufacture method of thin-film transistor array base-plate of the present invention；
Fig. 9 is the schematic diagram of the step 5 of manufacture method of thin-film transistor array base-plate of the present invention；
Figure 10 is the schematic diagram of the step 6 of manufacture method of thin-film transistor array base-plate of the present invention；
Figure 11 is the schematic diagram of the step 7 of manufacture method of thin-film transistor array base-plate of the present invention；
Figure 12 is the thin of the schematic diagram of the step 8 of manufacture method of thin-film transistor array base-plate of the present invention and the present invention
The structural representation of film transistor array base palte.
Specific embodiment
For further illustrating the technological means and its effect that the present invention taken, being preferable to carry out below in conjunction with the present invention
Example and its accompanying drawing are described in detail.
Refer to Fig. 2, present invention firstly provides a kind of manufacture method of thin-film transistor array base-plate, walk including following
Suddenly：
Step 1, as shown in Figure 3-4, provides a underlay substrate 10, buffer layer on described underlay substrate 10
(Buffer Layer) 12, deposited amorphous silicon (a-Si) layer 13 on described cushion 12, crystalline substance is carried out to described amorphous silicon layer 13
Change and process so as to be converted into polysilicon (Poly-Si) layer 14.
Specifically, in described step 1, using plasma strengthens chemical vapour deposition technique (PECVD) and forms described buffering
Layer 12 and amorphous silicon layer 13.
Specifically, the material of described cushion 12 can be silicon oxide (SiOx), silicon nitride (SiNx) or combination.
Preferably, described step 1 also includes：Before buffer layer 12 on described underlay substrate 10, in described substrate
Form light shield layer (LS) 11 on substrate 10, described light shield layer 11 is corresponding with the active layer 30 being subsequently formed, and at least cover institute
Stating the channel region 31 of active layer 30, thus avoiding incident ray that the channel region 31 of described active layer 30 is impacted, making TFT's
Property retention is stable.
Specifically, the material of described light shield layer 11 is metal, and described metal includes molybdenum (Mo), aluminum (Al), copper (Cu), titanium
One or more of (Ti).Described step 1 forms described light shield layer 11 using physical vaporous deposition (PVD).
Preferably, described step 1 also includes：Before Crystallizing treatment is carried out to described amorphous silicon layer 13, to described amorphous
Silicon layer 13 carries out dehydrogenation.
Specifically, by rapid thermal anneal process (RTA, Rapid Thermal Annealing) to described amorphous silicon layer
13 carry out dehydrogenation.
Preferably, in described step 1, crystalline substance is carried out to described amorphous silicon layer 13 using quasi-molecule laser annealing (ELA) method
Change is processed.
Preferably, described underlay substrate 10 is glass substrate.
Step 2, as seen in figs. 5-6, forms photoresist layer 15, using a gray-level mask 16 to institute on described polysilicon layer 14
State photoresist layer 15 to be exposed developing, obtain a photoresistance figure 20, described photoresistance figure 20 includes two first light positioned at two ends
Resistance section 21 and be located at the second photoresistance section 22 between two first photoresistance sections 21, the thickness of described first photoresistance section 21 is more than described the
The thickness of two photoresistance sections 22.
Step 3 is as shown in fig. 7, with described photoresistance figure 20 as etching barrier layer, be etched to described polysilicon layer 14
Process, the region not covered by described photoresistance figure 20 is removed on described polysilicon layer 14, obtains active layer 30.
Step 4, as shown in figure 8, being etched to described photoresistance figure 20 processing, removes and is located at the second middle photoresistance section
22, and thinning is located at the first photoresistance section 21 at two ends.
Step 5 is as shown in figure 9, with the first photoresistance section 21 of two ends thinning as etching barrier layer, enter to described active layer 30
Row etch processes, make the thickness thinning in the region between two first photoresistance sections 21 on described active layer 30, form channel region
31, the region that described active layer 30 corresponds to two first photoresistance section 21 lower section forms source contact area 32 and drain contact respectively
Area 33；
Peel off remaining first photoresistance section 21.
Preferably, described source contact area 32 is identical with the thickness of drain contact region 33.
Step 6, as shown in Figure 10, carries out p-type to the channel region 31 of described active layer 30 or N-type ion is lightly doped, to institute
The source contact area 32 stating active layer 30 carries out N-type or p-type ion heavy doping with drain contact region 33.
Specifically, described step 6 includes four kinds of doped scheme：
Scheme 1, with drain contact region 33, n-type doping is carried out respectively to described channel region 31 and source contact area 32；
Scheme 2, with drain contact region 33, p-type doping is carried out respectively to described channel region 31 and source contact area 32；
Scheme 3, n-type doping is carried out to described channel region 31, with drain contact region 33, P is carried out to described source contact area 32
Type adulterates；
Scheme 4, p-type doping is carried out to described channel region 31, with drain contact region 33, N is carried out to described source contact area 32
Type adulterates.
Specifically, the p-type in described channel region 31 or N-type ion concentration range are 1016～1017ions/cm3, described source
N-type in pole contact area 32 and drain contact region 33 or p-type ion concentration range are 1019～1021ions/cm3.
Specifically, described N-type ion is phosphonium ion or arsenic ion；Described p-type ion is boron ion or gallium ion.
Step 7, as shown in figure 11, forms gate insulator (GI) 40, in institute on described active layer 30 and cushion 12
State the grid (GE) 41 that the described active layer of correspondence 30 top is formed on gate insulator 40；
Described grid 41 and gate insulator 40 form interlayer dielectric layer (ILD) 50, in described interlayer dielectric layer 50
Correspond respectively to the first through hole 51 of described source contact area 32 and drain contact region 33 top with formation on gate insulator 40
With the second through hole 52；
Source electrode (S) 61 and drain electrode (D) 62 are formed on described interlayer dielectric layer 50, described source electrode 61 and drain electrode 62 are led to respectively
Cross described first through hole 51 and the second through hole 52 is contacted with described source contact area 32 and drain contact region 33.
So far, complete a basic film transistor array base plate structure, for being applied to plane conversion (In-Plane
Switching, IPS) type display panels or fringe field switching (Fringe field switching, FFS) type liquid crystal
For the manufacture method of the thin-film transistor array base-plate in display floater, also include step 8：
As shown in figure 12, described source electrode 61, drain electrode 62 and interlayer dielectric layer 50 form flatness layer (PLN) 70, in institute
State and form public electrode (ITO-COM) 71 on flatness layer 70, passivation layer is formed on described public electrode 71 and flatness layer 70
(PV)80；
Third through-hole 83 above corresponding to described drain electrode 62 is formed on described passivation layer 80 and flatness layer 70；
Described passivation layer 80 forms pixel electrode (ITO-TOP) 90, described pixel electrode 90 is by described threeway
Hole 83 is contacted with described drain electrode 62.
Specifically, described public electrode 71 and the material of pixel electrode 90 are tin indium oxide (ITO).
The manufacture method of above-mentioned thin-film transistor array base-plate, by depositing thicker amorphous silicon layer 13 so that at crystallization
The crystalline quality of the polysilicon layer 14 obtaining after reason preferably, adopts the raceway groove to active layer 30 for the gray-level mask photoetching technique afterwards
Area 31 carries out thinning etching so that the thickness of the channel region 31 of active layer 30 is thinning, so that channel region 31 has less lacking
Sunken state number, the output characteristics of lifting TFT device, source drain contact area 32/33 maintains original thicker thickness, thus keeping
Preferably conductive capability preferably contacts it is ensured that having between source drain contact area 32/33 and source/drain 61/62.
Refer to Figure 12, based on the manufacture method of above-mentioned thin-film transistor array base-plate, the present invention also provides a kind of thin film
Transistor (TFT) array substrate, including：Underlay substrate 10, the cushion 12 on described underlay substrate 10, located at described cushion
Active layer 30 on 12, the gate insulator 40 on described active layer 30 and cushion 12, located at described gate insulator
On 40 and the grid 41 of the described active layer of correspondence 30 top, the interlayer dielectric layer on described grid 41 and gate insulator 40
50 and the source electrode 61 on described interlayer dielectric layer 50 and drain electrode 62；
Described active layer 30 is polysilicon layer, and described active layer 30 includes connecing with drain electrode positioned at the source contact area 32 at two ends
Tactile area 33 and be located at channel region 31 between described source contact area 32 and drain contact region 33；Described source contact area 32 with
The thickness of drain contact region 33 is all higher than the thickness of described channel region 31；
Described interlayer dielectric layer 50 is provided with gate insulator 40 and corresponds respectively to described source contact area 32 and drain electrode
The first through hole 51 of contact area 33 top and the second through hole 52；Described source electrode 61 and drain electrode 62 are respectively by described first through hole 51
Contact with described source contact area 32 and drain contact region 33 with the second through hole 52.
Preferably, described source contact area 32 is identical with the thickness of drain contact region 33.
Preferably, described thin-film transistor array base-plate is also included located between described underlay substrate 10 and cushion 12
Light shield layer 11, described light shield layer 11 is corresponding with described active layer 30, and at least covers the channel region 31 of described active layer 30.
Preferably, described underlay substrate 10 is glass substrate.
Specifically, the material of described light shield layer 11 is metal, and described metal includes one of molybdenum, aluminum, copper, titanium or many
Kind.
Specifically, the material of described cushion 12 can be silicon oxide, silicon nitride or combination.
Specifically, described channel region 31 is p-type or N-type ion lightly doped district, described source contact area 32 and drain contact
Area 33 is N-type or p-type ion heavily doped region.
Specifically, the p-type in described channel region 31 or N-type ion concentration range are 1016～1017ions/cm3, described source
N-type in pole contact area 32 and drain contact region 33 or p-type ion concentration range are 1019～1021ions/cm3.
Specifically, described N-type ion is phosphonium ion or arsenic ion；Described p-type ion is boron ion or gallium ion.
When described thin-film transistor array base-plate is applied to plane conversion type display panels or fringe field switching type
When in display panels, also include：
Located at described source electrode 61, drain electrode 62 and interlayer dielectric layer 50 on flatness layer 70, on described flatness layer 70
Public electrode 71, located at the passivation layer 80 on described public electrode 71 and flatness layer 70 and on described passivation layer 80
Pixel electrode 90；
Described passivation layer 80 and flatness layer 70 are provided with the third through-hole 83 corresponding to described drain electrode 62 top, described pixel
Electrode 90 is passed through described third through-hole 83 and is contacted with described drain electrode 62.
Specifically, described public electrode 71 and the material of pixel electrode 90 are tin indium oxide.
Above-mentioned thin-film transistor array base-plate, by the channel region 31 of active layer 30 is set to relatively thin thickness, by source/
Drain contact region 32/33 is set to thicker thickness, so that channel region 31 has less defect state number, lifts TFT device
The output characteristics of part, makes source drain contact area 32/33 keep preferable conductive capability it is ensured that source drain contact area 32/ simultaneously
Have between 33 with source/drain 61/62 and preferably contact.
In sum, the present invention provides a kind of thin-film transistor array base-plate and preparation method thereof.The thin film of the present invention is brilliant
The manufacture method of body pipe array base palte, by depositing thicker amorphous silicon layer so that the polysilicon layer that obtains after Crystallizing treatment
Crystalline quality preferably, afterwards thinning etching is carried out using gray-level mask photoetching technique to the channel region of active layer so that active
The thickness of the channel region of layer is thinning, so that channel region has less defect state number, lifts the output characteristics of TFT device,
Source drain contact area maintains original thicker thickness, thus keep preferable conductive capability it is ensured that source drain contact area and source/
There is between drain electrode preferable contact.The thin-film transistor array base-plate of the present invention, by being set to the channel region of active layer
Relatively thin thickness, source drain contact area is set to thicker thickness, so that channel region has less defect state number,
The output characteristics of lifting TFT device, makes source drain contact area keep preferable conductive capability it is ensured that source drain contact area simultaneously
Have between source/drain and preferably contact.
The above, for the person of ordinary skill of the art, can be with technology according to the present invention scheme and technology
Design is made other various corresponding changes and is deformed, and all these change and deformation all should belong to the claims in the present invention
Protection domain.
Claims (10)
1. a kind of manufacture method of thin-film transistor array base-plate is it is characterised in that comprise the steps：
Step 1, offer one underlay substrate (10), in the upper buffer layer (12) of described underlay substrate (10), in described cushion
(12) upper deposition of amorphous silicon layers (13), carries out Crystallizing treatment to described amorphous silicon layer (13) so as to be converted into polysilicon layer (14)；
Step 2, formation photoresist layer (15) on described polysilicon layer (14), using a gray-level mask (16) to described photoresist layer
(15) it is exposed developing, obtain a photoresistance figure (20), described photoresistance figure (20) includes two first photoresistances positioned at two ends
Section (21) and the second photoresistance section (22) between two first photoresistance sections (21), the thickness of described first photoresistance section (21) is more than
The thickness of described second photoresistance section (22)；
Step 3, with described photoresistance figure (20) as etching barrier layer, described polysilicon layer (14) is etched process, remove
The region not covered by described photoresistance figure (20) on described polysilicon layer (14), obtains active layer (30)；
Step 4, described photoresistance figure (20) is etched process, removes and be located at the second middle photoresistance section (22), and thinning
The first photoresistance section (21) positioned at two ends；
Step 5, with the first photoresistance section (21) of two ends thinning as etching barrier layer, described active layer (30) is etched locate
Reason, makes the thickness thinning in the upper region being located between two first photoresistance sections (21) of described active layer (30), forms channel region (31),
Form source contact area (32) and drain electrode respectively corresponding to the region below two first photoresistance sections (21) on described active layer (30)
Contact area (33)；
Peel off remaining first photoresistance section (21)；
Step 6, the channel region (31) to described active layer (30) carries out p-type or N-type ion is lightly doped, to described active layer (30)
Source contact area (32) and drain contact region (33) carry out N-type or p-type ion heavy doping；
Step 7, formation gate insulator (40) on described active layer (30) and cushion (12), in described gate insulator
(40) the upper grid (41) being formed above corresponding described active layer (30)；
Form interlayer dielectric layer (50) described grid (41) and gate insulator (40) are upper, described interlayer dielectric layer (50) with
The upper formation of gate insulator (40) is corresponded respectively to described source contact area (32) and is led to first above drain contact region (33)
Hole (51) and the second through hole (52)；
In described interlayer dielectric layer (50) upper formation source electrode (61) and drain electrode (62), described source electrode (61) and drain electrode (62) are led to respectively
Cross described first through hole (51) and the second through hole (52) to contact with described source contact area (32) and drain contact region (33).
2. the manufacture method of thin-film transistor array base-plate as claimed in claim 1 is it is characterised in that described step 1 is also wrapped
Include：Before the upper buffer layer (12) of described underlay substrate (10), in described underlay substrate (10) upper formation light shield layer (11),
Described light shield layer (11) is corresponding with the active layer (30) being subsequently formed, and at least covers the channel region of described active layer (30)
(31).
3. the manufacture method of thin-film transistor array base-plate as claimed in claim 2 is it is characterised in that described light shield layer (11)
Material be metal, described step 1 forms described light shield layer (11) using physical vaporous deposition.
4. the manufacture method of thin-film transistor array base-plate as claimed in claim 1 is it is characterised in that described step 1 is also wrapped
Include：Before Crystallizing treatment is carried out to described amorphous silicon layer (13), dehydrogenation is carried out to described amorphous silicon layer (13).
5. the manufacture method of thin-film transistor array base-plate as claimed in claim 1 is it is characterised in that in described step 1, adopt
With quasi-molecule laser annealing method, Crystallizing treatment is carried out to described amorphous silicon layer (13).
6. the manufacture method of thin-film transistor array base-plate as claimed in claim 1 is it is characterised in that also include step 8：?
Described source electrode (61), drain electrode (62) and interlayer dielectric layer (50) upper formation flatness layer (70), in the upper formation of described flatness layer (70)
Public electrode (71), in described public electrode (71) and flatness layer (70) upper formation passivation layer (80)；
In the upper third through-hole (83) being formed above corresponding to described drain electrode (62) of described passivation layer (80) and flatness layer (70)；
Form pixel electrode (90) described passivation layer (80) is upper, described pixel electrode (90) pass through described third through-hole (83) with
Described drain electrode (62) contacts.
7. a kind of thin-film transistor array base-plate is it is characterised in that include：Underlay substrate (10), located at described underlay substrate
(10) cushion (12) on, the active layer (30) on described cushion (12), located at described active layer (30) and buffering
Gate insulator (40) on layer (12), the grid above the upper and corresponding described active layer (30) of described gate insulator (40)
Pole (41), the interlayer dielectric layer (50) on described grid (41) and gate insulator (40) and located at described interlayer be situated between
Source electrode (61) in electric layer (50) and drain electrode (62)；
Described active layer (30) is polysilicon layer, and described active layer (30) includes source contact area (32) and drain electrode positioned at two ends
Contact area (33) and be located at channel region (31) between described source contact area (32) and drain contact region (33)；Described source electrode
The thickness of contact area (32) and drain contact region (33) is all higher than the thickness of described channel region (31)；
Described interlayer dielectric layer (50) and gate insulator (40) are provided with and correspond respectively to described source contact area (32) and leakage
First through hole (51) above pole contact area (33) and the second through hole (52)；Institute is passed through in described source electrode (61) and drain electrode (62) respectively
State first through hole (51) and the second through hole (52) to contact with described source contact area (32) and drain contact region (33).
8. thin-film transistor array base-plate as claimed in claim 7 is it is characterised in that also include located at described underlay substrate
(10) light shield layer (11) and cushion (12) between, described light shield layer (11) is corresponding with described active layer (30), and at least
Cover the channel region (31) of described active layer (30).
9. thin-film transistor array base-plate as claimed in claim 7 is it is characterised in that the material of described light shield layer (11) is gold
Belong to, described channel region (31) is p-type or N-type ion lightly doped district, described source contact area (32) is with drain contact region (33) all
For N-type or p-type ion heavily doped region.
10. thin-film transistor array base-plate as claimed in claim 7 is it is characterised in that also include：Located at described source electrode
(61), drain electrode (62) and interlayer dielectric layer (50) on flatness layer (70), the public electrode on described flatness layer (70)
(71), the passivation layer (80) on described public electrode (71) and flatness layer (70) and on described passivation layer (80)
Pixel electrode (90)；
Described passivation layer (80) and flatness layer (70) are provided with the third through-hole (83) above corresponding to described drain electrode (62), described
Pixel electrode (90) is contacted with described drain electrode (62) by described third through-hole (83).
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