CN1542948A - Method for forming CMOS transistor - Google Patents
Method for forming CMOS transistor Download PDFInfo
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- CN1542948A CN1542948A CNA2003101142251A CN200310114225A CN1542948A CN 1542948 A CN1542948 A CN 1542948A CN A2003101142251 A CNA2003101142251 A CN A2003101142251A CN 200310114225 A CN200310114225 A CN 200310114225A CN 1542948 A CN1542948 A CN 1542948A
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- 238000000034 method Methods 0.000 title claims abstract description 57
- 239000010410 layer Substances 0.000 claims description 111
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 44
- 229920005591 polysilicon Polymers 0.000 claims description 44
- 229920002120 photoresistant polymer Polymers 0.000 claims description 24
- 230000003647 oxidation Effects 0.000 claims description 16
- 238000007254 oxidation reaction Methods 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 14
- 239000010936 titanium Substances 0.000 claims description 12
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 11
- 229910052698 phosphorus Inorganic materials 0.000 claims description 11
- 239000011574 phosphorus Substances 0.000 claims description 11
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 10
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 10
- 229910052796 boron Inorganic materials 0.000 claims description 10
- 239000011241 protective layer Substances 0.000 claims description 10
- 229910052719 titanium Inorganic materials 0.000 claims description 10
- 239000007943 implant Substances 0.000 claims description 9
- 239000011248 coating agent Substances 0.000 claims description 7
- 238000000576 coating method Methods 0.000 claims description 7
- 239000011651 chromium Substances 0.000 claims description 6
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 5
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- 239000004411 aluminium Substances 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052804 chromium Inorganic materials 0.000 claims description 5
- 239000011733 molybdenum Substances 0.000 claims description 5
- 229910052750 molybdenum Inorganic materials 0.000 claims description 5
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 3
- 230000002093 peripheral effect Effects 0.000 claims description 2
- 238000002513 implantation Methods 0.000 abstract description 5
- 239000002019 doping agent Substances 0.000 abstract 3
- 230000015572 biosynthetic process Effects 0.000 description 12
- 239000010408 film Substances 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 150000002500 ions Chemical group 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 229920003023 plastic Polymers 0.000 description 4
- 239000004033 plastic Substances 0.000 description 4
- 238000005496 tempering Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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Abstract
This invention relates to a method for forming a CMOS transistor on a base plate in which, only two implantation steps are needed to form all sources, drains and light doping, firstly form the source and drain of a NMOS transistor utilizing a photoresisive layer covering the source and drain as the shield and implanting a P dopant, then to form a light doping of NMOS and source and drain of PMOS utilizing the said photo resistive layer and the gate as the shield and implanting a B dopant, the dosage of which is smaller than that of the P dopant.
Description
Technical field
The invention relates to the transistorized manufacturing method thereof of a kind of formation CMOS, and particularly utilize twice implantation to form source/drain and the transistorized manufacturing method thereof of lightly doped CMOS relevant for a kind of.
Background technology
Thin-film transistor in the flat-panel screens is many with amorphous silicon (amorphous silicon) institute processing procedure now, and a few high-end product is then with the high polysilicon of electronics mobility (poly silicon) processing procedure.Polysilicon technology tolerable is integrated more electronic circuit, thereby can reduce the complexity and the weight of integral product.But, far surpass the temperature that plastics begin to soften, so can only be applicable to glass substrate because in the polysilicon processing procedure, maximum temperature is about more than 300 ℃.
Please refer to Figure 1A ~ 1I, it has shown the making flow process of a traditional low-temperature polysilicon film transistor.At first, in Figure 1A, a resilient coating 102, a polysilicon layer are formed on the substrate 100 in regular turn, and wherein, polysilicon layer utilizes excimer laser that one amorphous silicon layer is carried out the crystallization tempering and forms; Then, form the photoresist layer (not being shown among the figure) of a tool pattern again, and be that etching is carried out in shielding with the photoresist layer, and form the polysilicon layer 104 shown in Figure 1A.
Then, with reference to Figure 1B, deposition one deck gate pole oxidation layer 108 and forms a conductive layer on gate pole oxidation layer 108 on resilient coating 102 and polysilicon layer 104, utilize little shadow and etch process after, form a gate 110.Then, in Fig. 1 C, form a photoresist layer 112, photoresist layer 112 covers the gate and the lightly doped region of whole PMOS transistor area and nmos transistor region, and be shielding with photoresist layer 112, implant the phosphorus admixture of heavy concentration, and form source/drain 104a, 104b, 104c and the 104d of nmos pass transistor.
Afterwards, in Fig. 1 D, remove residual photoresistor layer 112, and be shielding directly, substrate 100 is implanted the phosphorus admixture of light concentration, and form light dope 104m, 104n, 104x and the 104y of nmos pass transistor with gate 110.Then, in Fig. 1 E, form a photoresist layer 114 once more, photoresist layer 114 covers whole nmos transistor region, and be shielding with photoresist layer 114, and substrate 100 is implanted the boron admixture of weight concentration, and the source/drain 104i and the 104j of formation P transistor npn npn.
In Fig. 1 F, remove earlier photoresist layer 114, form an inner layer dielectric layer 116 again on gate 110 and gate pole oxidation layer 108, and form several and be opened among inner layer dielectric layer 116 and the gate pole oxidation layer 108.Then, in Fig. 1 G, the electrode 118 that formation can electrically connect with source/ drain 104a, 104b, 104c, 104d, 104i and 104j.
Then, in Fig. 1 H, form a protective layer 120 on electrode layer 118 and inner layer dielectric layer 116, and formation is opened in the protective layer 120 of picture element region, with exposed electrode 118.At last, in Fig. 1 I, the transparency electrode 122 that formation can electrically connect with the electrode 118 of picture element region is to finish the processing procedure with low-temperature polysilicon film transistor.
Known technology needs the processing procedure of eight road light shields and the step that three secondary ions are implanted altogether, just can finish the processing procedure of whole low-temperature polysilicon film transistor, wherein, the processing procedure of eight road light shields is respectively at carrying out among Figure 1A～1C and Fig. 1 E～1I, and the step that three secondary ions are implanted is respectively at carrying out among Fig. 1 C～1E.Yet each fabrication steps all can increase the processing procedure cost, therefore, is necessary to propose a method that can reduce fabrication steps in fact.
Summary of the invention
In view of this, purpose of the present invention is exactly to provide one with the transistorized manufacturing method thereof of less fabrication steps formation CMOS.
According to purpose of the present invention, a kind of method that forms first transistor npn npn and second transistor npn npn on a substrate is proposed, wherein this first transistor npn npn has a lightly doped region and first heavily doped region, this second transistor npn npn has second heavily doped region, this method comprises at least: form a thickness be about 200～1000 dusts first polysilicon layer and second polysilicon layer on this substrate, wherein this first polysilicon layer and this second polysilicon layer are corresponding to this first transistor npn npn and this second transistor npn npn; Deposit a thickness and be about the gate pole oxidation layer of 500～1500 dusts on this first polysilicon layer and this second polysilicon layer; Form one by one of them first gate of forming of molybdenum, chromium or titanium/aluminium/titanium and second gate on this gate pole oxidation layer, and lay respectively at the top of this first polysilicon layer and this second polysilicon layer, this first gate outside is in regular turn around this lightly doped region and this first heavily doped region, and this second gate outer peripheral is around this second heavily doped region; First heavy doping that forms first transistor npn npn is in first heavily doped region of this first transistor npn npn, and it utilizes a photoresist layer that hides this second heavily doped region is to shield with this second gate, and implants first admixture and form; And in second heavily doped region of second heavy doping that forms the light dope of first transistor npn npn and second transistor npn npn respectively at the lightly doped region of this first transistor npn npn and this second transistor npn npn, it utilizes the photoresist layer of first heavily doped region that hides this first transistor npn npn and this first gate to be shielding, and implant second admixture and form, the dosage of this second admixture is less than the dosage of this first admixture.The dosage of first admixture of the present invention is about between the 3el3/cm2 to 5el5/cm2, and the dosage of second admixture is about between the 3el3/cm2 to 5el5/cm2, and this first heavy doping and this second heavy doping are source electrode and drain electrode.
The present invention also comprises: form a thickness and be about the inner layer dielectric layer of 500～7000 dusts on this gate pole oxidation layer, this first gate and this second gate after this forms the second heavy doping step of the light dope of first transistor npn npn and second transistor npn npn; Optionally expose this first heavy doping, this second heavy doping, first gate and second gate; And form one of them electrode of forming, this first heavy doping, this second heavy doping, first gate and second gate that are exposed with electric connection by molybdenum, chromium or titanium/aluminium/titanium.
The present invention also comprises after this forms the electrode step: the protective layer that forms a tool pattern is on this inner layer dielectric layer and this electrode, and the protective layer of this tool pattern exposure one is positioned at the partial electrode of first transistor npn npn of picture element region; And form the transparency electrode of being formed by indium tin oxide (ITO), to electrically connect the partial electrode that is exposed of first transistor npn npn.
First transistor npn npn of the present invention is a nmos pass transistor, and second transistor npn npn is the PMOS transistor, and wherein, first admixture is the phosphorus admixture, and second admixture is the boron admixture; Or first transistor npn npn be the PMOS transistor, second transistor npn npn is a nmos pass transistor, wherein, first admixture is the boron admixture, second admixture is the phosphorus admixture.
For further specifying above-mentioned purpose of the present invention, design feature and effect, the present invention is described in detail below with reference to accompanying drawing.
Description of drawings
Figure 1A ~ 1I, it has shown the making flow process of a traditional low-temperature polysilicon film transistor.
Fig. 2 A ~ 2H, it has shown the making flow process of low-temperature polysilicon film transistor of the present invention.
Embodiment
The invention provides a method that can reduce the fabrication steps of low-temperature polysilicon film transistor.
Please refer to Fig. 2 A ~ 2J, it has shown the making flow process of low-temperature polysilicon film transistor of the present invention.
At first, in Fig. 2 A, a resilient coating 202, a polysilicon layer 204, be formed in regular turn on the substrate 200, then, form the photoresist layer (not being shown among the figure) of a tool pattern again, and be that etching is carried out in shielding with the photoresist layer, and form the polysilicon layer 204 shown in Fig. 2 A.
Then, with reference to figure 2B, a gate pole oxidation layer 208 is formed on resilient coating 202 and the polysilicon layer 204, and the thickness of gate pole oxidation layer 208 is about between 500 ~ 1500 dusts, and its material can be silicon dioxide.Then, deposit a conductive layer on whole base plate 200, and utilize little shadow and etch process, form gate layer 210, gate layer 210 can be made up of with titanium/aluminium/titanium (Ti/Al/Ti) molybdenum (Mo), chromium (Cr).
Afterwards, in Fig. 2 C, by micro-photographing process, the photoresist layer 212 that forms a tool pattern is on substrate 210, and photoresist layer 212 covers desire fully and forms the transistorized PMOS transistor area of CMOS.And be shielding with photoresist layer 212, substrate 200 is implanted the phosphorus admixture of heavy concentration, its dosage is about between the 3el3dose/cm2 to 5el5dose/cm2, to form heavy doping 204A, 204B, 204C and 204D in the regions and source and lightly doped region of nmos pass transistor.At this moment, heavy doping 204A, 204B, 204C and 204D are formed at the part in the regions and source of nmos pass transistor, are the source/drain of nmos pass transistor, and this part will be done explanation again after the step among Fig. 2 D is finished.
Afterwards, in Fig. 2 D, remove residual photoresistor layer 212, and once more by micro-photographing process, the photoresist layer 214 that forms a tool pattern is on gate pole oxidation layer 208, photoresist layer 214 covers the regions and source of the transistorized nmos pass transistor of CMOS, and the regions and source of the nmos pass transistor in picture element zone, and does not cover the transistorized PMOS transistor area of CMOS.And be shielding with photoresist layer 214, substrate 200 is implanted the boron admixture of heavy concentration, its dosage is about between 3el3dose/cm2 ~ 5el5dose/cm2, with formation transistorized source/drain 204i of PMOS and 204j, and light dope 204m, 204n, 204x and the 204y of nmos pass transistor.In heavy doping 204A, 204B, 204C and 204D, except light dope 204m, 204n, 204x and 204y, remaining is source/drain 204a, 204b, 204c and the 204d of nmos pass transistor.
It should be noted that, the present invention must be less than implanting the employed dosage of phosphorus admixture, so in the employed dosage of boron implant admixture, then carry out the lightly doped region of the nmos pass transistor of boron admixture and twice implantation of phosphorus admixture, just can have light dope 204m, 204n, 204x and 204y.Certainly, embodiments of the invention are not limited to form has lightly doped nmos pass transistor, formation has lightly doped PMOS transistor and also can be another embodiment of the present invention, at this moment, the implantation step that utilizes photoresist layer 212 to be carried out for shielding is the boron implant admixture, the implantation step that utilizes photoresist layer 214 to be carried out for shielding, be to implant the phosphorus admixture, and the employed dosage of boron implant admixture, must be greater than implanting the employed dosage of phosphorus admixture.
Then, in Fig. 2 E, remove photoresist layer 214 earlier, form an inner layer dielectric layer 216 again on whole base plate 200, and utilize little shadow and etch process, form several openings, among inner layer dielectric layer 216 and gate pole oxidation layer 208, inner layer dielectric layer 216 can be made up of silicon dioxide, and its thickness is about 500 ~ 7000 dusts.Then, in Fig. 2 F, form a conductive layer on inner layer dielectric layer 216, and fill up the opening that is positioned among inner layer dielectric layer 216 and the gate pole oxidation layer 208, utilize little shadow and etch process again, formation can with the part of gate 210 and source/ drain 204a, 204b, 204c, 204d, 204i and 204j, the electrode 218 of electric connection.This embodiment is shown to be the situation that electrode 218 and source/ drain 204a, 204b, 204c, 204d, 204i and 204j electrically connect.
Then, in Fig. 2 G, form a protective layer 220 on electrode 218 and inner layer dielectric layer 216, and utilize little shadow and etch process, formation is opened in the protective layer 220 of picture element region.At last; in Fig. 2 H; the conductive layer that formation is made up of indium tin oxide (ITO) is on protective layer 220; and fill up opening among the protective layer 220; utilize little shadow and etch process again; the transparency electrode 222 that formation can electrically connect with the electrode 218 of picture element region is to finish the processing procedure with low-temperature polysilicon film transistor.
The manufacturing method thereof that the above embodiment of the present invention disclosed, only need the processing procedure of eight road light shields and the step that two secondary ions are implanted altogether, just can finish the processing procedure of whole low-temperature polysilicon film transistor, wherein, the processing procedure of eight road light shields carries out among the v at figure respectively, and the step that two secondary ions are implanted is carried out among d Fig. 2 C and Fig. 2 D respectively.Taking a broad view of method of the present invention, is to lack the step that an ion is implanted than known technology, therefore, can reduce the cost of processing procedure widely.
In sum; though the present invention discloses as above with a preferred embodiment; right its is not in order to limit the present invention; anyly be familiar with present technique field person; without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.
Though the present invention describes with reference to current specific embodiment, but those of ordinary skill in the art will be appreciated that, above embodiment is used for illustrating the present invention, under the situation that does not break away from spirit of the present invention, also can make the variation and the modification of various equivalences, therefore, as long as variation, the modification to the foregoing description all will drop in the scope of claims of the present invention in connotation scope of the present invention.
Claims (20)
1. method that on a substrate, forms first transistor npn npn and second transistor npn npn, wherein this first transistor npn npn has a lightly doped region and first heavily doped region, and this second transistor npn npn has second heavily doped region, and this method comprises at least:
Form first polysilicon layer and second polysilicon layer on this substrate, wherein this first polysilicon layer and this second polysilicon layer are corresponding to this first transistor npn npn and this second transistor npn npn;
Deposit a gate pole oxidation layer on this first polysilicon layer and this second polysilicon layer;
Form first gate and second gate on this gate pole oxidation layer, and lay respectively at the top of this first polysilicon layer and this second polysilicon layer, this first gate outside is in regular turn around this lightly doped region and this first heavily doped region, and this second gate outer peripheral is around this second heavily doped region;
First heavy doping that forms first transistor npn npn is in first heavily doped region of this first transistor npn npn, and it is that to utilize a photoresist layer that hides this second heavily doped region be to shield with this second gate, and implants one first admixture and form; And
In second heavily doped region of second heavy doping that forms the light dope of first transistor npn npn and second transistor npn npn respectively at the lightly doped region of this first transistor npn npn and this second transistor npn npn, it is to utilize the photoresist layer of first heavily doped region that hides this first transistor npn npn and this first gate to be shielding, and implant second admixture and form, the dosage of this second admixture is the dosage less than this first admixture.
2. the method for claim 1 is characterized in that, this forms before first polysilicon layer and the second polysilicon layer step, also comprises forming the step of a resilient coating on this substrate.
3. the method for claim 1 is characterized in that, after this forms the second heavy doping step of the light dope of first transistor npn npn and second transistor npn npn, also comprises:
Form an inner layer dielectric layer on this gate pole oxidation layer, this first gate and this second gate;
Optionally expose this first heavy doping, this second heavy doping, first gate and second gate; And
Form this first heavy doping, this second heavy doping, first gate and second gate that electrode is exposed with electric connection.
4. method as claimed in claim 3 is characterized in that the thickness of this inner layer dielectric layer is about 500～7000 dusts.
5. method as claimed in claim 3 is characterized in that, this electrode is formed by one of them of molybdenum, chromium or titanium/aluminium/titanium.
6. method as claimed in claim 3 is characterized in that, after this forms the electrode step, also comprises:
The protective layer that forms a tool pattern is on this inner layer dielectric layer and this electrode, and the protective layer of this tool pattern exposure one is positioned at the partial electrode of first transistor npn npn of picture element region; And
Form transparency electrode to electrically connect the partial electrode that is exposed of first transistor npn npn.
7. method as claimed in claim 6 is characterized in that this transparency electrode is formed by indium tin oxide.
8. the method for claim 1 is characterized in that, the thickness of this first polysilicon layer and second polysilicon layer is about 200～1000 dusts.
9. the method for claim 1 is characterized in that, the thickness of this gate pole oxidation layer is about 500～1500 dusts.
10. the method for claim 1 is characterized in that, this first gate is formed in this second gate one of them by molybdenum, chromium or titanium/aluminium/titanium.
11. the method for claim 1 is characterized in that, this first transistor npn npn is a nmos pass transistor, and this second transistor npn npn is the PMOS transistor.
12. method as claimed in claim 11 is characterized in that, this first admixture is the phosphorus admixture.
13. method as claimed in claim 11 is characterized in that, this second admixture is the boron admixture.
14. the method for claim 1 is characterized in that, this first transistor npn npn is the PMOS transistor, and this second transistor npn npn is a nmos pass transistor.
15. method as claimed in claim 14 is characterized in that, this first admixture is the boron admixture.
16. method as claimed in claim 14 is characterized in that, this second admixture is the phosphorus admixture.
17. the method for claim 1 is characterized in that, this first heavy doping is source electrode and drain electrode.
18. the method for claim 1 is characterized in that, this second heavy doping is source electrode and drain electrode.
19. the method for claim 1 is characterized in that, the dosage of this first admixture is about between the 3e13dose/cm2 to 5e15dose/cm2.
20. the method for claim 1 is characterized in that, the dosage of this second admixture is about between the 3e13dose/cm2 to 5e15dose/cm2.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101142251A CN100395884C (en) | 2003-11-07 | 2003-11-07 | Method for forming CMOS transistor |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2003101142251A CN100395884C (en) | 2003-11-07 | 2003-11-07 | Method for forming CMOS transistor |
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| CN1542948A true CN1542948A (en) | 2004-11-03 |
| CN100395884C CN100395884C (en) | 2008-06-18 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100353248C (en) * | 2005-07-04 | 2007-12-05 | 友达光电股份有限公司 | Pixel structure and mfg method therefor |
| CN102315105A (en) * | 2010-07-08 | 2012-01-11 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN102789971A (en) * | 2012-07-31 | 2012-11-21 | 京东方科技集团股份有限公司 | Poly-silicon TFT and ploy-silicon array substrate and manufacturing methods thereof as well as display equipment |
| CN105140124A (en) * | 2015-07-29 | 2015-12-09 | 武汉华星光电技术有限公司 | Method for manufacturing poly-silicon thin-film transistor |
| CN106876341A (en) * | 2015-12-10 | 2017-06-20 | 财团法人工业技术研究院 | Semiconductor device with a plurality of semiconductor chips |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3307021B2 (en) * | 1993-10-13 | 2002-07-24 | セイコーエプソン株式会社 | Method for manufacturing thin film semiconductor device |
| JP3678437B2 (en) * | 1994-03-16 | 2005-08-03 | 株式会社日立製作所 | Method for manufacturing liquid crystal display device and liquid crystal display device |
| TW322591B (en) * | 1996-02-09 | 1997-12-11 | Handotai Energy Kenkyusho Kk | |
| KR100582198B1 (en) * | 2000-02-24 | 2006-05-24 | 엘지.필립스 엘시디 주식회사 | Method of Fabricating CMOS Thin Film Transistor |
| JP3626734B2 (en) * | 2002-03-11 | 2005-03-09 | 日本電気株式会社 | Thin film semiconductor device |
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2003
- 2003-11-07 CN CNB2003101142251A patent/CN100395884C/en not_active Expired - Lifetime
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100353248C (en) * | 2005-07-04 | 2007-12-05 | 友达光电股份有限公司 | Pixel structure and mfg method therefor |
| CN102315105A (en) * | 2010-07-08 | 2012-01-11 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN102789971A (en) * | 2012-07-31 | 2012-11-21 | 京东方科技集团股份有限公司 | Poly-silicon TFT and ploy-silicon array substrate and manufacturing methods thereof as well as display equipment |
| WO2014019300A1 (en) * | 2012-07-31 | 2014-02-06 | 京东方科技集团股份有限公司 | Poly-silicon tft, poly-silicon array substrate, methods for manufacturing same, and display device |
| US9502446B2 (en) | 2012-07-31 | 2016-11-22 | Boe Technology Group Co., Ltd. | Poly-silicon TFT, poly-silicon array substrate and preparing method thereof, display device |
| CN105140124A (en) * | 2015-07-29 | 2015-12-09 | 武汉华星光电技术有限公司 | Method for manufacturing poly-silicon thin-film transistor |
| CN105140124B (en) * | 2015-07-29 | 2018-12-11 | 武汉华星光电技术有限公司 | A kind of production method of polycrystalline SiTFT |
| CN106876341A (en) * | 2015-12-10 | 2017-06-20 | 财团法人工业技术研究院 | Semiconductor device with a plurality of semiconductor chips |
| CN106876341B (en) * | 2015-12-10 | 2020-06-05 | 财团法人工业技术研究院 | Semiconductor device with a plurality of semiconductor chips |
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| CN100395884C (en) | 2008-06-18 |
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