CN1763975A - Thin film transistor and producing method thereof - Google Patents
Thin film transistor and producing method thereof Download PDFInfo
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- CN1763975A CN1763975A CN 200410084033 CN200410084033A CN1763975A CN 1763975 A CN1763975 A CN 1763975A CN 200410084033 CN200410084033 CN 200410084033 CN 200410084033 A CN200410084033 A CN 200410084033A CN 1763975 A CN1763975 A CN 1763975A
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Abstract
The manufacture method for TFT comprises: forming by turns a polysilicon layer, a grid insulation layer, and grid material layer; forming patternized photo-resist layer on grid material layer as etch mask to define grid; taking aeolotropic etching to grid insulation layer with photo-resist layer as mask to make it has different thickness on different part; removing photo-resist layer, with grid as mask to take doping and form light-doping drain region and source/drain regions in polysilicon layer under thicker/thinner grid insulation layer respectively. This method can form symmetrical doping drain regions simultaneously and reduce cost.
Description
Technical field
The invention relates to a kind of semiconductor element and manufacture method thereof, and particularly relevant for a kind of low-temperature polysilicon film transistor (Low TemperaturePoly-Silicon Thin Film Transistor, LTPS-TFT) and the invention of manufacture method.
Background technology
Along with the development of high-tech, the image device of digitlization become in general daily life common product, and in the image device of these digitlizations, gazed at most at present when belong to LCD (Liquid Crystal Display, LCD).In the LCD of active-matrix formula, its driving element can be thin-film transistor (thin film transistor) or diode etc., and thin-film transistor can be divided into amorphous silicon (amorphous silicon is called for short a-Si) thin-film transistor and polysilicon (poly-silicon) thin-film transistor according to the material of its channel region.Wherein, because the brilliant consumed power than amorphous silicon film transistor of polysilicon membrane electricity is little and electron mobility (electron mobility) big, therefore be subjected to the attention in market gradually.
The transistorized manufacturing employing of polycrystal silicon film solid-phase crystallization more than early stage (SolidPhase Crystallization, SPC) technology, but its technological temperature is up to 1000 degree Celsius, so the essential higher quartz base plate of fusing point that adopts.Yet because the quartz base plate cost is expensive more many than glass substrate, and under the restriction of substrate size, panel approximately only has 2 to 3 inches, therefore can only develop small panel in the past.In recent years along with the continuous progress of laser technology, develop and a kind of laser annealing (LaserAnnealing) technology, it uses laser beam irradiation in amorphous silicon membrane, crystallization again (recrystallization) becomes polysilicon membrane after making amorphous silicon membrane fusion (melting), and can finish whole manufacturing process below temperature 600 degree Celsius.Therefore, cost also can be applied to the manufacturing of polycrystalline SiTFT far below the glass substrate of quartz base plate, and then produce the panel of large-size, and utilize the polycrystalline SiTFT of this kind technology mode gained low-temperature polysilicon film transistor that is otherwise known as.
Fig. 1 is a kind of generalized section of known low-temperature polysilicon film transistor.Please refer to Fig. 1, substrate 100 is provided with resilient coating (buffer layer) 102, and polysilicon layer 110 is arranged on the resilient coating on 102, and be formed with source/drain regions 112,114 by (dopping) technology of mixing in the polysilicon layer 110, wherein then have channel region 116 between the source/drain regions 112,114.
From the above, gate insulation layer 120 covers polysilicon layer 110 and resilient coating 102, and grid 130 is arranged on the gate insulation layer 120 of channel region 116 tops.In addition, dielectric layer 140 cover gate 130 and gate insulation layer 120, and source/drain conductor layer 152,154 is arranged on the dielectric layer 140 and dielectric layer 140 and gate insulation layer 120 in, and source/drain conductor layer 152,154 is electrically connected with source/drain regions 112,114 respectively.
What deserves to be mentioned is,, can be formed with lightly mixed drain area (Lightly Doped Drain, LDD) 118 between source/drain regions 112,114 and the channel region 116 usually for preventing the generation of short-channel effect (short channel effect).As is generally known, when manufacturing has the polycrystalline SiTFT of lightly mixed drain area 118, usually need to carry out above doping process twice, to form different source/drain regions 112,114 and the lightly mixed drain areas 118 of doping content by the light shield more than the twice.Yet the mode that this kind made lightly mixed drain area 118 is the manufacturing cost height not only, and the difficulty of aiming at because of light mask image easily, and makes the length of lightly mixed drain area 118 of channel region 116 both sides be difficult to symmetry, and then influences the symmetry of element characteristic.
For solving above-mentioned problem, the someone proposes the another kind of source/drain regions of low-temperature polysilicon film transistor and the method for lightly mixed drain area of forming, this method is that mask carries out light dope technology with grid 130 earlier, with in forming channel region 216 and light doping section 218 (shown in Fig. 2 A) in the polysilicon layer 210.Then form clearance wall 132 and cover light doping section 218 partly in grid 130 both sides, carry out heavy doping technology (shown in Fig. 2 B) with clearance wall 132 as mask again, in the polysilicon layer 210 that is not covered, to form heavily doped region 214 by clearance wall 132.At this, light doping section 218 is the lightly mixed drain area of low-temperature polysilicon film transistor, and heavily doped region 214 is the source/drain regions of low-temperature polysilicon film transistor.Though this kind method can solve the AXIALLY SYMMETRIC PROBLEMS of lightly mixed drain area, comparatively complicated on the technology, therefore still fail to reduce the technology cost.
Summary of the invention
Therefore, the purpose of this invention is to provide a kind of low-temperature polysilicon film transistor, have the lightly mixed drain area that is symmetrical in grid, so element characteristic also has preferable symmetry.
Another object of the present invention provides a kind of manufacture method of low-temperature polysilicon film transistor, can be less manufacture source/drain regions and the lightly mixed drain area that original formation is symmetrical in grid.
The present invention proposes a kind of low-temperature polysilicon film transistor, mainly comprises polysilicon layer, gate insulation layer and grid.Wherein, polysilicon layer is arranged on the substrate, and polysilicon layer has channel region, source/drain regions and lightly mixed drain area.Source/drain regions is positioned at the both sides of channel region, and lightly mixed drain area is then between channel region and lightly mixed drain area.Gate insulation layer is arranged on the substrate, and covers polysilicon layer.Particularly, gate insulation layer is divided into first position and second position, and wherein first position is positioned at the top of the channel region and the lightly mixed drain area of polysilicon layer, and second position then is positioned at this source/drain regions of polysilicon layer and the top of substrate.The thickness at first position that it should be noted that gate insulation layer is greater than the thickness at second position of gate insulation layer.Grid then is arranged on the gate insulation layer of channel region top.
The present invention proposes a kind of manufacture method of low-temperature polysilicon film transistor, and the method earlier forms polysilicon layer on substrate, then on polysilicon layer, be docile and obedient preface formation gate insulation layer with gate material layers.On gate material layers, form graphical photoresist layer again.Be that mask carries out etch process to gate material layers then, on the gate insulation layer of polysilicon layer top, to form grid with graphical photoresist layer.Wherein, after forming grid, the bottom surface portions ground of graphical photoresist layer contact grid.Then, be mask with graphical photoresist layer once more, gate insulation layer is carried out anisotropic etching, and make the gate insulation layer after the etching have first position and second position, wherein first position of gate insulation layer is positioned at by graphical photoresist layer and covers part, and second position of gate insulation layer is not positioned at and is covered part by graphical photoresist layer.Particularly, the thickness at first position of gate insulation layer is greater than the thickness at second position of gate insulation layer.
From the above, after finishing the anisotropic etching process of gate insulation layer, removing graphical photoresist layer earlier, is that mask carries out doping process again with the grid, to form lightly mixed drain area and source/drain regions in polysilicon layer.Wherein, lightly mixed drain area is positioned at the below at first position of gate insulation layer, and source/drain regions is positioned at the below at second position of gate insulation layer.
The present invention carries out anisotropic etching as mask to gate insulation layer by the graphical photoresist layer of bottom surface portions contact grid, and then make gate insulation layer have two kinds of different thickness, and the thickness difference by gate insulation layer, and in technology, form source/drain regions and lightly mixed drain area.Therefore, the technology of the present invention's low-temperature polysilicon film transistor can be simplified the technology of lightly mixed drain area, and then saves manufacturing cost.
State with other purpose, feature and advantage and can become apparent on the present invention for allowing, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 is a kind of generalized section of known low-temperature polysilicon film transistor.
Fig. 2 A to Fig. 2 B is the manufacturing process generalized section of the known low-temperature polysilicon film transistor of another kind.
Fig. 3 A to Fig. 3 I is the manufacturing process generalized section of a kind of low-temperature polysilicon film transistor of a preferred embodiment of the present invention.
Fig. 4 changes the generalized section of the technology of polysilicon layer into for the amorphous silicon layer of one of the present invention preferred embodiment.
Fig. 5 A and Fig. 5 B are the part manufacturing process generalized section of a kind of low-temperature polysilicon film transistor of another preferred embodiment of the present invention.
The main element description of symbols
100,300: substrate
102,302: resilient coating
110,210,304: polysilicon layer
112,114,318: source/drain regions
116,216,320: channel region
118,316: lightly mixed drain area
120,306: gate insulation layer
130,310a: grid
140,322: dielectric layer
152,152,326: the source/drain metal layer
132: clearance wall
214: heavily doped region
218: light doping section
301: laser beam
303: amorphous silicon layer
305: the first retes
306a: first position of gate insulation layer
306b: second position of gate insulation layer
307: the second retes
310: gate material layers
312: photoresist layer
312a: graphical photoresist layer
314: light shield
321: dopant ion
324: opening
330: low-temperature polysilicon film transistor
Embodiment
Fig. 3 A to Fig. 3 H is the manufacturing process generalized section of a kind of low-temperature polysilicon film transistor of a preferred embodiment of the present invention.Please refer to Fig. 3 A, at first on substrate 300, form polysilicon layer 304, and the formation method of polysilicon layer 304 for example is to form earlier amorphous silicon layer (amorphous silicon layer) 303 (shown in Fig. 4 A) on substrate, and then amorphous silicon layer 303 carried out laser annealing technique (Laser annealing) with laser beam 301, so that crystallization again after the silicon molecule fusion in the amorphous silicon layer 303, and then change polysilicon layer 304 into.In addition, in one embodiment, before forming polysilicon layer 304, also comprise on substrate 300, forming resilient coating (bufferlayer) 302 earlier, and the material of resilient coating 302 for example is a silica.
Then please refer to Fig. 3 B, on substrate 300, be docile and obedient preface and form gate insulation layer 306, gate material layers 310 and photoresist layer 312, light shield 314 is set on photoresist layer 312 then, and photoresist layer 312 is carried out exposure technology.Again photoresist layer 312 is carried out developing process afterwards, to form graphical photoresist layer 312a, shown in Fig. 3 C.
Please refer to Fig. 3 D, is mask with graphical photoresist layer 312a, and the gate material layers 310 of Fig. 3 C is carried out isotropic etching, to form grid 310a on the gate insulation layer 306 of polysilicon layer 304 tops.Wherein, after forming grid 310a, be contacted with grid 310a the bottom surface portions of graphical photoresist layer 312a.In other words, define gate pattern at this because of using isotropic etching, the face that connects of therefore graphical photoresist layer 312a and grid 310a can produce the phenomenon of undercutting (undercut), the A place that is indicated as Fig. 3 D, thereby be contacted with grid 310a with making graphical photoresist layer 312a bottom surface portions.In a preferred embodiment, this isotropic etching for example is a wet etch process.What deserves to be mentioned is that because the present invention forms grid 310a with isotropic etching, so the phenomenon of undercutting can occur in the both sides of grid 310a symmetrically.In other words, grid 310a exposes the gate insulation layer 306 of part on its bilateral symmetry ground.
Please continue E with reference to Fig. 3, be mask with graphical photoresist layer 312a once more, carry out anisotropic etching process, to remove the segment thickness of gate insulation layer 306, and make the gate insulation layer after the etching have the first position 306a and the second position 306b, wherein the first position 306a of gate insulation layer is positioned at by graphical photoresist layer 312a and covers part, the second position 306b of gate insulation layer is not positioned at and is covered part by graphical photoresist layer 312a, and wherein the thickness of the first position 306a is greater than the thickness of the second position 306b.In one embodiment, above-mentioned anisotropic etching process for example is the segment thickness that removes portion's gate insulation layer with sputter etching (sputter etching) or plasma etching etch processs such as (plasma etching).Behind the anisotropic etching process of finishing gate insulation layer 306, promptly removable graphical photoresist layer 312a.
It should be noted that in another preferred embodiment of the present invention gate insulation layer 306 is made of two-layer above rete.Shown in Fig. 5 A, gate insulation layer 306 is made of first rete 305 and second rete 307.And, the material of first rete 305 for example is that the material with second rete 307 has etching selectivity (etching selectivity), so in the anisotropic etching process of above-mentioned gate insulation layer 306, can second rete 307 as etch stop layer (etching stop layer).Same, the gate insulation layer after the etching has the first position 306a and the second position 306b, and the first position 306a of gate insulation layer 306 has different thickness with the second position 306b of gate insulation layer 306.In one embodiment, first rete 305 for example is silica or silicon nitride, and second rete 307 for example is a silicon nitride.In another embodiment, when first rete 305 can be silicon nitride, second rete 307 for example was a silica.The present invention does not limit the thickness of first rete 305 and the thickness of second rete 307, and it can be for identical or inequality.
Please refer to Fig. 3 F, after removing graphical photoresist layer 312a, is that mask comes polysilicon layer 304 is carried out doping process with grid 310a just then.In a preferred embodiment, for example be to utilize ionic-implantation and with in the ion 321 implanted polysilicon layers 304.Particularly, because of the thickness of the first position 306a of the gate insulation layer thickness greater than the second position 306b of gate insulation layer, the dopant concentration of doped region of first position 306a below that therefore can make gate insulation layer is less than the dopant concentration of the doped region of the second position 306b below of gate insulation layer.Therefore, can form the lightly mixed drain area 316 of low-temperature polysilicon film transistor, and form the source/drain regions 318 of low-temperature polysilicon film transistor in the second position 306b below of gate insulation layer in the first position 306a below of gate insulation layer.Wherein, the not doped region between two lightly mixed drain areas 316 is the channel region 320 of low-temperature polysilicon film transistor, shown in Fig. 3 G.And because in aforesaid technology, undercut phenomenon takes place on the bilateral symmetry of grid 310a ground, therefore two lightly mixed drain areas 316 also are to be formed on symmetrically in the polysilicon layer 304 of grid 310a both sides.
Please refer to Fig. 3 H, after forming source/drain regions 318 and lightly mixed drain area 316, then on gate insulation layer 306, form dielectric layer 322, and cover grid 310a.Then, in dielectric layer 322, form opening 324, and run through gate insulation layer 306 to expose source/drain regions 318.Please refer to Fig. 3 I, form source/drain conductor layer 326 on dielectric layer 322, and insert in the opening 324, so that source/drain conductor layer 326 is electrically connected with source/drain regions 318, this promptly finishes the manufacturing of low-temperature polysilicon film transistor 330 haply.
Below will explain the low-temperature polysilicon film transistor of present embodiment.
Please refer to Fig. 3 I, low-temperature polysilicon film transistor 330 mainly is to be made of polysilicon layer 304, gate insulation layer 306, grid 310a, dielectric layer 322 and 326 on source/drain conductor layer.Wherein, polysilicon layer 304 is arranged on the substrate 300, and polysilicon layer 304 comprises channel region 320, source/drain regions 318 and lightly mixed drain area 316.Source/drain regions 318 is positioned at the both sides of channel region 320, and 316 of lightly mixed drain areas are between channel region 320 and source/drain regions 318.Particularly, lightly mixed drain area 316 is arranged in the polysilicon layer 304 of both sides of grid 310a symmetrically.In addition, in a preferred embodiment, also comprise between polysilicon layer 304 and the substrate 300 being provided with resilient coating 302.
From the above, gate insulation layer 306 is made of the first position 306a and the second position 306b, wherein the first position 306a of gate insulation layer 306 is positioned at the top of channel region 320 and lightly mixed drain area 316, and the second position 306b of gate insulation layer 306 is positioned at the both sides of the first position 306a of gate insulation layer 306.Particularly, the thickness of the first position 306a of gate insulation layer 306 is greater than the thickness of the second position 306b of gate insulation layer 306.
As shown in the above description, the present invention is in the graphical technology of the grid of low-temperature polysilicon film transistor, with graphical photoresist layer is that mask carries out isotropic etching to gate material layers, so after forming grid, the contact grid of graphical photoresist layer bottom surface meeting part.Therefore when being mask and when gate insulation layer carried out anisotropic etching with this graphical photoresist layer again, just can make the gate insulation layer after the etching have two kinds of different thickness, and the thickness difference by gate insulation layer, and can in technology, form source/drain regions and lightly mixed drain area.Therefore, the technology of the present invention's low-temperature polysilicon film transistor can be simplified the technology of lightly mixed drain area, and then saves the technology cost.
And, because the present invention forms grid by isotropic etching, and then make the grid and the face that the connects place of graphical photoresist layer produce the phenomenon of undercutting, therefore the bottom surface that graphical photoresist layer contact with grid is symmetrically located at the both sides of grid, thus follow-up be that the formed lightly mixed drain area of doping mask also can be formed in the polysilicon layer square under the grid both sides symmetrically with the grid.Hence one can see that, and the present invention can improve the symmetry of the lightly mixed drain area of low-temperature polysilicon film transistor, and then make the element characteristic of this low-temperature polysilicon film transistor have preferable symmetry.
Though the present invention with preferred embodiment openly as above; right its is not in order to limit the present invention; the ordinary skill of any technical field that the present invention belongs to; in thought that does not break away from the present invention and scope; when can doing a little change and improvement, so the present invention's protection range is as the criterion when looking claims person of defining.
Claims (19)
1. thin-film transistor is characterized in that comprising:
Polysilicon layer is arranged on the substrate, and have channel region in this polysilicon layer, at the source/drain region and the lightly mixed drain area between this channel region and this source/drain region of these channel region both sides;
Gate insulation layer, be arranged on this substrate, and cover this polysilicon layer, and this gate insulation layer comprises first position and second position, wherein this first position of this gate insulation layer is positioned at the top of this channel region and this lightly mixed drain area, and this second position of this gate insulation layer be positioned at this gate insulation layer this first position both sides and be positioned on this source/drain regions, and the thickness at this first position of this gate insulation layer is greater than the thickness at this second position of this gate insulation layer; And
Grid is arranged on this gate insulation layer directly over this channel region.
2. the thin-film transistor according to claim 1 is characterized in that also comprising:
Dielectric layer is arranged on this gate insulation layer, and covers this grid; And
The source/drain conductor layer is arranged on this dielectric layer and this dielectric layer and this gate insulation layer, and wherein this source/drain conductor layer and this source/drain regions are electrically connected.
3. the thin-film transistor according to claim 1 is characterized in that also comprising resilient coating, and this resilient coating is arranged between this substrate and this polysilicon layer.
4. the thin-film transistor according to claim 3 is characterized in that the material of this resilient coating comprises silica.
5. the thin-film transistor according to claim 1 is characterized in that this gate insulation layer comprises composite bed.
6. the thin-film transistor according to claim 5 is characterized in that this composite bed comprises first rete and second rete, and this first rete is arranged on this polysilicon layer and this substrate, and this second rete then is arranged on this first rete.
7. the thin-film transistor according to claim 6 is characterized in that this first rete and this second rete have etching selectivity.
8. the thin-film transistor according to claim 7 is characterized in that this first rete comprises silicon nitride layer or silicon oxide layer.
9. the thin-film transistor according to claim 7 is characterized in that this second rete comprises silicon nitride layer or silicon oxide layer.
10. method of manufacturing thin film transistor is characterized in that comprising:
On substrate, form polysilicon layer;
On this substrate, form gate insulation layer, and cover this polysilicon layer;
On this gate insulation layer, form gate material layers;
On this gate material layers, form graphical photoresist layer;
With this graphical photoresist layer is mask and this gate material layers of etching, to form grid, wherein after forming this grid, is contacted with this grid the bottom surface portions of this graphical photoresist layer;
With this graphical photoresist layer is mask and this gate insulation layer is carried out anisotropic etching, and make this gate insulation layer after the etching have first position and second position, this first position of this gate insulation layer is positioned at by this graphical photoresist layer covers part, this second position of this gate insulation layer is not positioned at is covered part by this graphical photoresist layer, and wherein the thickness at this first position is greater than the thickness at this second position of this gate insulation layer;
Remove this graphical photoresist layer; And
With this grid is mask, carry out doping process, to form lightly mixed drain area and source/drain regions in this polysilicon layer, wherein this lightly mixed drain area is positioned at this below, first position of this gate insulation layer, and this source/drain regions is positioned at this below, second position of this gate insulation layer.
11. the method for manufacturing thin film transistor according to claim 10 is characterized in that also being included on this substrate and forming resilient coating before forming this polysilicon layer.
12. the method for manufacturing thin film transistor according to claim 10 is characterized in that also comprising:
On this gate insulation layer, form dielectric layer, and cover this grid;
In this dielectric layer and this gate insulation layer, form opening, to expose this source/drain regions; And
On this dielectric layer, form the source/drain conductor layer, and insert in this opening, so that this source/drain conductor layer and this source/drain regions is electric couples.
13. the method for manufacturing thin film transistor according to claim 10 is characterized in that comprising in the step that forms this polysilicon layer:
On this substrate, form amorphous silicon layer; And
Carry out laser annealing technique, so that crystallization again after this amorphous silicon layer fusion, and change this polysilicon layer into.
14. the method for manufacturing thin film transistor according to claim 10 is characterized in that on this substrate and this polysilicon layer forming in the step of this gate insulation layer and comprises:
On this substrate and this polysilicon layer, form first rete; And
On this first rete, form second rete.
15. the method for manufacturing thin film transistor according to claim 14 is characterized in that this first rete and this second rete have etching selectivity.
16. the method for manufacturing thin film transistor according to claim 15 is characterized in that this first rete comprises silicon oxide layer or silicon nitride layer.
17. the method for manufacturing thin film transistor according to claim 15 is characterized in that this second rete comprises silicon oxide layer or silicon nitride layer.
18. the method for manufacturing thin film transistor according to claim 10 is characterized in that comprising in the step of this gate material layers of etching and carries out isotropic etching.
19. the method for manufacturing thin film transistor according to claim 18 is characterized in that this isotropic etching comprises wet etch process.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200410084033 CN1763975A (en) | 2004-10-18 | 2004-10-18 | Thin film transistor and producing method thereof |
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| CN 200410084033 CN1763975A (en) | 2004-10-18 | 2004-10-18 | Thin film transistor and producing method thereof |
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| CN1763975A true CN1763975A (en) | 2006-04-26 |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101533775B (en) * | 2008-03-14 | 2010-12-01 | 中华映管股份有限公司 | Thin film transistor and production method thereof |
| CN101488478B (en) * | 2008-01-17 | 2012-06-06 | 中芯国际集成电路制造(上海)有限公司 | Integrated method for protecting polycrystalline and substrate surface |
| CN103178006A (en) * | 2013-03-29 | 2013-06-26 | 上海和辉光电有限公司 | Method for adjusting threshold voltage of low-temperature polycrystalline silicon transistor valve |
| WO2016090687A1 (en) * | 2014-12-11 | 2016-06-16 | 深圳市华星光电技术有限公司 | Array substrate and method for manufacturing same |
| CN104241390B (en) * | 2013-06-21 | 2017-02-08 | 上海和辉光电有限公司 | Thin film transistor, active matrix organic light emitting diode assembly and manufacturing method |
| CN110349972A (en) * | 2019-06-20 | 2019-10-18 | 深圳市华星光电技术有限公司 | A kind of thin film transistor base plate and preparation method thereof |
| CN110729197A (en) * | 2018-06-29 | 2020-01-24 | 中华映管股份有限公司 | Manufacturing method of semiconductor thin film transistor and display panel |
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2004
- 2004-10-18 CN CN 200410084033 patent/CN1763975A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101488478B (en) * | 2008-01-17 | 2012-06-06 | 中芯国际集成电路制造(上海)有限公司 | Integrated method for protecting polycrystalline and substrate surface |
| CN101533775B (en) * | 2008-03-14 | 2010-12-01 | 中华映管股份有限公司 | Thin film transistor and production method thereof |
| CN103178006A (en) * | 2013-03-29 | 2013-06-26 | 上海和辉光电有限公司 | Method for adjusting threshold voltage of low-temperature polycrystalline silicon transistor valve |
| CN103178006B (en) * | 2013-03-29 | 2015-09-23 | 上海和辉光电有限公司 | The method of adjustment threshold voltage of low-temperature polycrystalline silicon transistor valve |
| CN104241390B (en) * | 2013-06-21 | 2017-02-08 | 上海和辉光电有限公司 | Thin film transistor, active matrix organic light emitting diode assembly and manufacturing method |
| WO2016090687A1 (en) * | 2014-12-11 | 2016-06-16 | 深圳市华星光电技术有限公司 | Array substrate and method for manufacturing same |
| CN110729197A (en) * | 2018-06-29 | 2020-01-24 | 中华映管股份有限公司 | Manufacturing method of semiconductor thin film transistor and display panel |
| CN110349972A (en) * | 2019-06-20 | 2019-10-18 | 深圳市华星光电技术有限公司 | A kind of thin film transistor base plate and preparation method thereof |
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