WO2016090687A1 - Array substrate and method for manufacturing same - Google Patents

Array substrate and method for manufacturing same Download PDF

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Publication number
WO2016090687A1
WO2016090687A1 PCT/CN2014/095367 CN2014095367W WO2016090687A1 WO 2016090687 A1 WO2016090687 A1 WO 2016090687A1 CN 2014095367 W CN2014095367 W CN 2014095367W WO 2016090687 A1 WO2016090687 A1 WO 2016090687A1
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layer
ion
region
gate
photoresist
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PCT/CN2014/095367
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French (fr)
Chinese (zh)
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杜海波
申智渊
占伟
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深圳市华星光电技术有限公司
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Publication of WO2016090687A1 publication Critical patent/WO2016090687A1/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular to a method for fabricating an array substrate and a corresponding array substrate.
  • LTPS Low Temperature Poly-silicon
  • the TFT low temperature polysilicon thin film transistor
  • LDD Lightly Doped Drain
  • a method of forming a SiNx Foot under the photoresist coverage region by a lateral etching process when the gate conductive layer is dry etched corresponds to a thickness at the SiNx Foot that is greater than a thickness of the gate insulating layer corresponding to the photoresist-free coverage region. Then, an ion doping treatment is performed. At the SiNx Foot, due to the large thickness of the gate insulating layer, an ion lightly doped region is finally formed in the low temperature polysilicon active layer below it.
  • the gate insulating layer has a smaller thickness corresponding to the photoresist-free coverage region, and finally forms an ion heavily doped region in the low-temperature polysilicon active layer below it. This method saves one yellow light and one ion implantation process, but it is difficult to control lateral etching when implemented.
  • the present invention provides a method for fabricating an array substrate based on an LDD structure thin film transistor that does not require lateral etching, and a corresponding array substrate.
  • a method for fabricating an array substrate comprising:
  • a substrate forming the ion lightly doped region and the ion heavily doped region is processed to form a gate, a source drain, and a pixel electrode.
  • the photoresist region of different photoresist thickness includes a central portion of the first thickness and a second thickness of the wing portion extending from the central portion toward the periphery of the periphery, wherein the first portion The thickness is greater than the second thickness, and the central portion is correspondingly formed by the opaque region of the semi-transmissive reticle, and the wing portion is correspondingly formed by the semi-transmissive region of the semi-transmissive reticle.
  • the hollowed out region is correspondingly formed by a completely transparent region of the semi-transmissive reticle.
  • the cover layer comprises a gate insulating layer.
  • the capping layer comprises a gate insulating layer and a gate conductive layer on the gate insulating layer.
  • forming the ion lightly doped region and the ion heavily doped region comprises:
  • forming the ion lightly doped region and the ion heavily doped region comprises:
  • the gate guide And a portion of the portion of the gate insulating layer corresponding to the hollow region and a portion of the photoresist of the central portion, wherein the gate insulating layer after the dry etching process corresponds to the original wing
  • the thickness of the portion of the portion is greater than the thickness of the portion of the gate insulating layer corresponding to the original hollow region, and the gate conductive layer forms a gate corresponding to the portion of the central portion;
  • processing a substrate forming an ion lightly doped region and an ion heavily doped region to form a gate, a source drain, and a pixel electrode includes:
  • an organic planarization layer Forming an organic planarization layer, a common electrode, a passivation layer, and a connection hole extending to the drain on the passivation layer on the source/drain metal layer, and coating a transparent conductive material on the passivation layer A pixel electrode electrically connected to the drain is formed.
  • processing a substrate forming an ion lightly doped region and an ion heavily doped region to form a gate, a source drain, and a pixel electrode includes:
  • an organic planarization layer Forming an organic planarization layer, a common electrode, a passivation layer, and a connection hole extending to the drain on the passivation layer on the source/drain metal layer, and coating a transparent conductive material on the passivation layer A pixel electrode electrically connected to the drain is formed.
  • an array substrate fabricated by any of the above methods.
  • the invention avoids the low temperature polysilicon thin film transistor which forms the LDD structure by the lateral etching process, and reduces the difficulty of fabricating the array substrate by using the low temperature polysilicon thin film transistor.
  • FIG. 1 is a flow chart of a method in accordance with one embodiment of the present invention.
  • FIG. 2a is a schematic view showing exposure results after forming a cap layer (without a gate layer) on a substrate according to an embodiment of the present invention
  • Figure 2b is a schematic view of the ion heavy doping treatment of the substrate of Figure 2a;
  • FIG. 2c is a schematic view of the ion light doping treatment after the dry etching process of the substrate of FIG. 2b;
  • 3a is a schematic view showing exposure results after forming a cap layer (including a gate layer) on a substrate according to an embodiment of the present invention
  • FIG. 3b is a schematic diagram of ion heavy doping treatment after dry etching of the substrate of FIG. 3a.
  • the off-state current of the LTPS TFT includes a light leakage current and a leakage current caused by a strong electric field of the drain.
  • an LDD structure is added between the highly doped N+ region and the intrinsic N region of the drain of the LTPS TFT, that is, a lightly doped N-region having an order of magnitude lower than the N+ region is doped to suppress leakage current.
  • N represents an N-type ion.
  • the LDD structure is equivalent to a large resistance connected in series between the drain source and the conductive channel. This structure reduces the horizontal electric field of the conductive channel and reduces the hot carriers generated by the impact ionization caused by the electric field acceleration, which can effectively Suppresses leakage currents of two orders of magnitude or so.
  • FIG. 1 is a flowchart of a method in accordance with an embodiment of the present invention, and the method of the present invention will be described in detail below with reference to FIG. 1.
  • step S110 a polysilicon active layer and a cap layer are sequentially formed on the substrate. This step can be further divided into the following steps.
  • a polysilicon active layer is formed on a substrate, and an intrinsic a-Si layer (amorphous silicon layer) is usually deposited by a PECVD (Plasma Enhanced Chemical Vapor Deposition) method; then, the a-Si layer is subjected to an a-Si layer. Dehydrogenation treatment; finally, a polysilicon active layer is formed by a process such as ELA (excimer laser annealing) or SLC (continuous lateral crystallization). As shown in Figures 2a and 3a, a polysilicon active layer 12 is deposited on the substrate 11, where Poly represents polysilicon.
  • PECVD Pullasma Enhanced Chemical Vapor Deposition
  • the cover layer is a gate insulating layer formed by depositing an insulating material by PECVD.
  • the gate insulating layer may be composed of a silicon oxide layer or a silicon oxide layer and a silicon nitride layer which are sequentially formed.
  • a polysilicon active layer 12 is deposited on the substrate 11, and a gate insulating layer 13 is deposited on the polysilicon active layer 12.
  • the gate insulating layer 13 includes a silicon oxide layer 131 (corresponding to GI-SiOx in FIG. 2a) and a silicon nitride layer 132 on the silicon oxide layer (corresponding to GI-SiNx in FIG. 2a).
  • the cap layer includes a gate insulating layer and a gate conductive layer on the gate insulating layer.
  • the gate insulating layer may be composed of a silicon oxide layer or a silicon oxide layer and a silicon nitride layer which are sequentially formed.
  • the gate conductive layer may be formed by depositing molybdenum or other metal on the gate insulating layer by a sputtering method. As shown in FIG. 3a, a polysilicon active layer 12 is deposited on the substrate 11, and a gate insulating layer 13 is deposited on the polysilicon active layer 12, the gate insulating layer including a silicon oxide layer 131 (corresponding to the GI in FIG.
  • a gate conductive layer 14 (corresponding to GE-Metal in Fig. 3a) is deposited on the silicon nitride layer 132.
  • a silicon oxide layer is usually deposited on the substrate as a buffer layer, and then a polysilicon active layer is formed on the buffer layer.
  • the buffer layer can shield the influence of defects on the substrate, prevent impurities such as metal ions on the substrate from diffusing and penetrating into the active layer of the polysilicon, and avoid various device defects caused thereby.
  • step S120 a photoresist region having a different photoresist thickness and a cutout region of the bare cap layer are formed on the cover layer.
  • a layer of photoresist (photoresist material) is coated on the cover layer; then, the coated photoresist material is exposed to light using a semi-transmissive mask.
  • a semi-transmissive reticle is employed as in the reticle 21 of Figures 2a and 3a.
  • the reticle 21 includes a non-exposed area 1 (opaque area), a half exposure area 2 (semi-transmissive area), and a full exposure area 3 (completely transparent area).
  • the photoresist material is exposed to light to form photoresist regions of different photoresist thicknesses.
  • the photoresist region includes a central portion 1' of a first thickness and a second thickness of the wing portion 2' extending toward both sides of the peripheral portion.
  • the central portion 1' is correspondingly formed by the non-exposure region 1 of the reticle 21, and the wing portion 2' is correspondingly formed by the half-exposure region 2 of the reticle 21.
  • the hollowed out regions 3' between the photoresist regions are correspondingly formed by the fully exposed regions 3 of the photomask 21.
  • the thickness of the photoresist corresponding to the central portion 1' is greater than the thickness of the photoresist corresponding to the wing portion 2'.
  • the hollowed out area 3' has no photoresist coverage, and the hollowed out area directly exposes the cover layer.
  • step S130 the substrates forming the photoresist regions of different photoresist thicknesses are processed to form an ion heavily doped region and an ion lightly doped region in the polysilicon active layer.
  • the following steps are included in forming the ion heavily doped region and the ion light doped region.
  • FIG. 2b is a schematic diagram of the ion heavy doping treatment of the substrate of FIG. 2a, where N-type ion implantation is taken as an example, and N+ represents a high concentration N ion current.
  • 41 denotes a high-concentration N ion current for performing ion heavy doping treatment.
  • the regions of the polysilicon active layer corresponding to the central portion 1' and the wing portion 2' are not ion doped due to the blocking of the photoresist. While the hollow region 3' is not blocked by the photoresist, the region corresponding to the hollow region in the polysilicon active layer is ion-doped, thereby forming the ion heavily doped region 121.
  • the substrate after the ion heavy doping treatment is subjected to dry etching treatment to remove the wings. Since the photoresist thickness of the central portion is greater than the photoresist thickness of the wing portion, the wing portion 2' is completely removed by controlling the amount of etching gas processed by the dry etching process, and part of the photoresist at the upper portion of the central portion 1' is removed, as shown in FIG. 2c. Show. Of course, other etching gases that can simultaneously etch away the photoresist and the gate insulating layer can be used here, but the thickness of the gate insulating layer after etching is required to meet the requirements.
  • the dry etch process may be replaced by a dry ashing process.
  • Dry ashing uses oxygen as the etching gas. When oxygen is used as the etching gas, only the photoresist is etched away without etching off the gate insulating layer.
  • 2c is a schematic diagram of the ion light doping treatment after the dry etching process of the substrate of FIG. 2b, and N- represents a low concentration N ion current. Wherein 42 represents a low concentration N ion stream for performing ion light doping treatment.
  • the regions of the polysilicon active layer corresponding to the original wing portion 2' and the original hollow region 3' are not blocked by light, and these regions in the polysilicon active layer are ionically lightly doped.
  • the corresponding original center portion 1' of the polysilicon active layer is not subjected to ion light doping.
  • ion light doping treatment is simultaneously performed simultaneously with the region corresponding to the original wing portion 2' in the polysilicon active layer. . In this way, the distribution of the lightly doped regions of the ions is ensured without weakening the original heavily doped regions of ions.
  • the resulting ion heavily doped region 121 and ion lightly doped region 122 are shown in Figure 2c.
  • the dry etching process and the ion light doping process performed on FIG. 2b can be completed by only one yellow light process, that is, simultaneous dry etching treatment and ion light doping treatment, thereby saving a yellow light and Photoresist stripping process.
  • the non-ion doped region is shielded by forming a semi-exposure photoresist for the semi-transmissive mask according to FIG. 2a, and the width of the ion heavily doped region and the ion lightly doped region can be effectively controlled without generating ion heavily doped regions and ions. Abnormal overlap in lightly doped areas question.
  • the photoresist is removed by dry etching or dry ashing, and the process is simple and easy to operate.
  • the following steps are included in forming the ion heavily doped region and the ion light doped region.
  • a dry etching process is performed on a substrate forming a photoresist region having different photoresist thicknesses for removing a portion of the wing portion, the gate conductive layer corresponding to the wing portion, and a portion of the gate insulating layer corresponding to the wing portion, and A portion of the gate conductive layer corresponding to the cutout region and a portion of the gate insulating layer corresponding to the cutout region are removed. Due to the influence of the wings, after the dry etching process is completed, the thickness of the portion of the gate insulating layer corresponding to the original wing portion is greater than the thickness of the portion of the gate insulating layer corresponding to the original hollow region. At the same time, since the photoresist thickness of the central portion is larger than the photoresist thickness of the wing portion, a portion of the central portion retains a portion of the photoresist after the wing portion is removed.
  • this step by controlling the amount of etching, it is possible to completely etch away the portion of the gate conductive layer corresponding to the original wing portion without etching the portion of the gate insulating layer corresponding to the original wing portion, as shown in FIG. 3b.
  • a portion of the insulating layer may be etched away from the corresponding original wing portion of the gate insulating layer, but it is ensured that the thickness of the finally formed gate insulating layer satisfies the requirements.
  • the substrate after the dry etching treatment is subjected to ion heavy doping treatment.
  • a thin region corresponding to the gate insulating layer is formed in the polysilicon active layer.
  • the 3' ion heavily doped region 121 forms an ion lightly doped region 122 corresponding to the thicker region 2' of the gate insulating layer in the polysilicon active layer.
  • the ion lightly doped region 122 forms an LDD as shown in Figure 3b.
  • a gate corresponding to the original central portion 1' is formed in the gate conductive layer.
  • the dry etching process and the ion heavy doping process performed for FIG. 3a can be completed by only one yellow light process, that is, the dry etching process and the ion heavy doping process are simultaneously performed, thereby saving a yellow light. , doping and photoresist stripping process.
  • the embodiment of FIG. 3a mainly utilizes the difference in photoresist thickness, and adjusts the thickness selection ratio between the photoresist and the gate conductive layer, the gate conductive layer and the gate insulating layer during the dry etching process, and finally forms the gate insulating layer.
  • the difference in thickness is to simultaneously form an ion heavily doped region and an ion lightly doped region in a subsequent ion heavy doping process.
  • the method only performs an ion implantation process and an exposure process, which reduces the process cost, is simple in process, and is easy to operate.
  • the ion implantation method adopted here can easily control the width of the ion heavily doped region and the ion lightly doped region, and does not cause the problem of abnormal overlap between the ion heavily doped region and the ion light doped region.
  • step S140 the remaining photoresist is removed and the substrate forming the ion heavily doped region and the ion lightly doped region is processed to obtain a desired array substrate.
  • the cap layer 12 in FIG. 2c does not include a gate conductive layer
  • the remaining photoresist in FIG. 2c is first removed after completing the ion doping process on FIG. 2c; Depositing chromium or other metal to form a gate conductive layer by sputtering; then performing exposure development on the gate conductive layer and other conventional processes to form a gate pole.
  • a transparent conductive material is coated on the substrate and a pixel electrode electrically connected to the drain is formed by a process such as yellowing, etching, stripping, or the like.
  • a gate conductive layer has been formed prior to the ion doping process.
  • the gate conductive layer forms a gate after the dry etching process.
  • the subsequent subsequent processes are the same as the processes after the gates are formed in the substrate shown in FIG. 2c.
  • an array substrate fabricated by the above method includes a polysilicon active layer and a cap layer sequentially formed on the substrate, an ion heavily doped region corresponding to the source and drain electrodes, and An ion lightly doped region and a gate, an interlayer insulating layer and a source/drain conductive layer, an organic flat layer attached to the interlayer insulating layer, a bottom common electrode layer, a passivation layer, and a top pixel electrode.
  • any one of an N-type ion or a P-type ion is performed by ion doping treatment.
  • a plurality of (two or more) regions of different light transmission amount may be disposed as needed, thereby forming a plurality of photoresist regions having different photoresist thicknesses during exposure, and further having Different regions in the source layer achieve different concentrations of ion doping.

Abstract

An array substrate and a method for manufacturing same comprising: sequentially forming a polycrystalline silicon active layer (12) and a covering layer on a substrate (11); coating the cover layer with photo-resist, and conducting exposure imaging treatment on a semi-transparent photo mask so as to correspondingly form at least one photo-resist area with different photo-resist thicknesses and at least one hollow area exposing the covering layer on the covering layer; processing the substrate (11) forming with the photo-resist area in order to form an ionic lightly doped area (122) corresponding to a partial area of the photo-resist area and an ionic heavily doped area (121) corresponding to the hollow area in the polycrystalline silicon active layer (12); processing the substrate (11) forming with the ionic lightly doped area (122) and the ionic heavily doped area (121) to form a gate electrode, a source drain electrode and a pixel electrode.

Description

用于制作阵列基板的方法及阵列基板Method for fabricating array substrate and array substrate
相关技术的交叉引用Cross-reference to related art
本申请要求享有2014年12月11日提交的名称为：“用于制作阵列基板的方法及阵列基板”的中国专利申请CN201410764490.2的优先权，其全部内容通过引用并入本文中。The present application claims priority to Chinese Patent Application No. CN201410764490.2, filed on Dec. 11, 2014, which is hereby incorporated by reference in its entirety, the entire disclosure of the disclosure of
技术领域Technical field
本发明涉及液晶显示技术领域，具体地说，涉及一种用于制作阵列基板的方法及对应的阵列基板。The present invention relates to the field of liquid crystal display technology, and in particular to a method for fabricating an array substrate and a corresponding array substrate.
背景技术Background technique
低温多晶硅(Low Temperature Poly-silicon，简称LTPS)被用于制作新一代薄膜晶体管液晶面板。与传统非晶硅液晶面板相比，该种液晶面板具有反应速度快、亮度高、解析度高与耗电量低等优点。Low Temperature Poly-silicon (LTPS) is used to make a new generation of thin film transistor liquid crystal panels. Compared with the conventional amorphous silicon liquid crystal panel, the liquid crystal panel has the advantages of high reaction speed, high brightness, high resolution and low power consumption.
在采用LTPS技术制作液晶面板时，当LTPS TFT(低温多晶硅薄膜晶体管)中的沟道长度变短时，随着TFT(thin film transistor，薄膜晶体管)的导通，该TFT靠近漏极处的电场强度变得很大。这就会导致漏极处的热载子效应加剧，进而使得TFT器件的可靠性变差。为提高TFT的可靠性，LDD(Lightly Doped Drain，轻掺杂漏极)结构的低温多晶硅薄膜晶体管应运而生。通过LDD调节漏极电压，降低漏极处的电场强度，从而提高低温多晶硅薄膜晶体管的可靠性。When the liquid crystal panel is fabricated by the LTPS technology, when the channel length in the LTPS TFT (low temperature polysilicon thin film transistor) becomes short, the TFT is close to the electric field at the drain as the thin film transistor is turned on. The intensity becomes very large. This causes an increase in the hot carrier effect at the drain, which in turn deteriorates the reliability of the TFT device. In order to improve the reliability of the TFT, a low-temperature polysilicon thin film transistor of LDD (Lightly Doped Drain) structure has emerged. The drain voltage is adjusted by the LDD to lower the electric field strength at the drain, thereby improving the reliability of the low temperature polysilicon thin film transistor.
目前，在制作LDD结构的低温多晶硅薄膜晶体管时，有一种方法是在对栅极导电层进行干蚀刻时，通过侧向蚀刻工艺在光阻覆盖区下方形成SiNx Foot(氮化硅脚)。栅极绝缘层对应于SiNx Foot处的厚度大于栅极绝缘层对应于无光阻覆盖区的厚度。然后进行离子掺杂处理，在SiNx Foot处，因栅极绝缘层的厚度较大，最终在其下方的低温多晶硅有源层中形成离子轻掺杂区。栅极绝缘层对应于无光阻覆盖区的厚度较小，最终在其下方的低温多晶硅有源层中形成离子重掺杂区。这种方法节省了1道黄光和1道离子植入工艺，但在实现时，控制侧向蚀刻的难度较高。At present, in the fabrication of a low temperature polysilicon thin film transistor of an LDD structure, there is a method of forming a SiNx Foot under the photoresist coverage region by a lateral etching process when the gate conductive layer is dry etched. The gate insulating layer corresponds to a thickness at the SiNx Foot that is greater than a thickness of the gate insulating layer corresponding to the photoresist-free coverage region. Then, an ion doping treatment is performed. At the SiNx Foot, due to the large thickness of the gate insulating layer, an ion lightly doped region is finally formed in the low temperature polysilicon active layer below it. The gate insulating layer has a smaller thickness corresponding to the photoresist-free coverage region, and finally forms an ion heavily doped region in the low-temperature polysilicon active layer below it. This method saves one yellow light and one ion implantation process, but it is difficult to control lateral etching when implemented.
发明内容 Summary of the invention
为解决上述问题，本发明提供了一种基于不需进行侧向蚀刻的LDD结构薄膜晶体管的阵列基板的制作方法及对应的阵列基板。In order to solve the above problems, the present invention provides a method for fabricating an array substrate based on an LDD structure thin film transistor that does not require lateral etching, and a corresponding array substrate.
根据本发明的一个方面，提供了一种用于制作阵列基板的方法，包括：According to an aspect of the invention, a method for fabricating an array substrate is provided, comprising:
在基板上依次形成多晶硅有源层和覆盖层；Forming a polysilicon active layer and a cap layer sequentially on the substrate;
在所述覆盖层上涂覆光阻，并采用半透光光罩经曝光显影处理以在所述覆盖层上对应形成至少一个具有不同光阻厚度的光阻区及裸露所述覆盖层的镂空区；Coating a photoresist on the cover layer, and exposing and developing the film by using a semi-transmissive reticle to form at least one photoresist region having different photoresist thicknesses on the cover layer and hollowing out the cover layer Area;
对形成所述光阻区的基板进行处理以在所述多晶硅有源层中形成对应于所述光阻区的部分区域的离子轻掺杂区和对应于所述镂空区的离子重掺杂区；Processing a substrate forming the photoresist region to form an ion lightly doped region corresponding to a partial region of the photoresist region and an ion heavily doped region corresponding to the void region in the polysilicon active layer ;
对形成所述离子轻掺杂区和所述离子重掺杂区的基板进行处理以形成栅极、源漏极和像素电极。A substrate forming the ion lightly doped region and the ion heavily doped region is processed to form a gate, a source drain, and a pixel electrode.
根据本发明的一个实施例，所述不同光阻厚度的光阻区包括第一厚度的中心部及由所述中心部向外围两侧延伸的第二厚度的翼部，其中，所述第一厚度大于所述第二厚度，通过所述半透光光罩的不透光区对应地形成所述中心部，通过所述半透光光罩的半透光区对应地形成所述翼部。According to an embodiment of the present invention, the photoresist region of different photoresist thickness includes a central portion of the first thickness and a second thickness of the wing portion extending from the central portion toward the periphery of the periphery, wherein the first portion The thickness is greater than the second thickness, and the central portion is correspondingly formed by the opaque region of the semi-transmissive reticle, and the wing portion is correspondingly formed by the semi-transmissive region of the semi-transmissive reticle.
根据本发明的一个实施例，通过所述半透光光罩的完全透光区对应地形成所述镂空区。According to an embodiment of the invention, the hollowed out region is correspondingly formed by a completely transparent region of the semi-transmissive reticle.
根据本发明的一个实施例，所述覆盖层包括栅极绝缘层。According to an embodiment of the invention, the cover layer comprises a gate insulating layer.
根据本发明的一个实施例，所述覆盖层包括栅极绝缘层及所述栅极绝缘层上的栅极导电层。According to an embodiment of the invention, the capping layer comprises a gate insulating layer and a gate conductive layer on the gate insulating layer.
根据本发明的一个实施例，形成所述离子轻掺杂区和所述离子重掺杂区包括：According to an embodiment of the invention, forming the ion lightly doped region and the ion heavily doped region comprises:
对形成所述光阻区的基板进行离子重掺杂处理，以在所述多晶硅有源层中形成对应所述镂空区的离子重掺杂区，在所述多晶硅有源层中对应所述中心部和所述翼部的部分没有离子掺杂；Performing an ion heavy doping treatment on the substrate forming the photoresist region to form an ion heavily doped region corresponding to the hollow region in the polysilicon active layer, corresponding to the center in the polysilicon active layer The portion and the portion of the wing are free of ion doping;
对进行离子重掺杂处理后的基板进行干蚀刻处理以去除所述翼部对应的光阻，对应原所述中心部的光阻部分保留；Performing a dry etching process on the substrate subjected to the ion heavy doping treatment to remove the photoresist corresponding to the wing portion, and retaining the photoresist portion corresponding to the original center portion;
对干蚀刻处理后的基板进行离子轻掺杂处理，其中，在所述多晶硅有源层中形成对应原所述翼部的离子轻掺杂区，在所述多晶硅有源层中对应原所述中心部的部分没有离子掺杂。Performing an ion light doping treatment on the substrate after the dry etching process, wherein an ion lightly doped region corresponding to the original wing portion is formed in the polysilicon active layer, corresponding to the original in the polysilicon active layer The portion of the center portion is free of ion doping.
根据本发明的一个实施例，形成所述离子轻掺杂区和所述离子重掺杂区包括：According to an embodiment of the invention, forming the ion lightly doped region and the ion heavily doped region comprises:
对形成所述光阻区的基板进行干蚀刻处理以去除以下的部分：所述翼部、所述栅极导电层中对应原所述翼部的部分及部分所述栅极绝缘层对应所述翼部的部分、所述栅极导 电层对应所述镂空区的部分及部分所述栅极绝缘层对应所述镂空区的部分、所述中心部的部分光阻，其中，干蚀刻处理后的栅极绝缘层对应原所述翼部的部分的厚度大于栅极绝缘层对应原所述镂空区的部分的厚度，所述栅极导电层对应原所述中心部的部分形成栅极；Performing a dry etching process on the substrate forming the photoresist region to remove the portion, the wing portion, a portion of the gate conductive layer corresponding to the original wing portion, and a portion of the gate insulating layer corresponding to the a portion of the wing, the gate guide And a portion of the portion of the gate insulating layer corresponding to the hollow region and a portion of the photoresist of the central portion, wherein the gate insulating layer after the dry etching process corresponds to the original wing The thickness of the portion of the portion is greater than the thickness of the portion of the gate insulating layer corresponding to the original hollow region, and the gate conductive layer forms a gate corresponding to the portion of the central portion;
对干蚀刻处理后的基板进行离子重掺杂处理以在所述多晶硅有源层中形成对应原所述翼部的离子轻掺杂区，在所述多晶硅有源层中形成对应原所述镂空区的离子重掺杂区。Performing an ion heavy doping treatment on the dry-etched substrate to form an ion lightly doped region corresponding to the original wing portion in the polysilicon active layer, and forming a corresponding hollow in the polysilicon active layer The ion heavily doped region of the region.
根据本发明的一个实施例，对形成离子轻掺杂区和离子重掺杂区的基板进行处理以形成栅极、源漏极和像素电极包括：According to an embodiment of the present invention, processing a substrate forming an ion lightly doped region and an ion heavily doped region to form a gate, a source drain, and a pixel electrode includes:
去除所述栅极绝缘层上的光阻，在所述栅极绝缘层上沉积导电材料并进行处理以形成栅极；Removing a photoresist on the gate insulating layer, depositing a conductive material on the gate insulating layer and processing to form a gate;
在形成栅极的基板上沉积绝缘材料形成层间绝缘层，并对所述层间绝缘层和所述栅极绝缘层进行蚀刻处理以形成连接到所述离子重掺杂区的接触孔，在所述层间绝缘层上形成对应连接所述接触孔的源漏极金属层，并定义形成源漏极；Depositing an insulating material on the substrate forming the gate to form an interlayer insulating layer, and etching the interlayer insulating layer and the gate insulating layer to form a contact hole connected to the ion heavily doped region, Forming a source/drain metal layer corresponding to the contact hole on the interlayer insulating layer, and defining a source and a drain;
在所述源漏极金属层上依次形成有机平坦化层、共通电极、钝化层及所述钝化层上延伸至漏极的连接孔，并在所述钝化层上涂覆透明导电材料形成与所述漏极电气连接的像素电极。Forming an organic planarization layer, a common electrode, a passivation layer, and a connection hole extending to the drain on the passivation layer on the source/drain metal layer, and coating a transparent conductive material on the passivation layer A pixel electrode electrically connected to the drain is formed.
根据本发明的一个实施例，对形成离子轻掺杂区和离子重掺杂区的基板进行处理以形成栅极、源漏极和像素电极包括：According to an embodiment of the present invention, processing a substrate forming an ion lightly doped region and an ion heavily doped region to form a gate, a source drain, and a pixel electrode includes:
去除所述栅极上的光阻以裸露光阻覆盖的栅极；Removing a photoresist on the gate to cover the gate covered by the exposed photoresist;
在形成栅极的基板上沉积绝缘材料形成层间绝缘层，并对所述层间绝缘层和所述栅极绝缘层进行蚀刻处理以形成连接到所述离子重掺杂区的接触孔，在所述层间绝缘层上形成对应连接所述接触孔的源漏极金属层，并定义形成源漏极；Depositing an insulating material on the substrate forming the gate to form an interlayer insulating layer, and etching the interlayer insulating layer and the gate insulating layer to form a contact hole connected to the ion heavily doped region, Forming a source/drain metal layer corresponding to the contact hole on the interlayer insulating layer, and defining a source and a drain;
在所述源漏极金属层上依次形成有机平坦化层、共通电极、钝化层及所述钝化层上延伸至漏极的连接孔，并在所述钝化层上涂覆透明导电材料形成与所述漏极电气连接的像素电极。Forming an organic planarization layer, a common electrode, a passivation layer, and a connection hole extending to the drain on the passivation layer on the source/drain metal layer, and coating a transparent conductive material on the passivation layer A pixel electrode electrically connected to the drain is formed.
根据本发明的另一个方面，还提供了一种采用以上任一项方法制作的阵列基板。According to another aspect of the present invention, there is also provided an array substrate fabricated by any of the above methods.
本发明避免了采用侧向蚀刻工艺形成LDD结构的低温多晶硅薄膜晶体管，降低了采用低温多晶硅薄膜晶体管制作阵列基板的难度。The invention avoids the low temperature polysilicon thin film transistor which forms the LDD structure by the lateral etching process, and reduces the difficulty of fabricating the array substrate by using the low temperature polysilicon thin film transistor.
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。 Other features and advantages of the invention will be set forth in the description which follows, The objectives and other advantages of the invention may be realized and obtained by means of the structure particularly pointed in the appended claims.
附图说明DRAWINGS
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例共同用于解释本发明，并不构成对本发明的限制。在附图中：The drawings are intended to provide a further understanding of the invention, and are intended to be a part of the description of the invention. In the drawing:
图1是根据本发明的一个实施例的方法流程图；1 is a flow chart of a method in accordance with one embodiment of the present invention;
图2a是根据本发明的一个实施例的在基板上形成覆盖层(不含栅极层)后的曝光结果示意图；2a is a schematic view showing exposure results after forming a cap layer (without a gate layer) on a substrate according to an embodiment of the present invention;
图2b是对图2a的基板进行离子重掺杂处理的示意图；Figure 2b is a schematic view of the ion heavy doping treatment of the substrate of Figure 2a;
图2c是对图2b的基板干蚀刻处理后进行离子轻掺杂处理的示意图；2c is a schematic view of the ion light doping treatment after the dry etching process of the substrate of FIG. 2b;
图3a是根据本发明的一个实施例的在基板上形成覆盖层(含栅极层)后的曝光结果示意图；以及3a is a schematic view showing exposure results after forming a cap layer (including a gate layer) on a substrate according to an embodiment of the present invention;
图3b是对图3a的基板干蚀刻处理后进行离子重掺杂处理的示意图。FIG. 3b is a schematic diagram of ion heavy doping treatment after dry etching of the substrate of FIG. 3a.
具体实施方式detailed description
为使本发明的目的、技术方案和优点更加清楚，以下结合附图对本发明作进一步地详细说明。In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail below with reference to the accompanying drawings.
目前，减小关态电流对用作像素开关的LTPS TFT特别重要，而影响LTPS TFT关态电流的主要因素是器件结构。LTPS TFT的关态电流包括光照漏电流和由漏极强电场引起的漏电流。一般在LTPS TFT的漏极的高掺杂N+区和本征N区中间追加LDD结构，即掺入比N+区低一个数量级的轻掺杂N-区，来抑制漏电流。此处的N表示N型离子。At present, reducing the off-state current is particularly important for the LTPS TFT used as a pixel switch, and the main factor affecting the off-state current of the LTPS TFT is the device structure. The off-state current of the LTPS TFT includes a light leakage current and a leakage current caused by a strong electric field of the drain. Generally, an LDD structure is added between the highly doped N+ region and the intrinsic N region of the drain of the LTPS TFT, that is, a lightly doped N-region having an order of magnitude lower than the N+ region is doped to suppress leakage current. Here, N represents an N-type ion.
LDD结构相当于在漏源极和导电沟道之间串联了一个大电阻，该结构降低了导电沟道的水平电场，减少了由电场加速引起的碰撞电离产生的热载流子，可以有效地抑制两个数量级左右的漏电流。The LDD structure is equivalent to a large resistance connected in series between the drain source and the conductive channel. This structure reduces the horizontal electric field of the conductive channel and reduces the hot carriers generated by the impact ionization caused by the electric field acceleration, which can effectively Suppresses leakage currents of two orders of magnitude or so.
如图1所示为根据本发明的一个实施例的方法流程图，以下参考图1来对本发明所述的方法进行详细说明。1 is a flowchart of a method in accordance with an embodiment of the present invention, and the method of the present invention will be described in detail below with reference to FIG. 1.
在步骤S110中，在基板上依次形成多晶硅有源层和覆盖层。该步骤可以进一步划分为以下的几个步骤。In step S110, a polysilicon active layer and a cap layer are sequentially formed on the substrate. This step can be further divided into the following steps.
首先，在基板上形成多晶硅有源层，通常采用PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学气相沉积)法沉积本征a-Si层(非晶硅层)；然后对a-Si层进行脱氢处理；最后采用ELA(准分子激光退火)或SLC(连续横向晶化)等工艺形成多晶硅有源层。如图2a和3a所示，在基板11上沉积有多晶硅有源层12，此处Poly表示多晶硅。 First, a polysilicon active layer is formed on a substrate, and an intrinsic a-Si layer (amorphous silicon layer) is usually deposited by a PECVD (Plasma Enhanced Chemical Vapor Deposition) method; then, the a-Si layer is subjected to an a-Si layer. Dehydrogenation treatment; finally, a polysilicon active layer is formed by a process such as ELA (excimer laser annealing) or SLC (continuous lateral crystallization). As shown in Figures 2a and 3a, a polysilicon active layer 12 is deposited on the substrate 11, where Poly represents polysilicon.
接下来，在多晶硅有源层上形成覆盖层。在本发明的一个实施例中，该覆盖层为一层由PECVD法沉积绝缘材料形成的栅极绝缘层。该栅极绝缘层可由一氧化硅层构成，或者由依次形成的氧化硅层和氮化硅层构成。如图2a所示，在基板11上沉积有多晶硅有源层12，在多晶硅有源层12上沉积有栅极绝缘层13。该栅极绝缘层13包括氧化硅层131(对应图2a中的GI-SiOx)和该氧化硅层上的氮化硅层132(对应图2a中的GI-SiNx)。Next, a cap layer is formed on the polysilicon active layer. In one embodiment of the invention, the cover layer is a gate insulating layer formed by depositing an insulating material by PECVD. The gate insulating layer may be composed of a silicon oxide layer or a silicon oxide layer and a silicon nitride layer which are sequentially formed. As shown in FIG. 2a, a polysilicon active layer 12 is deposited on the substrate 11, and a gate insulating layer 13 is deposited on the polysilicon active layer 12. The gate insulating layer 13 includes a silicon oxide layer 131 (corresponding to GI-SiOx in FIG. 2a) and a silicon nitride layer 132 on the silicon oxide layer (corresponding to GI-SiNx in FIG. 2a).
在本发明的一个实施例中，该覆盖层包括一层栅极绝缘层及该栅极绝缘层上的栅极导电层。该栅极绝缘层可由一氧化硅层构成，或者由依次形成的氧化硅层和氮化硅层构成。栅极导电层可采用溅射法在栅极绝缘层上沉积钼或其它金属形成。如图3a所示，在基板11上沉积有多晶硅有源层12，在多晶硅有源层12上沉积有栅极绝缘层13，该栅极绝缘层包括氧化硅层131(对应图3a中的GI-SiOx)和该氧化硅层131上的氮化硅层132(对应图3a中的GI-SiNx)。同时，在氮化硅层132上沉积有栅极导电层14(对应图3a中的GE-Metal)。In one embodiment of the invention, the cap layer includes a gate insulating layer and a gate conductive layer on the gate insulating layer. The gate insulating layer may be composed of a silicon oxide layer or a silicon oxide layer and a silicon nitride layer which are sequentially formed. The gate conductive layer may be formed by depositing molybdenum or other metal on the gate insulating layer by a sputtering method. As shown in FIG. 3a, a polysilicon active layer 12 is deposited on the substrate 11, and a gate insulating layer 13 is deposited on the polysilicon active layer 12, the gate insulating layer including a silicon oxide layer 131 (corresponding to the GI in FIG. 3a) - SiOx) and a silicon nitride layer 132 on the silicon oxide layer 131 (corresponding to GI-SiNx in Fig. 3a). At the same time, a gate conductive layer 14 (corresponding to GE-Metal in Fig. 3a) is deposited on the silicon nitride layer 132.
在步骤S110中，通常会在基板上沉积一氧化硅层用作缓冲层，然后在该缓冲层上形成多晶硅有源层。该缓冲层可以屏蔽基板上缺陷的影响，防止基板上的杂质如金属离子等扩散并渗透到多晶硅有源层，避免由此引起的各种器件不良。In step S110, a silicon oxide layer is usually deposited on the substrate as a buffer layer, and then a polysilicon active layer is formed on the buffer layer. The buffer layer can shield the influence of defects on the substrate, prevent impurities such as metal ions on the substrate from diffusing and penetrating into the active layer of the polysilicon, and avoid various device defects caused thereby.
在步骤S120中，在覆盖层上形成具有不同光阻厚度的光阻区和裸露覆盖层的镂空区。In step S120, a photoresist region having a different photoresist thickness and a cutout region of the bare cap layer are formed on the cover layer.
在该步骤中，首先，在覆盖层上涂布一层光阻(光阻材料)；然后，采用半透光光罩对涂布的光阻材料进行曝光处理。在本发明的一个实施例中，采用的半透光光罩如图2a和图3a中的光罩21。该光罩21包括非曝光区①(不透光区)，半曝光区②(半透光区)和全曝光区③(完全透光区)。In this step, first, a layer of photoresist (photoresist material) is coated on the cover layer; then, the coated photoresist material is exposed to light using a semi-transmissive mask. In one embodiment of the invention, a semi-transmissive reticle is employed as in the reticle 21 of Figures 2a and 3a. The reticle 21 includes a non-exposed area 1 (opaque area), a half exposure area 2 (semi-transmissive area), and a full exposure area 3 (completely transparent area).
当曝光光束31通过光罩21时，光罩21上的不同曝光区透过的光强不同。不同的曝光光强照射光阻材料，显影后形成的光阻厚度不同。再次如图2a和3a所示，对应光罩21的不同曝光区，光阻材料经曝光显影后形成不同光阻厚度的光阻区。该光阻区包括第一厚度的中心部①’和该中心部向外围两侧延伸的第二厚度的翼部②’。中心部①’通过光罩21的非曝光区①对应地形成，翼部②’通过光罩21的半曝光区②对应地形成。光阻区之间的镂空区③’通过光罩21的完全曝光区③对应地形成。其中，中心部①’对应的光阻厚度大于翼部②’对应的光阻厚度。镂空区③’无光阻覆盖，该镂空区直接裸露覆盖层。When the exposure light beam 31 passes through the reticle 21, the light intensity transmitted through the different exposure regions on the reticle 21 is different. Different exposure light intensity illuminates the photoresist material, and the thickness of the photoresist formed after development is different. Again, as shown in Figures 2a and 3a, corresponding to the different exposure regions of the mask 21, the photoresist material is exposed to light to form photoresist regions of different photoresist thicknesses. The photoresist region includes a central portion 1' of a first thickness and a second thickness of the wing portion 2' extending toward both sides of the peripheral portion. The central portion 1' is correspondingly formed by the non-exposure region 1 of the reticle 21, and the wing portion 2' is correspondingly formed by the half-exposure region 2 of the reticle 21. The hollowed out regions 3' between the photoresist regions are correspondingly formed by the fully exposed regions 3 of the photomask 21. The thickness of the photoresist corresponding to the central portion 1' is greater than the thickness of the photoresist corresponding to the wing portion 2'. The hollowed out area 3' has no photoresist coverage, and the hollowed out area directly exposes the cover layer.
在步骤S130中，对形成不同光阻厚度的光阻区的基板进行处理，以在多晶硅有源层中形成离子重掺杂区和离子轻掺杂区。 In step S130, the substrates forming the photoresist regions of different photoresist thicknesses are processed to form an ion heavily doped region and an ion lightly doped region in the polysilicon active layer.
在该步骤中，针对图2a和图3a两种不同的覆盖层结构分别采用不同的离子掺杂方法。In this step, different ion doping methods are employed for the two different overlay structures of Figures 2a and 3a, respectively.
在本发明的一个实施例中，针对图2a所示的覆盖层结构，在形成离子重掺杂区和离子轻掺杂区时包括以下步骤。In one embodiment of the invention, for the cap layer structure shown in FIG. 2a, the following steps are included in forming the ion heavily doped region and the ion light doped region.
首先，对形成不同光阻厚度的光阻区的基板进行离子重掺杂处理。图2b为对图2a的基板进行离子重掺杂处理的示意图，此处以N型离子植入为例来进行说明，N+表示高浓度N离子流。其中，41表示用于进行离子重掺杂处理的高浓度N离子流。如图所示，由于有光阻的阻挡，多晶硅有源层中对应中心部①’和翼部②’的区域没有离子掺杂。而镂空区③’由于没有光阻阻挡，在多晶硅有源层中对应该镂空区的区域进行了离子掺杂，由此形成了离子重掺杂区121。First, an ion heavy doping treatment is performed on the substrates forming the photoresist regions of different photoresist thicknesses. 2b is a schematic diagram of the ion heavy doping treatment of the substrate of FIG. 2a, where N-type ion implantation is taken as an example, and N+ represents a high concentration N ion current. Here, 41 denotes a high-concentration N ion current for performing ion heavy doping treatment. As shown, the regions of the polysilicon active layer corresponding to the central portion 1' and the wing portion 2' are not ion doped due to the blocking of the photoresist. While the hollow region 3' is not blocked by the photoresist, the region corresponding to the hollow region in the polysilicon active layer is ion-doped, thereby forming the ion heavily doped region 121.
接下来，对离子重掺杂处理后的基板进行干蚀刻处理，用以去除翼部。由于中心部的光阻厚度大于翼部的光阻厚度，通过控制干蚀刻处理的蚀刻气体量来将翼部②’完全去除，而将中心部①’上部的部分光阻去除，如图2c所示。当然，此处也可以采用其他可以同时蚀刻掉光阻和栅极绝缘层的蚀刻气体，但要保证蚀刻后的栅极绝缘层的厚度满足要求。Next, the substrate after the ion heavy doping treatment is subjected to dry etching treatment to remove the wings. Since the photoresist thickness of the central portion is greater than the photoresist thickness of the wing portion, the wing portion 2' is completely removed by controlling the amount of etching gas processed by the dry etching process, and part of the photoresist at the upper portion of the central portion 1' is removed, as shown in FIG. 2c. Show. Of course, other etching gases that can simultaneously etch away the photoresist and the gate insulating layer can be used here, but the thickness of the gate insulating layer after etching is required to meet the requirements.
在本发明的一个实施例中，干蚀刻处理可以由干法灰化处理代替。干法灰化处理采用氧气为蚀刻气体。当采用氧气作为蚀刻气体时，只蚀刻掉光阻，而不蚀刻掉栅极绝缘层。In one embodiment of the invention, the dry etch process may be replaced by a dry ashing process. Dry ashing uses oxygen as the etching gas. When oxygen is used as the etching gas, only the photoresist is etched away without etching off the gate insulating layer.
最后，对干蚀刻处理后的基板进行离子轻掺杂处理。图2c为图2b的基板干蚀刻处理后进行离子轻掺杂处理的示意图，N-表示低浓度N离子流。其中，42表示用于进行离子轻掺杂处理的低浓度N离子流。在该步骤中，多晶硅有源层中对应原翼部②’和原镂空区③’的区域没有光阻阻挡，多晶硅有源层中的这些区域进行了离子轻掺杂。原中心部①’由于还有光阻阻挡，多晶硅有源层中对应原中心部①’没有进行离子轻掺杂。此外，由于多晶硅有源层中对应原镂空区③’的区域进行了离子重掺杂处理，在此处又与多晶硅有源层中对应原翼部②’的区域同时进行了离子轻掺杂处理。这样，既保证了离子轻掺杂区的分布，又不会削弱原来的离子重掺杂区。最终形成的离子重掺杂区121和离子轻掺杂区122如图2c所示。Finally, the substrate after the dry etching treatment is subjected to ion light doping treatment. 2c is a schematic diagram of the ion light doping treatment after the dry etching process of the substrate of FIG. 2b, and N- represents a low concentration N ion current. Wherein 42 represents a low concentration N ion stream for performing ion light doping treatment. In this step, the regions of the polysilicon active layer corresponding to the original wing portion 2' and the original hollow region 3' are not blocked by light, and these regions in the polysilicon active layer are ionically lightly doped. Since the original center portion 1' is also blocked by the photoresist, the corresponding original center portion 1' of the polysilicon active layer is not subjected to ion light doping. In addition, since the region corresponding to the original hollow region 3' in the polysilicon active layer is subjected to ion heavy doping treatment, ion light doping treatment is simultaneously performed simultaneously with the region corresponding to the original wing portion 2' in the polysilicon active layer. . In this way, the distribution of the lightly doped regions of the ions is ensured without weakening the original heavily doped regions of ions. The resulting ion heavily doped region 121 and ion lightly doped region 122 are shown in Figure 2c.
在该实施例中，针对图2b进行的干蚀刻处理和离子轻掺杂处理可以只经一次黄光制程完成，即同时进行干蚀刻处理和离子轻掺杂处理，这样就可以节省一道黄光及光阻剥离制程。In this embodiment, the dry etching process and the ion light doping process performed on FIG. 2b can be completed by only one yellow light process, that is, simultaneous dry etching treatment and ion light doping treatment, thereby saving a yellow light and Photoresist stripping process.
针对图2a采用半透光光罩形成半曝光光阻对非离子掺杂区进行遮蔽，可以有效控制离子重掺杂区和离子轻掺杂区的宽度，不会产生离子重掺杂区和离子轻掺杂区异常重叠问 题。同时，采用干蚀刻或干法灰化去除光阻，工序简单，易于操作。The non-ion doped region is shielded by forming a semi-exposure photoresist for the semi-transmissive mask according to FIG. 2a, and the width of the ion heavily doped region and the ion lightly doped region can be effectively controlled without generating ion heavily doped regions and ions. Abnormal overlap in lightly doped areas question. At the same time, the photoresist is removed by dry etching or dry ashing, and the process is simple and easy to operate.
在本发明的一个实施例中，针对图3a所示的覆盖层结构，在形成离子重掺杂区和离子轻掺杂区时包括以下步骤。In one embodiment of the invention, for the cap layer structure shown in FIG. 3a, the following steps are included in forming the ion heavily doped region and the ion light doped region.
首先，对形成不同光阻厚度的光阻区的基板进行干蚀刻处理，用来去除翼部、栅极导电层中对应该翼部的部分和部分栅极绝缘层对应该翼部的部分，还要去除栅极导电层对应镂空区的部分和部分栅极绝缘层对应该镂空区的部分。由于翼部的影响，在完成干蚀刻处理后，栅极绝缘层对应原翼部的部分的厚度大于栅极绝缘层对应原镂空区的部分的厚度。同时，由于中心部的光阻厚度大于翼部的光阻厚度，在翼部去除后，中心部的上部保留部分光阻。First, a dry etching process is performed on a substrate forming a photoresist region having different photoresist thicknesses for removing a portion of the wing portion, the gate conductive layer corresponding to the wing portion, and a portion of the gate insulating layer corresponding to the wing portion, and A portion of the gate conductive layer corresponding to the cutout region and a portion of the gate insulating layer corresponding to the cutout region are removed. Due to the influence of the wings, after the dry etching process is completed, the thickness of the portion of the gate insulating layer corresponding to the original wing portion is greater than the thickness of the portion of the gate insulating layer corresponding to the original hollow region. At the same time, since the photoresist thickness of the central portion is larger than the photoresist thickness of the wing portion, a portion of the central portion retains a portion of the photoresist after the wing portion is removed.
在该步骤中，通过控制蚀刻量可以实现将栅极导电层中对应原翼部的部分完全蚀刻掉而不蚀刻栅极绝缘层对应原翼部的部分，如图3b所示。当然栅极绝缘层中对应原翼部也可以蚀刻掉部分绝缘层，但要保证最终形成的栅极绝缘层的厚度满足要求。In this step, by controlling the amount of etching, it is possible to completely etch away the portion of the gate conductive layer corresponding to the original wing portion without etching the portion of the gate insulating layer corresponding to the original wing portion, as shown in FIG. 3b. Of course, a portion of the insulating layer may be etched away from the corresponding original wing portion of the gate insulating layer, but it is ensured that the thickness of the finally formed gate insulating layer satisfies the requirements.
接下来，对干蚀刻处理后的基板进行离子重掺杂处理。在该步骤中，由于栅极绝缘层对应原翼部的部分的厚度大于栅极绝缘层对应原镂空区的部分的厚度，所以在多晶硅有源层中形成对应于栅极绝缘层较薄的区域③’的离子重掺杂区121，在多晶硅有源层中形成对应于栅极绝缘层较厚的区域②’的离子轻掺杂区122。离子轻掺杂区122形成LDD，如图3b所示。同时，在栅极导电层中形成对应于原中心部①’的栅极。Next, the substrate after the dry etching treatment is subjected to ion heavy doping treatment. In this step, since the thickness of the portion of the gate insulating layer corresponding to the original wing portion is larger than the thickness of the portion of the gate insulating layer corresponding to the original hollow region, a thin region corresponding to the gate insulating layer is formed in the polysilicon active layer. The 3' ion heavily doped region 121 forms an ion lightly doped region 122 corresponding to the thicker region 2' of the gate insulating layer in the polysilicon active layer. The ion lightly doped region 122 forms an LDD as shown in Figure 3b. At the same time, a gate corresponding to the original central portion 1' is formed in the gate conductive layer.
在该实施例中，针对图3a进行的干蚀刻处理和离子重掺杂处理可以只经一次黄光制程即可完成，即同时进行干蚀刻处理和离子重掺杂处理，从而可以节省一道黄光、掺杂及光阻剥离制程。In this embodiment, the dry etching process and the ion heavy doping process performed for FIG. 3a can be completed by only one yellow light process, that is, the dry etching process and the ion heavy doping process are simultaneously performed, thereby saving a yellow light. , doping and photoresist stripping process.
图3a的实施例主要利用光阻厚度的差异，在干蚀刻处理时调节光阻与栅极导电层、栅极导电层与栅极绝缘层之间的厚度选择比，最终形成栅极绝缘层的厚度差异，以在后续的离子重掺杂处理中同时形成离子重掺杂区和离子轻掺杂区。本方法只进行了一道离子植入工序和一道曝光工序，降低了工艺成本，工艺简单，易于操作。同时，此处采用的离子植入方法容易控制离子重掺杂区和离子轻掺杂区的宽度，不会产生离子重掺杂区和离子轻掺杂区异常重叠问题。The embodiment of FIG. 3a mainly utilizes the difference in photoresist thickness, and adjusts the thickness selection ratio between the photoresist and the gate conductive layer, the gate conductive layer and the gate insulating layer during the dry etching process, and finally forms the gate insulating layer. The difference in thickness is to simultaneously form an ion heavily doped region and an ion lightly doped region in a subsequent ion heavy doping process. The method only performs an ion implantation process and an exposure process, which reduces the process cost, is simple in process, and is easy to operate. At the same time, the ion implantation method adopted here can easily control the width of the ion heavily doped region and the ion lightly doped region, and does not cause the problem of abnormal overlap between the ion heavily doped region and the ion light doped region.
在步骤S140中，去除剩余光阻并对形成离子重掺杂区和离子轻掺杂区的基板进行处理以获得所需的阵列基板。In step S140, the remaining photoresist is removed and the substrate forming the ion heavily doped region and the ion lightly doped region is processed to obtain a desired array substrate.
在本发明的一个实施例中，由于图2c中的覆盖层12不包括栅极导电层，因此，在对图2c完成离子掺杂处理后需首先将图2c上的剩余光阻去除；然后采用溅射法沉积铬或其它金属形成栅极导电层；接着对栅极导电层进行曝光显影及其他常规工序处理来形成栅 极。In an embodiment of the present invention, since the cap layer 12 in FIG. 2c does not include a gate conductive layer, the remaining photoresist in FIG. 2c is first removed after completing the ion doping process on FIG. 2c; Depositing chromium or other metal to form a gate conductive layer by sputtering; then performing exposure development on the gate conductive layer and other conventional processes to form a gate pole.
接下来，在形成栅极的基板上采用PECVD工艺沉积氮化硅、氧化硅形成层间绝缘层；随后，对层间绝缘层进行热退火及氢化，激活掺杂离子并改善多晶硅界面；然后对层间绝缘层和栅极绝缘层进行蚀刻处理形成接触孔，接触孔延伸至离子重掺杂区；随后，沉积形成源漏极金属层，并定义形成源极和漏极；随后，在源漏极金属层上制作有机平坦化层，并在接触孔部位形成通孔；接着，在有机层上形成作为共通电极的底部氧化铟锡层；然后在有机平坦化层上形成钝化层，并在钝化层上开孔形成至漏极的接触孔。Next, depositing silicon nitride and silicon oxide on the substrate on which the gate is formed to form an interlayer insulating layer; subsequently, thermally annealing and hydrogenating the interlayer insulating layer, activating the doping ions and improving the polysilicon interface; The interlayer insulating layer and the gate insulating layer are etched to form a contact hole, and the contact hole extends to the ion heavily doped region; subsequently, a source/drain metal layer is formed and defined to form a source and a drain; subsequently, at the source and drain An organic planarization layer is formed on the polar metal layer, and a via hole is formed in the contact hole portion; then, a bottom indium tin oxide layer as a common electrode is formed on the organic layer; then a passivation layer is formed on the organic planarization layer, and An opening is formed in the passivation layer to form a contact hole to the drain.
最后，在该基板上涂覆透明导电材料并经黄光、蚀刻、剥离等制程形成与漏极电气连接的像素电极。Finally, a transparent conductive material is coated on the substrate and a pixel electrode electrically connected to the drain is formed by a process such as yellowing, etching, stripping, or the like.
在本发明的一个实施例中，对于图3b中的覆盖层12，其在离子掺杂处理前已经形成了栅极导电层。栅极导电层在干蚀刻处理后形成了栅极。栅极及离子掺杂处理完成后，接下来的后续制程与图2c所示的基板形成栅极以后的制程相同。In one embodiment of the invention, for the cap layer 12 of Figure 3b, a gate conductive layer has been formed prior to the ion doping process. The gate conductive layer forms a gate after the dry etching process. After the gate and ion doping treatment is completed, the subsequent subsequent processes are the same as the processes after the gates are formed in the substrate shown in FIG. 2c.
在本发明的一个实施例中，采用了以上方法制作的一种阵列基板，该阵列基板包括在基板上依次形成的多晶硅有源层和覆盖层、对应形成源漏极的离子重掺杂区和离子轻掺杂区以及栅极、层间绝缘层及源漏极导电层、附着在层间绝缘层上有机平坦层、底部共通电极层、钝化层和顶部像素电极。In an embodiment of the present invention, an array substrate fabricated by the above method is used, the array substrate includes a polysilicon active layer and a cap layer sequentially formed on the substrate, an ion heavily doped region corresponding to the source and drain electrodes, and An ion lightly doped region and a gate, an interlayer insulating layer and a source/drain conductive layer, an organic flat layer attached to the interlayer insulating layer, a bottom common electrode layer, a passivation layer, and a top pixel electrode.
在本发明中，进行离子掺杂处理的为N型离子或P型离子中的任一种。在设计采用的半透光光罩时，可以根据需要设置多个(2个以上)不同透光量的区域，从而在进行曝光时形成多个不同光阻厚度的光阻区，进而在多晶硅有源层中的不同区域实现不同浓度的离子掺杂。In the present invention, any one of an N-type ion or a P-type ion is performed by ion doping treatment. When designing the semi-transmissive reticle, a plurality of (two or more) regions of different light transmission amount may be disposed as needed, thereby forming a plurality of photoresist regions having different photoresist thicknesses during exposure, and further having Different regions in the source layer achieve different concentrations of ion doping.
虽然本发明所公开的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所揭露的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。 While the embodiments of the present invention have been described above, the described embodiments are merely illustrative of the embodiments of the invention and are not intended to limit the invention. Any modification and variation of the form and details of the invention may be made by those skilled in the art without departing from the spirit and scope of the invention. It is still subject to the scope defined by the appended claims.

Claims (18)

  1. 一种用于制作阵列基板的方法，包括：A method for fabricating an array substrate, comprising:
    在基板上依次形成多晶硅有源层和覆盖层；Forming a polysilicon active layer and a cap layer sequentially on the substrate;
    在所述覆盖层上涂覆光阻，并采用半透光光罩经曝光显影处理以在所述覆盖层上对应形成至少一个具有不同光阻厚度的光阻区及裸露所述覆盖层的镂空区；Coating a photoresist on the cover layer, and exposing and developing the film by using a semi-transmissive reticle to form at least one photoresist region having different photoresist thicknesses on the cover layer and hollowing out the cover layer Area;
    对形成所述光阻区的基板进行处理以在所述多晶硅有源层中形成对应于所述光阻区的部分区域的离子轻掺杂区和对应于所述镂空区的离子重掺杂区；Processing a substrate forming the photoresist region to form an ion lightly doped region corresponding to a partial region of the photoresist region and an ion heavily doped region corresponding to the void region in the polysilicon active layer ;
    对形成所述离子轻掺杂区和所述离子重掺杂区的基板进行处理以形成栅极、源漏极和像素电极。A substrate forming the ion lightly doped region and the ion heavily doped region is processed to form a gate, a source drain, and a pixel electrode.
  2. 如权利要求1所述的方法，其中，所述不同光阻厚度的光阻区包括第一厚度的中心部及由所述中心部向外围两侧延伸的第二厚度的翼部，其中，所述第一厚度大于所述第二厚度，通过所述半透光光罩的不透光区对应地形成所述中心部，通过所述半透光光罩的半透光区对应地形成所述翼部。The method of claim 1, wherein the photoresist regions of different photoresist thicknesses comprise a central portion of a first thickness and a second thickness of wings extending from the central portion to both sides of the periphery, wherein The first thickness is greater than the second thickness, and the central portion is correspondingly formed by the opaque region of the semi-transmissive reticle, and the semi-transmissive region of the semi-transmissive reticle is correspondingly formed Wings.
  3. 如权利要求2所述的方法，其中，通过所述半透光光罩的完全透光区对应地形成所述镂空区。The method of claim 2, wherein the hollowed out region is correspondingly formed by a completely transparent region of the semi-transmissive reticle.
  4. 如权利要求3所述的方法，其中，所述覆盖层包括栅极绝缘层。The method of claim 3 wherein said cap layer comprises a gate insulating layer.
  5. 如权利要求3所述的方法，其中，所述覆盖层包括栅极绝缘层及所述栅极绝缘层上的栅极导电层。The method of claim 3 wherein said capping layer comprises a gate insulating layer and a gate conductive layer on said gate insulating layer.
  6. 如权利要求4所述的方法，其中，形成所述离子轻掺杂区和所述离子重掺杂区的步骤进一步包括：The method of claim 4, wherein the step of forming the ion lightly doped region and the ionically heavily doped region further comprises:
    对形成所述光阻区的基板进行离子重掺杂处理，以在所述多晶硅有源层中形成对应所述镂空区的离子重掺杂区，在所述多晶硅有源层中对应所述中心部和所述翼部的部分没有离子掺杂；Performing an ion heavy doping treatment on the substrate forming the photoresist region to form an ion heavily doped region corresponding to the hollow region in the polysilicon active layer, corresponding to the center in the polysilicon active layer The portion and the portion of the wing are free of ion doping;
    对进行离子重掺杂处理后的基板进行干蚀刻处理以去除所述翼部对应的光阻，对应原所述中心部的光阻部分保留；Performing a dry etching process on the substrate subjected to the ion heavy doping treatment to remove the photoresist corresponding to the wing portion, and retaining the photoresist portion corresponding to the original center portion;
    对干蚀刻处理后的基板进行离子轻掺杂处理，其中，在所述多晶硅有源层中形成对应原所述翼部的离子轻掺杂区，在所述多晶硅有源层中对应原所述中心部的部分没有离子掺杂。Performing an ion light doping treatment on the substrate after the dry etching process, wherein an ion lightly doped region corresponding to the original wing portion is formed in the polysilicon active layer, corresponding to the original in the polysilicon active layer The portion of the center portion is free of ion doping.
  7. 如权利要求5所述的方法，其中，形成所述离子轻掺杂区和所述离子重掺杂区的步骤进一步包括：The method of claim 5 wherein the step of forming the ion lightly doped region and the ionically heavily doped region further comprises:
    对形成所述光阻区的基板进行干蚀刻处理以去除以下的部分：所述翼部、所述栅极 导电层中对应原所述翼部的部分及部分所述栅极绝缘层对应所述翼部的部分、所述栅极导电层对应所述镂空区的部分及部分所述栅极绝缘层对应所述镂空区的部分、所述中心部的部分光阻，其中，干蚀刻处理后的栅极绝缘层对应原所述翼部的部分的厚度大于栅极绝缘层对应原所述镂空区的部分的厚度，所述栅极导电层对应原所述中心部的部分形成栅极；Performing a dry etching process on the substrate forming the photoresist region to remove the portion: the wing portion, the gate electrode a portion of the conductive layer corresponding to the original wing portion and a portion of the gate insulating layer corresponding to the wing portion, a portion of the gate conductive layer corresponding to the hollow region, and a portion corresponding to the gate insulating layer a portion of the hollow region and a portion of the photoresist of the central portion, wherein a portion of the gate insulating layer after the dry etching process corresponds to a portion of the portion of the wing portion that is larger than a portion of the gate insulating layer corresponding to the original hollow region a thickness, the gate conductive layer forming a gate corresponding to a portion of the central portion;
    对干蚀刻处理后的基板进行离子重掺杂处理以在所述多晶硅有源层中形成对应原所述翼部的离子轻掺杂区，在所述多晶硅有源层中形成对应原所述镂空区的离子重掺杂区。Performing an ion heavy doping treatment on the dry-etched substrate to form an ion lightly doped region corresponding to the original wing portion in the polysilicon active layer, and forming a corresponding hollow in the polysilicon active layer The ion heavily doped region of the region.
  8. 如权利要求6所述的方法，其中，对具有离子轻掺杂区和离子重掺杂区的基板进一步处理以形成栅极、源漏极和像素电极的步骤包括：The method of claim 6 wherein the step of further processing the substrate having the ion lightly doped region and the ion heavily doped region to form the gate, source and drain and pixel electrodes comprises:
    去除所述栅极绝缘层上的光阻，在所述栅极绝缘层上沉积导电材料并进行处理以形成栅极；Removing a photoresist on the gate insulating layer, depositing a conductive material on the gate insulating layer and processing to form a gate;
    在形成栅极的基板上沉积绝缘材料形成层间绝缘层，并对所述层间绝缘层和所述栅极绝缘层进行蚀刻处理以形成连接到所述离子重掺杂区的接触孔，在所述层间绝缘层上形成对应连接所述接触孔的源漏极金属层，并定义形成源漏极；Depositing an insulating material on the substrate forming the gate to form an interlayer insulating layer, and etching the interlayer insulating layer and the gate insulating layer to form a contact hole connected to the ion heavily doped region, Forming a source/drain metal layer corresponding to the contact hole on the interlayer insulating layer, and defining a source and a drain;
    在所述源漏极金属层上依次形成有机平坦化层、共通电极、钝化层及所述钝化层上延伸至漏极的连接孔，并在所述钝化层上涂覆透明导电材料形成与所述漏极电气连接的像素电极。Forming an organic planarization layer, a common electrode, a passivation layer, and a connection hole extending to the drain on the passivation layer on the source/drain metal layer, and coating a transparent conductive material on the passivation layer A pixel electrode electrically connected to the drain is formed.
  9. 如权利要求7所述的方法，其中，对具有离子轻掺杂区和离子重掺杂区的基板进一步处理以形成栅极、源漏极和像素电极的步骤包括：The method of claim 7 wherein the step of further processing the substrate having the ion lightly doped region and the ion heavily doped region to form the gate, source and drain and pixel electrodes comprises:
    去除所述栅极上的光阻以裸露光阻覆盖的栅极；Removing a photoresist on the gate to cover the gate covered by the exposed photoresist;
    在形成栅极的基板上沉积绝缘材料形成层间绝缘层，并对所述层间绝缘层和所述栅极绝缘层进行蚀刻处理以形成连接到所述离子重掺杂区的接触孔，在所述层间绝缘层上形成对应连接所述接触孔的源漏极金属层，并定义形成源漏极；Depositing an insulating material on the substrate forming the gate to form an interlayer insulating layer, and etching the interlayer insulating layer and the gate insulating layer to form a contact hole connected to the ion heavily doped region, Forming a source/drain metal layer corresponding to the contact hole on the interlayer insulating layer, and defining a source and a drain;
    在所述源漏极金属层上依次形成有机平坦化层、共通电极、钝化层及所述钝化层上延伸至漏极的连接孔，并在所述钝化层上涂覆透明导电材料形成与所述漏极电气连接的像素电极。Forming an organic planarization layer, a common electrode, a passivation layer, and a connection hole extending to the drain on the passivation layer on the source/drain metal layer, and coating a transparent conductive material on the passivation layer A pixel electrode electrically connected to the drain is formed.
  10. 一种阵列基板，包括：An array substrate comprising:
    在基板上依次形成的多晶硅有源层和覆盖层；a polysilicon active layer and a cap layer sequentially formed on the substrate;
    在所述覆盖层上涂覆光阻，并采用半透光光罩经曝光显影处理以在所述覆盖层上对应形成的至少一个具有不同光阻厚度的光阻区及裸露所述覆盖层的镂空区；Coating a photoresist on the cover layer, and exposing and developing the semi-transmissive reticle to form at least one photoresist region having different photoresist thicknesses corresponding to the cover layer and exposing the cover layer Hollow area
    对形成所述光阻区的基板进行处理以在所述多晶硅有源层中形成的对应于所述光阻区的部分区域的离子轻掺杂区和对应于所述镂空区的离子重掺杂区； Processing a substrate forming the photoresist region to form an ion lightly doped region corresponding to a partial region of the photoresist region in the polysilicon active layer and an ion heavily doped corresponding to the hollow region Area;
    对形成所述离子轻掺杂区和所述离子重掺杂区的基板进行处理形成的栅极、源漏极和像素电极。A gate, a source drain, and a pixel electrode formed by processing a substrate forming the ion lightly doped region and the ion heavily doped region.
  11. 如权利要求10所述的阵列基板，其中，所述不同光阻厚度的光阻区包括第一厚度的中心部及由所述中心部向外围两侧延伸的第二厚度的翼部，其中，所述第一厚度大于所述第二厚度，通过所述半透光光罩的不透光区对应地形成所述中心部，通过所述半透光光罩的半透光区对应地形成所述翼部。The array substrate according to claim 10, wherein the photoresist region of the different photoresist thickness comprises a central portion of the first thickness and a second thickness of the wing portion extending from the central portion toward both sides of the periphery, wherein The first thickness is greater than the second thickness, and the central portion is correspondingly formed by the opaque region of the semi-transmissive reticle, and the semi-transmissive region of the semi-transmissive reticle is correspondingly formed Said wing.
  12. 如权利要求11所述的阵列基板，其中，通过所述半透光光罩的完全透光区对应地形成所述镂空区。The array substrate according to claim 11, wherein the hollowed out region is correspondingly formed by a completely transparent region of the semi-transmissive reticle.
  13. 如权利要求12所述的阵列基板，其中，所述覆盖层包括栅极绝缘层。The array substrate of claim 12, wherein the cover layer comprises a gate insulating layer.
  14. 如权利要求12所述的阵列基板，其中，所述覆盖层包括栅极绝缘层及所述栅极绝缘层上的栅极导电层。The array substrate according to claim 12, wherein the cover layer comprises a gate insulating layer and a gate conductive layer on the gate insulating layer.
  15. 如权利要求13所述的阵列基板，其中，形成所述离子轻掺杂区和所述离子重掺杂区的步骤进一步包括：The array substrate according to claim 13, wherein the step of forming the ion lightly doped region and the ion heavily doped region further comprises:
    对形成所述光阻区的基板进行离子重掺杂处理，以在所述多晶硅有源层中形成对应所述镂空区的离子重掺杂区，在所述多晶硅有源层中对应所述中心部和所述翼部的部分没有离子掺杂；Performing an ion heavy doping treatment on the substrate forming the photoresist region to form an ion heavily doped region corresponding to the hollow region in the polysilicon active layer, corresponding to the center in the polysilicon active layer The portion and the portion of the wing are free of ion doping;
    对进行离子重掺杂处理后的基板进行干蚀刻处理以去除所述翼部对应的光阻，对应原所述中心部的光阻部分保留；Performing a dry etching process on the substrate subjected to the ion heavy doping treatment to remove the photoresist corresponding to the wing portion, and retaining the photoresist portion corresponding to the original center portion;
    对干蚀刻处理后的基板进行离子轻掺杂处理，在所述多晶硅有源层中形成对应原所述翼部的离子轻掺杂区，在所述多晶硅有源层中对应原所述中心部的部分没有离子掺杂。Performing an ion light doping treatment on the substrate after the dry etching process, forming an ion lightly doped region corresponding to the original wing portion in the polysilicon active layer, corresponding to the original center portion in the polysilicon active layer The portion is not ion doped.
  16. 如权利要求15所述的阵列基板，其中，对具有离子轻掺杂区和离子重掺杂区的基板进一步处理以形成栅极、源漏极和像素电极的步骤包括：The array substrate according to claim 15, wherein the step of further processing the substrate having the ion lightly doped region and the ion heavily doped region to form the gate, the source and the drain, and the pixel electrode comprises:
    去除所述栅极绝缘层上的光阻，在所述栅极绝缘层上沉积导电材料并进行处理以形成栅极；Removing a photoresist on the gate insulating layer, depositing a conductive material on the gate insulating layer and processing to form a gate;
    在形成栅极的基板上沉积绝缘材料形成层间绝缘层，并对所述层间绝缘层和所述栅极绝缘层进行蚀刻处理以形成连接到所述离子重掺杂区的接触孔，在所述层间绝缘层上形成对应连接所述接触孔的源漏极金属层，并定义形成源漏极；Depositing an insulating material on the substrate forming the gate to form an interlayer insulating layer, and etching the interlayer insulating layer and the gate insulating layer to form a contact hole connected to the ion heavily doped region, Forming a source/drain metal layer corresponding to the contact hole on the interlayer insulating layer, and defining a source and a drain;
    在所述源漏极金属层上依次形成有机平坦化层、共通电极、钝化层及所述钝化层上延伸至漏极的连接孔，并在所述钝化层上涂覆透明导电材料形成与所述漏极电气连接的像素电极。Forming an organic planarization layer, a common electrode, a passivation layer, and a connection hole extending to the drain on the passivation layer on the source/drain metal layer, and coating a transparent conductive material on the passivation layer A pixel electrode electrically connected to the drain is formed.
  17. 如权利要求14所述的阵列基板，其中，形成所述离子轻掺杂区和所述离子重掺 杂区的步骤进一步包括：The array substrate according to claim 14, wherein said ion lightly doped region and said ion heavy doping are formed The steps of the miscellaneous area further include:
    对形成所述光阻区的基板进行干蚀刻处理以去除以下的部分：所述翼部、所述栅极导电层中对应原所述翼部的部分及部分所述栅极绝缘层对应所述翼部的部分、所述栅极导电层对应所述镂空区的部分及部分所述栅极绝缘层对应所述镂空区的部分、所述中心部的部分光阻，干蚀刻处理后的栅极绝缘层对应原所述翼部的部分的厚度大于栅极绝缘层对应原所述镂空区的部分的厚度，所述栅极导电层对应原所述中心部的部分形成栅极；Performing a dry etching process on the substrate forming the photoresist region to remove the portion, the wing portion, a portion of the gate conductive layer corresponding to the original wing portion, and a portion of the gate insulating layer corresponding to the a portion of the wing portion, a portion of the gate conductive layer corresponding to the hollow region, and a portion of the gate insulating layer corresponding to the hollow region, a partial photoresist of the central portion, and a gate after the dry etching process The thickness of the portion of the insulating layer corresponding to the original wing portion is greater than the thickness of the portion of the gate insulating layer corresponding to the original hollow region, and the gate conductive layer forms a gate corresponding to the portion of the original central portion;
    对干蚀刻处理后的基板进行离子重掺杂处理以在所述多晶硅有源层中形成对应原所述翼部的离子轻掺杂区，在所述多晶硅有源层中形成对应原所述镂空区的离子重掺杂区。Performing an ion heavy doping treatment on the dry-etched substrate to form an ion lightly doped region corresponding to the original wing portion in the polysilicon active layer, and forming a corresponding hollow in the polysilicon active layer The ion heavily doped region of the region.
  18. 如权利要求17所述的阵列基板，其中，对具有离子轻掺杂区和离子重掺杂区的基板进一步处理以形成栅极、源漏极和像素电极的步骤包括：The array substrate according to claim 17, wherein the step of further processing the substrate having the ion lightly doped region and the ion heavily doped region to form the gate, the source and the drain, and the pixel electrode comprises:
    去除所述栅极上的光阻以裸露光阻覆盖的栅极；Removing a photoresist on the gate to cover the gate covered by the exposed photoresist;
    在形成栅极的基板上沉积绝缘材料形成层间绝缘层，并对所述层间绝缘层和所述栅极绝缘层进行蚀刻处理以形成连接到所述离子重掺杂区的接触孔，在所述层间绝缘层上形成对应连接所述接触孔的源漏极金属层，并定义形成源漏极；Depositing an insulating material on the substrate forming the gate to form an interlayer insulating layer, and etching the interlayer insulating layer and the gate insulating layer to form a contact hole connected to the ion heavily doped region, Forming a source/drain metal layer corresponding to the contact hole on the interlayer insulating layer, and defining a source and a drain;
    在所述源漏极金属层上依次形成有机平坦化层、共通电极、钝化层及所述钝化层上延伸至漏极的连接孔，并在所述钝化层上涂覆透明导电材料形成与所述漏极电气连接的像素电极。 Forming an organic planarization layer, a common electrode, a passivation layer, and a connection hole extending to the drain on the passivation layer on the source/drain metal layer, and coating a transparent conductive material on the passivation layer A pixel electrode electrically connected to the drain is formed.
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