JPH06267987A - Method of manufacturing thin film transistor - Google Patents

Abstract

PURPOSE:To provide a method of manufacturing a thin film transistor which allows the diameter of the crystal particles to be different between the channel section and the contacting layer without making the manufacture processes complicated, and which makes it possible to increase the area of contact of a contact layer with a wiring electrode. CONSTITUTION:The method has a step where a conductive ground layer 2a, 2b having a thermal conductivity higher than that of a glass substrate 1 is formed on the glass substrate 1 which corresponds to the forming position of a source contact layer and a drain contact layer, and a step where poly-Si film 3' is so formed that it is positioned on the glass substrate 1 between the both ground layer 2a, 2b and on the both ground layer 2a, 2b and a part of it is exposed, further including a step where impurities are implanted into the part to be a contact layer in this poly-Si film 3', and a step where a metal film 6a, 6b is formed so as to contact with the part where the ground layer 2a, 2b is exposed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor.

[0002]

2. Description of the Related Art Devices such as liquid crystal displays and contact type line sensors are constructed by forming a large number of thin film transistors on a glass substrate. The material of the thin film transistor is amorphous silicon (hereinafter abbreviated as a-Si) or polycrystalline silicon (hereinafter p.
abbreviated as “oly-Si” is used, but a-
Since the Si film has a low electron mobility and is not suitable for improving the quality of a device, a poly-Si film having a relatively high electron mobility is often used.

As a method for forming the poly-Si film, a method for directly forming the poly-Si film by a low temperature CVD method or the like, or a solid phase growth method for recrystallizing by annealing the a-Si film for a long time Alternatively, recrystallization methods using various lasers are known.

[0004]

By the way, a poly-
It is desirable that the crystal grain size of the Si film is large in order to enhance the electron mobility described above. However, using a doping layer formed by ion implantation or ion doping of the Si film as a starting material, a contact dope layer is formed by laser recrystallization or the like. When formed, the sheet resistance may be small even if the crystal grain size is small. It is considered that this is mainly due to the decrease of the potential barrier at the crystal grain boundary of the poly-Si film.

In this case, it is necessary to perform a treatment for making the crystal grain size of recrystallization different between the region which becomes the channel portion and the region which becomes the contact dope layer. As this treatment, for example, contact doping at the time of recrystallization is performed. There is a method of forming a cap film such as a SiN film or a SiO ₂ film which weakens the amount of laser incident on a region to be a layer. However, this method requires a step of removing the above cap film before impurity doping, resulting in an increase in the number of steps.

Wiring electrodes are connected to the source contact dope layer and the drain contact dope layer for current extraction. In the conventional method of manufacturing a thin film transistor, the contact dope layer and the wiring electrode are contacted with each other. It has a drawback that the area is small and the current extraction efficiency is poor.

In view of the above circumstances, according to the present invention, the treatment for making the crystal grain size different between the channel portion and the contact dope layer can be performed without complicating the manufacturing process, and the contact dope layer and the wiring electrode can be brought into contact with each other. It is an object of the present invention to provide a method for manufacturing a thin film transistor that can increase the area and increase the current extraction efficiency.

[0008]

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides a thermal conductivity higher than that of an insulating substrate on an insulating substrate corresponding to the formation positions of a source contact layer and a drain contact layer. Forming an underlayer having a ratio, a step of forming a polycrystalline semiconductor film on the insulating substrate between both of the underlayers and both of the underlayers, and a portion of the polycrystalline semiconductor film to be the contact layer And a step of doping impurities with.

Further, a step of forming a conductive underlayer having a higher thermal conductivity than that of the insulating substrate on the insulating substrate corresponding to the positions where the source contact layer and the drain contact layer are formed; A step of forming a polycrystalline semiconductor film on the insulating substrate between the ground layers and on both of the underlayers so as to expose a part of these underlayers; and a step of forming a contact layer in the polycrystalline semiconductor film. The method is characterized by including a step of doping an impurity and a step of forming a wiring electrode so as to be in contact with an exposed portion of the base layer.

[0010]

According to the first structure, the crystal grain size of the contact layer, which is required to reduce the sheet resistance, can be reduced by the underlayer having a higher thermal conductivity than the insulating substrate. However, since it is not necessary to remove this underlayer after recrystallization, the process is simplified.

Further, according to the above second structure, the underlayer has conductivity, and the wiring electrode also contacts the lower surface of the contact layer through the conductive underlayer, so that the contact layer and the wiring are The contact area with the electrode is increased, and the current extraction efficiency is improved.

[0012]

The present invention will be described below with reference to the drawings showing the embodiments thereof. 1A to 1D are cross-sectional views showing a method of manufacturing a thin film transistor according to the present invention in the order of steps.

First, as shown in FIG. 1A, a base layer 2 is formed on a glass substrate 1 such as quartz. The underlayer 2 is
It has a higher thermal conductivity than that of the glass substrate 1, a high melting point, and electrical conductivity.
It is formed with a thickness of 0 to 700Å. Since the thermal conductivity of the glass substrate 1 is 1.38 W / (m · K), the underlayer 2
For this, one having a higher thermal conductivity than that may be selected. An example of such a material is shown in Table 1 below.

[0014]

[Table 1]

Next, as shown in FIG. 3B, the above-mentioned underlayer 2 is patterned by etching, leaving the portions of the underlayer 2 corresponding to the formation positions of the source contact layer and the drain contact layer, and leaving other portions. Remove the part. As a result, the source-side base layer 2a and the drain-side base layer 2b are obtained.

Next, as shown in FIG.
About 100 a-Si film 3 is formed by using D method or sputtering method.
The film is formed to a film thickness of 0Å, and a pattern nig is performed by etching to form an island. At this time, part of the source-side base layer 2a and the drain-side base layer 2b is exposed.
Then, the a-Si film 3 is irradiated with an excimer laser (3
00 mJ / cm ² × 8 shots), the a-Si film 3 is recrystallized to obtain a poly-Si film 3 ′. Note that this recrystallization can also be performed by a solid phase growth method by thermal annealing. As conditions for this solid phase growth method, the heating temperature is 650 ° C., and the time of being placed in that atmosphere is 20 hours.

By the above recrystallization, the crystal grain size becomes different between the channel region and the contact region. The reason for this and the specific difference in grain size will be described later.

Next, as shown in FIG.
Si used as a gate insulating film by using the D method or the sputtering method
The O ₂ film 4 is formed to a thickness of 1000 Å (up to 1500 Å), and a po electrode to be a gate electrode is formed by the LPCVD method.
The ly-Si film 5 is formed to a thickness of 1000Å (up to 5000Å). In this LPCVD method, the substrate temperature is 600 ° C.
Set to 100% SiH ₄ (silane gas) for 50 s
It was supplied at a flow rate of ccm and the pressure was 50 mTorr.
After that, a resist pattern (not shown) is formed, and the poly-Si film 5 and the SiO ₂ film 4 are etched using this as a mask to form a gate insulating film 4'and a gate electrode 5 '(not yet made conductive).

Next, as shown in FIG. 3E, an impurity doping process is performed by using the gate electrode 5'as a mask. For impurity doping, for example, P ⁺ (phosphorus) ions or As ⁺ (arsenic) ions are implanted by an ion implantation method. The injection output at that time is set to 80 KeV, and the injection amount is set to 2 × 10 ¹⁵ cm ⁻² . Or PH
An ion doping method using ₃ gases may be used. Then, irradiation with excimer laser (250 mJ / cm ² ×
8 shots) or by thermal annealing. As a result, the source contact layer 3a 'and the drain contact layer 3b' are formed on the poly-Si film 3 '. Also, the gate electrode 5'becomes conductive.

Next, as shown in FIG. 3F, a metal film 6 of Al or the like is formed by vapor deposition to have a thickness of 1 μm. At this time, the metal film 6 is formed so as to contact the exposed portion of the base layer 2. Then, the metal film 6 is patterned to form the source electrode 6a and the drain electrode 6
b is formed.

Through the above steps, a thin film transistor is formed.

According to the above structure, in the step of FIG. 7C, the pol formed on the underlayers 2a and 2b is formed.
The crystal grain size of the y-Si film 3 ′ (portion to be the contact layer) is the same as that of the poly-Si film 3 ′ formed on the glass substrate 1.
Of the contact layers 3a ', 3
The sheet resistance of b'is reduced.

The reason will be described below.

In FIG. 2, quartz is used as an insulating substrate and a Mo film is used as an underlayer, and the underlayer has a thickness of 0 to 1000.
The po formed on this underlayer when changed to Å
6 is a graph showing changes in the average crystal grain size of a ly-Si film. In addition, the poly-Si film is a PECV film on a quartz substrate.
An a-Si film is deposited to a thickness of 1000Å by the D method, and the excimer laser is irradiated at a substrate temperature of 550 ° C (250 mJ.
/ Cm ² × 8 shots) and recrystallized.

As can be seen from the above graph, when the thickness of the underlayer is 0, that is, when the underlayer is not formed, the average crystal grain size of poly-Si is as large as about 1800Å. However, since the heat dissipation rate increases when the underlayer is formed, the average crystal grain size of poly-Si decreases as the thickness of the underlayer increases. For example, when the thickness of the underlayer is 500 Å, the poly-
The average crystal grain size of Si is as small as about 200Å.

FIG. 3 is a graph showing changes in sheet resistance with respect to changes in average crystal grain size of poly-Si.
At this time, P ⁺ (phosphorus) ions were used as the doping ions, the injection output was 80 KeV, and the injection amount was 2 × 10 5.
^It was set to ¹⁵ cm ^-2 . Further, the activation was performed by irradiation with an excimer laser (250 mJ / cm ² × 8 shots). The sheet resistance was measured by the four-point probe method.

As can be seen from the above graph, poly
The smaller the -Si crystal grain size, the higher the activation rate by laser irradiation after ion implantation and the smaller the sheet resistance.

Therefore, the sheet resistance of the contact layers 3a 'and 3b' obtained by forming the base layers 2a and 2b is smaller than that of the contact layer obtained without forming the base layer.

In this embodiment, a conductive material is used as the underlayer 2 and a part of it is exposed.
This portion is in contact with the metal film 6 which is the wiring electrode.
As a result, the contact layers 3a 'and 3b' directly contact the metal film 6 on the upper surface side and contact the metal film 6 on the lower surface side via the conductive underlying layer 2. Due to the contact on both sides, the contact area between the contact layers 3a 'and 3b' and the metal film 6 is widened, and the current extraction efficiency is improved.

FIG. 4 is a graph showing the gate voltage-drain current characteristics of the thin film transistor having the underlayer 2 and the conventional thin film transistor having no underlayer 2, respectively. As is clear from this graph, in the thin film transistor of the present invention having the underlayer 2, the subthreshold characteristic was improved. In the figure, the drain voltage was set to 2 V, and the gate length (L) / gate width (W) was set to 10/10 μm.

In this embodiment, a conductive material is used as the underlayer 2, and a part of the underlayer is exposed and connected to the wiring electrode to improve the current extraction efficiency. Even when a part of 2 is not exposed (it is not necessary to make it conductive in this case), the effect of reducing the sheet resistance of the contact layer can be obtained by reducing the particle size of only the portion to be the contact layer. Even in this case, since the underlayers 2a and 2b do not need to be removed after recrystallization, the number of steps does not increase.

In addition, in the step of FIG. 6C, the gap (channel) between the base layers 2a and 2b is set to be somewhat wider, or in the step of FIG. The LDD (Lig
An html Doped Drain) structure can be obtained. That is, a large crystal grain size is formed at the drain end, and a low concentration impurity region (for example, n ⁻ region) resulting from this large grain size is obtained.

Further, in the step of FIG. 6D, the resist pattern for forming the gate electrode is formed by exposure from the front surface side of the substrate, but not limited to this, it is also formed by exposure from the rear surface side of the substrate. It is possible. This back exposure enables the gate electrode to be accurately formed in the large grain size portion.

The back side exposure process will be described below with reference to FIG. In addition, a light-shielding material is used as the underlayer 2,
A negative type resist film 11 is used.

First, as shown in FIG.
A negative type resist film 11 is applied on the Si film 5. Next, the first exposure is performed from the front side with a photomask m having an opening corresponding to the land pattern interposed.
Note that the mask alignment at this time does not require much accuracy. Further, in this first exposure, the resist film 11
The amount of light is adjusted so that it will not be completely developed.

Next, as shown in FIG. 3B, a second exposure is performed from the back side of the transparent glass substrate 1. The amount of light in this second exposure is also the amount of light that does not completely develop the resist film 11, and is the amount of light that develops the resist film 11 when both are exposed in the first and second exposures. Is set to.

By the above first and second exposures, the resist film in the region sufficiently irradiated with light from both of them, that is, the resist located above the portion corresponding to the channel portion between the underlying layers 2a and 2b. Only the film is developed, and the gate electrode can be accurately formed in the large grain size portion.

Further, in the present embodiment, in the step of FIG. 1D, the poly-Si film 5 is formed by directly forming the poly-Si film by the LPCVD method. However, the present invention is not limited to this. The poly-Si film 5 may be obtained by forming a Si film and recrystallizing it.

As the underlayer 2, an n ⁺ -type a-Si film or a poly-Si film can be used in addition to those described above.

[0040]

As described above, according to the present invention, in order to reduce the sheet resistance of the contact layer, the grain size of this portion is made smaller by forming an underlayer having a thermal conductivity higher than that of the insulating substrate. It is realized by doing. Further, since this underlayer does not need to be removed after recrystallization, the process is simplified. In addition, the underlying layer is made conductive, and the wiring electrode is also brought into contact with the bottom surface side of the contact layer through this conductive underlying layer, thereby increasing the contact area between the contact layer and the wiring electrode, and The extraction efficiency is improved.

[Brief description of drawings]

FIG. 1 is a vertical sectional view showing a method of manufacturing a thin film transistor according to the present invention in the order of steps.

FIG. 2 is a film thickness of an underlayer and po formed on this underlayer.
It is a graph which shows the relationship with the size of the crystal grain size of a ly-Si film.

FIG. 3 is a graph showing the relationship between the crystal grain size of poly-Si and the sheet resistance.

FIG. 4 is a graph showing gate voltage-drain current characteristics of a thin film transistor of the present invention and a conventional thin film transistor.

FIG. 5 is a cross-sectional view showing a step of developing a resist film by backside exposure according to the present invention.

[Explanation of symbols]

1 glass substrate 2 underlying layer 3 a-Si film 3 'poly-Si film 4 SiO ₂ film 5' gate electrode 6a source electrode 6b drain electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location H01L 21/265 8617-4M H01L 21/265 A

Claims (2)

[Claims] 1. A step of forming an underlayer having a higher thermal conductivity than that of the insulating substrate on the insulating substrate corresponding to the formation positions of the source contact layer and the drain contact layer, and between the underlayers. And a step of forming a polycrystalline semiconductor film on the insulating substrate and both underlying layers, and a step of doping an impurity into a portion of the polycrystalline semiconductor film to be the contact layer. Production method. 2. A step of forming a conductive underlayer having a higher thermal conductivity than that of the insulating substrate on the insulating substrate corresponding to the positions where the source contact layer and the drain contact layer are formed, and the both lower layers. A step of forming a polycrystalline semiconductor film on the insulating substrate between the ground layers and on both of the underlayers so as to expose a part of these underlayers; and a step of forming a contact layer in the polycrystalline semiconductor film. A method of manufacturing a thin film transistor, comprising: a step of doping an impurity; and a step of forming a wiring electrode so as to be in contact with an exposed portion of the base layer.