JP3025342B2 - Thin film transistor and method for forming the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a liquid crystal display,
The present invention relates to a structure of a thin film transistor used for a driving circuit of an image sensor or the like and a method for forming the thin film transistor.

[0002]

2. Description of the Related Art Polycrystalline silicon (hereinafter simply referred to as poly-Si)
(Poly-Si). ) Using conventional thin film transistors (hereinafter simply referred to as TFTs).
In some cases. 2) will be briefly described with reference to FIG.

FIG. 5 is a schematic sectional view of a main part of a typical conventional TFT. Amorphous silicon (hereinafter sometimes simply referred to as a-Si) on the insulating substrate 12.
Then, the a-Si film is recrystallized into a polycrystalline silicon film by a laser annealing method or a solid phase growth method. Ions are implanted into the polycrystalline silicon island region 14 protruding above the substrate 12 to form an n ⁺ -type region (ohmic layer) 16 and a channel region 18 including a remaining region where the ion implantation has not been performed. Thereafter, an insulating film made of SiO ₂ (silicon dioxide) or Si—N (silicon nitride) is formed on the entire surface of the insulating substrate 12 including the island region 14 of polycrystalline silicon. Next, as usual, a contact hole is formed in this insulating film, and thereafter, a gate insulating film 20 and an insulating layer 22 covering the ohmic layer 16 and the insulating substrate 12 are formed. Finally, each of the gate electrode 24, the source electrode 26, and the drain electrode 28 is formed.

In the solid phase growth method for recrystallizing an a-Si film into a polycrystalline silicon film, a high-temperature annealing at 600 ° C. or more is required, so that an expensive quartz substrate must be used as the substrate.

A method for forming a polycrystalline silicon film at a low temperature of 600 ° C. or less using an inexpensive glass substrate is as follows.
This is proposed in Japanese Patent Application No. 2-160572 of the present applicant. In the plasma CVD method disclosed therein, Si
F ₄ (silane tetrafluoride) / SiH ₄ (silane) / H
_{2 The} polycrystalline silicon is grown directly on the base under a constant flow rate ratio of the mixed gas of (hydrogen) and a low growth temperature of 250 ° C. to 300 ° C. This method has an advantage that an inexpensive glass substrate can be used because the kind of the base is not limited.

[0006]

However, in this method, the crystal grain size is very small in the initial stage of the growth of the polycrystalline silicon film. Therefore, in the case of a thin polycrystalline silicon film at the initial stage of film formation, the mobility in the channel region becomes small because the crystal grain size is small. Therefore,
By depositing a polycrystalline silicon film so as to have a thickness of 200 nm or more, preferably 300 nm or more,
It is necessary to increase the crystal grain size to increase the mobility in the channel region. However, when the film thickness is increased, the level difference between the surface of the polycrystalline silicon island region and the surface of the insulating substrate becomes large, so that the level difference or disconnection of the insulating layer, the source electrode, and the drain electrode at the level difference portion. It is easy to occur.

[0007]

SUMMARY OF THE INVENTION An object of the present invention is to provide a thin film transistor having a structure in which such an insulating layer or an electrode layer does not cause disconnection or disconnection, and a method for forming the same.

In order to achieve this object, according to the present invention, in a thin film transistor having a channel region and an ohmic region in a polycrystalline silicon film provided on an insulating substrate, the polycrystalline silicon film is first and second. The first polycrystalline silicon film is formed on the entire upper surface of the insulating substrate, and the area of the second polycrystalline silicon film where both the channel and ohmic regions are formed is The first polycrystalline silicon film is provided on the first polycrystalline silicon film in a state where the grain size is larger than that of the first polycrystalline silicon film. An intermediate insulating film is provided on a silicon film.

In practicing the present invention, it is preferable that the second polycrystalline silicon film extends on the intermediate insulating film.

According to the forming method of the present invention,
(A) a step of depositing a first polycrystalline silicon film on the insulating film; (b) a step of depositing an intermediate insulating film on the first polycrystalline silicon film; and (c) both a channel region and an ohmic region. Removing a portion of the intermediate insulating film corresponding to the region where the region is to be formed; (d) depositing a second polycrystalline silicon film on the upper side of the structure obtained in the step (c);
(E) forming the channel region and the ohmic region in the second polysilicon region, respectively;
Providing a gate electrode above the channel region and providing source / drain electrodes on the ohmic region.

In carrying out this forming method, preferably, there is provided a step of (g) forming an insulating film having a contact hole in the ohmic region after the step (e) and before the step (f). Is good.

In carrying out this forming method, preferably, a step of forming a part of the insulating film as a gate insulating film after the step (g) and before the step (f). And should be included.

[0013]

According to the above-described structure of the thin film transistor, the second polycrystalline silicon film has a smaller grain size than the first polycrystalline silicon film in the area where both the channel and the ohmic region are formed on the first polycrystalline silicon film. Is provided in a large state.
Then, an intermediate insulating film is provided on the first polycrystalline silicon film outside the formation area of both the channel and ohmic regions. The second polycrystalline silicon film having a large grain size has a low mobility because the mobility of carriers is large. On the other hand, outside the formation region of both the channel and ohmic regions, the second polycrystalline silicon film portion having a small grain size or the insulating layer can be used, so that the region has high resistance. Therefore, element separation can be substantially performed.

Further, by providing a second polycrystalline silicon film on the intermediate insulating film or providing another insulating layer, an area between the channel and ohmic region forming area and the other area is formed. Can be reduced or the heights can be made substantially the same, so that there is no problem of disconnection of the electrode or the insulating layer as in the related art.

According to the method of forming a thin film transistor of the present invention, after a small amount of the first polycrystalline silicon film is deposited, a thin intermediate insulating film is deposited thereon. Next, after removing the intermediate insulating film in the area where both the channel and the ohmic region are to be formed, the second polysilicon film is deposited again. As a result, the portion of the second polycrystalline silicon film in the area where both the channel and the ohmic region are formed has a large grain size.
The grain size of the portion of the second polycrystalline silicon film deposited on the intermediate insulating film is small. Another insulating film may be provided on the portion of the second polycrystalline silicon film having a small grain size or by removing this portion. Through these steps, a low-resistance region is formed in the formation region of both the channel and the ohmic region, and a high-resistance region is formed in the other regions. A process difference between a portion of the first polycrystalline silicon film having a small grain size and a portion of the intermediate polycrystalline silicon film or the second polycrystalline silicon film formed thereon;
Therefore, since the step can be reduced, there is no possibility that the insulating layer or the electrode provided thereabove will be disconnected.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. It should be noted that the drawings merely schematically show the dimensions, shapes, and arrangements of the components so that the present invention can be understood. In the following examples, a method of forming a thin film transistor will be described, and a structure of the thin film transistor will also be described.

FIGS. 1 and 4 are cross-sectional views of a principal part showing an embodiment of the structure of the thin film transistor of the present invention. 2A to 2C and FIGS. 3A to 3C.
(C) is a process diagram of the method of forming a thin film transistor of the present invention, the former is a diagram for explaining the first half of the process, and the latter is a diagram for explaining the latter half of the process. The drawings at each stage of the process are cross-sectional views of main parts of the structure obtained at that stage.

First, as shown in FIG. 2A, a first polycrystalline silicon film 52 is formed on an insulating substrate 50, for example, a glass substrate.
Is deposited to obtain a structure as shown in FIG. This film formation is performed using a normal plasma CVD apparatus.
In this embodiment, the source gas used for the film formation is a mixed gas of furan tetrafluoride (SiF ₄ ), silane (SiH ₄ ), and hydrogen (H ₂ ). First polycrystalline silicon film (hereinafter, may be simply referred to as a first poly-Si film) 5
2 is preferably as thin as about 200 nm to 300 nm. In this embodiment, the film thickness corresponding to the thickness at which the crystal whose (220) plane is reflected by X-ray diffraction starts to grow is 20 nm.
The thickness is set to 0 nm. The film forming conditions at this time are set as follows as an example. The SiF ₄ 300~500SCC
M and SiH ₄ are flow rates of 10 SCCM, and H ₂ is flow rate of 500 SCCM. The substrate temperature is 300 ° C., and the reaction pressure is 2 torr. This first poly Si
The film 52 has a small thickness and is formed by forming a film on the insulating substrate 50. Therefore, as is well known, the particle size of the poly-Si in this film is small.

Next, a thin intermediate insulating film is once formed on the entire surface of the first poly-Si film 52. This intermediate insulating film is made of, for example, silicon dioxide (SiO ₂ ), and is formed using a normal technique such as plasma CVD or sputtering. The thickness of the intermediate insulating film is preferably set to an appropriate value in the range of several nm to several tens nm.
In this embodiment, the thickness is set to 10 nm. Thereafter, the intermediate insulating film is patterned by using a usual photolithography technique to obtain a structure as shown in FIG.
In this case, the portion of the intermediate insulating film corresponding to the portion where the channel and ohmic regions of the thin film transistor (hereinafter sometimes referred to as TFT) are to be formed is removed by, for example, etching with dilute hydrofluoric acid to form the opening 54.
To form In this opening 54, a part of the underlying first poly-Si film 52 is exposed. Then, the remaining insulating film portion substantially becomes the intermediate insulating film 56 of the TFT.

Next, polycrystalline silicon is deposited again on the exposed surface of the first poly-Si film 52 and on the entire surface of the intermediate insulating film 56. In this case, the second poly-Si is formed using a plasma CVD apparatus under the same source gas, flow rate conditions, and other film formation conditions as in the case of forming the first poly-Si film 52. As a result of this film formation, as shown in FIG. 2C, the second poly-Si film 58 has a thickness of, for example, 100 nm to 3 nm.
A structure formed with appropriate values in the range of 00 nm is obtained. The second poly-Si film 58 includes a portion 58a directly grown on the first poly-Si film 52 and a portion 58b grown on the intermediate insulating film 56. This second poly-Si film portion 5
8a is a region where both the channel and ohmic regions of the TFT are to be formed. And this part 58a
Is directly grown on the first poly-Si film 52, so that the poly-Si grows taking over the grain size, reflecting the poly-Si underlayer. Therefore, the grain size of the poly-Si in the second poly-Si film portion 58a is larger than the grain size of the first poly-Si film 52. On the other hand, poly-Si grown on the intermediate insulating film 56
Since the film portion 58b is grown on the insulating film, the poly S
i starts growing from a state where the initial crystal grain size is small. Therefore, the grain size of the poly-Si portion 58b formed by growing the second poly-Si is smaller than that of the poly-Si portion 58a. The poly-Si portion 58a having a large particle size has a low resistance, and the poly-Si portion 58b having a small particle size has a high resistance. As a result of the formation of the poly-Si film 58, the height difference between the surfaces of both the poly-Si film portions 58a and 58b is substantially reduced by the thickness of the intermediate insulating film 56 substantially. .

The subsequent steps are similar to those of the conventional TFT, but will be briefly described. First, the poly-Si film portion 58
A mask 60 having an opening in the area where the ohmic region a is to be formed is formed on the surface of the second poly-Si film 58 with a resist of an appropriate material. Then, appropriate ions such as phosphorus (P) are implanted into the second poly-Si film 58 to form an n ⁺ -type region (ohmic region) 62, and a structure as shown in FIG. 3A is obtained. The portion of the poly-Si film remaining after the formation of the ohmic region 62 becomes the channel region 64.

Next, after removing the resist mask 60, another insulating film having an appropriate thickness is formed on the second poly-Si film 58 after ion implantation by plasma CVD or sputtering. This insulating film is preferably, for example, a silicon dioxide (SiO ₂ ) film or a Si—N film. This insulating film is patterned using a photolithography etching technique to form a gate insulating film 66 and another insulating film 68. The contact hole formed at this time is indicated by 70. The structure obtained in this way is shown in FIG.

Next, aluminum (Al), chromium (Cr), or other suitable conductive metal is deposited using a normal deposition technique to form an electrode wiring, thereby completing the TFT structure. The structure thus obtained is shown in FIG. 3C and FIG. 1, respectively. In the drawing, the gate electrode is indicated by 72, the source electrode is indicated by 74, and the drain electrode is indicated by 76.

The TFT thus formed is shown in FIG.
As shown in FIG. 5, a polycrystalline silicon (poly Si) film 80 is formed by the first and second polycrystalline silicon films 52 and 58. The thickness of the poly-Si film 80 can be made as thin as the conventional one. The first polycrystalline silicon film 52 is provided on the entire upper surface of the glass substrate 50. Further, channel region 6 of second polycrystalline silicon film 58 is formed.
4 and the formation area 58a of both the ohmic region 62
Has a larger grain size of poly-Si than the first polycrystalline silicon film 52. The mobility of the carrier in the area 58a is, for example, assuming that the particle size is about 100 nm.
This is a considerably high value of about 20 cm / V · sec. And both channel and ohmic regions 64 and 62
An intermediate insulating film 56 is provided on the first polycrystalline silicon film 52 outside the formation area 58a.

With the structure shown in FIG. 1, the first
A second poly-Si film portion 58a provided directly on the poly-Si film 52 and a second poly-Si film portion provided on the intermediate insulating film 56;
Since the height difference from the film portion 58b is small, even if an insulating film or an electrode wiring is formed on the upper side of the film portion 58b, there is no possibility that these steps will be disconnected.

Next, another embodiment of the present invention will be described. After the structure shown in FIG. 2C is obtained,
After the ion implantation step and before the step of forming the insulating film, the second poly-Si film portion 58b above the intermediate insulating film 56 is removed by using a suitable conventional technique. In this case, for example, if the intermediate insulating film 56 is formed of SiO ₂ and the poly-Si is removed by etching with CF ₄ / O ₂ , the SiO ₂ of the intermediate insulating film 56 functions as an etching stopper, so that the height difference with good reproducibility is obtained. A small step structure can be formed. Thereafter, the above-described gate insulating film 66 and other insulating films 68 are formed, and thereafter, the gate electrode 72, the source electrode 74, and the drain electrode 76 are formed as in the above-described embodiment. FIG. 4 shows the structure of the TFT transistor thus formed.

FIG. 4 shows a TF according to another embodiment of the present invention.
It is principal part sectional drawing of T. This structure differs from the structure of FIG. 1 in that the second poly-Si film portion (shown by 58b in FIG. 1) on the intermediate insulating film 56 is removed, and another intermediate silicon film is formed on the intermediate insulating film 56. The point is that an insulating film 68 is provided. Even in the case of this structure, since the height difference between the second poly-Si film portion 58a and the intermediate insulating film 56 is small, even if an insulating film or electrode wiring is formed on the upper side thereof, disconnection of these steps occurs. There is no fear.

[0028]

According to the above-described thin film transistor and the method of forming the same according to the present invention, the following effects can be obtained even when the thickness of the polycrystalline silicon film is substantially the same as that of the prior art.

(I) By increasing the grain size of the polycrystalline silicon in both the channel and ohmic regions, the electric resistance in these regions can be reduced. And the grain size of the polycrystalline silicon region outside these regions is small or
Since the polycrystalline silicon region having a large grain size is surrounded by an insulating film, the region having a small grain size and the insulating film have high electric resistance. Therefore, according to the structure and method of the present invention, the leak current of the thin film transistor is reduced, and therefore, a special thin film transistor element isolation step for forming an element structure for preventing the leak current is not required.

(Ii) The height difference between the polycrystalline silicon film portion in both the channel and ohmic regions and the intermediate insulating film, or the polycrystalline silicon film portion in both the channel and ohmic regions and the polycrystalline silicon around it Since the height difference from the film portion is small, there is no possibility of disconnection of the insulating film and the electrode layer provided thereabove.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a main part of an embodiment of the structure of a TFT according to the present invention.

FIGS. 2A to 2C are first-half process charts for explaining a method of forming a TFT according to the present invention;

FIGS. 3A to 3C are second half process diagrams for describing the method of forming a TFT according to the present invention;

FIG. 4 is a partial sectional view showing another embodiment of the structure of the TFT of the present invention.

FIG. 5 is a cross-sectional view of a main part of a structure of a conventional TFT.

[Explanation of symbols]

50: insulating substrate (for example, glass substrate) 52: first polycrystalline silicon film (first poly-Si film) 54: opening 56: intermediate insulating film 58: second polycrystalline silicon film (second poly-Si film) 58a : Second polycrystalline silicon film portion (in the formation area of both channel and ohmic region) 58b: polycrystalline silicon film portion (on intermediate insulating film) 60: mask, 62: ohmic region 64: channel region, 66: gate Insulating film 68: Insulating film, 70: Contact hole 72: Gate electrode, 74: Source electrode 76: Drain electrode 80: Polycrystalline silicon (poly Si film)

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/336

Claims (5)

(57) [Claims] 1. A thin film transistor comprising a channel region and an ohmic region in a polycrystalline silicon film provided on an insulating substrate, wherein the polycrystalline silicon film is formed of first and second polycrystalline silicon films. The polycrystalline silicon film is provided on the entire upper surface of the insulating substrate, and the formation region of both the channel and the ohmic region of the second polycrystalline silicon film is formed on the first polycrystalline silicon film by the first polycrystalline silicon film. A thin film transistor provided in a state where the grain size is larger than that of the polycrystalline silicon film, and an intermediate insulating film provided on the first polycrystalline silicon film outside the formation area of both the channel and the ohmic region. . 2. A thin film transistor, wherein the second polycrystalline silicon film extends on the intermediate insulating film according to claim 1. (A) depositing a first polycrystalline silicon film on the insulating film; (b) depositing an intermediate insulating film on the first polycrystalline silicon film; and (c) channel region. Removing a portion of the intermediate insulating film corresponding to the area where both the ohmic region and the ohmic region are to be formed; and (d) depositing a second polysilicon film on the structure obtained in the step (c). (E) forming the channel region and the ohmic region in the second polycrystalline silicon region, respectively; and (f) providing a gate electrode above the channel region and forming source / drain electrodes on the ohmic region. Forming a thin film transistor. 4. The method for forming a thin film transistor according to claim 3, further comprising: (g) forming an insulating film having a contact hole in the ohmic region after the step (e) and before the step (f). A method for forming a thin film transistor, comprising: 5. A step of forming a part of the insulating film as a gate insulating film after the step (g) of the claim 4 and before the step (f). Forming method.