JPH04336468A - Fabrication of thin film transistor - Google Patents

Abstract

PURPOSE:To eliminate constraint of temperature in the thermal activation of source.drain impurities due to an aluminum gate electrode by making it possible to compose the gate electrode of a heat resistant metal. CONSTITUTION:An active layer, i.e., an a-Si layer 2, a gate insulation layer 3 and a nucleus, i.e., an a-Si layer 4, for selective growth of tungsten are deposited on a transparent substrate 1, the a-Si layer 4 is then patterned according to the profile of gate electrode, and source.drain impurities are implanted into the first a-Si layer with a resist layer 5 as a mask. The resist layer 5 is then removed to expose the a-Si layer 4 on which a tungsten layer 6 is grown selectively. Consequently, a gate electrode composed of the tungsten film 6 is formed while being self-aligned with source and drain regions. Thus formed tungsten gate electrode causes no penetration through the gate insulation layer even if heat treatment is carried out at a temperature for sufficiently activating the source.drain impurities.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to thin-film transistors used in liquid crystal display devices, etc.
The present invention relates to a sis-tor (TFT) matrix, and in particular to a method for forming a gate electrode in a coplanar TFT.

0002

[Prior Art] A display device using a TFT matrix has a transistor switch for each pixel, so crosstalk during half-selection is completely eliminated and excellent display quality can be obtained. In particular, TFT
In a liquid crystal display (LCD) having a matrix, a driver circuit made of TFTs can be formed on the same substrate. In addition, by forming a TFT matrix on the back side substrate, the voltage applied to the electrodes formed on the display side substrate is independent of pixel address control, so the electrodes are formed in a stripe shape. There will be no need. Therefore, restrictions on the resistance value of the transparent electrode are significantly relaxed, making it possible to improve high resolution.

0003

[Problem to be solved by the invention] The active layer constituting the TFT is usually made of amorphous silicon (a-
Polysilicon (Si) has a higher mobility than Si.
-Si) layer, and an aluminum layer is used as the gate electrode. Then, using the gate electrode as a mask, impurity ions are implanted into the active layer to form the source and drain regions. In this combination, the heat treatment temperature for activating the source/drain impurities had to be kept below 450°C, and as a result, there was a problem that activation was not performed sufficiently. The restriction on the heat treatment temperature above is 450℃
This is because the aluminum gate electrode deteriorates or the gate insulating layer is penetrated by aluminum.

[0004] The method of implanting and activating source and drain impurities before forming the gate electrode does not allow forming the source and drain regions in a self-aligned manner using the gate electrode as a mask, and it is difficult to pattern them. This is undesirable because it results in variations in TFT characteristics and an increase in the number of steps due to mask positional deviation.

[0005]Also, it is conceivable to form the gate electrode using a high melting point metal such as tungsten instead of aluminum, but for example, in the usual etching method for patterning a tungsten layer,
Since there is not a sufficient selectivity with the resist mask, it is not possible to form a gate electrode with good dimensional accuracy.

[0006]

[Means for solving the problem] The above conventional problems are as follows:
A first film made of a semiconductor, a second film made of an insulator, and a third film serving as a nucleus for selective vapor phase growth of a high melting point metal film are sequentially formed on one surface of the substrate, and defined on the surface of the substrate. forming a resist film on the third film to selectively mask a region where a gate electrode is to be formed in each of the plurality of element formation regions, and then selecting the third film exposed from the resist film; and the etched third
impurity ions are implanted into the first film through the second film exposed from the second film to form a source region and a drain region, and the resist film is removed to expose the etched third film. The T according to the present invention is characterized in that it includes steps of removing the third film and selectively depositing a high melting point metal film on the exposed third film to form a gate electrode.
FT manufacturing method, or: sequentially forming on one surface of a substrate a first film made of a semiconductor, a second film made of an insulator, and a third film serving as a nucleus for selective vapor phase growth of a high melting point metal film. A resist film is formed on the third film to selectively mask a region where a gate electrode is formed in each of the plurality of element formation regions defined on the surface of the substrate, and then the resist film is exposed from the resist film. The third film and the second film are sequentially selectively etched to expose the first film, and impurities are implanted into the first film exposed from the etched third film. forming a source region and a drain region;
The resist film is removed to expose the etched third film, and a high melting point metal film is chemically vapor-deposited on the exposed third film to form a gate electrode. The problem is solved by a method for manufacturing a TFT according to the present invention, which is characterized by including the following.

[0007]

[Operation] Figure 1 is a diagram explaining the principle of the present invention.
a) As shown in FIG. 1, on a transparent substrate 1, an a-Si layer 2 serving as an active layer, a gate insulating layer 3, and an a-Si layer 4 serving as a nucleus for selective growth of tungsten, for example, are deposited. After patterning the a-Si layer 4 in the shape of a gate electrode, the first a-Si layer 4 is patterned using the resist layer 5 as a mask.
Source/drain impurities are ion-implanted into the Si layer. Next, as shown in FIG. 5B, the resist layer 5 is removed, and a tungsten layer 6 is selectively grown on the exposed a-Si layer 4 using, for example, chemical vapor deposition (CVD). . As a result, a gate electrode made of tungsten layer 6 is formed in self-alignment with the source and drain regions.

Further, the tungsten gate electrode formed as described above is heated at a temperature necessary to sufficiently activate the source/drain impurities, that is, 500 to 60°C.
Even during heat treatment at 0°C, there is no problem of deterioration or penetration of the gate insulating layer, which occurs with aluminum gate electrodes. Note that the a-Si layer 2 has a pol
y-Si layer. Furthermore, since the a-Si layer 4, which is the core of the selective growth of tungsten, is alloyed during the activation heat treatment, the interface with the tungsten layer 6 becomes unclear.

[0009]

[Example] Fig. 2 is a sectional view of a main part for explaining the process of an embodiment of the present invention, in which a transparent substrate 1 made of, for example, quartz glass is coated with a thickness of 100 nm using the well-known low pressure CVD method. an a-Si layer 2 is grown. a-Si
can be grown by CVD at a lower temperature than poly-Si. In this example, growth was performed at 400°C. Thereafter, a 150 nm thick gate insulating layer 3 made of SiO (silicon monoxide) and a 40 nm thick a-Si layer 4 are successively deposited on the a-Si layer 2. SiO
The gate insulating layer 3 may be deposited by a well-known low pressure CVD (chemical vapor deposition) method, and the a-Si layer 4 may be deposited by a plasma CVD method or the like as appropriate.

Next, as shown in the same figure (b),
A resist layer 5 is formed on the a-Si layer 4 to cover the gate electrode formation region, and the a-Si layer 5 is formed using the resist layer 5 as a mask.
The i-layer 4 is selectively etched. This etching is
Either well-known dry etching or wet etching may be used. After that, for the a-Si layer 2 in the area exposed from the resist layer 5,
Source/drain impurities are ion-implanted through the gate insulating layer 3. An example of ion implantation conditions when using phosphorus (P) as this impurity is an acceleration voltage of 120Ke.
V, the dose amount is 3×1015 pieces/cm−2.

Next, after removing the resist layer 5,
As shown in FIG. 4C, a 200 nm thick tungsten layer 6 is selectively grown on the a-Si layer 4. An example of this growth condition is a substrate temperature of 280 °C,
The growth raw material gas was diluted with H2 at a flow rate of 10S.
CCM tungsten hexafluoride (WF6) and flow rate 6SC
A mixed gas of CM and silane (SiH4) was used. Under these conditions, tungsten does not grow on the gate insulating layer 3. Since the tungsten layer 6 grows while reacting with the a-Si layer 4, in order to grow the tungsten layer 6 of 200 nm, the thickness of the a-Si layer 4 must be 40 nm.
About nm is required.

[0012] After the above, the substrate is heat treated at 600°C for 2 hours while flowing nitrogen gas into the vacuum container. As a result, the impurity is activated, and a source region and a drain region (both not shown) are formed. In this heat treatment, the a-Si layer 2 is made of poly-Si
Convert to

Next, as shown in the same figure (d),
After depositing a 300 nm thick insulating layer 7 made of, for example, SiO 2 to cover the tungsten layer 6, openings are formed in the insulating layer 7 to expose the gate electrode made of the tungsten layer 6 and the source and drain regions. Then, an aluminum layer with a thickness of 200 nm is deposited on the insulating layer 7, and this is patterned to form the gate wiring 8 and source/drain electrodes 9, thereby completing the TFT according to the present invention.

FIG. 3 is a sectional view of a main part for explaining the process of another embodiment of the present invention, and as shown in FIG. Similarly, a-Si layer 2 with a thickness of 100 nm and
150 nm thick gate insulating layer 31 made of SiO2
and an a-Si layer 4 with a thickness of 40 nm are sequentially deposited. After forming a resist layer 5 covering the gate electrode formation region, a-Si layer 4 exposed from the resist layer 5 is formed.
Then, the gate insulating layer 31 is sequentially and selectively etched. This etching may be performed using either well-known dry etching or wet etching. After that, a-
Source/drain impurities are implanted into the Si layer 2.

In the case of this embodiment, since the a-Si layer 2 is exposed, the method for implanting the impurity described above may be the so-called ion doping method or plasma doping method, in which ions are not separated by mass, in addition to the ion implantation method. can be used. For example, an example of the conditions for implantation using the ion doping method, assuming that phosphorus (P) is used as the impurity, is an acceleration voltage of 5 KeV and a dose of 1×10 15 atoms/cm −2 .

Next, after removing the resist layer 5,
As shown in FIG. 4B, a 200 nm thick tungsten layer 6 is selectively grown on the a-Si layer 4. The growth conditions may be the same as in the previous example. In this example, the a-
For example, a tungsten layer 61 is also grown on the Si layer 2. Since the tungsten layer 61 grows while reacting with the a-Si layer 2, the thickness of the a-Si layer 2 is reduced to about 60 nm.

After the above, the substrate is heat-treated at 550° C. for 4 hours while flowing nitrogen gas into the vacuum container. As a result, the impurity is activated, and a source region and a drain region (both not shown) are formed. In this heat treatment, the a-Si layer 2 is made of poly-Si
Convert to

Next, as shown in the same figure (c),
covering the tungsten layers 6 and 61, e.g. SiO
After depositing an insulating layer 7 with a thickness of 500 nm consisting of
An opening is formed in the insulating layer 7 to expose the gate electrode made of the tungsten layer 6 and the tungsten layer 61 on the source and drain regions. And insulating layer 7
A 200 nm thick aluminum layer is deposited on top and patterned to form gate wiring 8 and source wiring.
A drain electrode 9 is formed to complete the TFT according to the present invention.

As is clear from FIG. 3(b), the thickness of the gate insulating layer 31 is set so that the tungsten layer 6 and the tungsten layer 61 are formed separately.
It is necessary to make the thickness sufficiently larger than the thickness of the tungsten layer 61.

In both of the above embodiments, the a-Si layer was used as the core layer for selectively growing the tungsten layer 6, but other layers such as polysilicon may also be used. Further, instead of the tungsten layer 6, a high melting point metal layer such as titanium may be used. Furthermore, a SiOx film or a Si3N4 film may be used as the gate insulating layer 3 or 31, and known techniques such as CVD, sputtering, etc. may be appropriately used to form these films.

[0021]

[Effects of the Invention] According to the present invention, by forming the gate electrode with a heat-resistant metal, problems such as deterioration and penetration into the gate insulating layer, which occur with aluminum gate electrodes, are eliminated, and the gate electrode is made of a heat-resistant metal. This has the effect of allowing sufficient activation heat treatment to be performed and making it possible to form TFTs with excellent characteristics and low source/drain resistance.

[Brief explanation of the drawing]

[Figure 1] Diagram explaining the principle of the present invention

[Figure 2] Process explanatory diagram of one embodiment of the present invention

[Figure 3]
Process explanatory diagram of another embodiment of the present invention

[Explanation of symbols]

1 Transparent substrate
6, 61 Tungsten layer 2, 4 a-Si layer
7 Insulating layer 3, 31 Gate insulating layer 8 Gate wiring 5
resist layer
9 Source/drain electrode

Claims (4)

[Claims] 1. Step of sequentially forming on one surface of a substrate a first film made of a semiconductor, a second film made of an insulator, and a third film serving as a nucleus for selective vapor phase growth of a high melting point metal film. and,
A resist film is formed on the third film to selectively mask a region in which a gate electrode is formed in each of the plurality of element formation regions defined on the surface of the substrate, and then the resist film exposed from the resist film is a step of selectively etching the third film; and a step of selectively etching the second film exposed from the etched third film.
forming source and drain regions by ion-implanting impurities into the first film through the third film; removing the resist film to expose the etched third film; A method for manufacturing a thin film transistor, comprising the step of forming a gate electrode by selectively chemical vapor deposition of a high melting point metal film on the third film. 2. Step of sequentially forming on one surface of a substrate a first film made of a semiconductor, a second film made of an insulator, and a third film serving as a nucleus for selective vapor phase growth of a high melting point metal film. and,
A resist film is formed on the third film to selectively mask a region in which a gate electrode is formed in each of the plurality of element formation regions defined on the surface of the substrate, and then the resist film exposed from the resist film is 3 and the second film to expose the first film; and implanting impurities into the first film exposed from the etched third film. forming a source region and a drain region, removing the resist film to expose the etched third film, and depositing a high melting point metal film on the exposed third film. A method for manufacturing a thin film transistor, comprising the step of forming a gate electrode by chemical vapor deposition. 3. The method of manufacturing a thin film transistor according to claim 2, wherein the impurity is implanted into the first film without mass-separating the impurity ions. 4. The method of manufacturing a thin film transistor according to claim 1, further comprising the step of forming means for separating each of the element forming regions in the first film.